A chip stack structure, a manufacturing method and a memory

Abstract

The present disclosure relates to the field of semiconductor, aiming at the problems of poor yield and high repair cost of the stack of three-dimensional memory, the chip stack structure, the preparation method and the memory are provided, the memory comprises a plurality of storage chips, a target redundant chip and a plurality of repair groups; each repair group comprises A programmable transmission paths, different signal transmission paths are connected with the target redundant chip through the corresponding programmable transmission paths, and the different signal transmission paths are used for providing control signals for different storage chips stacked in sequence; A is a positive integer; wherein, in each repair group, the A programmable transmission paths are selectively enabled based on a flag signal; the flag signal is used to represent the position of the damaged storage chip, the target redundant chip is used to repair the damaged storage chip, can repair 1 storage chip damage and 2 storage chip damage in some scenarios, improve the overall stack yield.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a chip stack structure, a preparation method and a memory. BACKGROUND

[0002] In order to further improve performance, a dynamic random access memory (DRAM) can be selected to have a three-dimensional structure, specifically including a plurality of layers of storage chips stacked vertically. As the number of stacked layers gradually increases, the probability of failure of a storage chip in the stacked structure is higher and higher.

[0003] Improving the repair capability of the memory can be considered from the following three aspects: (1) increasing the redundancy of word lines, bit lines, storage sections and storage banks inside the storage chip, but this will increase the circuit area of a single storage chip; (2) increasing the redundant storage chip; however, since every 4 layers of storage chips are controlled as a memory rank, when any storage chip is damaged, repair needs to be performed in units of memory ranks, and the repair cost is high; (3) using a static random access memory (SRAM) to completely replace the read and write access of the failed address, i.e., redirecting the failed address to an SRAM area. However, the disadvantage is that the capacity of the SRAM is relatively small, and it is still a drop in the bucket under the condition of gradually increasing stacked capacity. Therefore, the yield of the three-dimensional memory stack is still a great challenge. SUMMARY

[0004] Embodiments of the present disclosure provide a chip stack structure, a preparation method and a memory.

[0005] In a first aspect, embodiments of the present disclosure provide a chip stack structure, the chip stack structure comprising at least one stack unit and a plurality of redundant chips stacked in a first direction in sequence; the stack unit comprises a plurality of storage chips stacked in the first direction in sequence, the plurality of storage chips comprising: a first storage chip, a second storage chip, a third storage chip and a fourth storage chip; the plurality of redundant chips comprises: a first redundant chip and a second redundant chip;

[0006] The storage chip and the redundant chip each comprise N port groups, each of the port groups comprising a first connection port, a second connection port, a third connection port and a fourth connection port; N is a positive integer;

[0007] The first connection port of the first storage chip is connected to the first connection port of the first redundant chip at least via the non-first connection port of the non-first storage chip stacked above;

[0008] the first connection port of the second memory chip is connected to the first connection port of the second redundancy chip at least via the non-first connection port of the non-second memory chip stacked above;

[0009] the first connection port of the third memory chip is connected to the fourth connection port of the second redundancy chip at least via the non-first connection port of the non-third memory chip stacked above;

[0010] the first connection port of the fourth memory chip is connected to the fourth connection port of the first redundancy chip at least via the non-first connection port of the non-fourth memory chip stacked above;

[0011] for each port group of each memory chip, only the first connection port is connected to the internal circuit of the memory chip; for each port group of each redundancy chip, only one of the first connection port and the fourth connection port is connected to the internal circuit of the redundancy chip.

[0012] In some embodiments, all port groups of the first redundancy chip are connected to the internal circuit of the redundancy chip by the first connection port; or, all port groups of the first redundancy chip are connected to the internal circuit of the redundancy chip by the fourth connection port; or, some port groups of the first redundancy chip are connected to the internal circuit of the redundancy chip by the first connection port, and the other port groups are connected to the internal circuit of the redundancy chip by the fourth connection port.

[0013] all port groups of the second redundancy chip are connected to the internal circuit of the redundancy chip by the first connection port; or, all port groups of the second redundancy chip are connected to the internal circuit of the redundancy chip by the fourth connection port; or, some port groups of the second redundancy chip are connected to the internal circuit of the redundancy chip by the first connection port, and the other port groups are connected to the internal circuit of the redundancy chip by the fourth connection port.

[0014] In some embodiments, the first redundancy chip is used to repair any first memory chip, and the second redundancy chip is used to repair any second memory chip; or, the first redundancy chip is used to repair any fourth memory chip, and the second redundancy chip is used to repair any third memory chip.

[0015] In some embodiments, in the case that the first redundant chip is used to repair any of the first memory chips and the second redundant chip is used to repair any of the second memory chips: for each of the port groups of the first redundant chip and the second redundant chip, the first connection port is connected with the internal circuit of the redundant chip; the second connection port, the third connection port and the fourth connection port are all electrically isolated from the internal circuit of the redundant chip; in the case that the first redundant chip is used to repair any of the fourth memory chips and the second redundant chip is used to repair any of the third memory chips: for each of the port groups of the first redundant chip and the second redundant chip, the fourth connection port is connected with the internal circuit of the redundant chip; the first connection port, the second connection port and the third connection port are all electrically isolated from the internal circuit of the redundant chip.

[0016] In some embodiments, the first connection port of each of the first memory chips, the second connection port of each of the second memory chips, the third connection port of each of the third memory chips, the fourth connection port of each of the fourth memory chips, the first connection port of the first redundant chip, and the second connection port of the second redundant chip are aligned in a first direction and electrically connected to form a signal path.

[0017] The second connection port of each of the first memory chips, the first connection port of each of the second memory chips, the fourth connection port of each of the third memory chips, the third connection port of each of the fourth memory chips, the second connection port of the first redundant chip, and the first connection port of the second redundant chip are aligned in a first direction and electrically connected to form a signal path.

[0018] The third connection port of each of the first memory chips, the fourth connection port of each of the second memory chips, the first connection port of each of the third memory chips, the second connection port of each of the fourth memory chips, the third connection port of the first redundant chip, and the fourth connection port of the second redundant chip are aligned in a first direction and electrically connected to form a signal path.

[0019] The fourth connection port of each of the first memory chips, the third connection port of each of the second memory chips, the second connection port of each of the third memory chips, the first connection port of each of the fourth memory chips, the fourth connection port of the first redundant chip, and the third connection port of the second redundant chip are aligned in a first direction and electrically connected to form a signal path.

[0020] In some embodiments, for each of the stack units, the first memory chip and the second memory chip are stacked face-to-face, the second memory chip and the third memory chip are stacked back-to-back, and the third memory chip and the fourth memory chip are stacked face-to-face; the first redundant chip and the fourth memory chip in the adjacent stack unit are stacked back-to-back, and the first redundant chip and the second redundant chip are stacked face-to-face.

[0021] In some embodiments, the memory chip further comprises N driving circuits; the driving circuits are connected with the first connection port and the internal circuit of the memory chip, configured to transmit the signal of the first connection port into the internal circuit of the memory chip, and transmit the output signal of the internal circuit of the memory chip to the first connection port.

[0022] In some embodiments, the redundant chip further comprises N first driving circuits, N second driving circuits, and a gate circuit,

[0023] the first driving circuits are connected with the first connection port and the internal circuit of the redundant chip, configured to transmit the signal of the first connection port into the internal circuit of the redundant chip, and transmit the output signal of the internal circuit of the redundant chip to the first connection port; the second driving circuits are connected with the fourth connection port and the internal circuit of the redundant chip, configured to transmit the signal of the fourth connection port into the internal circuit of the redundant chip, and transmit the output signal of the internal circuit of the redundant chip to the fourth connection port; and the gate circuit is connected with the first driving circuit and the second driving circuit, configured to control the first driving circuit to be enabled and the second driving circuit to be disabled, or control the first driving circuit to be disabled and the second driving circuit to be enabled.

[0024] In some embodiments, in the chip stack structure: each of the memory chips is divided into at least four channels in the second direction in sequence; the first redundant chip is divided into at least four channels in the second direction in sequence; the second redundant chip is divided into at least four channels in the second direction in sequence; the number of channels of the memory chips, the first redundant chip, and the second redundant chip is the same;

[0025] The plurality of channels of the first redundant chip are respectively used for repairing the channels of the first memory chip and / or the channels of the fourth memory chip;

[0026] The plurality of channels of the second redundant chip are respectively used for repairing the channels of the second memory chip and / or the channels of the third memory chip.

[0027] In a second aspect, the embodiments of the present disclosure provide a preparation method for preparing the chip stack structure, the method comprising:

[0028] manufacture a plurality of to-be-processed chips by using the same process steps; the to-be-processed chips include N groups of the ports, N first driving circuits and N second driving circuits;

[0029] for part of the to-be-processed chips, the first driving circuit or the second driving circuit is enabled to generate the redundant chip;

[0030] for part of the to-be-processed chips, the metal connection line between the N second driving circuits and the fourth connection port is broken to generate the storage chip.

[0031] In a third aspect, the embodiments of the present disclosure provide a memory including the chip stack structure as described in the first aspect.

[0032] The embodiments of the present disclosure provide a chip stack structure, a preparation method and a memory, the chip stack structure including a plurality of storage chips and 2 redundant chips, capable of repairing 1 storage chip damage and 2 storage chip damage in part of scenarios, improving the overall stack yield. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 a schematic diagram of a chip stack structure provided by the embodiments of the present disclosure;

[0034] Figure 2 a cross-sectional schematic diagram of a storage chip and a redundant chip provided by the embodiments of the present disclosure;

[0035] Figure 3 a signal transmission schematic diagram of a chip stack structure provided by the embodiments of the present disclosure;

[0036] Figure 4 a cross-sectional schematic diagram of another chip provided by the embodiments of the present disclosure;

[0037] Figure 5 a schematic diagram of different signal transmission channels provided by the embodiments of the present disclosure;

[0038] Figure 6 a distribution schematic diagram of connection ports corresponding to the signal transmission channels provided by the embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the present disclosure. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the disclosure.

[0041] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which are shown, by way of illustration, embodiments for practicing the present disclosure. It is understood that other embodiments can be utilized and mechanical changes can be made without departing from the scope of the present disclosure.

[0042] It should be noted that the terms "first", "second", "third", etc. used in the embodiments of the present disclosure are only to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that the "first", "second", "third" can be interchanged in a specific order or sequence as long as it is allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0043] In particular, the drawings presented in the present disclosure do not mean the actual view of any specific microelectronic device or its components, but only idealized representation for describing the illustrative embodiments, so the drawings are not necessarily drawn to scale.

[0044] It should be noted that the semiconductor chip (such as the rewiring chip, the target redundancy chip, the storage chip mentioned later) can include a top surface at the front surface and a bottom surface at the back surface opposite to the front surface; in the case of ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g. perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as the first direction Z. The semiconductor chip includes a substrate, one side of the substrate close to the top surface of the semiconductor chip is the top surface of the substrate, and the other side of the substrate close to the bottom surface of the semiconductor chip is the bottom surface of the substrate, and the first direction Z is also perpendicular to the top surface of the substrate.

[0045] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0046] Referring to Figure 1 , a structural schematic diagram of a chip stack structure 10 provided by the embodiments of the present disclosure is shown. As Figure 1 shown, the chip stack structure 10 includes at least one stack unit stacked in the first direction; the stack unit includes a plurality of storage chips 11 stacked in the first direction, and the plurality of storage chips include a first storage chip 11_0, a second storage chip 11_1, a third storage chip 11_2, and a fourth storage chip 11_3. Each stack unit can also be regarded as a memory rank.

[0047] For Figure 1The chip stack structure 10 includes 12 memory chips 11 (only one possible example), divided into 3 stack units, addressed by stack ID (SID) of the memory chips 11, for example, the SID of the memory chips in the 1st stack unit 60 is 0, the SID of the memory chips in the 2nd stack unit 61 is 1, and the SID of the memory chips in the 3rd stack unit 62 is 2. The equally numbered memory chips in each stack unit share control signals, i.e., all first memory chips 11_0 share the same control signals, all second memory chips 11_1 share the same control signals, and so on.

[0048] As shown in Figure 1 , the chip stack structure 10 further includes a plurality of redundant chips 12, specifically, a first redundant chip 12_0 and a second redundant chip 12_1, and the stack ID (SID) of the first redundant chip 12_0 and the second redundant chip 12_1 can both be 3.

[0049] Whether it is a memory chip 11 or a redundant chip 12, it includes N port groups, N being a positive integer, please refer to Figure 2 (a), which shows a cross-sectional view of a memory chip 11; please refer to Figure 2 (b), which shows a cross-sectional view of a redundant chip 12. As shown in Figure 2 , each port group includes a first connection port 0, a second connection port 1, a third connection port 2, and a fourth connection port 3. It should be understood that Figure 2 only 4 port groups are shown for one chip in , but it does not constitute a relevant quantity limit.

[0050] Please refer to Figure 3 , which shows a connection diagram between different chips. In particular, since the placement and connection of the equally numbered memory chips 11 in different stack units are the same, Figure 3 only a diagram of one stack unit, the first redundant chip 12_0 and the second redundant chip 12_1 is shown.

[0051] As shown in Figure 3 , the first connection port 0 of the first memory chip 11_0 is connected to the first connection port 0 of the first redundant chip 12_0 at least via the non-first connection port 0 of the non-first memory chip stacked above;

[0052] The first connection port 0 of the second memory chip 11_1 is connected to the first connection port 0 of the second redundant chip 12_1 at least via the non-first connection port 0 of the non-second memory chip stacked above;

[0053] The first connection port 0 of the third storage chip 11_2 is connected to the fourth connection port 3 of the second redundancy chip 12_1 at least via the non-first connection port 0 of the non-third storage chip stacked above.

[0054] The first connection port 0 of the fourth storage chip 11_3 is connected to the fourth connection port 3 of the first redundancy chip 12_0 at least via the non-first connection port 0 of the non-fourth storage chip stacked above.

[0055] It is also to be noted that for each port group of each storage chip 11, only the first connection port 0 is connected to the internal circuit of the storage chip. Referring to (a) in FIG. 1, only the first connection port 0 is connected to the driving circuit 111, and the control signal is received or the data is sent only via the first connection port 0. Figure 2

[0056] For each port group of each redundancy chip 12, only one of the first connection port 0 and the fourth connection port 3 is connected to the internal circuit of the redundancy chip. Referring to (b) in FIG. 1, the first connection port 0 is connected to the first driving circuit 121, the fourth connection port 3 is connected to the second driving circuit 122, the control signal can be received or the data can be sent via the first connection port 0, or the control signal can be received or the data can be sent via the fourth connection port 3. Figure 2

[0057] Thus, for the storage chip, the first connection port 0 is electrically connected to the internal circuit of the storage chip, and the second connection port 1, the third connection port 2 and the fourth connection port 3 are electrically isolated from the internal circuit of the storage chip. Specifically, each storage chip 11 only obtains the required signal from the first connection port 0 of itself, and the second connection port 1, the third connection port 2 and the fourth connection port 3 are only "bypassed" from the first storage chip 11_0, but are not connected to the internal circuit of the first storage chip 11_0.

[0058] For the redundancy chip, the first connection port 0 and the fourth connection port 3 in the same repair group are selectively connected to the internal circuit of the redundancy chip, and the second connection port 1 and the third connection port 2 are isolated from the internal circuit of the redundancy chip.

[0059] Based on the above structure, the repair principle of the chip stacking structure 10 is as follows:

[0060] ​​(1) Assuming that the first storage chip 11_0 is damaged, the first connection port 0 of the first redundant chip 12_0 can be connected to the internal circuit of the redundant chip, at this time, the first redundant chip 12_0 receives the control signal originally for the first storage chip 11_0 via the first connection port 0, or replaces the first storage chip 11_0 to send data externally via the first connection port 0, so that the first redundant chip 12_0 can be used to repair the first storage chip 11_0.

[0061] (2) Assuming that the second storage chip 11_1 is damaged, the first connection port 0 of the second redundant chip 12_1 can be connected to the internal circuit of the redundant chip, at this time, the second redundant chip 12_1 receives the control signal originally for the second storage chip 11_1 via the first connection port 0, or replaces the second storage chip 11_1 to send data externally via the first connection port 0, so that the second redundant chip 12_1 can be used to repair the second storage chip 11_1.

[0062] (3) Assuming that the third storage chip 11_2 is damaged: the fourth connection port 3 of the second redundant chip 12_1 can be connected to the internal circuit of the redundant chip, at this time, the second redundant chip 12_1 receives the control signal originally for the third storage chip 11_2 via the fourth connection port 3, or replaces the third storage chip 11_2 to send data externally via the fourth connection port 3, so that the second redundant chip 12_1 can be used to repair the third storage chip 11_2.

[0063] (4) Assuming that the fourth storage chip 11_3 is damaged: the fourth connection port 3 of the first redundant chip 12_0 can be connected to the internal circuit of the redundant chip, at this time, the first redundant chip 12_0 receives the control signal originally for the fourth storage chip 11_3 via the fourth connection port 3, or replaces the fourth storage chip 11_3 to send data externally via the fourth connection port 3, so that the first redundant chip 12_0 can be used to repair the fourth storage chip 11_3.

[0064] In this way, for the chip stacking structure 10, although only the first redundant chip 12_0 and the second redundant chip 12_1 are added, the first redundant chip 12_0 can cope with the failure of the first storage chip 11_0 or the fourth storage chip 11_3, and the second redundant chip 12_1 can cope with the failure of the second storage chip 11_1 and the third storage chip 11_2, the number of redundant chips is small, the overall repair cost is small, and the thermal resistance of the overall chip stacking structure 10 is also smaller, which is beneficial to the improvement of heat dissipation performance and data transmission performance.

[0065] In some embodiments, for the first redundant chip 12_0:

[0066] (1) All port groups of the first redundant chip 12_0 are connected with the internal circuit of the redundant chip by the first connection port 0;

[0067] (2) All port groups of the first redundant chip 12_0 are connected with the internal circuit of the redundant chip by the fourth connection port 3;

[0068] For the second redundant chip 12_1:

[0069] (1) All port groups of the second redundant chip 12_1 are connected with the internal circuit of the redundant chip by the first connection port 0;

[0070] (2) All port groups of the second redundant chip 12_1 are connected with the internal circuit of the redundant chip by the fourth connection port 3.

[0071] Two repair scenarios of damaged storage chips are provided below.

[0072] In the first repair scenario, for the first redundant chip 12_0 and the second redundant chip 12_1, both are connected with the internal circuit of the redundant chip by the first connection port 0.

[0073] In this scenario, the first redundant chip 12_0 is used to repair any first storage chip 11_0, and the second redundant chip 12_1 is used to repair any second storage chip 11_1. Specifically, for each port group of the first redundant chip 12_0 and the second redundant chip 12_1, the first connection port 0 is connected with the internal circuit of the redundant chip; the second connection port 1, the third connection port 2, and the fourth connection port 3 are all electrically isolated from the internal circuit of the redundant chip.

[0074] In the second repair scenario, for the first redundant chip 12_0 and the second redundant chip 12_1, both are connected with the internal circuit of the redundant chip by the fourth connection port 3.

[0075] In this scenario, the first redundant chip 12_0 is used to repair any fourth storage chip 11_3, and the second redundant chip 12_1 is used to repair any third storage chip 11_2. Specifically, for each port group of the first redundant chip 12_0 and the second redundant chip 12_1, the fourth connection port 3 is connected with the internal circuit of the redundant chip; the first connection port 0, the second connection port 1, and the third connection port 2 are all electrically isolated from the internal circuit of the redundant chip.

[0076] As can be seen from the above two repair scenarios, the selected connection port numbers in the first redundant chip 12_0 and the second redundant chip 12_1 are the same, so the control is relatively simple, only the driving circuit corresponding to the same connection port needs to be set, which is conducive to reducing the area occupied by the driving circuit corresponding to the port group in the storage chip.

[0077] In addition, there is another specific repair scenario:

[0078] In the third repair scenario, for the first redundant chip 12_0 and the second redundant chip 12_1, one is connected with the redundant chip internal circuit through the first connection port 0, and the other is connected with the redundant chip internal circuit through the fourth connection port 3.

[0079] In this scenario, the first redundant chip 12_0 is used to repair any first storage chip 11_0, the second redundant chip 12_1 is used to repair any third storage chip 11_2, or the first redundant chip 12_0 is used to repair any fourth storage chip 11_3, and the second redundant chip 12_1 is used to repair any second storage chip 11_1. Specifically, for each port group of the first redundant chip 12_0, the first connection port 0 is connected with the redundant chip internal circuit; the second connection port 1, the third connection port 2 and the fourth connection port 3 are all electrically isolated from the redundant chip internal circuit; for each port group of the second redundant chip 12_1, the fourth connection port 3 is connected with the redundant chip internal circuit; the first connection port 0, the second connection port 1 and the third connection port 2 are all electrically isolated from the redundant chip internal circuit.

[0080] In some embodiments, referring to Figure 3 , a first connection port 0 of each first storage chip 11_0, a second connection port 1 of each second storage chip 11_1, a third connection port 2 of each third storage chip 11_2, a fourth connection port 3 of each fourth storage chip 11_3, a first connection port 0 of the first redundant chip 12_0, and a second connection port 1 of the second redundant chip 12_1 are aligned in the first direction Z and electrically connected to form a first signal path 40, which provides control signals for the first storage chip 11_0;

[0081] Referring to Figure 3 , a second connection port 1 of each first storage chip 11_0, a first connection port 0 of each second storage chip 11_1, a fourth connection port 3 of each third storage chip 11_2, a third connection port 2 of each fourth storage chip 11_3, a second connection port 1 of the first redundant chip 12_0, and a first connection port 0 of the second redundant chip 12_1 are aligned in the first direction Z and electrically connected to form a second signal path 41, which provides control signals for the second storage chip 11_1;

[0082] Referring to Figure 3A third connection port 2 of each first storage chip 11_0, a fourth connection port 3 of each second storage chip 11_1, a first connection port 0 of each third storage chip 11_2, a second connection port 1 of each fourth storage chip 11_3, a third connection port 2 of the first redundant chip 12_0, and a fourth connection port 3 of the second redundant chip 12_1 are aligned along the first direction Z and electrically connected to form a third signal path 42, which provides control signals for the third storage chip 11_2.

[0083] Please refer to Figure 3 A fourth connection port 3 of each first storage chip 11_0, a third connection port 2 of each second storage chip 11_1, a second connection port 1 of each third storage chip 11_2, a first connection port 0 of each fourth storage chip 11_3, a fourth connection port 3 of the first redundant chip 12_0, and a third connection port 2 of the second redundant chip 12_1 are aligned along the first direction Z and electrically connected to form a fourth signal path 43, which provides control signals for the fourth storage chip 11_3.

[0084] In this way, different storage chips 11 obtain control signals from the first connection port 0 of the storage chip itself, and the same mask can be used for manufacturing.

[0085] It should be noted that Figure 3 The same signal path includes a plurality of through silicon vias (i.e., through silicon vias TSVs corresponding to different storage chips) extending along the Z direction. In other embodiments, a spiral through silicon via stacking strategy can also be used. In this case, the projection positions of a plurality of through silicon vias corresponding to the same signal path in the same stacking unit are different in the horizontal direction and form a rectangle, and the projection positions of different through silicon vias in the same signal path in different stacking units are the same in the horizontal direction. The present application does not limit the stacking manner of different storage chips in the stacking unit and the stacking manner between different stacking units.

[0086] Please refer to Figure 3 Each chip has a first symmetry axis AA' and a second symmetry axis BB' which are symmetrical Figure 3 Only AA' and BB' of the first storage chip 11_0 and the first redundant chip 12_0 are shown. The first symmetry axis AA' passes through the center point of the top surface of the storage chip 11 and is parallel to the first side edge of the storage chip 11, and the second symmetry axis BB' passes through the center point of the top surface of the storage chip 11 and is parallel to the second side edge of the storage chip 11. The first side edge and the second side edge are adjacent side edges. The first side edge can be one of a long side and a short side, and the second side edge can be the other of the long side and the short side.

[0087] The distribution positions of the connection ports of the storage chip 11 and the redundant chip 12 are symmetrical about the first symmetry axis AA' and symmetrical about the second symmetry axis BB'.

[0088] In some embodiments, referring to Figure 3 , the different chips in the chip stack structure 10 are arranged in different manners, specifically:

[0089] (1) The first storage chip 11_0 and the second storage chip 11_1 are stacked face to face, and the positioning marks F of the two are respectively located on different sides of the first symmetry axis AA' and on the same side of the second symmetry axis BB'.

[0090] (2) The second storage chip 11_1 and the third storage chip 11_2 are stacked back to back, and the positioning marks F of the two are respectively located on both sides of the second symmetry axis BB' and on the same side of the first symmetry axis AA'.

[0091] (3) The third storage chip 11_2 and the fourth storage chip 11_3 are stacked face to face, and the positioning marks F of the two are respectively located on both sides of the first symmetry axis AA' and on the same side of the second symmetry axis BB'.

[0092] (4) The first redundant chip 12_0 and the fourth storage chip 11_3 in the adjacent stacked unit are stacked back to back;

[0093] (5) The first redundant chip 12_0 and the second redundant chip 12_1 are stacked face to face.

[0094] In Figure 2 , the positioning mark F of the first storage chip 11_0 is located at the lower right corner, the positioning mark F of the second storage chip 11_1 is located at the upper right corner, the positioning mark F of the third storage chip 11_2 is located at the upper left corner, and the positioning mark F of the fourth storage chip 11_3 is located at the lower left corner. The first redundant chip 12_0 and the first storage chip 11_0 are arranged in the same manner, and the positioning marks F are located at the same position; the second redundant chip 12_1 and the second storage chip 11_1 are arranged in the same manner, and the positioning marks F are located at the same position.

[0095] In the embodiments of the present disclosure, "stacked face to face" means that the top surfaces of the two chips are close to each other along the first direction Z, and the bottom surfaces of the two chips are away from each other along the first direction Z. "Stacked back to back" means that the top surfaces of the two chips are away from each other along the first direction Z, and the bottom surfaces of the two chips are close to each other along the first direction Z.

[0096] It should be understood that Figure 3For a specific example, the storage chips 11 have flexibility in their placement, such as swapping the first storage chip 11_0 and the third storage chip 11_2, swapping the second storage chip 11_1 and the fourth storage chip 11_3. The redundant chips 12 also have flexibility in their placement, such as the first redundant chip 12_0 and the third storage chip 11_2 having the same placement, the second redundant chip 12_1 and the fourth storage chip 11_3 having the same placement, and so on.

[0097] In some embodiments, referring to (a) in Figure 2 , the storage chips 11 further comprise N driving circuits 111;

[0098] The driving circuit 111 is connected with a first connection port 0 and the internal circuit of the storage chip, and is configured to transmit the signal of the first connection port 0 into the internal circuit of the storage chip, and transmit the output signal of the internal circuit of the storage chip to the first connection port 0.

[0099] In some embodiments, referring to (b) in Figure 2 , the redundant chips 12 further comprise N first driving circuits 121, N second driving circuits 122, and a gate circuit;

[0100] The first driving circuit 121 is connected with a first connection port 0 and the internal circuit of the redundant chip, and is configured to transmit the signal of the first connection port 0 into the internal circuit of the redundant chip, and transmit the output signal of the internal circuit of the redundant chip to the first connection port 0;

[0101] The second driving circuit 122 is connected with a fourth connection port 3 and the internal circuit of the redundant chip, and is configured to transmit the signal of the fourth connection port 3 into the internal circuit of the redundant chip, and transmit the output signal of the internal circuit of the redundant chip to the fourth connection port 3;

[0102] The gate circuit is connected with the first driving circuit 121 and the second driving circuit 122, and is configured to control the first driving circuit 121 to be enabled and control the second driving circuit 122 to be disabled, or control the first driving circuit 121 to be disabled and control the second driving circuit 122 to be enabled.

[0103] Here, the gate circuit is not shown in Figure 2 , but can be implemented via devices such as multiplexers, fuses, and anti-fuses.

[0104] (1) If the gate circuit uses a multiplexer, the control end of the multiplexer receives a repair indication signal, and the repair indication signal indicates that one of the first driving circuit and the second driving circuit is enabled.

[0105] (2) If the gate circuit uses a fuse, the corresponding fuse structure can be melted in advance by laser, so that one of the first driving circuit and the second driving circuit is enabled.

[0106] In some embodiments, as shown in FIG. 1, in the chip stack structure 10: Figure 1

[0107] (1) The first storage chip 11_0 is divided into at least four channels, CH0, CH1, CH14 and CH15, in sequence along the second direction X.

[0108] (2) The second storage chip 11_1 is divided into at least four channels, CH4, CH5, CH10 and CH11, in sequence along the second direction X.

[0109] (3) The third storage chip 11_2 is divided into at least four channels, CH8, CH9, CH6 and CH7, in sequence along the second direction X.

[0110] (4) The fourth storage chip 11_3 is divided into at least four channels, CH12, CH13, CH2 and CH3, in sequence along the second direction X.

[0111] (5) The redundant chip 12 is divided into at least four channels in sequence along the second direction X. The number of channels of the redundant chip 12 is the same as that of the storage chip 11.

[0112] It should be further noted that the chip stack structure further includes a logic chip 13, and the logic chip 13 records a stack position identification code (SID) of each chip. In the repair process, a new mapping relationship needs to be generated in the logic chip 13 to map the subsequent externally input stack position identification code to the stack position identification code of the repaired storage chip, so as to operate the correct storage chip (the repaired storage chip).

[0113] In addition, a fuse is arranged in the logic chip 13 to record the repair state of the first redundant chip 12_0 and the second redundant chip 12_1. An optional example is as follows:

[0114] (1) In the case where the fuse state is 0, the first redundant chip 12_0 is used to repair the first storage chip 11_0, and the channels therein are CH0, CH1, CH14 and CH15 in sequence; the second redundant chip 12_1 is used to repair the second storage chip 11_1, and the four channels are CH4, CH5, CH10 and CH11 in sequence.

[0115] ​(2) When the fuse state is 1, the first redundant chip 12_0 is used to repair the fourth memory chip 11_3, and the four channels are CH12, CH13, CH2 and CH3 in sequence; the second redundant chip 12_1 is used to repair the third memory chip 11_2, and the four channels are CH8, CH9, CH6 and CH7 in sequence.

[0116] (3) When the fuse state is 2, the first redundant chip 12_0 is used to repair the first memory chip 11_0, and the channels therein are CH0, CH1, CH14 and CH15 in sequence; the second redundant chip 12_1 is used to repair the third memory chip 11_2, and the four channels are CH8, CH9, CH6 and CH7 in sequence.

[0117] (2) When the fuse state is 3, the first redundant chip 12_0 is used to repair the fourth memory chip 11_3, and the four channels are CH12, CH13, CH2 and CH3 in sequence; the second redundant chip 12_1 is used to repair the second memory chip 11_1, and the four channels are CH4, CH5, CH10 and CH11 in sequence.

[0118] In this way, during the power-on process, the fuse in the logic chip 13 broadcasts to the redundant chip, which determines whether to enable the first connection port 0 or the fourth connection port 3, and thus determines which two memory chips the redundant chip will repair.

[0119] It should be noted that, since both arbitrary memory chips and redundant chips contain multiple relatively independent channels, and the number of independent channels in a memory chip is the same as the number of independent channels in a redundant chip (e.g., Figure 1 (As shown in the four examples), therefore, the damaged channels repaired by different channels in the first redundant chip are not necessarily located in the same memory chip; the damaged channels may be arbitrarily distributed on the first memory chip 11_0 and the fourth memory chip 11_3. Similarly, the damaged channels repaired by different channels in the second redundant chip are not necessarily located in the same memory chip; the damaged channels may be arbitrarily distributed on the second memory chip 11_1 and the third memory chip 11_2. That is to say, in actual repair, the memory chip as a whole is not used as the unit, but rather the channels within the memory chip and the redundant chip are used as the unit. Within the same memory chip, some channels may be damaged and repaired, while the remaining channels are not damaged and do not need to be repaired. In actual access, it is only necessary to map the stacking position flag code of the damaged channels to the stacking position flag code of the first and second redundant chips; the undamaged channels do not need to be mapped to the stacking position flag code.

[0120] Specifically:

[0121] (1) The plurality of channels of the first redundancy chip 12_0 are respectively used to repair the channels of the first storage chip 11_0 and / or the channels of the fourth storage chip 11_3. At this time, a part of the port groups of the first redundancy chip 12_0 are connected with the internal circuit of the redundancy chip by the first connection port 0, and another part of the port groups are connected with the internal circuit of the redundancy chip by the fourth connection port 3.

[0122] For example, the 4 channels of the first redundancy chip 12_0 are used to repair CH0, CH1 (the first connection port 0 in the corresponding channel is connected with the internal circuit of the redundancy chip) of the first storage chip 11_0 and CH2, CH3 (the fourth connection port 3 in the corresponding channel is connected with the internal circuit of the redundancy chip) of the fourth storage chip 11_3 in turn.

[0123] (2) The plurality of channels of the second redundancy chip 12_1 are respectively used to repair the channels of the second storage chip 11_1 and / or the channels of the third storage chip 11_2. At this time, a part of the port groups of the second redundancy chip 12_1 are connected with the internal circuit of the redundancy chip by the first connection port 0, and another part of the port groups are connected with the internal circuit of the redundancy chip by the fourth connection port 3.

[0124] For example, the 4 channels of the second redundancy chip 12_1 are used to repair CH4, CH5 (the first connection port 0 in the corresponding channel is connected with the internal circuit of the redundancy chip) of the second storage chip 11_1 and CH6, CH7 (the fourth connection port 3 in the corresponding channel is connected with the internal circuit of the redundancy chip) of the third storage chip 11_2 in turn.

[0125] Figure 4 The cross-sectional schematic diagram of the storage chip 11 and the redundancy chip 12 is shown, wherein the channel numbers of the first storage chip 11_0 are temporarily labeled.

[0126] As shown in Figure 4 Each channel has a third symmetry axis CC' extending along the third direction Y, and the distribution positions of the connection ports in the channel are symmetrical about the first symmetry axis AA' and the third symmetry axis CC'. For the first storage chip 11_0, the connection ports of the channel CH_0 and the channel CH_15 are mirror symmetrical, the connection ports of the channel CH_1 and the channel CH_14 are mirror symmetrical, and the other chips also have similar symmetrical characteristics.

[0127] Please refer to Figure 5 , which shows four signal paths in the chip stacking structure 10, respectively CH0, CH4, CH8 and CH12 provide control signals. Figure 6 In the Figure 5 , the distribution positions of the connection ports corresponding to the four signal paths in the chip, Figure 6 The connection ports filled with shadows in the are aligned along the first direction Z.

[0128] (1) For Figure 5 The first signal path 40 shown is formed by connecting the first connection port 0 of the first memory chip 11_0, the second connection port 1 of the second memory chip 11_1, the third connection port 2 of the third memory chip 11_2, the fourth connection port 3 of the fourth memory chip 11_3, ... the first connection port 0 of the first redundant chip 12_0 and the second connection port 1 of the second redundant chip 12_1 from bottom to top, and transmits control signals for CH0;

[0129] (2) For Figure 5 The second signal path 41 shown is formed by connecting the second connection port 1 of the first memory chip 11_0, the first connection port 0 of the second memory chip 11_1, the fourth connection port 3 of the third memory chip 11_2, the third connection port 2 of the fourth memory chip 11_3, ... the second connection port 1 of the first redundant chip 12_0 and the first connection port 0 of the second redundant chip 12_1 from bottom to top, and transmits the control signal for CH4;

[0130] (3) For Figure 5 The third signal path 42 shown is formed by connecting the third connection port 2 of the first memory chip 11_0, the fourth connection port 3 of the second memory chip 11_1, the first connection port 0 of the third memory chip 11_2, the second connection port 1 of the fourth memory chip 11_3, ... the third connection port 2 of the first redundant chip 12_0 and the fourth connection port 3 of the second redundant chip 12_1 from bottom to top, and transmits control signals for CH8;

[0131] (4) For Figure 5 The fourth signal path 43 shown is formed by connecting the fourth connection port 3 of the first memory chip 11_0, the third connection port 2 of the second memory chip 11_1, the second connection port 1 of the third memory chip 11_2, the first connection port 0 of the fourth memory chip 11_3, ... the fourth connection port 3 of the first redundant chip 12_0 and the third connection port 2 of the third redundant chip from bottom to top, and transmits control signals for CH12.

[0132] At the same time, from Figure 5 As can be seen from the diagram, the memory chip only has its first connection port 0 connected to the drive circuit 111; while the redundant chip has its first connection port 0 connected to the first drive circuit 121, and its fourth connection port 3 connected to the second drive circuit 122, thus allowing selection of which connection port to receive the control signal from.

[0133] like Figure 5As shown, assuming that the redundant chips are all enabled by the first driving circuit 121, the first redundant chip 12_0 receives the control signal for CH0 via the first signal path 40, and the second redundant chip 12_1 receives the control signal for CH4 via the second signal path 41; conversely, assuming that the redundant chips are all enabled by the second driving circuit 122, the first redundant chip 12_0 receives the control signal for CH12 via the fourth signal path 43, and the second redundant chip 12_1 receives the control signal for CH8 via the third signal path 42.

[0134] The chip stack structure 10 described above can be, for example, a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a Synchronous Dynamic Random Access Memory (SDRAM), a Double Data Rate SDRAM (DDR SDRAM), etc., which is not specifically limited herein.

[0135] In the foregoing example, the chip stack structure 10 includes 12 memory chips and 2 redundant chips, but the number of memory chips can also be 4, 8, 16, 20, 24, etc., and the number of redundant chips can also be 2. On the one hand, the number of redundant chips is not large, and has little impact on heat dissipation, etc.; on the other hand, 2 redundant chips can repair 1 memory chip damage and 2 memory chip damage in some scenarios, improving the overall stack yield.

[0136] In another embodiment of the present disclosure, a preparation method is provided for preparing the chip stack structure 10 described above, which includes the following steps:

[0137] S71: manufacturing a plurality of to-be-processed chips using the same process steps; the to-be-processed chips include N port groups, N first driving circuits, and N second driving circuits;

[0138] Here, one end of the first driving circuit is connected to the first connection port, and the other end of the first driving circuit is connected to the internal circuit of the to-be-processed chip; one end of the second driving circuit is connected to the second connection port, and the other end of the first driving circuit is connected to the internal circuit of the to-be-processed chip.

[0139] S72: for some of the to-be-processed chips, enabling the first driving circuit or the second driving circuit to generate a redundant chip.

[0140] S73: For the part of the chip to be processed, break the metal connection line between the N second driving circuits and the fourth connection port 3, to generate a storage chip.

[0141] In this way, the storage chip and the redundant chip can be manufactured by the same process, that is, the first connection port 0 and the fourth connection port 3 in both of them are provided with corresponding driving circuits, and for the storage chip, the metal connection line between the fourth connection port 3 and the driving circuit is additionally broken, so that it is not necessary to design two separate manufacturing processes, which is beneficial to mass production.

[0142] In still another embodiment of the present disclosure, a memory is provided, which includes the chip stack structure 10 of the foregoing embodiments.

[0143] For details not disclosed in the embodiments of the present disclosure, reference can be made to the description of the foregoing embodiments.

[0144] The above merely describes preferred embodiments of the present disclosure, but is not intended to limit the protection scope of the present disclosure.

[0145] It should be noted that in the present disclosure, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive containing, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a…" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0146] The above-mentioned sequence numbers of the embodiments of the present disclosure are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0147] The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method embodiments.

[0148] The features disclosed in the several product embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new product embodiments.

[0149] The features disclosed in the several method or device embodiments provided by the present disclosure can be combined arbitrarily without conflict, to obtain new method or device embodiments.

[0150] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A chip stack structure, characterized by, The chip stack structure comprises at least one stack unit and a plurality of redundant chips stacked in sequence along a first direction; the stack unit comprises a plurality of memory chips stacked in sequence along the first direction, the plurality of memory chips comprising a first memory chip, a second memory chip, a third memory chip and a fourth memory chip; the plurality of redundant chips comprises a first redundant chip and a second redundant chip; Each of the memory chips and the redundant chips comprises N port groups, each of the port groups comprising a first connection port, a second connection port, a third connection port and a fourth connection port; N is a positive integer; The first connection port of the first memory chip is connected to the first connection port of the first redundant chip at least via the non-first connection port of the non-first memory chip stacked above; The first connection port of the second memory chip is connected to the first connection port of the second redundant chip at least via the non-first connection port of the non-second memory chip stacked above; The first connection port of the third memory chip is connected to the fourth connection port of the second redundant chip at least via the non-first connection port of the non-third memory chip stacked above; The first connection port of the fourth memory chip is connected to the fourth connection port of the first redundant chip at least via the non-first connection port of the non-fourth memory chip stacked above; or, the first connection port of the fourth memory chip is connected to the fourth connection port of the first redundant chip; For each of the port groups of each of the memory chips, only the first connection port is connected to the internal circuit of the memory chip; for each of the port groups of each of the redundant chips, only one of the first connection port and the fourth connection port is connected to the internal circuit of the redundant chip.

2. The chip stack structure according to claim 1, wherein All of the port groups of the first redundant chip are connected to the internal circuit of the redundant chip by using the first connection port; Or, all of the port groups of the first redundant chip are connected to the internal circuit of the redundant chip by using the fourth connection port; Or, part of the port groups of the first redundant chip are connected to the internal circuit of the redundant chip by using the first connection port, and the other part of the port groups are connected to the internal circuit of the redundant chip by using the fourth connection port; All of the port groups of the second redundant chip are connected to the internal circuit of the redundant chip by using the first connection port; Or, all of the port groups of the second redundant chip are connected to the internal circuit of the redundant chip by using the fourth connection port; Or, part of the port groups of the second redundant chip are connected to the internal circuit of the redundant chip by using the first connection port, and the other part of the port groups are connected to the internal circuit of the redundant chip by using the fourth connection port.

3. The chip stack structure according to claim 1 or 2, wherein The first redundant chip is used for repairing any first memory chip, and the second redundant chip is used for repairing any second memory chip; or The first redundant chip is used for repairing any fourth memory chip, and the second redundant chip is used for repairing any third memory chip.

4. The chip stack structure of claim 1, wherein, in the case that the first redundant chip is used to repair any of the first memory chips and the second redundant chip is used to repair any of the second memory chips: for each of the port groups of the first redundant chip and the second redundant chip, the first connection port is connected with the internal circuit of the redundant chip; the second connection port, the third connection port and the fourth connection port are all electrically isolated from the internal circuit of the redundant chip; in the case that the first redundant chip is used to repair any of the fourth memory chips and the second redundant chip is used to repair any of the third memory chips: for each of the port groups of the first redundant chip and the second redundant chip, the fourth connection port is connected with the internal circuit of the redundant chip; the first connection port, the second connection port and the third connection port are all electrically isolated from the internal circuit of the redundant chip.

5. The chip stack structure of claim 1, wherein, a first connection port of each of the first memory chips, a second connection port of each of the second memory chips, a third connection port of each of the third memory chips, a fourth connection port of each of the fourth memory chips, a first connection port of the first redundant chip, a second connection port of the second redundant chip are aligned in a first direction and electrically connected to form a signal path; a second connection port of each of the first memory chips, a first connection port of each of the second memory chips, a fourth connection port of each of the third memory chips, a third connection port of each of the fourth memory chips, a second connection port of the first redundant chip, a first connection port of the second redundant chip are aligned in a first direction and electrically connected to form a signal path; a third connection port of each of the first memory chips, a fourth connection port of each of the second memory chips, a first connection port of each of the third memory chips, a second connection port of each of the fourth memory chips, a third connection port of the first redundant chip, a fourth connection port of the second redundant chip are aligned in a first direction and electrically connected to form a signal path; a fourth connection port of each of the first memory chips, a third connection port of each of the second memory chips, a second connection port of each of the third memory chips, a first connection port of each of the fourth memory chips, a fourth connection port of the first redundant chip, a third connection port of the second redundant chip are aligned in a first direction and electrically connected to form a signal path.

6. The chip stack structure of claim 1, wherein, for each of the stack units, the first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face. The first redundant chip and the fourth storage chip in the adjacent stacked unit are stacked back-to-back, and the first redundant chip and the second redundant chip are stacked face-to-face.

7. The chip stack structure of claim 1, wherein, The storage chip further comprises N driving circuits; The driving circuit is connected with the first connection port and the internal circuit of the storage chip, configured to transmit the signal of the first connection port into the internal circuit of the storage chip; and transmit the output signal of the internal circuit of the storage chip to the first connection port.

8. The chip stack structure of claim 3, wherein, The redundant chip further comprises N first driving circuits, N second driving circuits and a gate circuit, The first driving circuit is connected with the first connection port and the internal circuit of the redundant chip, configured to transmit the signal of the first connection port into the internal circuit of the redundant chip; And transmit the output signal of the internal circuit of the redundant chip to the first connection port; The second driving circuit is connected with the fourth connection port and the internal circuit of the redundant chip, configured to transmit the signal of the fourth connection port into the internal circuit of the redundant chip; And transmit the output signal of the internal circuit of the redundant chip to the fourth connection port; The gate circuit is connected with the first driving circuit and the second driving circuit, configured to control the first driving circuit to be enabled and control the second driving circuit to be disabled; or control the first driving circuit to be disabled and control the second driving circuit to be enabled.

9. The chip stack structure of claim 1, wherein, In the chip stacking structure: Each of the storage chips is divided into at least four channels in the second direction in turn; The first redundant chip is divided into at least four channels in the second direction in turn; The second redundant chip is divided into at least four channels in the second direction in turn; The number of channels of the storage chip, the first redundant chip and the second redundant chip is the same; The channels of the first redundant chip are respectively used for repairing the channels of the first storage chip and / or the channels of the fourth storage chip; The channels of the second redundant chip are respectively used for repairing the channels of the second storage chip and / or the channels of the third storage chip.

10. A method of manufacturing the chip stack structure according to claim 8, wherein The method comprises: Manufacturing a plurality of to-be-processed chips by using the same process steps; the to-be-processed chip comprises N port groups, N first driving circuits and N second driving circuits; For part of the to-be-processed chips, the first driving circuit or the second driving circuit is selected to generate the redundant chip; For part of the to-be-processed chips, the metal connection line between the N second driving circuits and the fourth connection port is broken to generate the storage chip.

11. A memory, comprising: The memory comprises the chip stacking structure according to any one of claims 1-9.

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