Synchronous drive and timing lock control circuit and power module of magnetic latching relay

Abstract

The present application relates to the technical field of magnetic latching relay, in particular to a synchronous driving and timing locking control circuit and power module of a magnetic latching relay, comprising a power module for connecting with BMS to output a trigger signal; a timing module for converting a long-level trigger signal into a short-time single pulse and transmitting the short-time single pulse to a driving module; a locking module for outputting an enable signal to control the on-off of the electrical loop of the driving module; and the driving module for driving the magnetic latching relay in response to the enable signal provided by the locking module and the short-time single pulse provided by the timing module at the same time, which solves the dilemma of high standby power consumption of ordinary relays and long on-off of magnetic relays.

Description

Technical Field

[0001] This invention relates to the field of magnetic latching relay technology, specifically to a synchronous drive and timing latching control circuit and power module for a magnetic latching relay. Background Technology

[0002] In the power modules of DC charging piles for new energy vehicles, the contactor must automatically disconnect and remain de-energized after a set period of time, while meeting stringent requirements for zero standby power consumption, high vibration resistance, and long lifespan. Traditional electromagnetic relays have a monostable structure, requiring continuous coil energization to maintain engagement. They consume 2 W to 4 W of static power, experience rapid temperature rise and insulation aging under long-term excitation, and are prone to power loss and reset during grid fluctuations. They cannot provide a "memory" function and no longer meet the new energy-saving and safety standards for charging piles.

[0003] Magnetic latching relays (commonly known as magnetic relays) utilize permanent magnets to achieve bistable self-locking. They require only a short pulse of less than 100 ms to switch contacts, and retain power after de-energization due to the permanent magnet force. Static power consumption is zero, and contact life and vibration resistance are superior to ordinary relays. Therefore, they are increasingly used in timed tripping, security access control, and charging contactor applications. However, magnetic relay pulse coils are designed with high current density (>20 A / mm²). Continuous energization for 10 seconds can raise the coil temperature to over 150°C, causing demagnetization of the permanent magnet and a decrease in holding force of over 30%. This makes the contacts prone to accidental flipping under external vibration or short-circuit electrodynamic forces, creating a safety hazard. Therefore, datasheets explicitly limit the "maximum energization time to ≤100 ms." This means that they cannot be continuously energized like ordinary relays, nor can they be simply driven by power frequency pulses; otherwise, poor timing accuracy, low contact synchronization, and a series of new problems will arise, such as concentrated arcing after sequential power-off and reverse high voltage breakdown of the driver chip.

[0004] In summary, the industry urgently needs a hardware solution that combines "zero-power self-locking" with "short-time pulse excitation". Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a synchronous drive and timing lockout control circuit and power module for a magnetic latching relay. Under the premise of not being continuously powered on, it can achieve settable timing and reduce contact synchronization error, thereby solving the dilemma of high standby power consumption of ordinary relays and the inability of magnetic relays to be continuously powered on.

[0006] To achieve the above objectives / to solve the above technical problems, the present invention is implemented using the following technical solution:

[0007] In a first aspect, the present invention provides a synchronous drive and timing latching control circuit for a magnetic latching relay, comprising:

[0008] A power module is used to connect to the BMS and output trigger signals. The power module is electrically connected to the timing module, the drive module, and the locking module respectively.

[0009] The timing module is used to convert long-level trigger signals into short-time single pulses and transmit them to the driver module.

[0010] A locking module, which is connected to the drive module, is used to output an enable signal to control the on / off state of the electrical circuit of the drive module;

[0011] The drive module is used to drive the magnetic latching relay in response to both the enable signal provided by the latching module and the short single pulse provided by the timing module.

[0012] In conjunction with the first aspect, optionally, the drive module includes a control stage circuit and a power stage circuit;

[0013] A control-level circuit is used to respond to the short-duration single pulse output by the timing module;

[0014] The power stage circuit is electrically connected to the control stage circuit and the locking module;

[0015] The locking module controls the on / off state of the electrical circuit of the power stage circuit through the enable signal to form a controlled drive circuit.

[0016] The control stage circuit responds to the short-time single pulse and controls the power stage circuit to inject drive pulse current into the magnetic latching relay coil when the controlled drive circuit is turned on.

[0017] Furthermore, the current path in the control stage circuit is isolated from the drive pulse current path flowing through the power stage circuit and the magnetic latching relay coil.

[0018] In conjunction with the first aspect, optionally, a protection module is also included, which is connected in parallel with the coil of the magnetic latching relay for absorbing and clamping voltage spikes.

[0019] In conjunction with the first aspect, optionally, the power module includes resistor R5 and resistor R7, with resistor R4 connected in parallel across resistor R5 and resistor R6 connected in parallel across resistor R7. One end of resistor R5 is connected to the positive power output terminal of the BMS, and the other end of resistor R5 is connected to the timing module. One end of resistor R7 is connected to the negative power output terminal of the BMS, and the other end of resistor R7 is connected to the timing module.

[0020] In conjunction with the first aspect, optionally, the timing module includes a first timing unit and then a second timing unit with the same structure. The first timing unit includes a resistor R813, one end of which is connected to the other end of a resistor R5, and the other end of which is connected to the anode of a switching diode D57. The cathode of the switching diode D57 is connected to the other end of a resistor R7. A switching diode D101 and a resistor R814 are connected in parallel across two ends of a TVS diode D2. A capacitor C2 and a capacitor C3 are connected in parallel across two ends of a capacitor C94. The anode of the TVS diode D2 is connected to the other end of a resistor R5, and the cathode of the TVS diode D2 is connected to one end of a capacitor C94. The other end of the capacitor C94 is connected to the anode of the switching diode D57.

[0021] In conjunction with the first aspect, optionally, the latching module includes an optocoupler OT6 and an optocoupler OT4. The first pin of the optocoupler OT6 is connected to a 5V power supply via a resistor R100. The second pin of the optocoupler OT6 is connected to the first pin of the optocoupler OT4. The second pin of the optocoupler OT4 is connected to the collector of a transistor Q70. The base of the transistor Q70 is connected to the DSP output signal terminal via a resistor R101. The emitter of the transistor Q70 is grounded. A resistor R102 is connected in parallel between the base and emitter of the transistor Q70. A resistor R831 is connected in parallel between the fourth and third pins of the optocoupler OT6. The fourth and third pins of the optocoupler OT6 are respectively connected to the drive module. A resistor R823 is connected in parallel between the fourth and third pins of the optocoupler OT4. The fourth and third pins of the optocoupler OT6 are respectively connected to the drive module.

[0022] In conjunction with the first aspect, optionally, the power stage circuit of the drive module includes MOSFETs Q13 and Q15. The conduction and turn-off of MOSFETs Q13 and Q15 are directly controlled by the enable signal of the latching module to turn on or off the controlled drive circuit. The control stage circuit of the drive module includes MOSFETs Q21 and Q18. MOSFETs Q21 and Q18 respond to the short-time single pulse output by the timing module and control the gate voltages of MOSFETs Q15 and Q13 respectively. The gate of MOSFET Q13 is connected to the fourth pin of optocoupler OT6. The gate of MOSFET Q13 is also connected to the drain of MOSFET Q18 after passing through switching diode D154 and resistor R830. The gate of MOSFET Q18 is connected to the second timing module. In the time unit connection, the source of MOSFET Q18 is connected to the source of MOSFET Q15 through resistor R2. The source of MOSFET Q13 is connected to the third pin of optocoupler OT6. The source of MOSFET Q13 is also connected to the source of MOSFET Q21 through resistor R3. The gate of MOSFET Q21 is connected to one end of capacitor C94. The drain of MOSFET Q21 is connected to the gate of MOSFET Q15 through resistor R819 and switching diode D165. The drain of MOSFET Q13 is connected to the first drive input terminal of magnetic latching relay. The drain of MOSFET Q15 is connected to the second drive input terminal of magnetic latching relay. The gate of MOSFET Q15 is also connected to the fourth pin of optocoupler OT4. The source of MOSFET Q15 is also connected to the third pin of optocoupler OT4.

[0023] In conjunction with the first aspect, optionally, the protection module includes a resistor R1 and a capacitor C1, wherein the resistor R1 and the capacitor C1 are connected in series to form an RC absorption branch, and the RC absorption branch and the TVS diode D1 are both connected in parallel across the coil of the magnetic latching relay.

[0024] In a second aspect, the present invention provides a power module including a synchronous drive and timing latching control circuit for a magnetic latching relay as described in any one of the first aspects.

[0025] Compared with the prior art, the beneficial effects achieved by the present invention are as follows:

[0026] 1) This application controls the on / off state of the electrical circuit of the drive module by setting the enable signal output of the latching module. At the same time, the drive module responds to the enable signal provided by the latching module and the short single pulse provided by the timing module to drive the magnetic latching relay. This enables the hardware AND logic interconnection between the DPS request signal and the BMS status signal. The subsequent drive transistor is only enabled when the DPS is allowed and the BMS is fault-free, thus completely blocking external false triggering. The timing module converts the long-level trigger signal into a short single pulse and transmits it to the drive module, achieving a settable time and preventing the magnetic latching relay from being continuously turned on. The enable signal of the latching module opens the L-type push-pull stage of the drive module, and the timing module injects a bipolar pulse into the coil instantaneously, reducing the synchronization error of the magnetic latching relay contacts.

[0027] 2) This application designs the drive module as a control-level circuit and a power-level circuit, separating the control function from the power switching function. This allows the MOSFETs in the control-level circuit to function only as control signal processing elements and not carry large currents, resulting in minimal power loss. This reduces the overall circuit power consumption, simplifies thermal management, and improves energy efficiency. At the same time, it keeps the control elements away from high-current paths, reducing electrical stress and failure rate. The current in the drive circuit forms a complete pulse current path through the power-level circuit without passing through the control-level circuit. Furthermore, the timing module achieves rapid cutoff of the pulse current path through the control-level circuit, thus ensuring synchronous switching of the power-level circuit. This reduces contact arcing and further reduces the synchronization error between the contacts of the magnetic latching relay. Attached Figure Description

[0028] Figure 1 This is the circuit diagram of the present invention;

[0029] Reference numerals in the attached diagram: 1 is the power supply module; 2 is the timing module; 3 is the drive module; 4 is the protection module; 5 is the locking module. Detailed Implementation

[0030] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations thereof. In the absence of conflict, the embodiments and technical features in the embodiments can be combined with each other.

[0031] In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order of the technical features indicated.

[0032] In the description of this invention, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0033] Example 1:

[0034] like Figure 1 As shown, the present invention provides a synchronous drive and timing latching control circuit for a magnetic latching relay, comprising:

[0035] The power supply module is used to connect to the BMS and output trigger signals. The power supply module is electrically connected to the timing module, drive module and latching module respectively.

[0036] In some embodiments, the power module includes a voltage divider network and a current limiting circuit for receiving positive and negative trigger signals provided by the BMS and safely transmitting the trigger signals to the timing module to provide a stable input source; specifically, such as Figure 1 As shown, the power module includes resistors R5 and R7. Resistor R4 is connected in parallel across resistor R5, and resistor R6 is connected in parallel across resistor R7. One end of resistor R5 is connected to the positive power output terminal of the BMS, and the other end of resistor R5 is connected to the timing module. One end of resistor R7 is connected to the negative power output terminal of the BMS, and the other end of resistor R7 is connected to the timing module. In one illustrative embodiment, the positive and negative power supplies of the BMS are connected to ±12V trigger signals.

[0037] The timing module is used to convert the long-level trigger signal into a short-time single pulse and transmit it to the drive module. After passing through the RC monostable network, the 12V trigger signal of the power supply module is converted into a single pulse of fixed width. In one embodiment, the RC monostable network adopts an 80ms time constant.

[0038] In some embodiments, the timing module includes a first timing unit and a second timing unit symmetrically arranged. Each timing unit includes an RC delay circuit and a voltage clamping circuit, used to convert a long-level trigger signal into a short-time single pulse of fixed width, and to set the drive time constant through the RC delay circuit to ensure the accuracy of the pulse width. Specifically, as shown... Figure 1As shown, the first timing unit includes a resistor R813, one end of which is connected to the other end of a resistor R5, and the other end of which is connected to the anode of a switching diode D57. The cathode of the switching diode D57 is connected to the other end of a resistor R7. A switching diode D101 and a resistor R814 are connected in parallel across the two ends of a TVS diode D2. A capacitor C2 and a capacitor C3 are connected in parallel across the two ends of a capacitor C94. The anode of the TVS diode D2 is connected to the other end of a resistor R5, and the cathode of the TVS diode D2 is connected to one end of a capacitor C94. The other end of a capacitor C94 is connected to the anode of the switching diode D57. In the above circuit, the resistor R814, the capacitor C94, and the switching diode D57 constitute an RCD delay circuit. The switching diode D101 is an accelerating discharge diode, and the resistor R813 is a capacitor discharge resistor. Similarly, the second timing unit includes a resistor R828, one end of which is connected to the other end of a resistor R7, and the other end of which is connected to the anode of a switching diode D135. The cathode of the switching diode D135 is connected to the other end of a resistor R5. A switching diode D102 and a resistor R829 are connected in parallel across two ends of a TVS diode D3. A capacitor C4 and a capacitor C5 are connected in parallel across two ends of a capacitor C102. The anode of the TVS diode D3 is connected to the other end of a resistor R7, and the cathode of the TVS diode D3 is connected to one end of a capacitor C102. The other end of a capacitor C102 is connected to the anode of the switching diode D135.

[0039] The latching module is connected to the drive module and is used to output an enable signal to control the on / off state of the drive module's electrical circuit. The DPS request signal and BMS status signal are interconnected by hardware AND logic. The subsequent drive transistor is enabled only when the DPS is allowed and the BMS is fault-free, thus completely blocking external false triggering.

[0040] In some embodiments, the latching module includes an isolating switch circuit and a logic control circuit, controlled by an external DSP signal, for outputting an enable signal; the output terminal of the latching module is connected to the drive module to directly control the on / off state of the electrical circuit of the drive module through the enable signal, thereby forming a controlled drive circuit, wherein the drive circuit is fully conductive only when the enable signal is valid, such as... Figure 1As shown, the latching module includes optocoupler OT6 and optocoupler OT4. The first pin of optocoupler OT6 is connected to a 5V power supply through resistor R100. The second pin of optocoupler OT6 is connected to the first pin of optocoupler OT4. The second pin of optocoupler OT4 is connected to the collector of transistor Q70. The base of transistor Q70 is connected to the DSP output signal terminal through resistor R101. The emitter of transistor Q70 is grounded. Resistor R102 is connected in parallel between the base and emitter of transistor Q70. Resistor R831 is connected in parallel between the fourth and third pins of optocoupler OT6. The fourth and third pins of optocoupler OT6 are respectively connected to the drive module. Resistor R823 is connected in parallel between the fourth and third pins of optocoupler OT4. The fourth and third pins of optocoupler OT6 are respectively connected to the drive module.

[0041] The drive module is used to simultaneously respond to the enable signal provided by the latching module and the short single pulse provided by the timing module to drive the magnetic latching relay. The latching module enable signal opens the L-type push-pull stage, and the timing module injects a ±12 V bipolar pulse into the coil instantaneously; the positive pulse completes the engagement, and the reverse pulse completes the release.

[0042] In some embodiments, the drive module includes a control stage circuit and a power stage circuit; the control stage circuit is used to respond to a short-time single pulse output by the timing module; the power stage circuit is electrically connected to the control stage circuit and the latching module; the latching module controls the on / off state of the electrical circuit of the power stage circuit through an enable signal to form a controlled drive circuit; in response to the short-time single pulse, the control stage circuit controls the power stage circuit to inject a drive pulse current into the magnetic latching relay coil when the controlled drive circuit is turned on; and the current path in the control stage circuit is isolated from the drive pulse current path flowing through the power stage circuit and the magnetic latching relay coil.

[0043] like Figure 1As shown, the power stage circuit of the drive module includes MOSFETs Q13 and Q15. The on / off state of MOSFETs Q13 and Q15 is directly controlled by the enable signal of the latching module to turn the controlled drive circuit on or off. The control stage circuit of the drive module includes MOSFETs Q21 and Q18. MOSFETs Q21 and Q18 respond to the short-time single pulse output by the timing module and control the gate voltages of MOSFETs Q15 and Q13 respectively. The gate of MOSFET Q13 is connected to the fourth pin of optocoupler OT6. The gate of MOSFET Q13 is also connected to the drain of MOSFET Q18 after passing through switching diode D154 and resistor R830. The gate of MOSFET Q18 is connected to the second timing unit. The source of S-channel transistor Q18 is connected to the source of MOSFET Q15 via resistor R2. The source of MOSFET Q13 is connected to the third pin of optocoupler OT6. The source of MOSFET Q13 is also connected to the source of MOSFET Q21 via resistor R3. The gate of MOSFET Q21 is connected to one end of capacitor C94. The drain of MOSFET Q21 is connected to the gate of MOSFET Q15 via resistor R819 and switching diode D165. The drain of MOSFET Q13 is connected to the first drive input terminal of magnetic latching relay. The drain of MOSFET Q15 is connected to the second drive input terminal of magnetic latching relay. The gate of MOSFET Q15 is also connected to the fourth pin of optocoupler OT4. The source of MOSFET Q15 is also connected to the third pin of optocoupler OT4.

[0044] The protection module is connected in parallel with the coil of the magnetic latching relay to absorb and clamp peak voltages. A TVS diode and an RC absorption branch are connected in parallel across the relay coil to clamp the induced voltage at the moment of disconnection to ≤40 V and eliminate the arc.

[0045] In some embodiments, the protection module includes a spike absorption circuit and a voltage clamping element connected in parallel across the magnetic latching relay coil to absorb and clamp induced voltage spikes generated when the coil is disconnected, protecting the drive circuit and latching circuit from high-voltage breakdown. Figure 1 As shown, the protection module includes a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are connected in series to form an RC absorption branch. The RC absorption branch and the TVS diode D1 are both connected in parallel across the coil of the magnetic latching relay.

[0046] like Figure 1As shown in the figure, when the DSP issues an enabling instruction, that is, the DSP_EN port outputs a low level, the triode Q70 is cut off. At this time, the opto-isolator OT6 and the opto-isolator OT4 are not conducting; when it is necessary to make the magnetic latching relay close, the BMS_H port is connected to the positive 12V power supply, and the BMS_L is connected to 0V. When the power supply is just connected, the gate of the MOS transistor Q21 is 0V, and the source of the MOS transistor Q21 is 12V. Since the MOS transistor Q21 is a PMOS, at this time, UG of the MOS transistor Q21 < US, and it is in the conducting state. Therefore, at this time, the gate of the MOS transistor Q15 is 12V, and the source is 0V. Since the MOS transistor Q15 is an NMOS, at this time, UG of the MOS transistor Q15 > US, and it is also in the conducting state. Therefore, at this time, a complete closing circuit of the magnetic latching relay is formed: BMS_H terminal - resistor R_{4}, resistor R_{5} - MOS transistor Q_{13} - RLYH terminal - RLYL terminal - MOS transistor Q_{15} - BMS_L terminal; as the power supply is connected for a period of time, both ends of the capacitor C_{94} are filled to the power supply voltage. At this time, the gate of the MOS transistor Q21 is 12V, the source of the MOS transistor Q21 is 12V, UG of the MOS transistor Q21 = US, and the MOS transistor Q21 is in the cut-off state. Therefore, at this time, the gate of the MOS transistor Q15 is 0V, the source is 0V, and the MOS transistor Q15 is also in the cut-off state. Therefore, due to the cut-off of the MOS transistor Q15, the closing circuit of the magnetic latching relay is disconnected. Similarly, when it is necessary to make the magnetic latching relay close, the BMS_H port is connected to the positive 0V power supply, and the BMS_L is connected to the negative 12V. The working principle is the same as above, and will not be elaborated here.

[0047] When the DSP issues a locking instruction, that is, the DSP_EN port outputs a high level, the triode Q70 conducts. At this time, the opto-isolator OT6 and the opto-isolator OT4 conduct. Correspondingly, when the opto-isolator OT6 and the opto-isolator OT4 conduct, the MOS transistors Q13 and Q15 are cut off, and then the electric circuit of the magnetic latching relay is disconnected, achieving the locking purpose.

[0048] Embodiment 2:

[0049] The present invention provides a power module, including the synchronous drive and timing locking control circuit of the magnetic latching relay as described in any one of Embodiment 1. [[ID=((11))]]

[0050] The power module provided by the embodiment of the present invention can execute what is provided by any embodiment of the present invention and has corresponding functions and beneficial effects.

[0051] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A synchronous drive and timing latching control circuit for a magnetic latching relay, characterized in that, include: A power module is used to connect to the BMS and output trigger signals. The power module is electrically connected to the timing module, the drive module, and the locking module respectively. The timing module is used to convert long-level trigger signals into short-time single pulses and transmit them to the driver module. A locking module, which is connected to the drive module, is used to output an enable signal to control the on / off state of the electrical circuit of the drive module; The drive module is used to drive the magnetic latching relay in response to both the enable signal provided by the latching module and the short single pulse provided by the timing module.

2. The synchronous drive and timing latching control circuit for the magnetic latching relay according to claim 1, characterized in that, The drive module includes a control stage circuit and a power stage circuit; A control-level circuit is used to respond to the short-duration single pulse output by the timing module; The power stage circuit is electrically connected to the control stage circuit and the locking module; The locking module controls the on / off state of the electrical circuit of the power stage circuit through the enable signal to form a controlled drive circuit. The control stage circuit responds to the short-time single pulse and controls the power stage circuit to inject drive pulse current into the magnetic latching relay coil when the controlled drive circuit is turned on. Furthermore, the current path in the control stage circuit is isolated from the drive pulse current path flowing through the power stage circuit and the magnetic latching relay coil.

3. The synchronous drive and timing latching control circuit for the magnetic latching relay according to claim 1, characterized in that, It also includes a protection module connected in parallel with the coil of the magnetic latching relay for absorbing and clamping voltage spikes.

4. The synchronous drive and timing latching control circuit for the magnetic latching relay according to claim 2, characterized in that, The power module includes resistors R5 and R7. Resistor R4 is connected in parallel across resistor R5, and resistor R6 is connected in parallel across resistor R7. One end of resistor R5 is connected to the positive power output terminal of the BMS, and the other end of resistor R5 is connected to the timing module. One end of resistor R7 is connected to the negative power output terminal of the BMS, and the other end of resistor R7 is connected to the timing module.

5. The synchronous drive and timing latching control circuit for the magnetic latching relay according to claim 4, characterized in that, The timing module includes a first timing unit and then a second timing unit with the same structure. The first timing unit includes a resistor R813, one end of which is connected to the other end of a resistor R5, and the other end of which is connected to the anode of a switching diode D57. The cathode of the switching diode D57 is connected to the other end of a resistor R7. A switching diode D101 and a resistor R814 are connected in parallel across two ends of a TVS diode D2. A capacitor C2 and a capacitor C3 are connected in parallel across two ends of a capacitor C94. The anode of the TVS diode D2 is connected to the other end of a resistor R5, and the cathode of the TVS diode D2 is connected to one end of a capacitor C94. The other end of a capacitor C94 is connected to the anode of the switching diode D57.

6. The synchronous drive and timing latching control circuit for the magnetic latching relay according to claim 5, characterized in that, The locking module includes optocoupler OT6 and optocoupler OT4. The first pin of optocoupler OT6 is connected to a 5V power supply through resistor R100. The second pin of optocoupler OT6 is connected to the first pin of optocoupler OT4. The second pin of optocoupler OT4 is connected to the collector of transistor Q70. The base of transistor Q70 is connected to the DSP output signal terminal through resistor R101. The emitter of transistor Q70 is grounded. Resistor R102 is connected in parallel between the base and emitter of transistor Q70. Resistor R831 is connected in parallel between the fourth and third pins of optocoupler OT6. The fourth and third pins of optocoupler OT6 are respectively connected to the drive module. Resistor R823 is connected in parallel between the fourth and third pins of optocoupler OT4. The fourth and third pins of optocoupler OT6 are respectively connected to the drive module.

7. The synchronous drive and timing latching control circuit for the magnetic latching relay according to claim 6, characterized in that, The power stage circuit of the drive module includes MOSFETs Q13 and Q15. The conduction and turn-off of MOSFETs Q13 and Q15 are directly controlled by the enable signal of the latching module to turn the controlled drive circuit on or off. The control stage circuit of the drive module includes MOSFETs Q21 and Q18. MOSFETs Q21 and Q18 respond to a short single pulse output by the timing module and control the gate voltages of MOSFETs Q15 and Q13, respectively. The gate of MOSFET Q13 is connected to the fourth pin of optocoupler OT6. The gate of MOSFET Q13 is also connected to the drain of MOSFET Q18 after passing through switching diode D154 and resistor R830. The gate of MOSFET Q18 is connected to the second timing unit. The source of MOSFET Q18 is connected to the source of MOSFET Q15 via resistor R2. The source of MOSFET Q13 is connected to the third pin of optocoupler OT6. The source of MOSFET Q13 is also connected to the source of MOSFET Q21 via resistor R3. The gate of MOSFET Q21 is connected to one end of capacitor C94. The drain of MOSFET Q21 is connected to the gate of MOSFET Q15 via resistor R819 and switching diode D165. The drain of MOSFET Q13 is connected to the first drive input terminal of magnetic latching relay. The drain of MOSFET Q15 is connected to the second drive input terminal of magnetic latching relay. The gate of MOSFET Q15 is also connected to the fourth pin of optocoupler OT4. The source of MOSFET Q15 is also connected to the third pin of optocoupler OT4.

8. The synchronous drive and timing latching control circuit for the magnetic latching relay according to claim 3, characterized in that, The protection module includes a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are connected in series to form an RC absorption branch. The RC absorption branch and the TVS diode D1 are both connected in parallel across the coil of the magnetic latching relay.

9. A power module, characterized in that, Includes a synchronous drive and timing latching control circuit for a magnetic latching relay as described in any one of claims 1-8.

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