Shallow trench isolation structure and method of manufacturing the same
By forming an epitaxial layer in a shallow trench isolation structure and changing the trench shape, the loss problem of the active region of small-sized MOS devices caused by rounding is solved, and the electric field distribution is optimized and the performance is maintained.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-03-27
AI Technical Summary
Existing technologies struggle to achieve both optimized electric field distribution for large-size MOS devices and reduced active region size for small-size MOS devices when smoothly processing shallow trench isolation structures, leading to performance degradation.
In the fabrication of shallow trench isolation structures, an epitaxial layer is formed on the inner wall of the trench and smoothed. Combined with ion implantation and etching processes, the trench shape is transformed into a square shape, ensuring that the epitaxial layer material is homogeneous with the semiconductor substrate material and reducing the loss at the limit size of the active region.
After smoothing, the electric field distribution was optimized, leakage current was reduced, and the performance of small-sized MOS devices was maintained. The influence of material interface differences was avoided, and the overall performance of the device was improved.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, in particular to a shallow trench isolation structure and a preparation method thereof. BACKGROUND
[0002] The active area (AA) isolation layer of a Metal-Oxide-Semiconductor (MOS) device is usually made by a shallow trench isolation (STI) process to avoid leakage caused by carrier aggregation.
[0003] To optimize the electric field distribution, reduce the electric field concentration, avoid the occurrence of sharp tip discharge phenomenon, reduce the leakage current and improve the performance of the device, after etching a shallow trench, the corner region of the active area needs to be rounded. However, through research, it is found that the more rounded the corner region (i.e. the larger the rounding radius / diameter), the smaller the potential line and current density, and the lower the leakage current (Ioff) of the MOS device. For large-size MOS devices (e.g. pull-down transistors), the limit size (CD) of the active area is large, so better rounding can be achieved. However, for small-size MOS devices (e.g. pull-up transistors), the limit size of the active area is small itself, and rounding will cause the active area size to shrink, thereby affecting the performance of the MOS device. Therefore, the requirements of large-size MOS devices and small-size MOS devices for rounding are mutually inhibiting. SUMMARY
[0004] In view of the problems mentioned in the background art, the present application provides a shallow trench isolation structure and a preparation method thereof, which can achieve better rounding while ensuring the performance of small-size transistors.
[0005] To achieve the above object and other related objects, on the one hand, the present application provides a preparation method of a shallow trench isolation structure, which comprises:
[0006] providing a semiconductor substrate, and sequentially forming a pad oxide layer and a nitride layer on the semiconductor substrate;
[0007] forming a trench in the pad oxide layer, the nitride layer and the semiconductor substrate; the trench extends from the nitride layer to the semiconductor substrate, dividing the semiconductor substrate into a plurality of active areas;
[0008] back-etching the pad oxide layer and the nitride layer on both sides of the trench to expose the top surface of the active area of the semiconductor substrate near the top of the sidewall of the trench;
[0009] forming an epitaxial layer on the inner wall of the trench and the exposed top surface of the active region of the semiconductor substrate; the epitaxial layer is made of silicon-based material which can be used as semiconductor substrate material;
[0010] smoothing the exposed top corner of the active region of the semiconductor substrate and forming a line oxide layer; the thickness of the line oxide layer is equal to the thickness of the epitaxial layer plus the thickness of the active region consumed;
[0011] forming an isolation region in the trench and performing planarization treatment on the isolation region to expose the nitrided layer and remove the nitrided layer.
[0012] In some embodiments, the method for forming a trench comprises:
[0013] forming a photoresist pattern on the nitrided layer and performing exposure and development to form an isolation region of the active region;
[0014] etching the nitrided layer, the pad oxide layer and the semiconductor substrate to form a reverse trapezoidal trench with a wide top and a narrow bottom.
[0015] In some embodiments, the method for forming a trench further comprises:
[0016] measuring the depth, the bottom width and the top width of the reverse trapezoidal trench, and the thickness of the pad oxide layer and the thickness of the nitrided layer;
[0017] calculating the angle of ion implantation according to the measured data, and determining the dose and energy of ion implantation according to the volume of the two side regions of the reverse trapezoidal trench;
[0018] implanting ions into the two side regions of the reverse trapezoidal trench according to the angle, dose and energy of ion implantation, so that the substance of the two side regions of the reverse trapezoidal trench is modified, and the modified substance is removed by using a corresponding solution in a subsequent etching-back process to form a square trench.
[0019] In some embodiments, the angle of ion implantation ranges from 15° to 45°; the dose of ion implantation is 1×10 14 cm -2 ~1×10 17 cm -2 ; and the energy of ion implantation is 1 keV to 10 keV.
[0020] In some embodiments, the method for forming a trench comprises:
[0021] forming a photoresist pattern on the nitrided layer and performing exposure and development to form an isolation region of the active region;
[0022] etching the nitride layer and the liner oxide layer so that the isolation region exposes a top surface of an active region of the semiconductor substrate;
[0023] ion implantation into the exposed active region of the semiconductor substrate to form a wet etching stop layer in the semiconductor substrate;
[0024] ion implantation into the exposed active region of the semiconductor substrate to convert a single crystal structure of the active region of the semiconductor substrate into an amorphous structure;
[0025] etching the semiconductor substrate to form an inverted trapezoidal trench with a wide top and a narrow bottom;
[0026] removing the amorphous structure of the side wall of the inverted trapezoidal trench to form a square trench.
[0027] In some embodiments, in the process of forming the wet etching stop layer, the projection range of ion implantation is greater than or equal to the depth of the trench.
[0028] In some embodiments, in the process of removing the amorphous structure of the side wall of the inverted trapezoidal trench, the etching solution used is any one or a combination of the following solutions: potassium hydroxide solution, tetramethylammonium hydroxide solution; the etching temperature is 70-90°C; the selectivity ratio of amorphous to single crystal is 3:1-5:1.
[0029] In some embodiments, the material of the epitaxial layer belongs to the same type of material as the material of the semiconductor substrate.
[0030] In some embodiments, in the smoothing process, the size of the smoothing arc is controlled by the thickness of the epitaxial layer.
[0031] In another aspect, the application also provides a shallow trench isolation structure prepared by any one of the above preparation methods.
[0032] The unexpected effect of the present application is that the epitaxial process is used to form an epitaxial layer of a certain thickness before the smoothing process, which reduces the loss of the limit size of the active region in the subsequent smoothing process, obtains a better smoothing effect while avoiding the impact on the device performance; and the epitaxial process only forms an epitaxial layer on the exposed surface of the semiconductor substrate, which does not affect other layer forms and does not require additional auxiliary processes. At the same time, the material of the epitaxial layer is the same as that of the semiconductor substrate, so as to ensure that the material of the oxide layer formed by the subsequent smoothing process is the same, avoid the interface difference in the oxide layer due to the different materials, and affect the subsequent process effect and further affect the device performance. Further, in order to better form and control the thickness and morphology of the epitaxial layer, the inverted trapezoidal trench is converted into a square trench, which is conducive to the formation of a better epitaxial layer. BRIEF DESCRIPTION OF DRAWINGS
[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on these drawings.
[0034] Figure 1 The preparation method flowchart of the shallow trench isolation structure provided by the embodiments of the present application.
[0035] Figure 2 The schematic diagram for forming the pad oxide layer and the deep N well in the first embodiment of the present application.
[0036] Figure 3 The schematic diagram for forming the photoresist pattern layer and performing exposure and development in the first embodiment of the present application.
[0037] Figure 4 The schematic diagram for etching to form the inverted trapezoidal trench in the first embodiment of the present application.
[0038] Figure 5 The schematic diagram for etching back the pad oxide layer and the nitride layer in the first embodiment of the present application.
[0039] Figure 6 The schematic diagram for forming the epitaxial layer in the first embodiment of the present application.
[0040] Figure 7 The schematic diagram for rounding in the first embodiment of the present application.
[0041] Figure 8 The schematic diagram for forming the isolation region in the first embodiment of the present application.
[0042] Figure 9 The schematic diagram for removing the nitride layer in the first embodiment of the present application.
[0043] Figure 10 The schematic diagram for parameter measurement and calculation principle in the second embodiment of the present application.
[0044] Figure 11 The schematic diagram for forming the square trench in the second embodiment of the present application.
[0045] Figure 12 The schematic diagram for forming the epitaxial layer in the second embodiment of the present application.
[0046] Figure 13 The schematic diagram for rounding in the second embodiment of the present application.
[0047] Figure 14 The schematic diagram for forming the isolation region in the second embodiment of the present application.
[0048] Figure 15 A schematic diagram for removing the nitride layer in the second embodiment of the present application.
[0049] Figure 16 A schematic diagram for etching the nitride layer and the liner oxide layer in the third embodiment of the present application.
[0050] Figure 17 A schematic diagram for forming the wet etching stop layer in the third embodiment of the present application.
[0051] Figure 18 A schematic diagram for modifying the active region material in the opened semiconductor substrate in the third embodiment of the present application.
[0052] Figure 19 A schematic diagram for etching to form the inverted trapezoidal trench in the third embodiment of the present application.
[0053] Figure 20 A schematic diagram for etching to form the square trench in the third embodiment of the present application.
[0054] Figure 21 A schematic diagram for forming the N-type well in the embodiment of the present application.
[0055] Figure 22 A schematic diagram for forming the P-type well in the embodiment of the present application.
[0056] BRIEF DESCRIPTION OF DRAWINGS
[0057] 10 - semiconductor substrate, 11 - deep N well, 12 - active region, 13 - wet etching stop layer, 14 - N-type well, 15 - P-type well, 20 - liner oxide layer, 30 - nitride layer, 40 - photoresist pattern layer, 50 - inverted trapezoidal trench, 51 - square trench, 60 - epitaxial layer, 70 - isolation region. DETAILED DESCRIPTION
[0058] In order to facilitate the understanding of the present application, the present application will be described in more detail below with reference to the relevant drawings. The drawings show embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.
[0060] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.
[0061] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other directions (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0062] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", or the like, as used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0063] The embodiment of the present application provides a preparation method of a shallow trench isolation structure, as shown in the figure. Figure 1 The preparation method of the shallow trench isolation structure provided by the embodiment of the present application comprises the following steps 110 to 160.
[0064] Step 110, providing a semiconductor substrate, forming a pad oxide layer on the semiconductor substrate, and then implanting N-type doping ions into the semiconductor substrate to form a deep N well;
[0065] Step 120, forming a nitride layer on the pad oxide layer, and forming a trench in the pad oxide layer, the nitride layer and the semiconductor substrate; the trench extends from the nitride layer to the semiconductor substrate, and divides the semiconductor substrate into a plurality of active regions;
[0066] Step 130, performing etch-back on the pad oxide layer and the nitride layer on both sides of the trench, so that the top surface of the active region of the semiconductor substrate close to the top of the side wall of the trench is exposed;
[0067] Step 140, epitaxially forming an epitaxial layer with a certain thickness on the inner wall of the trench and the exposed top surface of the active region of the semiconductor substrate;
[0068] Step 150, performing smoothing treatment on the top corner of the exposed active region of the semiconductor substrate to form a line oxide layer; the thickness of the line oxide layer is equal to the thickness of the epitaxial layer plus the thickness consumed by the active region;
[0069] Step 160, forming an isolation layer in the trench, and performing planarization treatment on the isolation layer to expose the nitride layer and remove the nitride layer.
[0070] As shown in the figure, the method for forming the pad oxide layer 20 and the deep N well 11 in step 110 of the embodiment of the present application is as follows: Figure 2
[0071] First, a pad oxide layer 20 (Pad Oxide) with a thickness of about 55 angstroms is formed on the semiconductor substrate 10, which is used to prevent damage to the silicon surface in the subsequent ion implantation process;
[0072] Then, N-type doping ions are implanted into the pad oxide layer 20 by an ion implantation process to form a deep N well 11, and a structure as shown in the figure is obtained. Figure 2
[0073] Optionally, the material of the semiconductor substrate 10 can be at least one of the following materials or a combination thereof: Si, SiC and other silicon-based materials. The forming method of the pad oxide layer 20 can adopt, but is not limited to, furnace tube growth, rapid thermal processing (RTP) and the like; and the material of the pad oxide layer 20 can adopt silicon dioxide.
[0074] In step 120 of the embodiment, the forming method of the nitride layer 30 can use, but is not limited to, chemical vapor deposition (CVD), furnace tube growth, etc. The material of the nitride layer 30 can use one or a combination of silicon nitride, silicon oxygen nitride, silicon carbon nitride, etc.
[0075] The method for forming the trench has various forms, Figure 3 and Figure 4 A method for forming a trench in an optional embodiment is shown. First, a photoresist pattern layer 40 is formed on the nitride layer 30 by a patterning process and isolated region exposure and development are performed to form an isolated region of the active region of the MOS device, obtaining a structure as shown in FIG. 4A. Figure 3 Then, a dry etching process is used to etch the nitride layer 30, the pad oxide layer 20 and the semiconductor substrate 10 to form an inverted trapezoidal trench 50 with a wide upper part and a narrow lower part, as shown in FIG. 4B. The inverted trapezoidal trench 50 extends from the nitride layer 30 to the semiconductor substrate 10 and divides the semiconductor substrate 10 into a plurality of active regions 12. Figure 4
[0076] In step 130 of the embodiment, a wet etching process can be used for the etching back. Specifically, the wet etching process can first use phosphoric acid to soak at a temperature of 160°C for 50s, and then use a mixed solution (APM) composed of ammonium hydroxide, hydrogen peroxide and deionized water to soak at a temperature of 45°C for 300s, obtaining a structure as shown in FIG. 5A. Figure 5 It can be understood that the time and temperature required in the etching back process are mainly determined according to the thickness of the side advance of the pad oxide layer 20 and the nitride layer 30. The etching back process is beneficial for the subsequent smoothing of the corner region and can also reduce the step height when the inverted trapezoidal trench 50 is filled, so that the tetraethyl orthosilicate (TEOS) can be better filled into the inverted trapezoidal trench 50, so that it is not easy to produce voids.
[0077] In step 140 of the embodiment, an epitaxial layer 60 with a certain thickness is formed on the inner wall of the inverted trapezoidal trench 50 and the active region 12 by an epitaxial process, obtaining a structure as shown in FIG. 6A. Figure 6 The epitaxial process only forms an epitaxial layer on the exposed surface of the semiconductor substrate and does not affect other layer forms, and no additional auxiliary process is required. Optionally, the material of the epitaxial layer 60 can be at least one or a combination of the following materials: Si, SiC, etc. silicon-based materials (i.e. semiconductor substrate materials), so as to ensure the homogeneity of the line oxide layer material formed by the subsequent smoothing process. The thickness of the epitaxial layer 60 is determined according to the thickness of the subsequent line oxide layer, and the thickness of the epitaxial layer 60 is preferably 40 angstroms. The embodiment forms an epitaxial layer 60 with a certain thickness by the epitaxial process, so that the subsequent smoothing process can reduce the loss of the limit size of the active region 12, and the size of the smoothing arc can be controlled by the thickness of the epitaxial layer.
[0078] In step 150 of the embodiment, a thermal oxidation process is used to perform thermal oxidation treatment to obtain a structure as shown in FIG. 2C. Figure 7 The thermal oxidation treatment smoothes the corner region to reduce the sharp corners of the trench corner region and reduce the electric field concentration, and can also repair the damage to the active region 12 caused by dry etching. The thickness of the oxide layer is equal to the thickness of the epitaxial layer 60 plus the thickness consumed by the active region 12.
[0079] In step 160 of the embodiment, a high aspect ratio process is used to deposit tetraethyl orthosilicate in the trench to form the isolation region 70, and then annealing treatment is performed at a certain temperature to make the deposited tetraethyl orthosilicate more dense. Then, chemical mechanical polishing (CMP) process is performed for planarization treatment, and an endpoint detection method is used to stop polishing at the upper surface of the nitrided layer 30 to obtain a structure as shown in FIG. 2D. Figure 8
[0080] In step 160 of the embodiment, phosphoric acid and diluted hydrofluoric acid are used to remove the nitrided layer 30 and the tetraethyl orthosilicate deposited in the middle region of the nitrided layer 30 to obtain a structure as shown in FIG. 2E, and the preparation of the STI structure is completed. Figure 9
[0081] Figure 3 Figure 4 The trench forming method shown in FIG. 1 uses a dry etching process to form a reversed trapezoidal trench with a wide upper part and a narrow lower part. However, it is difficult to form a regular epitaxial layer on the inner sidewall of the reversed trapezoidal structure in the actual process. Therefore, the embodiment of the present application proposes another method for forming a trench, and the specific implementation process includes:
[0082] After the dry etching process is used to form a reversed trapezoidal trench 50 as shown in FIG. 2A, a measurement process is used to measure the size of the reversed trapezoidal trench 50, the pad oxide layer 20, and the nitrided layer 30, including the depth H of the reversed trapezoidal trench 50, the bottom width W1 and the top width W2 of the reversed trapezoidal trench 50, the thickness of the pad oxide layer 20, and the thickness of the nitrided layer 30, as shown in FIG. 2B. Figure 4 Figure 10 According to the above size data measured, the angle between the ion implantation and the normal line is calculated. Alternatively, when the cross section of the two side regions of the reversed trapezoidal trench 50 is triangular, the angle calculation formula of the ion implantation is as follows:
[0083]
[0084]
[0085]
[0086] In the formula, The angle of ion implantation (i.e., the angle between the ion implantation line and the normal). To calculate the required transition angle.
[0087] At the same time, based on the volume of the areas on both sides of the trench (e.g. Figure 10 The volume of the regions corresponding to the cross-sections ACE and BDF on both sides of the trench shown is used to determine the ion implantation dose and energy. Optionally, the ion implantation angle ranges from 15° to 45°, the ion implantation energy is from 1 keV to 10 keV, and the ion implantation dose is in the range of 1 × 10⁻⁶. 14 cm -2 ~1×10 17 cm -2 .
[0088] Following the determined ion implantation angle, dosage, and energy, ions are implanted into the regions on both sides of the inverted trapezoidal trench 50 using an ion implantation process, thereby modifying the material in these regions. Optionally, nitrogen atoms can be implanted in this step to form a bond between silicon-based materials such as Si or SiC and nitrogen in the regions on both sides of the inverted trapezoidal trench 50, facilitating the removal of this bond along with the nitride layer during subsequent etch-back processes. Optionally, hydrogen atoms can also be implanted in this step. + Ar + If other inert gas ions are present, an additional etching process is required. A different solution must be used than that used in the etching-back process to remove the modified substance, such as Ar. + Ions can be removed using potassium hydroxide solution.
[0089] Next, the re-engraving process described in step 130 above is performed to obtain the following result: Figure 11 The square trench 51 shown. This application embodiment utilizes metrology processes, advanced process control system (APC) parameter calculations, and ion implantation processes to address the above-mentioned... Figure 3 and Figure 4 The regions on both sides of the formed inverted trapezoidal trench 50 are modified to change the shape of the trench, facilitating the formation of a regular epitaxial layer 60. This allows for better control over the thickness and morphology of the epitaxial layer 60, reducing losses to the limiting dimensions of the active region 12 during subsequent smoothing processes and ensuring its performance. Since the subsequent processes are the same as steps 150 to 170, except that the formed trench is square, as shown... Figures 12 to 15 As shown, it will not be elaborated further here.
[0090] Considering that the process of material modification by using a metrology process, parameter calculation of an advanced process control system and a quantum injection process is relatively complex and the control is relatively difficult, in view of this, the embodiment of the present application proposes another optional embodiment of the method for forming a trench, and the specific implementation process comprises the following steps:
[0091] After the isolation region is formed by exposure and development, that is, after the structure shown in Figure 3 is formed, the dry etching process is used to etch the nitride layer 30 and the pad oxide layer 20, so that the top surface of the active region of the semiconductor substrate corresponding to the isolation region is exposed, and the structure shown in Figure 16 is obtained.
[0092] Then, the ion implantation process is used to implant ions into the exposed active region of the semiconductor substrate, and the wet etching stop layer 13 is formed in the semiconductor substrate 10, and the structure shown in Figure 17 is obtained. Optionally, the ion implantation process comprises implanting C + ions with an implantation depth greater than or equal to the etching depth of the subsequent trench. Optionally, the implantation depth is greater than or equal to 3300 angstroms, the implantation dose is greater than 1×10 17 cm⁻², and the implantation into the semiconductor substrate can completely block the wet etching to form the wet etching stop layer 13; optionally, to achieve a 330 nm projection range (Rp), an energy range of 280-320 keV is required, and an energy of 300 keV is preferred, which can ensure that Rp≈330 nm (longitudinal standard deviation ΔRp≈65 nm).
[0093] Then, the ion implantation process is used to implant ions into the exposed active region of the semiconductor substrate, so that the chemical properties of the active region of the semiconductor substrate are changed, that is, the single crystal structure is converted into an amorphous structure, and the structure shown in Figure 18 is obtained. Optionally, the implanted ions can be H + , Ar⁺ or other inert gas ions, for example, Ar⁺ ions, and the energy of the implanted ions is preferably about 500 keV, which can ensure that Rp≈330 nm. It can be understood that the energy of the implanted ions can be determined according to actual needs. If a single implantation cannot cover sufficient depth, multiple energy superposition implantation (such as 450 keV, 500 keV, 550 keV) can be used to widen the amorphous layer thickness, and the implantation dose can be set to 1×10 15 ~ 5×10 15 ions / cm², and in actual processes, the combination of energy and dose can be verified and optimized by a design of experiments (DOE) method, and the amorphous layer quality can be optimized by transmission electron microscopy (TEM) analysis.
[0094] Then, the dry etching process is used to etch the semiconductor substrate 10, and theFigure 19 The inverted trapezoidal trench 50 is shown.
[0095] Then, the amorphous structure of the trench sidewall is removed by a wet etching process, so as to form a square trench 51 as shown. Figure 20 Optionally, the etching solution can be any one or a combination of the following solutions: potassium hydroxide (KOH) solution, tetramethylammonium hydroxide (TMAH) solution, etc.; preferably, the tetramethylammonium hydroxide solution, such as 5-25wt% TMAH aqueous solution; the etching temperature is preferably 70-90°C, and the selectivity ratio (amorphous / single crystal) is preferably 3:1-5:1. In the actual process, the selection of the etching solution, concentration, temperature, and selectivity ratio can be verified and optimized by the design of experiments.
[0096] Since the subsequent process is the same as the above steps 130-170, the formed structure is also as shown, and thus the details are not repeated here. The embodiment of the present application only needs to add two steps of ion implantation to the isolation region, the first step of ion implantation forms a wet etching stop layer, and the second step of ion implantation converts the single crystal structure into an amorphous structure, that is, the regions on both sides of the trench can be accurately etched, so as to form a square trench, which is beneficial to the subsequent formation of a better epitaxial layer. Figures 11 to 15 Further, after obtaining the above STI structure, subsequent substrate preparation of NMOS and PMOS is performed, including:
[0097] Ion implantation of P-type well (PW) and N-type well (NW) is performed on the left and right sides of the STI structure, respectively. As shown, the ion implantation of NW is performed: first, a photoresist pattern layer 40 is formed on the surface of the pad oxide layer 20 and the NW region is exposed and developed, and then ions are implanted into the active region corresponding to the NW region to form an N-type well 14; preferably, the implanted ions can be selected from phosphorus (P), arsenic (As), etc., and can be implanted in three steps to different depths.
[0098] Figure 21 As shown, the ion implantation of PW is performed: first, a photoresist pattern layer 40 is formed on the surface of the pad oxide layer 20 and the PW region is exposed and developed, and then ions are implanted into the active region corresponding to the PW region to form a P-type well 15; preferably, the implanted ions can be selected from boron (B), boron fluoride (BF2), etc., and can be implanted in four steps to different depths, so as to form the most basic substrate unit of NMOS and PMOS. The subsequent process is not the core of the present application, and thus the details are not repeated here.
[0099] As shown, the ion implantation of PW is performed: first, a photoresist pattern layer 40 is formed on the surface of the pad oxide layer 20 and the PW region is exposed and developed, and then ions are implanted into the active region corresponding to the PW region to form a P-type well 15; preferably, the implanted ions can be selected from boron (B), boron fluoride (BF2), etc., and can be implanted in four steps to different depths, so as to form the most basic substrate unit of NMOS and PMOS. The subsequent process is not the core of the present application, and thus the details are not repeated here. Figure 22 It can be understood that,
[0100] and Figure 21 and Figure 22 Only the NMOS and PMOS substrate preparation based on the inverted trapezoidal STI structure is shown, and the NMOS and PMOS substrate preparation process based on the square STI structure is the same, except that the STI structure in the formed structure profile is square, which will not be described here.
[0101] The unexpected effect of the present application is that: a certain thickness of epitaxial layer is formed by epitaxial process before the smoothing process, that is, the width of the active region limit size is increased, the loss of the active region limit size in the subsequent smoothing process is reduced, better smoothing effect is obtained while the performance of the device is ensured; and the epitaxial process only forms an epitaxial layer on the exposed surface of the semiconductor substrate, does not affect other layer shapes, and does not require additional auxiliary processes, and the material of the epitaxial layer is homologous with the material of the semiconductor substrate, so that the material of the line oxide layer formed by the subsequent smoothing process is homologous, avoiding the interface difference in the line oxide layer due to the different materials, which affects the subsequent process effect and further affects the device performance. Further, in order to better form and control the thickness and morphology of the epitaxial layer, the inverted trapezoidal trench is converted into a square trench through a measurement process, an ion implantation process, etc., which is conducive to the subsequent formation of a better epitaxial layer.
[0102] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "optional embodiments", etc. means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.
[0103] The technical features of the above-described embodiments can be combined in any manner, and in order to make the description concise, all possible combinations of the technical features of the above-described embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.
[0104] It can be understood that the above-described embodiments only disclose several preferred implementation manners of the present application, and the above-described embodiments are not used to limit the protection scope of the present application. For those skilled in the art, any simple modification and equivalent change to the above-described embodiments according to the technical concept of the present application without departing from the technical concept of the present application, all fall within the protection scope of the present application.
Claims
1. A method of forming a shallow trench isolation structure, comprising: The preparation method comprises: providing a semiconductor substrate, sequentially forming a pad oxide layer and a nitride layer on the semiconductor substrate; forming a trench in the pad oxide layer, the nitride layer and the semiconductor substrate; the trench extends from the nitride layer to the semiconductor substrate, and divides the semiconductor substrate into a plurality of active regions; back-etching the pad oxide layer and the nitride layer on both sides of the trench, so that a top surface of the active region of the semiconductor substrate close to a top of a side wall of the trench is exposed; forming an epitaxial layer on an inner wall of the trench and the exposed top surface of the active region of the semiconductor substrate; the epitaxial layer adopts a silicon-based material capable of serving as a semiconductor substrate material; performing a smoothing treatment on a top corner of the exposed active region of the semiconductor substrate, and forming a line oxide layer; a thickness of the line oxide layer is equal to a thickness of the epitaxial layer plus a consumed thickness of the active region; forming an isolation region in the trench, and performing a planarization treatment on the isolation region to expose the nitride layer and remove the nitride layer; wherein the trench forming method comprises: a first forming method: etching the nitride layer, the pad oxide layer and the semiconductor substrate to form an inverted trapezoidal trench with a wide top and a narrow bottom, then performing a modification treatment on regions on both sides of the inverted trapezoidal trench through ion implantation, and finally etching the regions on both sides of the inverted trapezoidal trench to form a square trench; or, a second forming method: etching the nitride layer and the pad oxide layer to expose a top surface of an active region of the semiconductor substrate, then performing two-step ion implantation, the first step of ion implantation forms a wet etching stop layer, the second step of ion implantation converts a single crystal structure of the active region of the semiconductor substrate into an amorphous structure, and finally etching the semiconductor substrate to form an inverted trapezoidal trench with a wide top and a narrow bottom and remove the amorphous structure of a side wall of the inverted trapezoidal trench, to form a square trench.
2. The method of claim 1, wherein The first forming method comprises: forming a photoresist pattern on the nitride layer and performing exposure and development to form an isolation region of the active region; etching the nitride layer, the pad oxide layer and the semiconductor substrate to form an inverted trapezoidal trench with a wide top and a narrow bottom.
3. The method for preparing a shallow trench isolation structure according to claim 2, characterized in that, The first forming method further comprises: measuring a depth, a bottom width and a top width of the inverted trapezoidal trench, and a thickness of the pad oxide layer and a thickness of the nitride layer; calculating an ion implantation angle according to the measured data, and determining a dose and an energy of ion implantation according to a volume of the regions on both sides of the inverted trapezoidal trench; implanting ions to the regions on both sides of the inverted trapezoidal trench according to the ion implantation angle, the dose and the energy, so that substances of the regions on both sides of the inverted trapezoidal trench are modified, and a corresponding solution is used to remove the modified substances in a subsequent back-etching process, to form a square trench.
4. The method for preparing a shallow trench isolation structure according to claim 3, characterized in that, The first forming method further comprises: the angle range of ion implantation is 15°-45°; the dose of ion implantation is 1x10 14 cm -2 ~1x10 17 cm -2 ; and the energy of ion implantation is 1 keV-10 keV.
5. The method of claim 1, wherein The second forming method comprises: forming a photoresist pattern on the nitride layer and performing exposure and development to form an isolation region of the active region; etching the nitride layer and the pad oxide layer to expose a top surface of an active region of the semiconductor substrate corresponding to the isolation region; implanting ions to the exposed active region of the semiconductor substrate to form a wet etching stop layer in the semiconductor substrate; Ion implantation is performed on the exposed active region of the semiconductor substrate to convert the single crystal structure of the active region into an amorphous structure; The semiconductor substrate is etched to form a reverse trapezoidal trench with a wide top and a narrow bottom; The amorphous structure of the side wall of the reverse trapezoidal trench is removed to form a square trench.
6. The method of claim 5, wherein In the process of forming the wet etching barrier, the projection range of ion implantation is greater than or equal to the depth of the trench.
7. The method for preparing a shallow trench isolation structure according to claim 5, characterized in that, In the process of removing the amorphous structure of the side wall of the reverse trapezoidal trench, the etching solution used is any one or a combination of the following solutions: potassium hydroxide solution, tetramethylammonium hydroxide solution; the etching temperature is 70-90°C; the selectivity ratio of amorphous to single crystal is 3:1-5:
1.
8. The method of claim 1-7, wherein The material of the epitaxial layer belongs to the same type of material as the material of the semiconductor substrate.
9. The method of claim 1-7, wherein In the rounding process, the size of the rounding arc is controlled by the thickness of the epitaxial layer.
10. A shallow trench isolation structure, comprising: The preparation method of any one of claims 1-9 is used to prepare.
Citation Information
Patent Citations
Manufacturing method of semiconductor device
CN118841373A