IGZO thin film transistor resistant to space ionizing radiation and preparation method thereof

Abstract

The invention discloses a space ionizing radiation resistant IGZO thin film transistor and a preparation method thereof. The method comprises the following steps: obtaining a substrate; forming a gate electrode layer on the substrate; covering the gate electrode layer and the substrate with a gate dielectric layer; forming an IGZO active layer on the gate dielectric layer; a source region electrode layer and a drain region electrode layer are formed on the two sides of the upper surface of the IGZO active layer at intervals, and the source region electrode layer and the drain region electrode layer are overlapped with the two sides of the gate electrode layer in the horizontal direction respectively; covering a passivation layer on the source region electrode layer, the drain region electrode layer and the IGZO active layer; performing X-ray irradiation on the prepared device; and then low-temperature annealing is carried out. Positive oxidation trapped charges, interface defects and the number of H ions generated by radiation are effectively reduced by means of high-dose X-ray irradiation (1Mrad) and relatively thin IGZO thickness (10nm), a stable anti-radiation structure is formed, the radiation resistance of the device is further enhanced, and a complex heterojunction or high-temperature process does not need to be introduced.

Description

Technical Field

[0001] This invention relates to the field of thin-film transistors and their radiation reliability technology, specifically to an IGZO thin-film transistor resistant to space ionizing radiation and its fabrication method. Background Technology

[0002] InGaZnO (a-IGZO) thin-film transistors (TFTs) have gained widespread commercial application in indoor and outdoor displays, gradually replacing amorphous silicon TFTs (a-Si TFTs), especially in the field of active matrix displays (AMD). This is due to their superior electrical performance, sufficiently high transparency, excellent large-area uniformity, and good cost-effectiveness. Reliability is a key issue for the practical application of IGZO TFTs, and numerous research reports on the electrical stress reliability of these devices have been published over the past few decades. However, reports on the space radiation reliability of a-IGZO TFTs are scarce, limiting their application in space technology.

[0003] As a type of metal-oxide-semiconductor field-effect transistor (MOSFET), a-IGZO TFTs are significantly affected by the total ionizing dose (TID) effect, a key factor to consider when applying these devices in space and other environments with high radiation levels. The TID effect induced by space ionizing radiation is a common threat to the performance degradation of semiconductor devices, but its damage mechanism differs fundamentally from that of traditional silicon-based devices in amorphous IGZO thin-film transistors (a-IGZO TFTs): In silicon MOSFETs, TID damage is concentrated in the gate dielectric layer (e.g., hole trapping in SiO2 leads to a negative threshold voltage drift), while in a-IGZO TFTs, the active layer, due to the disorder of its amorphous structure, becomes the radiation-sensitive core—high-energy particles not only induce defects in the dielectric and passivation layers but also directly affect the IGZO active layer. After radiation, H ions are released and migrate in a-IGZO, acting as free carriers unaffected by gate bias, leading to an increase in the device's off-state current and further negatively shifting the threshold voltage. Most existing radiation protection technologies follow the "dielectric layer center" protection approach for silicon-based devices, but do not address the impact of the IGZO active layer. To address this limitation, this invention innovatively proposes an "X-ray irradiation-annealing synergistic repair" process: high-dose X-ray irradiation (1Mrad) induces the early generation of defects and H ions in the dielectric layer, passivation layer, and active layer, followed by 300℃ low-temperature annealing to achieve defect recombination and hydrogen removal, forming a stable radiation-resistant structure and thus enhancing the device's radiation resistance. This solution breaks through the traditional passive protection paradigm. Implementation examples have verified that the threshold voltage drift of the device after gamma-ray radiation is ≤1.1V, providing a highly compatible solution for space-grade flexible electronic devices. Summary of the Invention

[0004] Technical Problem Solved: The purpose of this invention is to overcome the shortcomings of existing technologies and solve the problem of improving the resistance of IGZO thin-film transistors to space ionizing radiation without introducing complex heterojunctions or high-temperature processes. To address these challenges, this invention proposes a space ionizing radiation-resistant IGZO thin-film transistor and its fabrication method, innovatively proposing an "X-ray irradiation-annealing synergistic repair" process: By applying high-dose X-ray (1Mrad) irradiation pretreatment to the formed IGZO thin-film transistor, defects and H ions in the dielectric layer, passivation layer, and active layer are induced to form in advance. This is then combined with low-temperature annealing at 300℃ to achieve defect recombination and hydrogen removal, forming a stable radiation-resistant structure.

[0005] Technical solution: The first objective of this invention is to provide a method for fabricating IGZO thin-film transistors resistant to space ionizing radiation, the steps of which are as follows:

[0006] S10. Obtain the substrate;

[0007] S20. A gate electrode layer is formed on the substrate;

[0008] S30. Cover the gate electrode layer and the substrate with a gate dielectric layer;

[0009] S40. An IGZO active layer is formed on the gate dielectric layer;

[0010] S50. A source electrode layer and a drain electrode layer are formed at intervals on both sides of the upper surface of the IGZO active layer, and the source electrode layer and the drain electrode layer overlap with both sides of the gate electrode layer in the horizontal direction.

[0011] S60. A passivation layer is applied to the source electrode layer, the drain electrode layer, and the IGZO active layer;

[0012] S70. The device prepared in step S60 is subjected to X-ray irradiation. The irradiation source is an unfiltered molybdenum target X-ray tube. The irradiation process conditions are as follows: the accelerating voltage is fixed at 45 kV, the dose rate is 1000 rad / s (Si), and the processing time is 1000 s.

[0013] S80. The device after X-ray irradiation is subjected to low-temperature annealing. The low-temperature annealing conditions are: annealing in an atmospheric environment, annealing temperature of 300 ℃, and processing time of 1 h; finally, an IGZO thin film transistor resistant to space ionizing radiation is obtained.

[0014] Preferably, after the IGZO active layer is formed in step S40, it is annealed in an Ar atmosphere at a temperature of 350°C for 1 hour.

[0015] Preferably, in step S50, the overlap length between the source electrode layer, the drain electrode layer, and the gate electrode layer is 5 μm.

[0016] Preferably, after the passivation layer is applied in step S60, the material is annealed in an atmospheric environment at a temperature of 300°C for 1 hour.

[0017] The second objective of this invention is to provide an IGZO thin-film transistor resistant to space ionizing radiation, wherein the IGZO thin-film transistor is subjected to X-ray irradiation and low-temperature annealing at 300°C after molding, comprising:

[0018] Base;

[0019] A gate electrode layer disposed on a substrate;

[0020] A gate electrode layer and a gate dielectric layer on the substrate;

[0021] An IGZO active layer disposed on the gate dielectric layer;

[0022] Source electrode layer and drain electrode layer respectively located on both sides of the upper surface of the IGZO active layer;

[0023] A passivation layer covering the source electrode layer, drain electrode layer, and IGZO active layer.

[0024] Preferably, the substrate is a rigid substrate (silicon oxide).

[0025] Preferably, the gate electrode layer is a molybdenum (Mo) metal film with excellent conductivity, fabricated using magnetron sputtering, with a gate electrode layer thickness of 100 nm and a horizontal length of 105 μm; the source electrode layer and drain electrode layer are molybdenum (Mo) and aluminum (Al) metal films, fabricated using magnetron sputtering, with the molybdenum (Mo) metal layer thickness of 20 nm and the aluminum (Al) metal layer thickness of 100 nm.

[0026] Preferably, the gate dielectric layer is an aluminum oxide film layer, which is manufactured using the ALD process.

[0027] Preferably, the IGZO active layer is prepared using a magnetron sputtering process.

[0028] Preferably, the passivation layer is a silicon dioxide film layer, prepared using a PECVD process.

[0029] Preferably, during X-ray irradiation, the irradiation source is an unfiltered molybdenum target X-ray tube, and the irradiation process conditions are as follows: the accelerating voltage is fixed at 45 kV, the dose rate is 1000 rad / s (Si), and the processing time is 1000 s; the low-temperature annealing process conditions are as follows: annealing in an atmospheric environment, the annealing temperature is 300 ℃, and the processing time is 1 h.

[0030] Preferably, the gate dielectric layer has a thickness of 50 nm; the IGZO active layer has a thickness of 10 nm; and the passivation layer has a thickness of 200 nm.

[0031] Beneficial Effects: This invention induces the early generation of defects and H ions in the dielectric layer, passivation layer, and active layer of IGZO thin-film transistors through X-ray irradiation pretreatment. This, combined with 300℃ low-temperature annealing, achieves defect recombination and hydrogen removal, forming a stable radiation-resistant structure. Furthermore, compared to traditional methods that alter material properties and device structure, this invention significantly improves the resistance of IGZO thin-film transistors to space ionizing radiation by reducing the experimental annealing temperature and simplifying process steps. Attached Figure Description

[0032] To illustrate embodiments and / or examples of the invention more clearly and concisely, the present invention provides several accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed invention, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0033] Figure 1 This is a schematic diagram of the structure of an IGZO thin-film transistor after X-ray irradiation and annealing in an embodiment of the present invention. The numbers in the figure represent the following: 110. Substrate; 120. Gate electrode layer; 130. Gate dielectric layer; 140. IGZO active layer; 150. Source electrode layer; 152. Drain electrode layer; 160. Passivation layer;

[0034] Figure 2 This is a schematic diagram of the IGZO thin-film transistor in Comparative Example 1 without X-ray irradiation and annealing treatment. The numbers in the figure represent the following: 210. Substrate; 220. Gate electrode layer; 230. Gate dielectric layer; 240. IGZO active layer; 250. Source electrode layer; 252. Drain electrode layer; 260. Passivation layer;

[0035] Figure 3 This is a schematic diagram of the 45 nm thick IGZO thin-film transistor structure in Comparative Example 2, which has undergone X-ray irradiation and annealing treatment. The numbers in the figure represent the following: 310. Substrate; 320. Gate electrode layer; 330. Gate dielectric layer; 340. IGZO active layer; 350. Source electrode layer; 352. Drain electrode layer; 360. Passivation layer;

[0036] Figure 4 This is a flowchart of the manufacturing method of IGZO thin film transistors in an embodiment of the present invention;

[0037] Figure 5 This is a flowchart of the X-ray irradiation-annealing process for IGZO thin-film transistors in an embodiment of the present invention;

[0038] Figure 6 These are current curves of the IGZO thin-film transistors before and after γ-ray irradiation in the embodiments of the present invention and Comparative Examples 1 and 2.

[0039] Figure 7 This is a schematic diagram of the defect distribution of the IGZO thin film transistor in Comparative Example 1 after gamma ray irradiation without X-ray irradiation-annealing treatment;

[0040] Figure 8 This is a schematic diagram of the defect distribution of a 45 nm thick IGZO thin-film transistor after X-ray irradiation-annealing in Comparative Example 2.

[0041] Figure 9 This is a schematic diagram of the defect distribution of an IGZO thin-film transistor after X-ray irradiation-annealing in an embodiment of the present invention. Detailed Implementation

[0042] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0043] Example 1

[0044] Figure 1 Embodiments of the invention are given herein. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to enable the reader to gain a more thorough and complete understanding of the disclosure of the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0045] Figure 4 This is a flowchart of a method for manufacturing an IGZO thin-film transistor according to an embodiment of the present invention. This method can be used to manufacture... Figure 1 The IGZO thin-film transistor shown includes the following steps:

[0046] S10, obtain substrate 110.

[0047] The substrate can be a rigid substrate (e.g., glass) or a flexible substrate, as is known in the art. In one embodiment of the invention, the substrate is a semiconductor substrate, such as a silicon / silicon oxide substrate. The substrate is ultrasonically cleaned for five minutes each at 100 W in the order of deionized water, acetone, anhydrous ethanol, and then deionized water to obtain a substrate suitable for subsequent operations.

[0048] S20, a gate electrode layer 120 is formed on the substrate 110.

[0049] In one embodiment of the present invention, patterned photoresist is obtained by performing homogenization, photolithography, drying, exposure, and development on the surface of the substrate 110. Any residual photoresist in the patterned area is removed using a German photoresist stripper. A Mo metal layer is formed on the substrate 110 (at which point the patterned photoresist is present on the substrate surface) using magnetron sputtering. A lift-off process is then used to obtain the patterned gate electrode layer 120. Other materials / structures known in the art can also be used as the gate electrode layer. In this embodiment, the prepared gate electrode layer has a thickness of 100 nm and a horizontal length of 105 μm.

[0050] S30, a gate dielectric layer 130 is formed on the gate electrode layer 120 and the substrate 110.

[0051] In this embodiment, a gate dielectric layer 130 is deposited on the gate electrode layer 120 and the substrate 110 using an ALD process. The gate dielectric layer 130 is made of aluminum oxide. The ALD process parameters used in this embodiment are as follows: Al source pulse time is 20 ms, purge time is 25 s; H2O source pulse time is 20 ms, purge time is 20 s; the number of cycles is set to 200, the reaction chamber temperature is 200℃, the pressure is 33.3 Pa, and the N2 flow rate introduced into the chamber during the reaction is 20 sccm. In this embodiment, the thickness of the prepared gate dielectric layer 130 is 50 nm.

[0052] S40, an IGZO active layer 140 is formed on the gate dielectric layer 130.

[0053] In this embodiment, patterned photoresist is obtained by performing spin coating, photolithography, drying, exposure, and development on the surface of the gate dielectric layer 130. Any residual photoresist in the patterned area is removed using a German photoresist stripper. An IGZO semiconductor layer is formed on the gate dielectric layer 130 using magnetron sputtering. A lift-off process is then used to obtain a patterned IGZO active layer 140. The reaction conditions used in this embodiment are as follows: sputtering pressure 0.67 Pa, Ar:O2 ratio 50:0.5, sputtering power 60 W, and sputtering time 2120 s. Annealing is then performed. The annealing conditions in this embodiment are as follows: temperature 350 °C, annealing atmosphere Ar, and annealing time 1 h. In this embodiment, the thickness of the prepared IGZO active layer is 10 nm.

[0054] S50, a source electrode layer 150 and a drain electrode layer 152 are formed on the IGZO active layer 140.

[0055] In this embodiment, the IGZO active layer 140 and gate dielectric layer 130 are subjected to homogenization, photolithography, drying, exposure, and development processes to obtain patterned photoresist. A German photoresist stripper is used to remove any residual photoresist in the patterned areas. Mo and Al metal layers are then deposited on the IGZO active layer 140 and gate dielectric layer 130 using a measurement and control sputtering process. A lift-off process is then used to obtain the patterned source electrode layer 150 and drain electrode layer 152. In other embodiments, other materials known in the art can also be used as the source / drain electrode layer materials. In this embodiment, the Mo thickness in the prepared source electrode layer 150 and drain electrode layer 152 is 20 nm, and the Al thickness is 100 nm. The spacing between the source electrode layer 150 and drain electrode layer 152 is 100 μm, and there is a 5 μm overlap region between the source and drain electrode layers and the gate electrode layer at a horizontal position.

[0056] S60, a passivation layer 160 is formed on the IGZO active layer 140, the source electrode layer 150 and the drain electrode layer 152.

[0057] In this embodiment, a SiO2 passivation layer 160 is deposited on the IGZO active layer 140, source electrode layer 150, and drain electrode layer 152 using a PECVD process. An annealing treatment is then performed. The annealing conditions in this embodiment are as follows: temperature 300°C, annealing atmosphere air, and annealing time 1 h. In other embodiments, other materials known in the art can also be used as the passivation layer material. In this embodiment, the prepared SiO2 passivation layer has a thickness of 200 nm.

[0058] Figure 5 This is a flowchart of the X-ray irradiation-annealing process for IGZO thin-film transistors in an embodiment of the present invention. This method can be used to enhance... Figure 1 The radiation resistance of the IGZO thin-film transistor shown includes the following steps:

[0059] S70, the device is irradiated with X-rays.

[0060] In this embodiment, the device is irradiated using an unfiltered molybdenum target X-ray tube. The irradiation process conditions used in this embodiment are as follows: the accelerating voltage is fixed at 45 kV, the dose rate is 1000 rad / s (Si), and the irradiation time is 1000 s.

[0061] S80, the device irradiated by X-rays is annealed.

[0062] The annealing conditions in this embodiment are as follows: temperature is 300℃, annealing atmosphere is air, and annealing time is 1 h.

[0063] This application also provides an IGZO thin-film transistor without X-ray irradiation-annealing and a 45 nm IGZO thin-film transistor with X-ray irradiation-annealing as comparative examples, as follows:

[0064] Comparative Example 1

[0065] Similar to Example 1, except that this comparative example does not undergo X-ray irradiation-annealing treatment. Details are as follows:

[0066] like Figure 2 As shown, the IGZO thin-film transistor includes a substrate 210, a gate electrode layer 220, a gate dielectric layer 230, an IGZO active layer 240, a source electrode layer 250, a drain electrode layer 252, and a passivation layer 260. It should be noted that each film layer... Figure 2 The dimensions shown are for illustrative purposes only and do not represent the actual dimensions.

[0067] exist Figure 2 In Comparative Example 1 shown:

[0068] The gate electrode layer 220 is disposed on the substrate 210 and is made of Mo metal film.

[0069] The gate dielectric layer 230 is formed on the gate electrode layer 220 and the substrate 210 and completely covers the gate electrode layer 220. The material is aluminum oxide.

[0070] The IGZO active layer 240 is formed on the gate dielectric layer 230.

[0071] The source electrode layer 250 and the drain electrode layer 252 are spaced apart on opposite sides of the surface of the IGZO active layer 240. The source electrode layer 250 and the drain electrode layer 252 are both Mo and Al metal films. The source electrode layer 250 and the drain electrode layer 252 have a 5 μm overlap with the gate electrode layer 220 in the horizontal direction.

[0072] The passivation layer 260 is formed on the IGZO active layer 240, the source electrode layer 250 and the drain electrode layer 252 and completely covers the IGZO active layer 240, the source electrode layer 250 and the drain electrode layer 252.

[0073] exist Figure 2In the comparative example shown, the gate electrode layer 220 has a thickness of 100 nm and a length of 105 μm, the gate dielectric layer 230 has a thickness of 50 nm, the IGZO active layer 240 has a thickness of 10 nm, the source electrode layer 250 and the drain electrode layer 252 have a Mo thickness of 20 nm and an Al thickness of 100 nm, the spacing between the source electrode layer 250 and the drain electrode layer 252 is 100 μm, and the passivation layer 260 has a thickness of 200 nm.

[0074] Comparative Example 2

[0075] Similar to Example 1, except that the thickness of the IGZO active layer 340 in this comparative example is adjusted to 45 nm. Specifically:

[0076] like Figure 3 As shown, the IGZO thin-film transistor includes a substrate 310, a gate electrode layer 320, a gate dielectric layer 330, an IGZO active layer 340, a source electrode layer 350, a drain electrode layer 352, and a passivation layer 360. It should be noted that each film layer... Figure 3 The dimensions shown are for illustrative purposes only and do not represent the actual dimensions.

[0077] exist Figure 3 In Comparative Example 2 shown:

[0078] The gate electrode layer 320 is disposed on the substrate 310 and is made of Mo metal film.

[0079] The gate dielectric layer 330 is formed on the gate electrode layer 320 and the substrate 310 and completely covers the gate electrode layer 320. The material is aluminum oxide.

[0080] The IGZO active layer 340 is formed on the gate dielectric layer 330.

[0081] The source electrode layer 350 and the drain electrode layer 352 are spaced apart on opposite sides of the surface of the IGZO active layer 340. The source electrode layer 350 and the drain electrode layer 352 are both Mo and Al metal films. The source electrode layer 350 and the drain electrode layer 352 have a 5 μm overlap with the gate electrode layer 320 in the horizontal direction.

[0082] The passivation layer 360 is formed on the IGZO active layer 340, the source electrode layer 350 and the drain electrode layer 352 and completely covers the IGZO active layer 340, the source electrode layer 350 and the drain electrode layer 352.

[0083] The device covered with the passivation layer 360 was then subjected to X-ray irradiation and annealing: The device was irradiated using an unfiltered molybdenum target X-ray tube. The irradiation conditions used in this comparative example were as follows: accelerating voltage fixed at 45 kV, dose rate 1000 rad / s (Si), and irradiation time 1000 s. The X-ray-irradiated device was then annealed under the following conditions: temperature 300℃, annealing atmosphere air, and annealing time 1 h.

[0084] exist Figure 3 In Comparative Example 2 shown, the gate electrode layer 320 has a thickness of 100 nm and a length of 105 μm, the gate dielectric layer 330 has a thickness of 50 nm, the IGZO active layer 340 has a thickness of 45 nm, the source electrode layer 350 and the drain electrode layer 352 have a Mo thickness of 20 nm and an Al thickness of 100 nm, the distance between the source electrode layer 250 and the drain electrode layer 252 is 100 μm, and the passivation layer 360 has a thickness of 200 nm.

[0085] Figure 6 These are current curves of the IGZO thin-film transistors in the embodiments of the present invention and Comparative Examples 1 and 2 before and after gamma-ray irradiation. The vertical axis represents the magnitude of the drain electrode layer current, and the horizontal axis represents the magnitude of the applied gate electrode layer voltage. It can be seen that, compared to the device without X-ray irradiation-annealing treatment (Comparative Example 1), the treated device exhibits a significantly reduced negative threshold voltage drift after gamma-ray irradiation, decreasing by approximately 6.1 V; the subthreshold characteristic degradation is also significantly reduced, with the subthreshold swing decreasing by approximately 261 mV / dec. Compared to the 45 nm thick IGZO TFT device that underwent X-ray irradiation-annealing treatment (Comparative Example 2), the device in the embodiments exhibits a significantly reduced negative threshold voltage drift after gamma-ray irradiation, decreasing by approximately 1.8 V; the subthreshold characteristic degradation is also significantly reduced, with the subthreshold swing decreasing by approximately 60 mV / dec.

[0086] Table 1 is a summary table of the changes in electrical performance of the IGZO thin film transistors of the present invention and Comparative Examples 1 and 2 after gamma-ray irradiation; including threshold voltage, mobility, and subthreshold swing.

[0087] Table 1

[0088] As can be seen from Table 1, the embodiment reduced the negative threshold voltage drift caused by gamma-ray radiation compared to the comparative example, improved the subthreshold performance, and greatly enhanced the radiation resistance of the IGZO thin film transistor.

[0089] Figure 7This is a schematic diagram of the defect distribution of the IGZO thin film transistor in Comparative Example 1 of the present invention after being irradiated with γ-rays; including positive oxide trap charges in the passivation layer and the gate dielectric layer, interface defects between the passivation layer and the active layer, interface defects between the active layer and the gate dielectric layer, and H ions in the active layer.

[0090] Figure 8 This is a schematic diagram of the defect distribution of the IGZO thin film transistor in Comparative Example 2 of the present invention after γ-ray irradiation; including positive oxide trap charges in the passivation layer and the gate dielectric layer, interface defects between the passivation layer and the active layer, interface defects between the active layer and the gate dielectric layer, and H ions in the active layer.

[0091] Figure 9 This is a schematic diagram of the defect distribution of an IGZO thin-film transistor after gamma-ray irradiation in an embodiment of the present invention; it includes positive oxide trap charges in the passivation layer and the gate dielectric layer, interface defects between the passivation layer and the active layer, interface defects between the active layer and the gate dielectric layer, and H ions in the active layer. Compared with the comparative example, this embodiment effectively reduces the number of positive oxide trap charges, interface defects, and H ions generated by gamma-ray irradiation, forming a stable radiation-resistant structure, thereby enhancing the device's radiation resistance.

[0092] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating an IGZO thin-film transistor resistant to space ionizing radiation, characterized in that, The steps are as follows: S10. Obtain the substrate (110); S20. A gate electrode layer (120) is formed on the substrate (110). S30. A gate dielectric layer (130) is covered on the gate electrode layer (120) and the substrate (110). S40. An IGZO active layer (140) is formed on the gate dielectric layer (130). S50. A source electrode layer (150) and a drain electrode layer (152) are formed at intervals on both sides of the upper surface of the IGZO active layer (140), and the source electrode layer (150) and the drain electrode layer (152) overlap with both sides of the gate electrode layer (120) in the horizontal direction. S60. A passivation layer (160) is covered on the source electrode layer (150), the drain electrode layer (152) and the IGZO active layer (140). S70. The device prepared in step S60 is subjected to X-ray irradiation. The irradiation source is an unfiltered molybdenum target X-ray tube. The irradiation process conditions are as follows: the accelerating voltage is fixed at 45 kV, the dose rate is 1000 rad / s (Si), and the processing time is 1000 s. S80. The device after X-ray irradiation is subjected to low-temperature annealing. The low-temperature annealing conditions are: annealing in an atmospheric environment, annealing temperature of 300℃, and processing time of 1h; finally, an IGZO thin film transistor resistant to space ionizing radiation is obtained.

2. The method for fabricating an IGZO thin-film transistor resistant to space ionizing radiation according to claim 1, characterized in that, After the IGZO active layer (140) is formed in step S40, it is annealed in an Ar atmosphere at a temperature of 350 °C for 1 h.

3. The method for fabricating an IGZO thin-film transistor resistant to space ionizing radiation according to claim 1, characterized in that, In step S50, the overlap length between the source electrode layer (150) and the drain electrode layer (152) and the gate electrode layer (120) is 5 μm.

4. The method for fabricating an IGZO thin-film transistor resistant to space ionizing radiation according to claim 1, characterized in that, After the passivation layer (160) is covered in step S60, the material is annealed in an atmospheric environment at a temperature of 300°C for 1 hour.

5. A space ionizing radiation resistant IGZO thin-film transistor, characterized in that, The IGZO thin-film transistor, after being formed, undergoes X-ray irradiation and low-temperature annealing at 300°C, including: Base (110); A gate electrode layer (120) is disposed on a substrate (110). A gate dielectric layer (130) is covered on the gate electrode layer (120) and the substrate (110). An IGZO active layer (140) is disposed on the gate dielectric layer (130). Source electrode layer (150) and drain electrode layer (152) are respectively disposed on both sides of the upper surface of the IGZO active layer (140). A passivation layer (160) is applied to the source electrode layer (150), the drain electrode layer (152), and the IGZO active layer (140).

6. The IGZO thin-film transistor resistant to space ionizing radiation according to claim 5, characterized in that, The gate electrode layer (120) is a molybdenum metal film layer; the source electrode layer (150) and the drain electrode layer (152) are molybdenum and aluminum metal films.

7. The IGZO thin-film transistor resistant to space ionizing radiation according to claim 5, characterized in that, The gate dielectric layer (130) is an aluminum oxide film.

8. The IGZO thin-film transistor resistant to space ionizing radiation according to claim 5, characterized in that, The passivation layer (160) is a silicon dioxide film.

9. The IGZO thin-film transistor resistant to space ionizing radiation according to claim 5, characterized in that, During the X-ray irradiation, the irradiation source is an unfiltered molybdenum target X-ray tube, and the irradiation process conditions are as follows: the accelerating voltage is fixed at 45 kV, the dose rate is 1000 rad / s (Si), and the processing time is 1000 s; the low-temperature annealing process conditions are as follows: annealing in an atmospheric environment, the annealing temperature is 300 ℃, and the processing time is 1 h.

10. The IGZO thin-film transistor resistant to space ionizing radiation according to claim 5, characterized in that, The gate dielectric layer (130) has a thickness of 50 nm; the IGZO active layer (140) has a thickness of 10 nm; and the passivation layer (160) has a thickness of 200 nm.

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