Preparation method of low-temperature deposited silicon dioxide passivation layer

Abstract

The invention relates to a preparation method of a low-temperature deposited silicon dioxide passivation layer, which comprises the following steps of: firstly, selecting an n-type silicon wafer etched with a pyramid structure, and cleaning to remove pollutants on the surface of the n-type silicon wafer; h2SO4 and H2O in a volume ratio of 2: 50 are mixed to form a 5% dilute sulphuric acid aqueous solution; secondly, taking the pretreated n-type silicon wafer as a working electrode and platinum as a counter electrode, connecting an electrochemical workstation and setting a constant potential mode; applying 0.8 V voltage to the counter electrode at the normal temperature of 20-27 DEG C, and growing a 2-5nm silicon dioxide passivation layer on the substrate n-type silicon wafer; and finally, after deposition of the silicon dioxide passivation layer is completed, washing the silicon wafer with deionized water, and carrying out nitrogen blow-drying or normal-temperature airing. The method is realized through electrochemical anodic oxidation: the working temperature is the normal temperature of 23-27 DEG C, spontaneous heating is performed to 80 DEG C, the energy consumption is only 3-5% of that of a thermal oxidation method, the equipment requirement is low, and the method can be realized through a standard electrochemical workstation.

Description

Technical Field

[0001] This invention relates to the technical field of material preparation, and more specifically, to a method for preparing a low-temperature deposited silicon dioxide passivation layer. Background Technology

[0002] Solar cells are one of the core technologies of renewable energy. Among them, silicon-based solar cells, such as monocrystalline silicon and polycrystalline silicon cells, dominate the global photovoltaic market, accounting for more than 90% of the market share, due to their high conversion efficiency, stability, and mature manufacturing processes. However, silicon wafers have a large number of dangling bonds on their surface. These dangling bonds can form carrier recombination centers, causing photogenerated electrons and holes to recombine before reaching the electrodes, resulting in energy loss and reducing the cell's open-circuit voltage and photoelectric conversion efficiency.

[0003] To reduce carrier recombination and improve battery efficiency, scientists employ surface passivation technology, which involves coating the silicon wafer with a passivation layer such as SiO2, Al2O3, or SiN. x Passivation materials are used to "passivate" these dangling bonds and prevent carrier recombination. Among them, silicon dioxide (SiO2) is one of the most ideal passivation materials due to its perfect lattice matching with silicon, few interface defects, and high chemical stability.

[0004] Currently, the commonly used SiO2 deposition methods in industry mainly include:

[0005] I. Thermal Oxidation Method: This method involves reacting silicon (Si) with oxygen (O2) or water vapor (H2O) at a high temperature of 800-1200℃ to form a dense SiO2 passivation layer on the silicon surface. This method is extremely energy-intensive, complex, and the high temperature may cause silicon wafer deformation and impurity diffusion, making it unsuitable for temperature-sensitive materials such as flexible devices.

[0006] II. Plasma-Enhanced Chemical Vapor Deposition (PECVD): This method uses radio frequency or microwave-excited plasma to decompose silicon source gases such as SiH4 or tetraethyl orthosilicate, and oxygen source gases such as O2 or N2O, at 200–400°C, achieving efficient SiO2 deposition. This method involves expensive equipment, low deposition rates, and requires precise control of gas ratios and temperature.

[0007] Therefore, the existing technology has problems and needs further improvement and development. Summary of the Invention

[0008] (I) Purpose of the invention: In order to solve the problems existing in the prior art, the purpose of the present invention is to provide a method for preparing a low-temperature deposited silicon dioxide passivation layer.

[0009] (II) Technical Solution: To solve the above-mentioned technical problems, a method for preparing a low-temperature deposited silicon dioxide passivation layer is provided, comprising the following steps:

[0010] First: Select an n-type silicon wafer with an etched pyramid structure, and clean it to remove contaminants from the surface of the n-type silicon wafer; then mix H2SO4 and H2O in a volume ratio of 2:50 to form a 5% dilute sulfuric acid aqueous solution.

[0011] Next, the pretreated n-type silicon wafer was used as the working electrode and platinum as the counter electrode. The electrochemical workstation was connected and the constant potential mode was set. At room temperature of 20° to 27°, a voltage of 0.8V was applied relative to the counter electrode to grow a 2-5nm silicon dioxide passivation layer on the substrate n-type silicon wafer.

[0012] Finally, after the silicon dioxide passivation layer is deposited, rinse the silicon wafer with deionized water and dry it with nitrogen or air dry at room temperature.

[0013] The method for preparing a low-temperature deposited silicon dioxide passivation layer, wherein the resistivity of the n-type silicon wafer is 2.8 Ω·cm and the thickness is 300 μm.

[0014] The method for preparing a low-temperature deposited silicon dioxide passivation layer includes an electrochemical workstation that further comprises an Ag / AgCl reference electrode, a working electrode formed by the substrate n-type silicon wafer, and a counter electrode, forming a three-electrode system for real-time monitoring and calibration of the working electrode potential, controlling the potential fluctuation range to ≤ ±0.02V.

[0015] The method for preparing a low-temperature deposited silicon dioxide passivation layer includes a three-electrode system that further comprises a dynamic potential calibration module. This module is pre-set with potential reference frames for different deposition stages: the potential fluctuation threshold during the initial film formation stage is ≤ ±0.01V, the potential fluctuation threshold during the stable growth stage is ≤ ±0.02V, and the potential fluctuation threshold during the passivation layer repair stage is ≤ ±0.015V. When the Ag / AgCl reference electrode detects that the working electrode potential exceeds the current stage threshold, it automatically triggers the electrode current fine-tuning region within ±0.5~2mA, with a response time ≤0.5s.

[0016] The method for preparing a low-temperature deposited silicon dioxide passivation layer includes an electrochemical workstation that further comprises a multi-parameter linkage unit. This unit couples and calculates the real-time potential data of the reference electrode with the electrolyte temperature and deposition time: automatically compensating for a potential of -0.001V for every 1°C increase in temperature; and automatically shortening the subsequent deposition time by 10% to 15% based on the potential change rate when the deposition thickness reaches 80% of the target value.

[0017] The method for preparing a low-temperature deposited silicon dioxide passivation layer includes a pyramid structure prepared by a wet etching process. The etching solution is a NaOH aqueous solution with a mass concentration of 1% to 5%. The reaction is carried out at 80 to 90°C for 20 to 30 minutes to form a pyramid-like surface with a height of 1 to 3 μm and a base length of 2 to 5 μm. The spacing between adjacent pyramid structures is ≤1 μm.

[0018] The method for preparing a low-temperature deposited silicon dioxide passivation layer includes a pyramid structure with a surface coverage of ≥90%, and a pyramid height at the edge of the silicon wafer that is 10% to 15% lower than that at the center, in order to reduce the passivation layer thickness deviation caused by edge effects.

[0019] The method for preparing a low-temperature deposited silicon dioxide passivation layer, wherein the exposure rate of the (111) crystal plane of the pyramid structure is ≥85%, and after pretreatment with hydrofluoric acid solution for 3-5 minutes to remove the natural oxide layer on the surface, electrochemical deposition is immediately performed to ensure that the interfacial contact resistance between the passivation layer and the silicon substrate is ≤10Ω·cm. 2 .

[0020] (III) Beneficial Effects: The low-temperature deposition method for preparing a silicon dioxide passivation layer based on electrochemical anodic oxidation provided by this invention firstly improves minority carrier lifetime: unpassivated n-Si: 163.8 μs, after electrochemical SiO2 passivation: 384 μs, a 135% increase in minority carrier lifetime, significantly improving passivation performance. Increased minority carrier lifetime indicates effective suppression of carrier recombination, directly increasing the battery open-circuit voltage (Voc). Secondly, photoelectric conversion efficiency (PCE): without SiO2 passivation: 12.46%, after introducing electrochemical SiO2: 13.49%, an absolute efficiency increase of 1.03%; a significant breakthrough in battery efficiency. This invention achieves this through electrochemical anodic oxidation: the operating temperature is room temperature (23℃-27℃), it self-heats to 80℃, and the energy consumption is only 3-5% of that of thermal oxidation methods. Equipment requirements are low; a standard electrochemical workstation is sufficient. Attached Figure Description

[0021] Figure 1 This is a flowchart of a method for preparing a low-temperature deposited silicon dioxide passivation layer according to the present invention.

[0022] Figure 2 This is a schematic diagram of the workflow of the electrochemical workstation of this invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to preferred embodiments. More details are set forth in the following description in order to provide a full understanding of the present invention. However, the present invention can obviously be implemented in many other ways different from those described herein. Those skilled in the art can make similar extensions and derivations based on actual application situations without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention should not be limited by the content of this specific embodiment.

[0024] The accompanying drawings are schematic diagrams of embodiments of the present invention. It should be noted that these drawings are for illustrative purposes only and are not drawn to scale, and should not be construed as limiting the actual scope of protection of the present invention.

[0025] The abbreviations and key terms used in the method for preparing a low-temperature deposited silicon dioxide passivation layer of the present invention are defined as follows:

[0026] n-Si (n-type silicon): Silicon semiconductors doped with pentavalent elements such as phosphorus (P) or arsenic (As), with electrons as the majority of charge carriers.

[0027] Charge carriers are charged particles in semiconductors or conductors that can move freely and conduct current. They mainly include electrons, which are negatively charged, and holes, which are positively charged. Essentially, they are the vacancies left behind after electrons move.

[0028] Photogenerated carriers: Electron-hole pairs excited by semiconductor materials after absorbing photon energy under illumination.

[0029] Photogenerated carrier recombination refers to the process by which electron-hole pairs generated in semiconductors, such as silicon, under illumination recombine and disappear due to defects, impurities, or surface states before being collected by electrodes. This process leads to the conversion of light energy into heat energy instead of electrical energy, and is one of the main reasons for the efficiency loss of solar cells.

[0030] Dangling bonds: Chemical bonds on the silicon surface that are not bonded to other atoms can trap electrons or holes, leading to recombination of photogenerated carriers.

[0031] Passivation: Eliminating dangling bonds by covering with a layer of material, thereby reducing photogenerated carrier recombination losses.

[0032] like Figure 1 , Figure 2 As shown, the method for preparing a low-temperature deposited silicon dioxide passivation layer based on electrochemical anodic oxidation of the present invention includes the following steps:

[0033] Step 1: Silicon Wafer Pretreatment

[0034] Substrate selection: Use n-type silicon wafers (n-Si) with an etched pyramid structure, resistivity ~2.8Ω·cm, thickness ~300μm, and clean the n-type silicon wafers with the etched pyramid structure to remove contaminants on the surface of the n-type silicon wafers, including organic matter, metal ions, etc., to ensure that the surface of the n-type silicon wafers is clean.

[0035] Step 2: Electrolyte preparation

[0036] A 5% dilute sulfuric acid aqueous solution is prepared by mixing H2SO4 and H2O at a volume ratio of 2:50. The dilute sulfuric acid electrolyte must be uniformly mixed to avoid excessively high local concentrations. This invention can also replace H2SO4 with other oxidizing electrolytes; this is not a limitation.

[0037] Step 3: The electrochemical workstation comprises: a counter electrode (platinum (Pt) electrode), a potential calibration reference electrode (Ag / AgCl electrode), and a working electrode. The counter electrode, potential calibration reference electrode, and working electrode are interconnected to form a three-electrode system, constituting the electrochemical workstation. The electrochemical workstation is set to a constant potential mode. The pretreated n-Si substrate must be completely immersed in the electrolyte prepared in Step 2, and the electrolyte containing the n-Si substrate is placed in the electrochemical workstation, using the n-Si substrate as the working electrode.

[0038] Step 4: Deposition process parameters

[0039] The preparation temperature of this invention is 20°C to 27°C, preferably 25°C, without the need for indoor heating. A voltage of 0.8V is applied to the working electrode relative to the counter electrode. The deposition reaction time is adjusted according to the thickness of the silicon dioxide passivation layer deposited on the n-type silicon wafer n-Si, preferably at room temperature to oxidize and generate a 2-5nm SiO2 layer.

[0040] The reaction mechanism of the oxidation reaction process in the low-temperature deposition method for preparing a silicon dioxide passivation layer based on electrochemical anodic oxidation of this invention is as follows:

[0041] An electric field drives oxygen-containing substances, such as H2O, OH-, and O. 2- It reacts with the dangling bonds on the silicon surface to generate SiO2.

[0042] Step 5: Post-processing and characterization

[0043] The low-temperature deposited silica passivation layer is rinsed with deionized water to remove residual electrolyte, and then dried by blowing with nitrogen or air drying at room temperature.

[0044] In a preferred embodiment of the method for preparing a low-temperature deposited silicon dioxide passivation layer according to the present invention, the three-electrode system further includes a dynamic potential calibration module. This module is preset with potential reference frameworks for different deposition stages: during the initial film formation period, the potential fluctuation threshold within 0–50 s is ≤ ±0.01 V; during the stable growth region, the potential fluctuation threshold within 50–300 s is ≤ ±0.02 V; and during the passivation layer repair period, the potential fluctuation threshold within 300–400 s is ≤ ±0.015 V. When the Ag / AgCl reference electrode detects that the working electrode potential exceeds the current stage threshold, it automatically triggers the electrode current fine-tuning region of ±0.5–2 mA with a response time ≤ 0.5 s.

[0045] The electrochemical workstation described in this invention also includes a multi-parameter linkage unit. This unit couples and calculates the real-time potential data of the reference electrode with the electrolyte temperature and deposition time: for every 1°C increase in temperature, it automatically compensates for a potential of -0.001V; when the deposition thickness reaches 80% of the target value, it automatically shortens the subsequent deposition time by 10%–15% based on the potential change rate to avoid interface defects caused by over-deposition. Preferably, the electrolyte temperature is generally between 20 and 27°C, and the deposition time is between 10 and 20 minutes. The potential change rate (dE / dt) refers to the real-time rate of change of the working electrode potential (E) with time (t), and its mathematical expression is the potential change ΔE / Δt per unit time, usually expressed in volts or millivolts per second.

[0046] In a preferred embodiment of the method for preparing a low-temperature deposited silicon dioxide passivation layer according to the present invention, the pyramid structure is prepared by a wet etching process, wherein the etching solution is a NaOH aqueous solution with a mass concentration of 1% to 5%, and the reaction is carried out at 80 to 90°C for 20 to 30 minutes to form a pyramid-like surface with a height of 1 to 3 μm and a base length of 2 to 5 μm, and the spacing between adjacent pyramid structures is ≤1 μm.

[0047] In a preferred embodiment of the method for preparing a low-temperature deposited silicon dioxide passivation layer according to the present invention, the surface coverage of the pyramid structure is ≥90%, which is the ratio of the actual surface area of ​​the n-type silicon wafer occupied by the pyramid structure to the total exposed surface area of ​​the n-type silicon wafer. For example, if the front surface area of ​​the n-type silicon wafer is 100 mm²... 2 90mm 2 The above-mentioned area is covered by a pyramid structure. Preferably, in the edge region of the n-type silicon wafer, the height of the pyramid within 5 mm from the edge is reduced by 10% to 15% compared to the center region, in order to reduce the passivation layer thickness deviation caused by edge effects.

[0048] In another preferred embodiment of the method for preparing a low-temperature deposited silicon dioxide passivation layer, the (111) crystal plane exposure rate of the pyramid structure is ≥85%, and after pretreatment with hydrofluoric acid solution (5% volume concentration) for 3-5 minutes to remove the natural oxide layer on the surface, electrochemical deposition is immediately performed to ensure that the interfacial contact resistance between the passivation layer and the silicon substrate is ≤10Ω·cm. 2 The (111) crystal face exposure rate of the pyramid structure refers to the percentage of the area of ​​the (111) crystal face exposed on the surface of the pyramid structure to the total surface area of ​​the pyramid structure.

[0049] This invention provides a method for preparing a low-temperature deposited silicon dioxide passivation layer. Firstly, the minority carrier lifetime is improved: without passivation n-Si: 163.8 μs; after electrochemical SiO2 passivation: 384 μs, a 135% increase in minority carrier lifetime, significantly improving passivation performance. Increased minority carrier lifetime indicates effective suppression of carrier recombination, directly increasing the battery open-circuit voltage (Voc). Secondly, the photoelectric conversion efficiency (PCE) is improved: without SiO2 passivation: 12.46%; after introducing electrochemical SiO2: 13.49%, an absolute efficiency improvement of 1.03%; a significant breakthrough in battery efficiency. This invention achieves this through electrochemical anodic oxidation: the operating temperature is room temperature (23℃-27℃), it self-heats to 80℃, and the energy consumption is only 3-5% of that of thermal oxidation methods. The equipment requirements are low; a standard electrochemical workstation is sufficient.

[0050] The above description illustrates preferred embodiments of the present invention and helps those skilled in the art to more fully understand the technical solution of the present invention. However, these embodiments are merely illustrative and should not be construed as limiting the specific implementation of the present invention to these embodiments. For those skilled in the art, several simple deductions and modifications can be made without departing from the inventive concept, and all such modifications should be considered within the protection scope of the present invention.

Claims

1. A method for producing a low-temperature deposited silicon dioxide passivation layer, characterized in that The method comprises the following steps: Firstly, select n-type silicon wafer etched with pyramid structure, clean the surface of the n-type silicon wafer to remove contaminants; And adopt H2SO4 and H2O mixed in a volume ratio of 2:50 to form a 5% dilute sulfuric acid aqueous solution; Secondly, use the pretreated n-type silicon wafer as the working electrode, platinum as the counter electrode, connect the electrochemical workstation and set the constant potential mode; apply a voltage of 0.8V to the counter electrode at room temperature of 20-27℃, and grow a 2-5nm silicon dioxide passivation layer on the substrate n-type silicon wafer; Finally, after the deposition of the silicon dioxide passivation layer is completed, rinse the silicon wafer with deionized water, and dry it with nitrogen or air dry at room temperature.

2. The method of claim 1, wherein the low temperature deposition of the silicon dioxide passivation layer is performed at a temperature of 300 °C or less. The resistivity of the n-type silicon wafer is 2.8Ω·cm, and the thickness is 300μm.

3. The method of claim 1, wherein the low temperature deposition of the silicon dioxide passivation layer is performed at a temperature of 300 °C or less. The electrochemical workstation also includes an Ag / AgCl reference electrode, which forms a three-electrode system with the working electrode and the counter electrode formed by the substrate n-type silicon wafer, for real-time monitoring and calibration of the potential of the working electrode, and the potential fluctuation range is controlled to be ≤±0.02V.

4. The method of claim 3, wherein the low-temperature deposited silicon dioxide passivation layer is formed by a plasma enhanced chemical vapor deposition process. The three-electrode system also includes a dynamic potential calibration module, which is pre-set with a potential reference framework for different deposition stages: the potential fluctuation threshold of the initial film formation period is ≤±0.01V, the potential fluctuation threshold of the stable growth region is ≤±0.02V, and the potential fluctuation threshold of the passivation layer repair period is ≤±0.015V; when the Ag / AgCl reference electrode detects that the potential of the working electrode exceeds the threshold of the current stage, the counter electrode current fine-tuning area is automatically triggered in the range of ±0.5-2mA, and the response time is ≤0.5s.

5. The method for preparing a low-temperature deposited silicon dioxide passivation layer according to claim 1, characterized in that, The electrochemical workstation also includes a multi-parameter linkage unit, which couples the real-time potential data of the reference electrode with the electrolyte temperature and deposition time for coupled calculation: when the temperature increases by 1℃, the potential is automatically compensated by-0.001V; when the deposition thickness reaches 80% of the target value, the subsequent deposition time is automatically shortened by 10%-15% based on the potential change rate.

6. The method for preparing a low-temperature deposited silicon dioxide passivation layer according to claim 1, characterized in that, The pyramid structure is prepared by a wet etching process, and the etching solution is a NaOH aqueous solution with a mass concentration of 1%-5%, which is reacted at 80-90℃ for 20-30 minutes to form a pyramid-like surface with a height of 1-3μm and a bottom edge length of 2-5μm, and the distance between adjacent pyramid structures is ≤1μm.

7. The method of claim 1, wherein the low temperature deposition of the silicon dioxide passivation layer is performed at a temperature of 300 °C or less. The surface coverage of the pyramid structure is ≥90%, and the pyramid height in the edge region of the silicon wafer is reduced by 10%-15% compared with the center region, so as to reduce the thickness deviation of the passivation layer caused by the edge effect.

8. The method for preparing a low-temperature deposited silicon dioxide passivation layer according to claim 1, characterized in that, The 111 crystal face exposure rate of the pyramid structure is greater than or equal to 85%, and after the surface natural oxide layer is removed by pretreatment with a hydrofluoric acid solution for 3-5 minutes, electrochemical deposition is immediately performed, so that the interface contact resistance between the passivation layer and the silicon wafer substrate is less than or equal to 10 Ω·cm 2 .

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