MIMO equalizer circuit, communication unit and method for successive interference cancellation

Abstract

The MIMO equalizer circuit (300) includes: a controller (339); a calculation circuit (302) generates and outputs an autocorrelation matrix W (308) in response to receiving the covariance matrix RI (123) and the channel estimation matrix H (121). A matrix calculation circuit (316) that receives and combines the inverse autocorrelation matrix (315) and the channel estimation matrix H (121), and outputs an equalization gain P matrix (324); an inverse autocorrelation matrix (315), a received signal vector y (301), and a channel estimation matrix H (121) are received and combined, and a vector'f '(323) is output. A successive interference cancellation (SIC) detection circuit (325) converts the received P matrix (324) into a first orthogonal unitary matrix Q (328) and a first upper triangular matrix R (327), and converts the matrix Q (328), the matrix R (327), and the f vector (323) into an SIC estimated equalization symbol Z2 vector (330), which is output.

Description

Technical Field

[0001] This invention relates to a communication unit and method for continuous interference cancellation (SIC) in equalizers. The invention is applicable to, but not limited to, multiple-input multiple-output (MIMO) equalization based on current and future generations of communication criteria, particularly those that may employ minimum mean square error interference suppression combining (MMSE-IRC) equalizer circuitry based on continuous interference cancellation (SIC). Background Technology

[0002] The most promising wireless technologies that can effectively improve data transmission rates must also be able to expand system coverage and enhance link reliability. Figure 1 An exemplary multiple-input multiple-output (MIMO) communication system is shown, wherein the number of transmit antenna elements is equal to the number of transmit antenna ports N. T The number of receiving antenna elements is equal to the number of receiving antenna ports N. R Here, the information bits 102 to be transmitted are mapped to Quadrature Amplitude Modulation (QAM) symbols by QAM mapper 103. These QAM symbols are then mapped to N by layer mapper 104. L A transport layer. Then, the MIMO precoder 105 is used to project QAM symbols from the transport layer onto N. T On each transmit antenna port.

[0003] Specifically, the precoding matrix generated by the precoder is applied to QAM symbols on the transport layer, where the first dimension of the precoding matrix is ​​the number of transport layers N. L The second dimension is the number of transmit antenna ports N. T This allows the number of transmission layers in a MIMO communication system to vary during operation, even if the number of transmit and receive antenna elements for a given device is fixed. Specifically, the demodulation reference signal (DM-RS) generator 130 generates a signal from N based on the reference signal configuration 131. L The demodulation reference signal (DM-RS) symbol 132 for each layer. The pre-encoder projects the DM-RS symbol onto N. T On each transmit antenna port, the precoded symbols are mapped to the allocated physical resources by RE mapper 106, followed by digital beamforming 107, orthogonal frequency division multiplexing (OFDM) modulation 108, cyclic prefix (CP) insertion, and analog beamforming 109. Finally, the radio frequency (RF) stage 110 is used to transmit the signal to the transmit antenna element set, which, in the case of beamforming, may exceed N. TA transmit antenna port, especially in the downlink. It should be noted that in some applications, some or all of the steps in precoding, digital beamforming, and analog beamforming can be omitted or combined. Then, OFDM symbols are simultaneously transmitted by transmit antenna element 111 and reach receive antenna element 113, where the received signal is affected by fading channel 112, noise 114, and inter-cell or inter-user interference 133, as detailed below.

[0004] The receiver's RF stage 110 collects the signals output from each receive antenna element 113, then performs analog beamforming 116, OFDM demodulation 117, CP removal, and digital beamforming 118 to generate signals for the receive antenna ports, where the number of receive antenna ports may be less than the number of receive antenna elements. In a multi-user MIMO system with uplink beamforming, each user simultaneously scheduled to the same time and frequency resources may be represented by different subsets of these receive antenna ports and may also be subject to some residual interference from other simultaneously scheduled users. The number of receive antenna ports allocated to a particular user to receive the signal can be represented by N. R This indicates that the number may change during runtime, depending on the number of users co-scheduling. For example, a receiver may have '64' receive antenna elements, which, after beamforming, provide '16' receive antenna ports.

[0005] Assuming there are 8 users co-scheduling, each user may be assigned a different set of receive antenna ports, N. R =2. In other cases, assume there are 16 users co-scheduled, and each user is allocated N receiver antenna ports. R =1. Therefore, the number N receiving antenna ports allocated to a specific user is... R This may change at runtime. It's important to note that in some applications, some or all of the precoding, digital beamforming, and analog beamforming may be omitted or combined. (N for a specific user) R The demodulated frequency domain signal at each receiving antenna port is demapped by RE demapper 119, and then the channel estimation matrix H 121 is obtained by using channel estimator 120, and the equalization signal 126 is obtained by MIMO equalizer 125. Specifically, as Figure 1 As shown, the signal is mixed together through a multipath channel in the air, where the channel estimator attempts to estimate the information of the multipath channel 112 and the MIMO equalizer 125 will use the channel estimation matrix H 121 to recover the mixed signal, where the MIMO deprecoding operation has been integrated into the channel estimator 120.

[0006] Then, by using the layer demapper 127, N LThe MIMO equalization signal 126 on the layer is demapped into a symbol sequence. The symbol sequence is typically demapped into soft bits or hard bits 129 by the QAM demapper 128. Similar to hard bits, soft bits represent the most likely value of each bit. However, unlike hard bits, soft bits also represent the probability of that bit value. Soft bits are typically represented using the log-likelihood ratio (LLR), where in some applications LLR = ln[Pr(bit=0) / Pr(bit=1)], and in other applications LLR = ln[Pr(bit=1) / Pr(bit=0)]. Specifically, MIMO equalizers play an important role in combating inter-symbol interference, where MIMO equalizers based on the minimum mean square error (MMSE) and MMSE interference suppression combined (MMES-IRC) criteria have been regarded as the benchmark MIMO equalizers in the 3GPP criteria [1], as detailed below.

[0007] Linear MMSE equalizer

[0008] Specifically, the MMSE-based MIMO equalizer aims to obtain the estimated signal z based on the received signal from the receive antenna port and channel estimation. MMSE The optimal signal-to-noise ratio (SNR) is achieved. The MMSE equalizer circuit includes: a first input for receiving the received signal from the receive antenna port; a second input for receiving the channel estimate; a third input for receiving the noise power scalar; and an output that provides the equalized signal z. MMSE Consider an exemplary MIMO system where the number of transmit antenna elements 111 is exactly equal to the number of transmit antenna ports N. T The number of receiving antenna elements 113 is exactly equal to the number of receiving antenna ports N. R ,like Figure 1 As shown, after transmission through the fading channel, the frequency domain received signal of a specific receiver can be expressed as:

[0009] y = Hs + n, (1)

[0010] in:

[0011]

[0012] Where the H matrix represents the frequency domain channel estimation, s=[s1,s2,…,s NL ] T Indicates through N L The symbol vector transmitted by the layer, y = [y1, y2, ..., y NR ] T This represents the frequency domain received observation signal, n = [n1, n2, ..., n]. NR ] TThis represents the noise vector contained in the received observation. It's important to note that if the number of transmit or receive antenna elements exceeds the corresponding number of antenna ports due to beamforming, the channel matrix H can be considered as N. L One transport layer and N R The effective channel between the receiving antenna ports will be described in detail below. Here, the channel matrix H effectively integrates the effects of MIMO precoding, transmit beamforming, OFDM modulation, time-domain channel effects, OFDM demodulation, and receive beamforming.

[0013] In a linear equalizer, the equalization signal f MMSE =G MMSE y is obtained by combining the received signal vector y with the filter matrix G MMSE Multiply, then perform parallel decision-making across all layers to obtain the result. When considering the MMSE equalizer, the filter matrix G... MMSE The choice should be such that the transmitted signal vector s and its estimated vector f MMSE Minimize the mean square error (MSE) between them. Specifically, the minimization problem of the MMSE equalizer can be expressed as [2]:

[0014]

[0015] Where: argmin{} is the independent variable of the minimum value, E[] is the expectation operation, and ||·|| is the Frobenius norm.

[0016] Minimizing equation (1) yields the following filter matrix:

[0017] W MMSE =HH H +σ n 2 I.

[0018] G MMSE =H H W MMSE -1 (3)

[0019] Where, σ n 2 Let be the noise variance, (·) H I represents the Hermitian transpose of a vector or matrix, where I is a vector of dimension (N). R xN R The identity matrix W MMSE This is the autocorrelation matrix of the received signal vector.

[0020] When the MMSE criterion shown in formula (2) is satisfied, the decision statistic can be expressed as:

[0021] fMMSE =G MMSE y = G MMSE Hs+G MMSE n. (4)

[0022] Among them, f MMSE =[(f MMSE )1, (f MMSE )2,…,(f MMSE ) NL ] T This is the filtered received signal vector.

[0023] In addition, it is used to detect the symbol s i The filter vector (G) MMSE ) i for:

[0024] (G MMSE ) i =H(:,i) H (HH H +σ n I ) -1 (i = 1, ..., N) L (3b)

[0025] Where H(:,i) represents the i-th column vector of the channel estimation matrix.

[0026] Then, using formula (3b), the filtered received symbol (f) MMSE ) i It can be represented as:

[0027] (f MMSE ) i =(G MMSE ) i H(:,i)s i +(G MMSE ) i n i (i = 1, ..., N) L (4b)

[0028] According to formula (4b), the filtered symbol (f) MMSE ) i Equalization gain (μ) MMSE ) i and variance (β) MMSE ) i It can be represented as:

[0029] (μ MMSE ) i =(G MMSE ) i H(:,i), (4c)

[0030] (β MSE ) i =σ n 2 (G MMSE ) i (G MMSE ) i H (i = 1, ..., N) L (4d)

[0031] Therefore, in the i-th transport layer, the transmitted symbol s i The estimated QAM symbol (z) MMSE ) i It can be rewritten as:

[0032]

[0033] Used to calculate the noise variance (v) of soft bits MMSE ) i It can be rewritten as:

[0034]

[0035] (z) is represented by formula (4e) MMSE ) i The constructed estimated vector will be demapped into a sequence by a layer demapper, and then demapped into soft bits or hard bits by a QAM demapper. Soft bits are typically denoted by LLR, where the noise variance (v) in equation (4f) is... MMSE ) i This will be used to calculate the LLR, and its expression is:

[0036]

[0037] Where: P(bit=0) represents the probability that the bit is 0, P(bit=1) represents the probability that the bit is 1, and soft bits are represented by LLR.

[0038] For example, after obtaining the equalization symbol in formula (4e) and the noise variance in formula (4f), if QPSK modulation with two bits per symbol is used, the corresponding two LLRs can be derived:

[0039]

[0040] Where LLR1 is the LLR of the first bit in the QPSK symbol, LLR2 is the LLR of the second bit in the QPSK symbol, and Re(.) and Im(.) are the real and imaginary parts of (.), respectively.

[0041] MMSE-IRC Equalizer

[0042] With the development of electronic hardware and MIMO technology, the application of inter-cell or inter-user interference suppression technology was previously limited by the large amount of computation, but now it can be implemented economically and efficiently in the receiver. Specifically, Interference Suppression Combining (IRC) is a linear combining technique that relies on multiple receiver antenna ports and estimation of the interference channel to project the received signal onto the subspace with the minimum mean square error (MSE) [3]. IRC is a supplement to the known minimum mean square error (MMSE) criterion. Compared with the MIMO equalizer based on the MMSE criterion in formula (3), the MIMO equalizer based on the MMSE-IRC criterion not only considers noise, but also inter-cell or inter-user interference, such as Figure 1 As shown, interference plus noise is estimated in a MIMO equalizer based on the MMSE-IRC criterion to obtain the estimated signal z. IRC The optimal signal-to-interference-plus-noise ratio (SINR).

[0043] Consider an exemplary MIMO system, such as Figure 1 As shown, for both the target user and the interference source, the number of transmitting antenna elements 111 is exactly equal to the number of transmitting antenna ports N. T The number of receiving antenna elements 113 is exactly equal to the number of receiving antenna ports N. R After transmission through a fading channel, the frequency domain received signal of a specific receiver can be expressed as:

[0044] y = Hs + H I s I +n, (5)

[0045] in:

[0046]

[0047] The H matrix represents the frequency domain channel matrix of the target user, s=[s(1),s(2),…,s( NL )] T H represents the symbol vector sent by the target user. I The matrix represents the channel matrix and the transmitted symbols of the interference source, y = [y(1), y(2), ..., y( NR )] T Represents the frequency domain received observation vector, n=[n(1),n(2),…,n( NR )] T This is the noise vector contained in the received observation. It's important to note that when the number of transmitting or receiving antenna elements exceeds the corresponding number of antenna ports due to beamforming, the channel matrices H and H'... I N can be considered as the expected user and the interfering user. LOne transport layer and N R The effective channel between the receiving antenna ports will be described in further detail below. Here, the channel matrices H and H' are... I It effectively integrates the effects of MIMO precoding, transmit beamforming, OFDM modulation, time-domain channel effects, OFDM demodulation, and receive beamforming. It's also important to note that interfering users do not need to use the same system parameters as the desired user, or even the same waveforms. In fact, in real-world systems, interference can originate from any number of sources or any RF signal from any user.

[0048] The minimization formula can be expressed as:

[0049]

[0050] Where: argmin{} is the independent variable for the minimum value, E[] is the expectation operation, and ||.|| is the Frobenius norm.

[0051] The minimization formula in equation (6) yields the GIRC matrix of the MMSE-IRC filter:

[0052] W IRC =HH H +R I

[0053] G IRC =H H W IRC -1 (7)

[0054] Wherein, the H matrix represents the channel estimation for the target user, (·) H Represents the Hermitian transpose of a vector or matrix, and the covariance matrix R. I 123 represents the covariance matrix of interference plus noise, W IRC This represents the autocorrelation matrix of the received signal vector. Specifically, to obtain the filter matrix based on the MMSE-IRC criterion, as shown in Equation (7), it is necessary to estimate the covariance matrix containing inter-cell / inter-user interference and noise sources. In the 3GPPNR example, the covariance matrix can be estimated from the demodulation reference symbol (DM-RS) subcarriers using the following formula:

[0055]

[0056] R IPN =(y-Hs) DMRS )(y-Hs DMRS ) H (7c)

[0057] Among them, DM-RS symbol 132s DMRSUsed to estimate the covariance matrix, Nsp is the number of DM-RS symbols in each average cell under different DM-RS modes 131.

[0058] Skilled professionals will recognize that, in addition to 3GPP NR, pilot symbols or other techniques can be used to calculate the covariance matrix in various MIMO applications. Furthermore, besides averaging the individual DM-RS signals, skilled professionals can also employ other time-domain or frequency-domain interpolation techniques to obtain the covariance matrix R. I .

[0059] When the MMSE-IRC criterion is met, the decision statistic can be expressed as:

[0060] f IRC =G IRC y = G IRC Hs+G IRC (H I s I +n). (8)

[0061] Where f IRC =[(f IRC )1, (f IRC )2,…,(f IRC ) NL ] T It is the filtered received signal vector.

[0062] In addition, it is used to detect the symbol s i The filter vector (G) IRC ) i Represented as:

[0063] (G IRC ) i =H(:,i) H (HH H +R I ) -1 (i = 1, ..., N) L (7d)

[0064] Where H(:,i) represents the i-th column vector of the channel estimation matrix.

[0065] Then, using formula (3b), the filtered received symbol (f) IRC ) i It can be written as

[0066]

[0067] According to formula (4b), the equalization gain (μ) IRC ) i and filter symbol (f IRC) i variance (β) IRC ) i It can be represented as:

[0068] (μ IRC ) i =(G IRC ) i H(:,i), (8c)

[0069] (β IRC ) i =(G IRC ) i R I (G IRC ) i H (i = 1, ..., N) L (8d)

[0070] Therefore, in the i-th transport layer, for the transmitted symbol s i Estimated QAM symbol (z) IRC ) i It can be rewritten as:

[0071]

[0072] Used to calculate the noise variance (v) of soft bits IRC ) i It can be rewritten as:

[0073]

[0074] (z) is represented by formula (4e) IRC ) i The constructed estimated vector will be demapped into a sequence by a layer demapper, and then demapped into soft bits or hard bits by a QAM demapper. Soft bits are typically denoted by LLR, where the noise variance (v) in equation (4f) is... IRC ) i This will be used to calculate the LLR, and its expression is:

[0075]

[0076] Where: P(bit=0) represents the probability that the bit is 0, P(bit=1) represents the probability that the bit is 1, and soft bits are represented by LLR.

[0077] For example, after obtaining the equalization symbol in formula (8e) and the noise variance in formula (8f), if QPSK modulation with two bits per symbol is used, the corresponding two LLRs can be derived as follows:

[0078]

[0079] Where LLR1 is the LLR of the first bit in the QPSK symbol, LLR2 is the LLR of the second bit in the QPSK symbol, and Re(.) and Im(.) are the real and imaginary parts of (.) respectively.

[0080] However, the inventors found a lack of techniques in the literature that combine MMSE-IRC processing with nonlinear processing. Both methods have been demonstrated separately. MMSE-IRC offers advantages in terms of anti-interference capabilities and low complexity, but its drawback is reduced equalization performance. Meanwhile, nonlinear processing enhances equalization performance, but its disadvantage is high complexity, especially when performing anti-interference tasks. Currently, no technique in the literature combines MMSE-IRC processing with nonlinear processing in a way that retains the advantages of both while avoiding their disadvantages. Summary of the Invention

[0081] This invention provides a MIMO equalizer and a MIMO equalization method. Specific embodiments of the invention describe in detail algorithms suitable for hardware implementation, thereby enabling high throughput in a cost-effective manner. Specific exemplary embodiments are set forth in the dependent claims. These and other aspects will be apparent from and in connection with the exemplary embodiments described below.

[0082] In a first aspect, a multiple-input multiple-output (MIMO) equalizer circuit includes: a controller; and an autocorrelation matrix calculation circuit operatively coupled to the controller and having an operatively receiving covariance matrix R. I The covariance matrix input and the channel estimation matrix input of the operably received channel estimation matrix H, wherein the autocorrelation matrix calculation circuit is configured to respond to the received covariance matrix R IAn autocorrelation matrix W is generated from the channel estimation matrix H, and the autocorrelation matrix W is output to the first output terminal; a matrix inversion circuit, operably coupled to the controller and the autocorrelation matrix calculation circuit, and having an autocorrelation matrix input to receive the autocorrelation matrix W from the autocorrelation matrix calculation circuit, wherein the matrix inversion circuit is configured to invert the autocorrelation matrix W and output the inverse autocorrelation matrix to a second output; a matrix operation circuit, operably coupled to the controller and the matrix inversion circuit, and having: an inverse autocorrelation matrix input for receiving the inverse autocorrelation matrix; a received signal vector input for receiving the received signal vector y; and a channel estimation matrix input for receiving the channel estimation matrix H; wherein the matrix operation circuit is configured to: combine the received inverse autocorrelation matrix input. The correlation matrix and the channel estimation matrix H are used to generate an equalization gain matrix ('P' matrix) and output it to a third output; and the received inverse autocorrelation matrix, the received signal vector y, and the channel estimation matrix H are combined to generate a vector 'f' and output it to a fourth output; and a continuous interference cancellation (SIC) detection circuit is operatively coupled to the controller and operatively coupled to the third and fourth outputs of the matrix operation circuit, wherein the SIC detection circuit is configured to: convert the received P matrix into a first orthogonal unitary matrix Q and a first upper triangular matrix R, and convert the first orthogonal unitary matrix Q, the first upper triangular matrix R, and the f vector into an equalization symbol Z2 vector estimated by SIC (330), wherein the SIC detection circuit is configured to output the Z2 vector. In this way, linear MMSE-IRC processing is combined with nonlinear processing, which has the advantages of interference suppression, low complexity, and enhanced equalization capability.

[0083] In an alternative embodiment of the MIMO equalizer circuit, the covariance matrix R I It can have a number of spatial flows equal to N. R The sum of the first dimensions equals the number of spatial flows N R The second dimension; where the channel estimation matrix H has a value equal to the number of spatial streams N. R The sum of the first dimensions equals the number of layers N L The second dimension; and where the received signal vector y has a spatial flow number N equal to the number of spatial flows. R The length of the Z2 vector (330) is equal to the number of layers N. L The length. In this way, MIMO equalizer circuits can support multiple spatial streams and multiple layers.

[0084] In one alternative embodiment of the MIMO equalizer circuit, the number of space streams N R Number of layers N LThe operation can vary between different modes during MIMO equalizer circuit operation. In this way, the MIMO equalizer circuit can support transmissions from multiple transmitters with different numbers of layers and can be used in conjunction with beamforming combiners that distribute different numbers of spatial streams to recover transmissions from different transmitters.

[0085] In an alternative embodiment of the MIMO equalizer circuit, the autocorrelation matrix W and the inverse autocorrelation matrix can have a value equal to the number of spatial flows N. R The sum of the first dimensions equals the number of spatial flows N R The second dimension; and where the P matrix has a number of layers N. L The sum of the first dimensions equals the number of layers N L The second dimension; and where the vector f has a number of layers N. L The length. In this way, MIMO equalizer circuits can support multiple spatial streams and multiple layers.

[0086] In an optional embodiment of the MIMO equalizer circuit, the autocorrelation matrix calculation circuit includes: a Hermitian transpose circuit configured to receive the channel estimation matrix H and perform a Hermitian transpose to convert the channel estimation matrix H into a Hermitian transpose matrix H2; a matrix multiplication circuit operably coupled to the output of the Hermitian transpose circuit and configured to receive the channel estimation matrix H and convert the received channel estimation matrix H and the Hermitian transpose matrix H2 into a Hermitian matrix H3; and a matrix addition circuit operably coupled to the output of the matrix multiplication circuit and configured to receive the covariance matrix R. I And the Hermitian H3 matrix and the covariance matrix R I The autocorrelation matrix W is generated by adding the two sides. In this way, the autocorrelation matrix W can be calculated with low complexity.

[0087] In an alternative embodiment of the MIMO equalizer circuit, the matrix inversion circuit may include: a first QR decomposition circuit QRD operable to receive and perform QR decomposition on the autocorrelation matrix W, converting the autocorrelation matrix W into a second orthogonal unitary matrix Q and a second upper triangular matrix R under the instruction of the controller; and a first Gaussian elimination circuit operable to perform Gaussian elimination, converting the second orthogonal unitary matrix Q, the second upper triangular matrix R, and the identity matrix I into an inverse autocorrelation matrix under the instruction of the controller. In this way, the complex matrix inversion function can be avoided and instead, the simpler QR decomposition and Gaussian elimination can be used instead.

[0088] In an alternative embodiment of the MIMO equalizer circuit, the first Gaussian elimination circuit is operable to perform a Hermitian variant of Gaussian elimination. In this way, the complexity of Gaussian elimination can be reduced.

[0089] In an alternative example of the MIMO equalizer circuit, the MIMO equalizer circuit may further include a first switch that operates under the instruction of a controller, wherein: in a first operating mode, the first switch is configured to receive and output the covariance matrix R. I In the second operating mode, the MIMO equalizer further includes a covariance matrix generation circuit operatively coupled to the first switch and configured to receive a noise power scalar, wherein the covariance matrix generation circuit uses the noise power scalar to generate a diagonal covariance matrix, which is provided to the first switch, and the first switch outputs the diagonal covariance matrix as a covariance matrix R. I In this way, interference suppression combinations can be enabled or disabled at runtime, depending on which approach is expected to provide the best signal reconstruction quality.

[0090] In an alternative embodiment of the MIMO equalizer circuit, the matrix operation circuit may further include: a first matrix operation sub-circuit operable to convert the inverse autocorrelation matrix and the channel estimation matrix H into a G matrix and a P matrix; and a second matrix operation sub-circuit operablely coupled to the first matrix operation sub-circuit and configured to convert the G matrix and the received signal vector y into the f vector. In this way, the P matrix and the f vector can be generated with low complexity.

[0091] In an optional embodiment of the MIMO equalizer circuit, the first matrix operation sub-circuit may further include: a Hermitian transpose circuit configured to perform a Hermitian transpose of the channel estimation matrix H into a Hermitian transpose H4 matrix; a first matrix multiplication circuit configured to convert the Hermitian transpose H4 matrix and the inverse autocorrelation matrix into the G matrix; and a second matrix multiplication circuit configured to convert the G matrix and the channel estimation matrix H into the P matrix. In this way, the G matrix and the P matrix can be generated with low complexity.

[0092] In an alternative embodiment of the MIMO equalizer circuit, the second matrix operation subcircuit may include a third matrix multiplication circuit operatively performing multiplication operations and converting the G matrix and the received signal vector y into the f vector. In this way, the f vector can be generated with low complexity.

[0093] In an alternative embodiment of the MIMO equalizer circuit, the SIC detection circuit further includes: a second QR decomposition (QRD) circuit operable to perform QR decomposition under the instruction of the controller, converting the P matrix into the first orthogonal unitary matrix Q and the first upper triangular matrix R; and a second Gaussian elimination circuit operablely coupled to the second QRD circuit and configured to perform Gaussian elimination under the instruction of the controller, converting the first orthogonal unitary matrix Q, the first upper triangular matrix R, and the f vector into the Z2 vector. In this way, the Z2 vector can be generated with low complexity.

[0094] In an alternative embodiment of the MIMO equalizer circuit, the SIC detection circuit further includes a second switch operatively coupled to the second Gaussian elimination circuit and the controller and configured to support: a third operating mode in which the second Gaussian elimination circuit performs Gaussian elimination with quantization; and a fourth operating mode in which the second Gaussian elimination circuit performs Gaussian elimination without quantization. In this way, quantization can be enabled or disabled at runtime, depending on which mode is expected to provide the best signal reconstruction quality.

[0095] In an alternative embodiment of the MIMO equalizer circuit, the MIMO equalizer circuit may further include: a first output providing an equalized signal vector x; a division circuit configured to receive the f vector and the P matrix and perform a division operation to convert the f vector and the P matrix into the z vector; and a third switch operatively coupled to the output of the controller and the SIC detection circuit, and configured by the controller to support: a fifth operating mode, wherein the equalized signal vector x is provided by the z vector; and a sixth operating mode, wherein the equalized signal vector x is provided by the Z2 vector. In this way, SIC detection can be enabled or disabled during operation, depending on which mode is expected to provide the best signal reconstruction quality.

[0096] In an alternative embodiment of the MIMO equalizer circuit, the third switch is configured by the controller to select a fifth operating mode when the channel signal-to-interference-plus-noise ratio (SINR) is below a threshold, and by the controller to select a sixth operating mode when the channel SINR is above a threshold. In this way, whether to perform SIC detection can be automatically determined depending on the channel SINR.

[0097] In an optional embodiment of the MIMO equalizer circuit, the MIMO equalizer circuit may further include a SIC noise variance calculation circuit, the SIC noise variance calculation circuit being configured to receive the G matrix, the first upper triangular matrix R, the first orthogonal unitary matrix Q, and the covariance matrix R. IAnd operably coupled to a second output, wherein, when the third switch is configured to support a sixth operating mode, the SIC noise variance calculation circuit calculates the G matrix, the first upper triangular matrix R, the first orthogonal unitary matrix Q, and the covariance matrix R. I The noise variance vector is converted into the first noise variance vector and provided to the second output. In this way, the noise variance vector can be configured to support QAM demapping when performing SIC detection.

[0098] In an alternative embodiment of the MIMO equalizer circuit, the second output can be operatively coupled to a non-SIC noise variance calculation circuit configured to calculate the G matrix and the covariance matrix R. I The P matrix is ​​then converted into a second noise variance vector, wherein the second noise variance vector is provided to the second output when the third switch is configured to support the fifth operating mode. In this way, the noise variance vector can be configured to support QAM demapping during SIC detection.

[0099] Secondly, a communication unit comprising the MIMO equalizer circuit described in the first aspect is described. In this way, the linear MMSE-IRC processing is combined with the nonlinear processing in the communication unit, offering advantages such as interference resistance, low complexity, and enhanced equalization capabilities.

[0100] Thirdly, a method for performing multiple-input multiple-output (MIMO) equalization is described, including: receiving the covariance matrix R through an autocorrelation matrix calculation circuit. I The process involves: generating an autocorrelation matrix W from the channel estimation matrix H; inverting the autocorrelation matrix W using a matrix inversion circuit and outputting an inverse autocorrelation matrix; combining the inverse autocorrelation matrix and the channel estimation matrix H using a matrix operation circuit to generate an equalization gain matrix ('P' matrix); receiving and combining the inverse autocorrelation matrix, the received signal vector y, and the channel estimation matrix H using a matrix operation circuit to generate a vector 'f'; converting the P matrix into a first orthogonal unitary matrix Q and a first upper triangular matrix R using a continuous interference cancellation (SIC) detection circuit; converting the first orthogonal unitary matrix Q, the first upper triangular matrix R, and the f vector into an equalization symbol Z2 vector estimated by SIC using the SIC detection circuit; and outputting the Z2 vector. In this way, linear MMSE-IRC processing is combined with nonlinear processing, offering advantages such as interference resistance, low complexity, and enhanced equalization capabilities. Brief description of the attached diagram

[0102] The following description, by way of example only, refers to the accompanying drawings for further details, aspects, and implementation. In the drawings, the same reference numerals are used to identify elements that are the same or functionally similar. Elements in the drawings are for simplicity and clarity only and are not necessarily drawn to scale.

[0103] Figure 1 A known schematic diagram of exemplary physical layer uplink transceiver signal processing operation of an exemplary MIMO system is shown, wherein the number of transmit antenna elements is exactly equal to the number of transmit antenna ports N. T And the number of receiving antenna elements is exactly equal to the number of receiving antenna ports N. R .

[0104] Figure 2 A known representation of the covariance matrix of a MIMO equalizer is shown.

[0105] Figure 3 A MIMO equalizer circuit for operating a MIMO equalizer incorporating a SiC-based MMSE-IRC is shown according to some embodiments.

[0106] Figure 4 An exemplary implementation of a SIC detection circuit for a MIMO equalizer incorporating SIC and MMSE-IRC, according to some embodiments, is shown.

[0107] Figure 5 A known representation of a QPSK constellation diagram for an exemplary implementation of quantization operations, according to some embodiments, is shown.

[0108] Figure 6 An implementation circuit for MIMO equalizer operation of MMSE-SIC with matrix extension combined with IRC, according to some embodiments, is shown.

[0109] Figure 7 A table showing the simulation limits and simulation parameters for operating a MIMO equalizer according to some embodiments is provided.

[0110] Figure 8 Exemplary simulation results of a MIMO equalizer combining IRC with MMSE-SIC operation according to some embodiments are shown.

[0111] Figure 9 Exemplary simulation results are shown for a MIMO equalizer based on matrix extension and incorporating IRC-SIC, according to some embodiments.

[0112] Figure 10 A typical computing system for performing a MIMO equalizer in an electronic device or wireless communication unit is shown, according to some exemplary embodiments.

[0113] Figure 11 A flowchart illustrating an exemplary implementation of a MIMO equalizer incorporating IRC-SIC according to some embodiments is shown.

[0114] Figure 12 A flowchart is shown of an exemplary implementation of a matrix-extended MMSE-SIC MIMO equalizer with IRC integration, according to some embodiments. Detailed Implementation

[0115] As mentioned above, MMSE-IRC equalizers can be used to separate the desired signal from interference and noise. Other techniques have been proposed for this purpose, including nonlinear equalizers, such as maximum likelihood equalizers [4]. Compared with nonlinear equalizers, MMSE-IRC equalizers have the advantages of low complexity and no need for channel estimation of interfering users, but their disadvantage is limited spectral efficiency, especially when the number of layers equals the number of receiver antenna ports. In contrast, nonlinear equalizers have the disadvantage of high complexity and the need for channel estimation of interfering users, but their advantage is higher spectral efficiency, especially when the number of layers equals the number of receiver antenna ports. How to achieve the best balance between the two is a problem, designing an equalizer that has all the above advantages without disadvantages, that is, low complexity and no need for channel estimation of interfering users, while maintaining high spectral efficiency when the number of layers equals the number of receiver antenna ports.

[0116] The embodiments described in this paper aim to address this problem by modifying the MMSE-IRC equalizer to support the interface with nonlinear equalizers performing SIC. The proposed solution employs an algorithm suitable for hardware implementation, enabling high throughput in a cost-effective manner.

[0117] MMSE-IRC combined with SIC MIMO equalizer implementation

[0118] In some embodiments, the inventors propose an MMSE-IRC equalizer incorporating SIC, which can be used to meet and exceed the detection reliability of the known MMSE-IRC criterion, which specifies the requirements for linear combination techniques that rely on multiple receive antenna ports and interference channel estimation to project the received signal into the subspace with the minimum mean square error.

[0119] The following will first discuss based on Figure 3 This section first explains the basic principles and operation of the MMSE-IRC equalizer implemented with SIC, then discusses the specific functional modules. Finally, we will present an exemplary simulation result. For simplicity, the subscript '_IRC' has been omitted from all symbols below.

[0120] Specifically, substituting formula (7) into formula (8), we can obtain:

[0121] f = H H (HH H +R I ) -1 Hs+H H (HH H +R I ) -1 (H I s I +n)

[0122] =H H W -1 Hs+H H W -1 (H I s I +n), (9)

[0123] The equalization gain matrix can be defined as:

[0124] P = H H (HH H +R I ) -1 H = H H W -1 H. (10)

[0125] More specifically, in formula (9), W = HH H +R I Let W308 represent the autocorrelation matrix W308 of the received signal vector y301 in formula (5), where the channel estimation matrix H121 is multiplied by its Hermitian transpose H2 matrix 304 to generate the Hermitian H3 matrix 306, and according to the calculations of formulas (7b) and (7c), the covariance matrix R I 123 is also a Hermitian matrix, which makes the autocorrelation matrix W308 a Hermitian matrix. The special Hermitian structure of the W matrix can be used to simplify... Figure 3 The implementation details of the matrix inversion circuit 309 shown will be discussed later.

[0126] According to some embodiments, a continuous interference cancellation (SIC) detection circuit 325, operating under the instruction of controller 339 and based on QR decomposition (QRD) circuit 326, can be used to meet and exceed the detection reliability of the known MMSE-IRC criterion based on formula (7), although skilled practitioners will recognize that other methods can also be used to implement SIC detection. For example, conventional MMSE-based SIC detection requires multiple iterations to achieve layer-by-layer interference cancellation, and each iteration requires recalculation of the filter matrix. While this detection method can obtain more reliable detection results, it comes at the cost of higher latency, higher power consumption, and higher hardware complexity. More specifically, the equalization gain matrix (P matrix) 324 is first factored based on QR decomposition to obtain P = QR, so the f vector 323 in formula (9) can be expressed as:

[0127] f = QRs + G(H) I s I +n), (11)

[0128] Among them, the orthogonal unitary matrix Q328 has orthogonal columns with unit norm, and the upper triangular matrix R327 is an upper triangular matrix. Connect the vector f323 with Q... H Multiplying them together yields a sufficient statistic.

[0129] f1 = Q H f = Rs + Q H G(H I s I +n)=Rs+G2(H I s I +n), (12)

[0130] Used to estimate the emission vector s, where G2 = Q H G.

[0131] Let the upper triangular matrix R327 in formula (12) be represented as

[0132]

[0133] The first term on the right side of formula (12) contains the expected signal and the interference from the detected symbol, and constitutes the SIC architecture that introduces continuous interference cancellation through the Gaussian elimination circuit.

[0134] Then, the entire process of implementing the Gaussian elimination circuit 329 can be controlled by the controller 339 and represented as the following pseudocode:

[0135] Algorithm-1

[0136] Input: Orthogonal unitary matrix Q = 328, upper triangular matrix R = 327, vector f = 323

[0137] Output: SIC-estimated equalization sign Z2 vector 330 and noise variance vector v 337

[0138] Step 1 - Formula

[0139] Assume the detection order is [N] L ,…,1]. Typically, the i-th filter symbol f1(i) in formula (12) (i=N L ,…,1) can be represented as:

[0140]

[0141] Where (.)ii represents the element in the i-th row and i-th column of the matrix, and ri represents the remaining interference and noise in the i-th detection layer.

[0142] The first component on the right side of formula (14) contains the expected signal, the second component on the right side contains interference from the detection symbols, which will be eliminated sequentially by the Gaussian elimination circuit, and the third component represents the remaining filtering interference plus noise of the i-th detection layer.

[0143] For ease of analysis, according to formula (14), the equalization gain of the i-th detection layer can be expressed as:

[0144] μ i =R ii (15)

[0145] Then, formula (14) can be reformulated as:

[0146]

[0147] Step 2 – Initialization

[0148] According to the general formulas in formulas (14)-(16), when i = N L The first detection layer, the first equalization symbol z2(i) and the noise variance v i It can be represented as:

[0149]

[0150] Where G2(i,:) represents the i-th row vector of the G2 matrix in formula (12).

[0151] Step 3 – Gaussian Elimination

[0152] For i = N L , ..., 1

[0153]

[0154] Finish

[0155] Where: d in formula (19) iCorresponding to the second term on the right-hand side of formula (16), and in the first detection layer shown in the algorithm, when i = N L When, di = 0.

[0156] Furthermore, Quant(.) in Equation (20) reveals the quantization operation, which is used to find the QAM constellation point closest to the equalization symbol to further improve detection reliability, but at the cost of higher circuit power consumption and longer delay. Here, different QAM constellation schemes can be selected during operation, such as BPSK, QPSK, 16QAM, 64QAM, and 256QAM, depending on the scheme adopted by the transmitter. For example, in Figure 5 In the QPSK constellation scheme shown, the estimated complex value of the received symbol 501 is 0.9 + 0.8i. The quantization operation Quant(.) is used to find the constellation point closest to the estimated symbol, such as... Figure 5 As shown, constellation point A502 located at 0.707+0.707i is the point closest to the estimated sign. Therefore, in this embodiment, the output of Quant(.) in formula (20) is 0.707+0.707i.

[0157] In the introduction Figure 3 Following the explanation of the basic principles and operations of the proposed MMSE-IRC equalizer with IRC, some functional modules will be discussed in detail below.

[0158] Specifically, the noise variance vector calculated in formula (21) corresponds to Figure 3 The output of the optional SIC noise variance calculation circuit 333 shown is... Figure 3 The output of the optional non-SIC noise variance calculation circuit 335 shown can be calculated based on formula (8f). In a practical system, the decision to enable SIC can be controlled during operation based on the channel SINR, where it may be preferable to disable SIC when the SINR is below a certain threshold, and to enable SIC when the SINR is above that threshold. Skilled practitioners will recognize that other characteristics (such as channel gain or covariance matrix characteristics) can be used to control the decision.

[0159] According to some embodiments described herein, such as Figure 3 The MIMO equalizer circuit 300 shown includes a controller 339, an autocorrelation matrix calculation circuit 302, a matrix inversion circuit 309, a matrix operation circuit 316, and a SiC detection circuit 325. It can be used to equalize a matrix with dimension (N...) R The first input is provided by the received signal vector y 301 of dimension (N). R XN L The second input is provided by the channel estimation matrix H121 of dimension (N) and the input is provided by the channel estimation matrix H121 of dimension (N). RXN R The covariance matrix R) I The third input provided by 123 is transformed into a input with dimension (N) L The output of the equalized signal vector x332 of X1), where N R Size and N L Size supports multiple values. Skilled practitioners will recognize that all dimensions of a matrix can be interchanged, such as rows becoming columns and vice versa. Skilled practitioners will readily recognize that some reordering of the terms in the matrix expression is required, but the operation is the same as described in this discussion.

[0160] More specifically, such as Figure 3 As shown, the autocorrelation matrix calculation circuit 302 operates under the instruction of the controller 339 and further includes a Hermitian transpose circuit 303, a matrix multiplication circuit 305, and a matrix addition circuit 307, which can be used to generate the autocorrelation matrix W 308.

[0161] In addition, such as Figure 3 As shown, the matrix operation circuit 316 operates under the instruction of the controller 339, and further includes a pair of sub-circuits, wherein the first matrix operation sub-circuit 343 includes a Hermitian transpose circuit 317, a first multiplication circuit 319 and a second multiplication circuit 322, and the second matrix operation sub-circuit 344 includes a multiplication circuit 321, which can be used to generate a P matrix 324 and an f vector 323.

[0162] More specifically, in order to reduce the implementation complexity of inverting the autocorrelation matrix involved in the calculation of G matrix 320 in formula (7), it is possible to... Figure 3 The MIMO equalizer circuit 300 shown employs a matrix inversion circuit 309 based on QRD using Hermitian Gaussian elimination. Specifically, in the MIMO equalizer circuit 300 where the matrix inversion circuit 309 operates under the instruction of the controller 339, as shown... Figure 3 As shown, it includes a QRD circuit 310 and a Hermitian Gaussian elimination circuit 314, wherein the QRD circuit can convert the autocorrelation matrix W 308 into a dimension (N) R ×N R The orthogonal unitary matrix Q311 and the dimension of (N) R ×N R The upper triangular matrix R 312 of dimension (N) can be used to eliminate the orthogonal unitary matrix Q 311, the upper triangular matrix R 312, and the Hermitian Gaussian elimination circuit 314. R ×N R The identity matrix I 313 is transformed into the inverse autocorrelation matrix I 315. To simplify the analysis, the overall process of combining QRD with matrix inversion based on Hermitian Gaussian elimination is described in the following pseudocode:

[0163] Algorithm 2

[0164] Input: Autocorrelation matrix W 308

[0165] Output: inverse autocorrelation matrix 315T = W -1

[0166] Step 1: Formulating the problem

[0167] Assuming the dimension is (N) R ×N R The autocorrelation matrix W308 is invertible, and T = W -1 Then the following relationship may exist:

[0168] WW -1 =I (22)

[0169] Step 2: Perform QR decomposition on the W matrix

[0170] Based on QR decomposition:

[0171] QRT=I(23)

[0172] Applying Q to formula (23) H We can obtain:

[0173] RT = Q H (twenty four)

[0174] Step 3: Hermitian Gaussian elimination

[0175] Thanks to the upper triangular structure of the upper triangular matrix R 312 and the Hermitian structure of the autocorrelation matrix W 308 discussed earlier, the Hermitian Gaussian elimination method can be used to calculate the T matrix, which can be described as follows:

[0176] For i = 1, ..., N R

[0177] for

[0178]

[0179] Finish

[0180] Finish

[0181] Among them, formulas (25) and (26) execute (0.5N) R 2 +0.5N R The number of operations is required by the Hermitian Gaussian elimination method shown in the pseudocode. However, in the traditional Gaussian elimination method in matrix inversion circuits, as shown in the following pseudocode, N operations are required. R 2 This is the second operation.

[0182] Traditional Gaussian elimination

[0183] For i = 1, ..., N R

[0184] for

[0185]

[0186] Finish

[0187] Finish

[0188] More specifically, the W or T matrix always possesses Hermitian properties, and an example of a (3×3) Hermitian T matrix can be represented as:

[0189]

[0190] According to the Hermitian structure shown in Equation (29), calculating the lower triangular elements of the inverse autocorrelation matrix 315 (matrix T in this example) is sufficient to obtain the full matrix, where the upper off-diagonal elements can be obtained by calculating the Hermitian matrices of the lower off-diagonal elements. Note that in some embodiments described herein, the less complex Hermitian Gaussian elimination method may always be used in the matrix inversion circuit. Skilled practitioners will recognize that conventional Gaussian elimination can be used instead of Hermitian Gaussian elimination, but at the cost of higher latency, higher power consumption, and / or hardware complexity.

[0191] According to some embodiments described herein, such as Figure 3 and Figure 4 The MIMO equalizer circuit 300 shown optionally employs three switches, each of which supports two operating modes under the instruction of the controller 339, and the four switches can support a combination of eight operating modes.

[0192] More specifically, such as Figure 3 As shown, the first switch 340 supports a first operating mode, where the covariance matrix input 200 (in this example, includes both interference and noise, such as...) Figure 2 (As shown in the example on the left) for equalization following the MMSE-IRC criterion, and wherein the first switch 340 optionally supports a second operating mode, wherein a diagonal covariance matrix 201 is generated from the fourth input of the noise power scalar 124 (as shown in the example on the left) Figure 2 (As shown in the example on the right), and used for equalization following the MMSE criterion under the instruction of controller 339. The fourth input of the noise power scalar 124 is optional and needs to be as follows. Figure 3 The covariance matrix generation circuit 122 shown is used to calculate the diagonal covariance matrix 201, as follows. Figure 2 The example of the covariance matrix on the right side is shown.

[0193] also, Figure 4 The second switch 404 supports a third operating mode, in which a Gaussian elimination circuit 400 with quantization, as described in the pseudocode of Algorithm 1, is used. The second switch 404 optionally supports a fourth operating mode, in which a Gaussian elimination circuit 401 without quantization is used under the instruction of the controller 339. The Quant(f1(i)-d) in Algorithm 1... i / μ i The function is defined in formula (20) as (f1(i)-d i ) / μ i The quantization operation is used to find the QAM constellation point closest to the equalization symbol to further improve detection reliability, but at the cost of higher power consumption and longer latency. The quantization operation can be disabled when lower power consumption and lower latency circuitry are required. Furthermore, in practical systems, quantization can be enabled or disabled at runtime based on the channel SINR, where it may be preferable to disable quantization when the SINR is below a certain threshold and to enable it when the SINR is above the threshold. Skilled practitioners will recognize that other features (such as channel gain or covariance matrix characteristics) can be used to control the decision. It should be noted that in practical implementations, the Gaussian elimination circuit 400 with quantization and the Gaussian elimination circuit 401 without quantization can be implemented separately and combined with the physical implementation of the second switch 404. Alternatively, skilled practitioners will recognize that hardware complexity can be reduced by reusing the circuitry between the Gaussian elimination circuit 400 with quantization and the Gaussian elimination circuit 401 without quantization and incorporating the second switch 404 into the controller 339 of the final circuit.

[0194] Then, as Figure 3 As shown, the third switch 331 supports a fifth operating mode under the instruction of the controller 339, wherein, Figure 3 The z vector 342 shown and represented by formula (8e) is operatively coupled to the equalization signal vector x 332, and the MMSE-IRC criterion is enabled; and the third switch 331 optionally supports a sixth operating mode, wherein, Figure 3The SIC-estimated equalized symbol (Z2) vector 330, as shown in the diagram and in equation (20) of Algorithm 1, is operatively coupled to the equalized signal vector x332, and our SIC-integrated MMSE-IRC equalizer is in the ON state. Specifically, the estimated symbol vector z342, as shown in equation (8e), can be obtained by dividing the f vector 323 in equation (9) by the equalization gain scalar represented by equation (8c) using the division circuit 341. For example, the third switch 331 can operatively support the fifth operating mode when the channel SINR value is below the threshold, and can optionally support the sixth operating mode when the channel SINR value is above the threshold. It should be noted that the decision on when to support the fifth and sixth operating modes is merely an example, and those skilled in the art should recognize that other characteristics (such as channel gain or covariance matrix characteristics) can be used to control this decision.

[0195] all in all, Figure 11 Flowchart 1100 describes the specific manifestation of the MIMO equalization example. The operation begins at 1101, where the covariance matrix R... I In step 1103, the autocorrelation matrix W 308 is calculated using the channel estimation matrix H 121. Then, in step 1102, the autocorrelation matrix W 308 is inverted to generate the inverse autocorrelation matrix 315. In step 1103, operations are performed on the inverse autocorrelation matrix 315, the received signal vector y 301, and the channel estimation matrix H 121 to generate the P matrix 324 and the f vector 323. Subsequently, in step 1104, SIC detection is performed, converting the P matrix 324 and the f vector 323 into the SIC-estimated equalized symbol (z2) vector 330. Further, SIC detection 1104 includes a first step 1105, in which QR decomposition is applied to the P matrix 324 to obtain the orthogonal unitary matrix Q 328 and the upper triangular matrix R 327. Subsequently, the SIC detection 1104 ends with the second step 1106, in which Gaussian elimination is performed to convert the f vector 323, the orthogonal unitary matrix Q 328, and the upper triangular matrix R 327 into the z2 vector 330.

[0196] According to some embodiments described herein, Figure 7 Showing based on Figure 6 The simulation results shown illustrate exemplary simulations of an MMSE-IRC MIMO equalizer with SIC in the shown configuration, demonstrating the relationship between SINR gain and SINR based on the linear MMSE criterion. Specifically, as... Figure 9As shown, based on our preliminary simulations using the 3GPP criterion scenario, the MMSE-IRC criterion has been demonstrated to offer approximately 3 dB of SINR gain over a wide SINR range compared to the linear MMSE criterion. Particularly in the low SINR region, the SINR gain exceeds 3 dB, even reaching 8.9 dB higher than the linear MMSE criterion. Furthermore, in the medium SINR region, the proposed MIMO equalizer incorporating SIC and MMSE-IRC provides approximately 1.0 dB of SINR gain compared to the MMSE-IRC criterion.

[0197] MIMO equalizer implementation based on matrix extension and combined with IRC MMSE-SIC

[0198] In some embodiments, the inventors propose a matrix-extended combined IRC-based MMSE-SIC equalizer that can be used to satisfy and exceed the known MMSE-IRC criterion for detection. This criterion specifies the requirements of a linear combination technique that relies on multiple receive antenna ports and estimation of the interference channel to project the received signal onto the subspace with the minimum mean square error. In some embodiments, the proposed matrix-extended MMSE-SIC equalizer can utilize QR decomposition or ordered QR decomposition of the extended channel matrix to obtain a continuous detection structure. Specifically, ordered QR decomposition of the extended channel matrix can be used to compute the optimized detection order of the SIC architecture.

[0199] In the following discussion, we will discuss based on Figure 8 This paper first introduces the basic principles and operation of the MMSE-SIC equalizer circuit 800 based on MIMO matrix extension and combined with IRC, then discusses the specific functional modules. Finally, we present an example simulation result. For simplicity, the subscript _IRC will be omitted for all symbols in the following discussion.

[0200] According to some embodiments described herein, such as Figure 8 The matrix-extended MMSE-SIC MIMO equalizer circuit 800 shown includes a controller 848, an inverse square root matrix circuit 802, an IRC preprocessing circuit 817, a matrix extension circuit 822, and a SIC detection circuit 825. It can be used to convert MMSE-SIC MIMO equalizers of dimension (N...) into SIC values. R The first input is provided by the received signal vector y 801 of dimension (N × 1), and the input is provided by the received signal vector y 801 of dimension (N × 1). R ×N L The second input is provided by the channel estimation matrix H121 of dimension (N) and the input is provided by the channel estimation matrix H121 of dimension (N). R ×N R The covariance matrix R) I The third input provided by 123 is transformed into a input with dimension (N) LThe output of the equalized signal vector x 842 (×1), where N R and N L The size can support multiple values.

[0201] Skilled practitioners will recognize that the dimensions of all matrices can be interchanged, for example, rows can be converted to columns and vice versa. Skilled practitioners will readily recognize that some reordering of the terms in the matrix expression is required, but the operation is the same as described in this discussion.

[0202] More specifically, the MMSE-IRC criterion minimizes the mean square error between the actual transmitted symbol and the equalized symbol output, thus obtaining the filter matrix G as shown in Equation (7). Then, by utilizing the matrix inverse lemma, the filter matrix in Equation (7) can also be expressed as:

[0203]

[0204] in, I represents the inverse of the interference plus noise covariance matrix. NL It is a dimension of (N) R ×N L The identity matrix of ).

[0205] According to formula (30), the extended preprocessed channel estimation H3 matrix 823 and the extended preprocessed received signal y2 vector 824 can be obtained through the matrix extension circuit 822, which is defined as:

[0206]

[0207] Among them, the inverse square root matrix It is the inverse of the square root covariance matrix, calculated by the inverse square root matrix circuit 802, such as... Figure 8 As shown, y is the received signal vector y 801 shown in formula (5). With the help of the third multiplication circuit 819, the preprocessed channel estimation matrix H 2821 can be obtained, which is expressed as The preprocessed received signal vector y1 can be obtained by using the second multiplication circuit 818, and is represented as follows: like Figure 8 The IRC preprocessing circuit 817 is shown in the figure.

[0208] According to some embodiments, it is possible to use Figure 8 The Shure decomposition circuit 803 shown calculates the inverse of the square root covariance matrix. Specifically, the covariance matrix R... I The Shure decomposition can be expressed as:

[0209] R I =UDU H(33)

[0210] Among them, the orthogonal eigenvector matrix U804 is a matrix with dimension (N) R ×N R An orthogonal unitary matrix of N, whose N R The N column vectors represent the covariance matrix. R There are 3 orthogonal eigenvectors, denoted as U2 = U H The Hermitian transpose of matrix U2, matrix 810, is the Hermitian transpose of matrix U. This matrix can be obtained by using... Figure 8 The Hermitian transpose circuit 809 shown is obtained. Specifically, the dimension is (N) R ×N R The real-valued diagonal matrix D 805 has real-valued diagonal elements, which are the eigenvalues ​​of the covariance matrix.

[0211] Then, according to formula (33), we can obtain the following: Figure 8 The B1 matrix 812 shown is represented as The following can be calculated:

[0212] R I -1 / 2 =UD -1 / 2 U H (34)

[0213] By using Figure 8 The matrix operation circuit 808 shown includes a B1 matrix 812, which can be obtained by the multiplication circuit 811, while the inverse square root real-valued diagonal matrix D is obtained by the inverse square root circuit 806. -1 / 2 807 only requires performing individual scalar inverse square root operations on each real diagonal element of the real diagonal matrix D 805.

[0214] According to some embodiments, a QR decomposition-based SIC detection circuit 825 can be used, but those skilled in the art will understand that other methods can also be used to implement SIC detection. For example, traditional MMSE-based SIC detection requires multiple iterations to achieve layer-by-layer interference cancellation, and each iteration requires recalculating the filter matrix. While this can achieve more reliable detection, it comes at the cost of higher latency, higher power consumption, and higher hardware complexity. More specifically, firstly, the extended channel H3 matrix is ​​factored based on the QR decomposition (QRD) circuit 826 to obtain:

[0215]

[0216] In this embodiment, the orthogonal unitary matrix Q 834, which has exactly orthogonal columns, is divided into (N... R ×N L ) matrix Q1 and (NL ×N L ) matrix Q2, and the upper triangular matrix R 835 is also an upper triangular matrix.

[0217] According to formulas (35) and (36), the relationship between Q1 and Q2 can be described as follows:

[0218]

[0219] Using the relationship shown in formula (37), the extended preprocessed received signal vector y2 824 is compared with Q. H Multiplying them together yields the following statistics:

[0220]

[0221] The first term on the right side of formula (38) (containing the upper triangular matrix R835) represents the interference from the detected symbol and constructs the SIC architecture for introducing continuous interference cancellation. The second term on the right side of formula (containing the lower triangular matrix Q2) H The first term represents interference from undetected symbols, and the third term represents the remaining interference plus noise, where the expected signal is contained in the first and second terms.

[0222] Then, the entire process of SIC detection based on formula (38) can be represented by the following pseudocode:

[0223] Algorithm 3

[0224] Input: an orthogonal unitary matrix Q834, an upper triangular matrix R835, and a y3 vector.

[0225] Output: Equalized signal vector x842, noise variance vector v844

[0226] Step 1 - Formulation

[0227] Assume the detection order is [N] L ,…,1]. Typically, the i-th detected symbol y3(i) (i=N) L ,…,1) can be represented as:

[0228]

[0229] Where: (.)ii represents the element in the i-th row and i-th column of the matrix, r i This represents the remaining interference and noise in the i-th detection layer.

[0230] The first component on the right side of formula (39) contains the expected signal, the second component on the right side contains the interference from the detected symbols, which will be continuously canceled by the Gaussian elimination circuit, the third component represents the interference from the undetected symbols, and the fourth component represents the remaining filtered interference plus noise.

[0231] For ease of analysis, the third and fourth components on the right-hand side of equation (39) can be expressed as e i That is, the equivalent interference plus noise of the i-th detection layer:

[0232]

[0233] The equalization gain of the i-th detection layer can be expressed as:

[0234]

[0235] Then, formula (39) can be reformulated as:

[0236]

[0237] Step 2 – Initialization

[0238] According to the general formulas in formulas (39)-(42), when i = N L The first detection layer, the first equalization symbol x i and noise variance v i It can be defined as:

[0239]

[0240] Step 3 – Gaussian Elimination

[0241] For i = N L , ..., 1

[0242]

[0243] Finish

[0244] In formula (45), d i Corresponding to the second term on the right-hand side of formula (39), and in the first detection layer shown in the algorithm, i = N L , to obtain d i =0. Furthermore, Quant(.) in formula (46) reveals the quantization operation, where quantization is used to find the QAM constellation point closest to the equalization symbol to further improve detection reliability, but at the cost of higher circuit power consumption and longer delay. Here, different QAM constellation schemes can be selected during operation, such as BPSK, QPSK, 16QAM, 64QAM, and 256QAM, depending on the scheme adopted by the transmitter. For example, in... Figure 5 In the QPSK constellation scheme shown, the estimated complex value of the received symbol is 0.9 + 0.8i. The quantization operation Quant(.) is used to find the constellation point closest to the estimated symbol, where constellation point A located at 0.707 + 0.707i is the closest point to the estimated symbol, as shown below. Figure 5As shown, 0.707 + 0.707i is the output of Quant(.) in formula (46) in this embodiment. In addition, the noise variance vector v844 can be calculated by means of the noise variance calculation circuit 843 according to formulas (44) and (47).

[0245] In the introduction Figure 8 After discussing the basic principles and operation of the matrix-extended combined IRC MMSE-SIC equalizer proposed in the previous paper, some functional modules will be discussed in detail below.

[0246] According to some embodiments described herein, Figure 8 The MIMO equalizer circuit 800 shown can optionally include four switches, each of which supports two operating modes under the instruction of the controller 848, and the four switches can support a combination of sixteen operating modes.

[0247] More specifically, such as Figure 8 As shown, the first switch 849 supports the first operating mode, where the covariance matrix input 200 (in this example, it contains both interference and noise, such as...) Figure 2 (As shown in the example on the left) for equalization following the MMSE-IRC criterion as described above, wherein the first switch 849 optionally supports a second operating mode, wherein the noise power scalar 124 is generated from the fourth input. Figure 2 The diagonal covariance matrix 201 shown in the example on the right is used for equalization following the MMSE criterion under the instruction of controller 848. The fourth input, the noise power scalar 124, is optional and requires... Figure 8 The covariance matrix generation circuit 122 shown is used to calculate... Figure 2 The diagonal covariance matrix 201 is shown in the example covariance matrix on the right.

[0248] Figure 8 The second switch 815 supports a third operating mode, in which the inverse square root circuit described above is used, which can be based on the Schul decomposition expressed in Equation (33). Furthermore, the second switch 815 may optionally support a fourth operating mode, in which the diagonal inverse square root matrix circuit 813 is used under the instruction of the controller 848. Specifically, the diagonal inverse square root matrix circuit only needs to be used for... Figure 2 The example of the covariance matrix on the right side shows a diagonal covariance matrix 201. The noise power scalar 124 is used as an optional fourth input. The real-valued diagonal elements generated are inverted by taking the square root of each element, resulting in a B2 matrix 814, which provides the inverse square root matrix. For example, a real-valued diagonal covariance matrix R with dimension (2×2) I It can be defined as shown in formula (48)

[0249]

[0250] In formula (48) R I The square root matrix R I 1 / 2 It can be represented as:

[0251]

[0252] Based on formula (49), the inverse square root matrix R of formula (48) I -1 / 2 It can be represented as:

[0253]

[0254] Due to its lower complexity, using the diagonal inverse square root matrix circuit 813 can offer benefits such as reduced latency and lower power consumption. For example, the second switch 815 can operate in a fourth mode when the input is provided by a diagonal covariance matrix 201 generated from an optional fourth input of the noise power scalar 124, and in a third mode when the input is provided by a covariance matrix input 200 containing interference and noise. Alternatively, the third mode can be used when only minimal interference is detected in the received signal vector y 801. It should be noted that skilled practitioners will recognize that hardware complexity can be reduced by reusing the circuitry between the Shure decomposition-based inverse square root circuit and the diagonal inverse square root matrix circuit 813, and by incorporating the second switch 815 into the controller 848 of the final circuit.

[0255] Then, Figure 6 The third switch 847 supports a fifth operating mode, in which the QRD circuit 826 is used in the SIC detection circuit as described above, and the permutation P matrix output of the QRD circuit 826 is an identity matrix, indicating that the detection sequence is based on [N]. L [,...,1], as described in step 1 of Algorithm 3. Furthermore, the third switch 847 optionally supports a sixth operating mode, in which the sorting QRD (SQRD) circuit 830 is used to determine an optimized detection order, wherein the permutation P matrix for determining the optimized detection order is generated by the SQRD circuit 830 and used to permutate the order of detected symbols after Gaussian elimination is performed under the instruction of the controller 848. Specifically, the detection order can be modified by permuting the x elements in Algorithm 3 and the corresponding columns of the channel estimation matrix H before the QR decomposition in Equation (35), thereby obtaining an updated Q matrix and an updated R matrix. To find the optimal sequence, it is necessary to maximize the norm |h| of the column vector hi in the channel estimation matrix H. i | 2 (i=N) L ,…,1), where the norm |h i| 2 (i=N) L The calculation and sorting of ,…,1) are performed before formula (35), and these operations only need to be performed once.

[0256] Specifically, the dimension is (N) L ×N L The permutation M matrix represents the detection order calculated based on the norm. It is a variant of the identity matrix where the M matrix has a "1" in each row and each column, and zeros in all other positions. More specifically, the basic idea of ​​the sorting process in the SQRD circuit 830 is that consecutive layers detected in the SIC process can only propagate errors to layers detected sequentially after them. By detecting layers in descending order of input SINR, the probability of error propagation can be reduced, and the output SINR between layers can be improved. The sorting process in the SQRD circuit 830 can be achieved by estimating the N of the preprocessed channel estimate H3 matrix 823 according to the extended formula (35). L The norm of the columns is used to sort the layers, with the layer with the smallest norm being detected first.

[0257] More specifically, by applying the permutation matrix M to the equalized signal vector output 839 of the Gaussian elimination circuit 837 with quantization, the equalized signal vector x 842 in Equation (46) can be updated to Mx, and the noise variance vector v 844 in Equation (47) can be updated to Mv. Specifically, it is preferable to enable the fifth operating mode to eliminate the delay and power consumption associated with the sequencing operation. Furthermore, in a practical system, the decision to enable the sequencing process can be controlled at runtime based on the channel SINR, where it is preferable to disable the sequencing process when the SINR is below a certain threshold and to enable the sequencing process when the SINR is above that threshold. Skilled practitioners will recognize that other features, such as channel gain or covariance matrix properties, can be used to control the decision.

[0258] It is important to note that in actual implementation, QRD circuit 826 and SQRD circuit 830 can be implemented separately and together with the physical implementation of the third switch 847. Alternatively, skilled practitioners will recognize that hardware complexity can be reduced by reusing the circuitry between QRD circuit 826 and SQRD circuit 830 and incorporating the third switch 847 into the controller 848 of the final circuit. Alternatively, implementers of the examples described herein may choose to use only the SQRD variant of the SIC detection circuit without supporting the QRD variant. In summary, there are three options for the SIC detection circuit 825: a first variant using only QRD, a second variant using only SQRD, and a third variant that includes the third switch and allows selection between QRD and SQRD at runtime.

[0259] also, Figure 8 The fourth switch 841 supports a seventh operating mode, in which the Gaussian elimination circuit 837 with quantization described in the pseudocode of Algorithm 3 is used. The fourth switch 841 optionally supports an eighth operating mode, in which the Gaussian elimination circuit 838 without quantization is used under the instruction of the controller 848, wherein Quant(y3(i)-d) in Algorithm 3... i / μ i The function is defined by (y3(i)-d) in formula (46). i ) / μ i Replacement. Quantization is used to find the QAM constellation point closest to the equalization symbol to further improve detection reliability, but at the cost of higher power consumption and higher latency. Quantization can be disabled when lower power consumption and lower latency circuitry are required. It's important to note that in practical implementations, the Gaussian elimination circuit 837 with quantization and the Gaussian elimination circuit 838 without quantization can be implemented separately, reducing the physical implementation of the fourth switch. Alternatively, skilled practitioners will recognize that hardware complexity can be reduced by reusing the circuitry between the Gaussian elimination circuit 837 with quantization and the Gaussian elimination circuit 838 without quantization and incorporating the fourth switch into the final circuit's controller.

[0260] all in all, Figure 12 Flowchart 1200 illustrates the specific performance of a MIMO equalization example. Operations begin at 1201, where the covariance matrix R is used... I 123 Calculate the inverse square root covariance matrix R I -1 / 2 816. Subsequently, an IRC preprocessing operation is performed at 1202, which converts the inverse square root covariance matrix R... I -1 / 2 816. The received signal vector y301 and the channel estimation matrix H121 are converted into a preprocessed received signal vector y1 820 and a preprocessed channel estimation matrix H2 821. Subsequently, the preprocessed received signal vector y1 820 and the preprocessed channel estimation matrix H2 821 are extended at 1203 to generate an extended preprocessed received signal vector y2 824 and an extended preprocessed channel estimation matrix H3 823. Then, the equalization signal vector x 842 is calculated, and in some embodiments, the equalization signal vector x 842 is output at 1204 as part of the SIC detection and as a function of the extended preprocessed received signal vector y2 and the extended preprocessed channel estimation matrix H3 823.

[0261] According to some embodiments described herein, Figure 9 Showing Figure 6The example simulation results shown are for a matrix-extended MMSE-SICMIMO equalizer configuration, illustrating the relationship between SINR gain and SINR under the linear MMSE criterion. Figure 9 As shown, based on our exemplary simulations of a 3GPP criterion scenario, we have demonstrated that the MMSE-IRC criterion offers approximately 3 dB of SINR gain over a wide SINR range compared to the linear MMSE criterion. Specifically, in the low SINR region, the SINR gain exceeds 3 dB, even reaching 9.2 dB higher than the linear MMSE criterion. Furthermore, in the medium SINR region, the proposed matrix-extended MMSE-SIC MIMO equalizer provides up to 1.0 dB of SINR gain compared to the MMSE-IRC criterion.

[0262] application

[0263] Now for reference Figure 10 The figure illustrates a typical computing system 1000, which can be used to implement equalizer calculations according to some exemplary embodiments. Such computing systems can be used in wireless communication units. Those skilled in the art will also understand how to implement the examples described herein using other computer systems or architectures. The computing system 1000 can represent, for example, a desktop computer, a laptop or notebook computer, a handheld computing device (PDA, mobile phone, PDA, etc.), a mainframe, a server, a client, or any other type of dedicated or general-purpose computing device required or suitable for a particular application or environment. The computing system 1000 may include at least one processor, such as processor 1004. Processor 1004 may be implemented using a general-purpose or dedicated processing engine (e.g., a microprocessor, microcontroller, or other control logic). In this embodiment, processor 1004 is connected to bus 1002 or other communication media. In some embodiments, the computing system 1000 may be a non-transitory tangible computer program product containing executable code for implementing equalizer calculations.

[0264] The computing system 1000 may further include a main memory 1008, such as random access memory (RAM) or other dynamic memory, for storing information and instructions to be executed by the processor 1004. The main memory 1008 may also be used to store temporary variables or other intermediate information during instruction execution by the processor 1004. The computing system 1000 may also include a read-only memory (ROM) or other static storage device coupled to the bus 1002 for storing static information and instructions of the processor 1004.

[0265] The computing system 1000 may also include an information storage system 1010, which may include, for example, a media drive 1012 and a removable storage interface 1020. The media drive 1012 may include a drive or other mechanism to support fixed or removable storage media, such as a hard disk drive, floppy disk drive, magnetic tape drive, optical disc drive, compact optical disc (CD) or digital video drive (DVD) read or write drive (R or RW), or other removable or fixed media drives. Storage media 1018 may include, for example, a hard disk, floppy disk, magnetic tape, optical disc, CD or DVD, or other fixed or removable media that can be read and written by the media drive 1012. As these examples illustrate, storage media 1018 may include a computer-readable storage medium storing specific computer software or data.

[0266] In an alternative embodiment, the information storage system 1010 may include other similar components for allowing computer programs or other instructions or data to be loaded into the computing system 1000. These components may include, for example, removable storage unit 1022 and interface 1020 (e.g., program cartridge and cartridge interface), removable memory (e.g., flash memory or other removable memory modules) and memory slots, as well as other removable storage unit 1022 and interface 1020 for transferring software and data from removable storage unit 1018 to computing system 1000.

[0267] The computing system 1000 may also include a communication interface 1024. The communication interface 1024 allows software and data to be transferred between the computing system 1000 and external devices. Examples of the communication interface 1024 may include a modem, a network interface (e.g., Ethernet or other NIC card), a communication port (e.g., a Universal Serial Bus (USB) port), a PCMCIA slot, and cards. Software and data transmitted through the communication interface 1024 exist in the form of signals, which may be electronic signals, electromagnetic signals, optical signals, or other signals that can be received by the communication interface 1024. These signals are provided to the communication interface 1024 through a channel 1028. This channel 1028 can carry signals and can be implemented using wireless media, wired or cable, fiber optics, or other communication media. Examples of channels include telephone lines, cellular telephone links, radio frequency links, network interfaces, local area networks (LANs) or wide area networks (WANs), and other communication channels.

[0268] In this document, terms such as "computer program product" and "computer-readable medium" generally refer to media such as memory 1008, storage device 1018, or storage unit 1022. These and other forms of computer-readable media may store at least one instruction for use by processor 1004 to cause the processor to perform a specified operation. Such instructions are generally referred to as "computer program code" (which may be classified as a computer program or other type of code) and, when executed, enable computing system 1000 to perform the functions of the examples described herein. It should be noted that the code may directly cause the processor to perform the specified operation, or it may be compiled to perform the specified operation, and / or combined with other software, hardware, and / or firmware elements (e.g., libraries for performing guideline functions) to perform the specified operation.

[0269] In implementations that use software to implement these elements, the software may be stored on a computer-readable medium and loaded into the computing system 1000 using, for example, a removable storage drive 1022, a drive 1012, or a communication interface 1024. When the control logic (in this embodiment, software instructions or computer program code) is executed by the processor 1004, it causes the processor 1004 to perform the functions described herein.

[0270] In the foregoing specification, embodiments have been described with reference to specific implementation methods. However, it is apparent that various modifications and alterations can be made thereto without departing from the scope of the invention as set forth in the appended claims, and the claims are not limited to the specific embodiments described above.

[0271] The connections described herein can be any type of connection suitable for transmitting / towards signals from / to corresponding nodes, units, or devices, for example, via intermediate devices. Therefore, unless otherwise implied or stated, connections can be, for example, direct or indirect connections. Connections can be described or illustrated as a single connection, multiple connections, unidirectional connections, or bidirectional connections. However, different implementations may change how the connection is implemented. For example, a single unidirectional connection may be used instead of a bidirectional connection, and vice versa. Furthermore, a single connection transmitting multiple signals serially or in time-division multiplexing mode may be used instead of multiple connections. Similarly, a single connection carrying multiple signals may be separated into various different connections carrying subsets of these signals. Therefore, a variety of signal transmission options exist.

[0272] Those skilled in the art should recognize that the architecture described herein is merely exemplary, and many other architectures can actually be implemented to achieve the same functionality.

[0273] Any arrangement of components used to achieve the same function is effectively “associated” with each other to achieve the desired functionality. Therefore, any two components combined to achieve a specific function in this paper can be considered “associated” with each other to achieve the desired functionality, regardless of their architecture or intermediate components. Similarly, any two such associated components can also be considered “operationally connected” or “operationally coupled” with each other to achieve the desired functionality.

[0274] Furthermore, those skilled in the art should recognize that the boundaries between the above operations are merely exemplary. Multiple operations can be combined into a single operation, a single operation can be distributed among other operations, and operations can be performed with at least partial overlap in time. Moreover, alternative implementations may include multiple instances of a particular operation, and the order of operations can be varied in various other implementations.

[0275] Embodiments are described with reference to integrated circuit devices that include a microprocessor (e.g., a microprocessor configured to perform equalizer calculations). However, it should be understood that the examples described herein are not limited to such integrated circuit devices and are equally applicable to integrated circuit devices that include any other type of operational functionality. Examples of such integrated circuit devices that include any other type of operational functionality may include (by way of example only) application-specific integrated circuit (ASIC) devices, field-programmable gate array (FPGA) devices, or those integrated with other components, etc. Furthermore, since the embodiments described herein are largely implemented using electronic components and circuits known to those skilled in the art, excessive detail has not been provided unless it is deemed necessary to understand and grasp the basic concepts of the embodiments described herein and to avoid confusion or deviation from the teachings of the embodiments described herein. Alternatively, circuit and / or component embodiments may be implemented as any number of separate integrated circuits or separate devices and interconnected in a suitable manner.

[0276] For example, these embodiments or portions thereof may be implemented as a software or code representation of physical circuitry, or a logical representation of physical circuitry that can be converted into such a representation as any suitable type of hardware description language.

[0277] Furthermore, the embodiments described herein are not limited to physical devices or units implemented in non-programmable hardware, but can also be applied to programmable devices or units capable of performing the required equalizer calculations by running appropriate program code, such as minicomputers, personal computers, laptops, personal digital assistants, video games, automobiles and other embedded systems, mobile phones and various other wireless devices, which are generally referred to as "computer systems" in this application.

[0278] However, other modifications, changes, and substitutions are possible. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0279] In the claims, any reference signs within parentheses should not be construed as limiting the claims. The word 'comprising' does not exclude the presence of elements or steps other than those listed in the claims. Furthermore, the terms 'a(a)' or 'an(a)' as used herein are defined as at least one. Moreover, the use of introductory phrases such as "at least one" in the claims should not be construed as implying that the introduction of another claim element by the indefinite article "a" or "an" limits any particular claim containing that introduced claim element to an invention containing only one such element, even if the same claim contains the introductory phrase "at least one" and indefinite articles such as "a" or "an". The same applies to the use of definite articles. Unless otherwise stated, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate the time or other priority of these elements. The mere recitation of certain measures in mutually different claims does not mean that an advantage cannot be gained by utilizing a combination of these measures. The term "subset" refers to elements selected from a set, which may include one, some, or all of the elements in that set.

[0280] References

[0281] [1]"3rd Generation Partnership Project; Technical Specification GroupRadio Access Network; Performance Requirements of MMSE-IRC receiver for LTE BS(Release 13)", 3GPP TR 36.884V13.1.0, September 2016.

[0282] [2] Yang, Lie-Liang. Multicarrier communications. John Wiley & Sons, 2009.

[0283] [3]Tavares, Fernando ML, et al. "On the potential of interferencerejection combining in B4G networks." 2013IEEE 78th Vehicular Technology Conference (VTC Fall). IEEE, 2013.

[0284] [4]Zhu,X.and Murch,R.D.,2002.Performance analysis of maximumlikelihood detection in a MIMO antenna system.IEEE Transactions onCommunications,50(2),pp.187-191.

Claims

1. A multiple-input multiple-output (MIMO) equalizer circuit (300), comprising: Controller (339); An autocorrelation matrix calculation circuit (302), operably coupled to the controller (339), and having the capability to operably receive the covariance matrix R I (123) is the covariance matrix input and the channel estimation matrix input of the operably received channel estimation matrix H(121), wherein the autocorrelation matrix calculation circuit (302) is configured to respond to the received covariance matrix R I (123) and the channel estimation matrix H (121) generate the autocorrelation matrix W (308), and output the autocorrelation matrix W (308) to the first output; A matrix inversion circuit (309), operably coupled to the controller (339) and the autocorrelation matrix calculation circuit (302), and having an autocorrelation matrix input to receive the autocorrelation matrix W (308) from the autocorrelation matrix calculation circuit (302), wherein the matrix inversion circuit (309) is configured to invert the autocorrelation matrix W (308) and output the inverse autocorrelation matrix (315) to a second output; A matrix operation circuit (316), operably coupled to the controller (339) and the matrix inversion circuit (309), and having: Receive the inverse autocorrelation matrix input of the inverse autocorrelation matrix (315); The received signal vector input is the received signal vector y(301); and Receive the channel estimation matrix input of the channel estimation matrix H(121); The matrix operation circuit (316) is configured as follows: The received inverse autocorrelation matrix (315) and the channel estimation matrix H (121) are combined to generate an equalization gain P matrix (324) and output to a third output; and The received inverse autocorrelation matrix (315), the received signal vector y (301), and the channel estimation matrix H (121) are combined to generate a vector f (323) and output it to the fourth output; and A continuous interference cancellation (SIC) detection circuit (325), operably coupled to the controller (339) and operably coupled to the third and fourth outputs of the matrix operation circuit (316), wherein the SIC detection circuit (325) is configured as follows: The received P matrix (324) is converted into a first orthogonal unitary matrix Q (328) and a first upper triangular matrix R (327), and The first orthogonal unitary matrix Q (328), the first upper triangular matrix R (327), and the f vector (323) are converted into the equilibrium symbol Z2 vector (330) estimated by SIC. The SIC detection circuit (325) is configured to output the Z2 vector (330).

2. The MIMO equalizer circuit (300) according to claim 1, wherein, The covariance matrix R I (123) has an equal number of spatial flows N R The sum of the first dimensions equals the number of spatial flows N R The second dimension, wherein the channel estimation matrix H(121) has a spatial flow number N equal to the number of spatial flows. R The sum of the first dimensions equals the number of layers N L The second dimension, wherein the received signal vector y(301) has a spatial flow number N equal to the number of spatial flows. R The length of the Z2 vector (330) is equal to the number of layers N. L The length.

3. The MIMO equalizer circuit (300) according to claim 2, wherein, The number of spatial flows N R and the number of layers N L The operation varies between the cycles of the MIMO equalizer circuit during operation.

4. The MIMO equalizer circuit (300) according to claim 2 or 3, wherein, The autocorrelation matrix W (308) and the inverse autocorrelation matrix (315) have a spatial flow number N equal to the number of spatial flows. R The sum of the first dimensions equals the number of spatial flows N R The second dimension, where the P matrix (324) has an equal number of layers N. L The sum of the first dimensions equals the number of layers N L The second dimension, wherein the f vector (323) has a number of layers N. L The length.

5. The MIMO equalizer circuit (300) according to any one of the preceding claims, wherein, The autocorrelation matrix calculation circuit (302) includes: Hermitian transpose circuit (303) is configured to receive the channel estimation matrix H (121) and perform Hermitian transpose to convert the channel estimation matrix H (121) into Hermitian transpose matrix H2 (304); A matrix multiplication circuit (305), operably coupled to the output of the Hermitian transpose circuit (303), and configured to receive the channel estimation matrix H (121) and convert the received channel estimation matrix H (121) and the Hermitian transpose H2 matrix (304) into a Hermitian H3 matrix (306); and A matrix addition circuit (307), operably coupled to the output of the matrix multiplication circuit (305), and configured to receive the covariance matrix R I (123), and the Hermitian H3 matrix (306) and the covariance matrix R I (123) are added together to generate the autocorrelation matrix W(308).

6. The MIMO equalizer circuit (300) according to any one of the preceding claims, wherein, The matrix inversion circuit (309) includes: A first QR decomposition circuit QRD (310) operable to receive and perform QR decomposition on the autocorrelation matrix W (308), converting the autocorrelation matrix W (308) into a second orthogonal unitary matrix Q (311) and a second upper triangular matrix R (312) under the instruction of the controller (339); and A first Gaussian elimination circuit (314) is operable to perform Gaussian elimination, converting the second orthogonal unitary matrix Q (311), the second upper triangular matrix R (312), and the identity matrix I (313) into the inverse autocorrelation matrix (315) under the instruction of the controller (339).

7. The MIMO equalizer circuit (300) according to claim 6, wherein, The first Gaussian elimination circuit (314) is operable to perform a Hermitian variant of Gaussian elimination.

8. The MIMO equalizer circuit (300) according to any one of the preceding claims further includes a first switch (340), the first switch being operated under the instruction of the controller (339), wherein: In the first operating mode, the first switch is configured to receive and output the covariance matrix R. I (123); and In the second operating mode, the MIMO equalizer circuit (300) further includes a covariance matrix generation circuit (122), which is operatively coupled to the first switch (340) and configured to receive a noise power scalar (124). The covariance matrix generation circuit (122) uses the noise power scalar (124) to generate a diagonal covariance matrix (201), and the first switch outputs the diagonal covariance matrix (201) as a covariance matrix R. I (123).

9. The MIMO equalizer circuit (300) according to any one of the preceding claims, wherein, The matrix operation circuit (316) also includes: A first matrix operation subcircuit (343) operable to convert the inverse autocorrelation matrix (315) and the channel estimation matrix H (121) into a G matrix (320) and a P matrix (324); and A second matrix operation subcircuit (344) is operatively coupled to the first matrix operation subcircuit (343) and configured to convert the G matrix (320) and the received signal vector y (301) into the f vector (323).

10. The MIMO equalizer circuit (300) according to claim 9, wherein, The first matrix operation sub-circuit (343) further includes: Hermitian transpose circuit (317), configured to perform a Hermitian transpose of the channel estimation matrix H (121) into a Hermitian transpose matrix H4 (318); and A first matrix multiplication circuit (319) is configured to convert the Hermitian transpose H4 matrix (318) and the inverse autocorrelation matrix (315) into the G matrix (320); and A second matrix multiplication circuit (322) is configured to convert the G matrix (320) and the channel estimation matrix H (121) into the P matrix (324).

11. The MIMO equalizer circuit (300) according to claim 9, wherein, The second matrix operation sub-circuit (344) includes a third matrix multiplication circuit (321), which is operable to perform multiplication operations and convert the G matrix (320) and the received signal vector y (301) into the f vector (323).

12. The MIMO equalizer circuit (300) according to any one of the preceding claims, wherein, The SiC detection circuit (325) also includes: A second QR decomposition QRD circuit (326), operable to perform QR decomposition under the instruction of the controller (339), transforming the P matrix (324) into the first orthogonal unitary matrix Q (328) and the first upper triangular matrix R (327); and A second Gaussian elimination circuit (329), which is operatively coupled to the second QRD circuit (326) and configured to perform Gaussian elimination under the instruction of the controller (339) to convert the first orthogonal unitary matrix Q (328), the first upper triangular matrix R (327) and the f vector (323) into the Z2 vector (330).

13. The MIMO equalizer circuit (300) according to claim 12, wherein, The SIC detection circuit (325) further includes a second switch (404) operatively coupled to the second Gaussian elimination circuit (329) and the controller (339) and configured to support: In the third operating mode, the second Gaussian elimination circuit (329) performs Gaussian elimination with quantization (400); and The fourth operating mode, wherein the second Gaussian elimination circuit (329) performs Gaussian elimination (401) without quantization.

14. The MIMO equalizer circuit (300) according to any one of the preceding claims further includes: The first output (332) provides the equalization signal vector x; A division circuit (341) is configured to receive the f vector (323) and the P matrix (324) and perform a division operation to convert the f vector (323) and the P matrix (324) into the z vector (342); as well as A third switch (331), operably coupled to the output of the controller (339) and the SIC detection circuit (325), and configured by the controller (339) to support: The fifth operating mode, wherein the equalization signal vector x (332) is provided by the z vector (342); and The sixth operating mode, wherein the equalization signal vector x (332) is provided by the Z2 vector (330).

15. The MIMO equalizer circuit (300) according to claim 14, wherein, The third switch (331) is configured by the controller (339) to select the fifth operating mode when the channel signal-to-interference-plus-noise ratio (SINR) is lower than the threshold, and is also configured by the controller (339) to select the sixth operating mode when the channel SINR is higher than the threshold.

16. The MIMO equalizer circuit (300) according to any one of claims 14 to 15, wherein, The MIMO equalizer circuit (300) further includes a SiC noise variance calculation circuit (333), which is configured to receive the G matrix (320), the first upper triangular matrix R (327), the first orthogonal unitary matrix Q (328), and the covariance matrix RI (123), and is operatively coupled to a second output (337). When the third switch is configured to support a sixth operating mode, the SiC noise variance calculation circuit (333) will receive the G matrix (320), the first upper triangular matrix R (327), the first orthogonal unitary matrix Q (328), and the covariance matrix RI (123), and is operatively coupled to a second output (337). I (123) is converted into the first noise variance vector (334), and the first noise variance vector is provided to the second output (337).

17. The MIMO equalizer circuit (300) according to claim 16, when subordinate to any one of claims 14 and 9 to 11, wherein, The second output is operatively coupled to a non-SIC noise variance calculation circuit (335), which is configured to calculate the G matrix (320) and the covariance matrix R. I (123) and the P matrix (324) are converted into a second noise variance vector (336), wherein the second noise variance vector (336) is provided to the second output (337) when the third switch (331) is configured to support the fifth operating mode.

18. A communication unit comprising a MIMO equalizer circuit (300) according to any one of the preceding claims.

19. A method for performing multiple-input multiple-output (MIMO) equalization, comprising: The covariance matrix R is received by the autocorrelation matrix calculation circuit (302). I (123) and the channel estimation matrix H(121), and generate the autocorrelation matrix W(308); The autocorrelation matrix W (308) is inverted by the matrix inversion circuit (309), and the inverse autocorrelation matrix (315) is output. The inverse autocorrelation matrix (315) and the channel estimation matrix H (121) are combined by the matrix operation circuit (316) to generate the equalization gain P matrix (324); as well as The matrix operation circuit (316) receives and combines the inverse autocorrelation matrix (315), the received signal vector y (301), and the channel estimation matrix H (121) to generate the vector 'f' (323). The P matrix (324) is converted into a first orthogonal unitary matrix Q (328) and a first upper triangular matrix R (327) by a continuous interference cancellation (SIC) detection circuit (325); The first orthogonal unitary matrix Q (328), the first upper triangular matrix R (327), and the f vector (323) are converted into the equilibrium symbol Z2 vector (330) estimated by the SIC detection circuit (325); and Output the Z2 vector (330).

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