Semiconductor device with test element set and test method thereof
By setting up shared test element groups and phase decoders among integrated circuit chips, the chip location can be dynamically identified, solving the problems of resource waste and inefficiency in existing technologies, and achieving efficient chip testing and cost reduction.
Patent Information
- Application Number
- CN202511439253.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-09
- Publication Date
- 2025-12-26
AI Technical Summary
Existing technologies lack dynamic identification and selection mechanisms, making it impossible to effectively distinguish the source or location of integrated circuit chips, resulting in wasted testing resources and low efficiency.
A chip-shared test element group based on phase recognition is adopted, and the chip is dynamically selected for testing through a phase decoder, which simplifies probe card design and reduces the number of test pads and wafer area waste.
It enables dynamic identification of chip origin and location, reduces probe card maintenance costs, improves testing efficiency, reduces wafer area waste and testing time, and reduces post-packaging interference and power consumption risks.
Smart Images
Figure CN121208588A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit manufacturing technology, specifically relating to a semiconductor device with a test element group and its test method. Background Technology
[0002] In recent years, very large-scale integrated circuits (VLSI) have developed rapidly. To ensure the quality of integrated circuits, it is necessary to strictly monitor the manufacturing process of integrated circuit chips. Among these measures, electrical testing is one of the important chip monitoring methods.
[0003] By fabricating test circuits in dicing slots between chips and performing electrical tests on the test pads within these circuits, the electrical performance and anomalies of semiconductor devices can be fully reflected. The wafer testing stage requires providing independent test pads for each chip, leading to a waste of dicing slot (cutting track) space and testing resources. Current testing technologies are mostly static or single-chip testing, lacking dynamic identification and selection mechanisms, and unable to effectively distinguish chip origin or chip location. Summary of the Invention
[0004] The purpose of this invention is to provide a semiconductor device with a test element group and a testing method thereof. Based on phase recognition, several chips share the test element group, which can effectively distinguish the source or location of several chips; a dynamic identification and selection mechanism is employed. This simplifies the probe card, reducing probe card maintenance costs. It also reduces the number of test pads, minimizes wafer area waste, and improves testing efficiency.
[0005] This invention provides a semiconductor device having a test element group, comprising: A substrate on which a plurality of chips and dicing grooves are formed, wherein a plurality of chips are formed and dicing grooves are located between the chips; A test element group is provided in the dicing groove; the test element group is shared by N adjacent chips, where N≥2 and N is an integer; The test element group is equipped with a test circuit, which includes a phase decoder. The test circuit selects one chip from the N chips based on the received phase signal and uses the test element group for testing.
[0006] Furthermore, the test circuit also includes: a plurality of test pads, test devices, and metal wires; the test pads and the test devices are electrically connected through the metal wires.
[0007] Furthermore, the test pads are rectangular or square in shape, and several test pads are spaced apart; the test devices involve various test types such as voltage, current, resistance, and capacitance; during electrical testing, test probes are inserted into the test pads, and different voltages and currents are applied according to different test purposes, while the electrical signals fed back by the test devices are received to determine the electrical performance of the chip.
[0008] Furthermore, the chip includes a multitasking unit, which performs at least one of the following functions: signal selection, test mode switching, and support for programmable testing; the test pad in the test circuit is electrically connected to the multitasking unit.
[0009] Furthermore, the number of test pads in one of the test element groups is 2 to 8.
[0010] Furthermore, the phase-recognition selected chip is connected to the tester and the test pad in the test circuit for testing.
[0011] Furthermore, the test circuit uses phase offset or frequency modulation as an identifier based on the received phase signal to select a corresponding chip from the N chips.
[0012] Furthermore, the test element group is shared by two adjacent chips, the left chip and the right chip.
[0013] Furthermore, the four adjacent chips of the test element group share the test element group, and the four chips are the upper left chip, the upper right chip, the lower right chip, and the lower left chip; the phase angles corresponding to the four chips include 0°, 90°, 180°, and 270°; the encoding quadrants corresponding to the four chips include the first to the fourth quadrants.
[0014] The present invention also provides a testing method for a semiconductor device having a test element group, using the above-mentioned semiconductor device, comprising: The testing equipment sends a test signal, which contains phase information used to identify the chip; The test circuit in the test element group receives the test signal; The phase decoder decodes the test signal and selects one chip from the N chips that corresponds to the decoding; The test circuit tests the selected chip; The test results are transmitted back to the test equipment. The testing machine performs the above steps on the selected chip, and after the test is completed, it switches to the next chip, and so on, until all the chips under test have been tested.
[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a semiconductor device with a test element group and a testing method thereof, comprising: a substrate on which multiple chips and dicing grooves are formed, and a test element group is disposed within the dicing grooves; N adjacent chips of the test element group share the test element group, where N≥2, and N is an integer; a test circuit is disposed within the test element group, and the test circuit includes a phase decoder. This invention provides a phase recognition-based method for multiple chips to share a test element group, effectively distinguishing the origin or location of multiple chips; the test circuit selects one chip from the N chips for testing using the test element group based on a received phase signal, employing a dynamic identification and selection mechanism. This simplifies the probe card, reducing probe card maintenance costs. Sharing the test element group among multiple chips reduces the number of test pads, reduces wafer area waste, improves testing efficiency, and automatically removes the test circuit along with the dicing groove after wafer testing. It also reduces dicing groove width and wiring complexity, as the test circuit does not occupy internal chip space, reducing testing time and minimizing post-packaging interference and power consumption risks. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a semiconductor device with a test element group according to an embodiment of the present invention.
[0017] Figure 2 This is a schematic diagram of another semiconductor device with a test element group according to an embodiment of the present invention.
[0018] Figure 3 This is a schematic diagram illustrating the source of a phase recognition chip in a semiconductor device with a test element group according to an embodiment of the present invention.
[0019] Figure 4 This is a schematic diagram of the encoding quadrant in phase recognition of a semiconductor device with a test element group according to an embodiment of the present invention.
[0020] The reference numerals in the attached figures are as follows: 10 - Left chip; 20 - Right chip; 11 - Left chip internal solder pad; 21 - Right chip internal solder pad; 31 - Test device; 32 - Test pad. Detailed Implementation
[0021] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0022] For ease of description, some embodiments of this application may use spatially relative terms such as “above,” “below,” “top,” and “under” to describe the relationship between one element or component and another (or more) elements or components as shown in the accompanying drawings. It should be understood that, in addition to the orientations described in the drawings, spatially relative terms are also intended to include different orientations of the device during use or operation. For example, if the device in the drawings is flipped, it is described as an element or component “below” or “under” other elements or components, and will subsequently be positioned “above” or “on” other elements or components. The terms “first,” “second,” etc., used below are used to distinguish between similar elements and are not necessarily used to describe a particular order or temporal sequence. It should be understood that these terms, as used, may be replaced where appropriate.
[0023] This invention provides a semiconductor device with a test element group, comprising: A substrate on which multiple chips and dicing grooves are formed between the chips; A test element group is set in the dicing slot; N adjacent chips share the test element group, where N≥2 and N is an integer; The test element group includes a test circuit, which contains a phase decoder. The test circuit selects one chip from N chips based on the received phase signal and uses the test element group for testing.
[0024] Specifically, a test element group is set up in the dicing slot. The N adjacent chips of the test element group share the test element group, where N≥2 and N is an integer. The value of N is not limited and can be determined according to the actual configuration requirements.
[0025] In one example, such as Figure 1 and Figure 2 As shown, the test element group consists of two adjacent chips, left chip 10 and right chip 20, sharing the same test element group. The test element group includes a test circuit, which contains a phase decoder. The test circuit also includes several test pads 32, test devices 31, and metal wires. The test pads 32 are mostly rectangular or square in shape and are spaced apart. The test devices 31 handle voltage, current, resistance, and capacitance tests. The test pads 32 and the test devices 31 are connected by metal wires. During electrical testing, test probes are inserted into the test pads 32, and different voltages and currents are applied depending on the test objective. Simultaneously, the electrical signals fed back from the test devices 31 are received and converted into current, voltage, and resistance parameters. By analyzing these parameters, the electrical performance of each component within the chip can be determined.
[0026] The number of test pads 32 (also known as shared pins) in a shared test element group depends on the chip and is not limited; for example, it can be 2 to 8.
[0027] For three-terminal devices (such as bipolar transistors), the shared pin can be coupled to at least two of the base, emitter, and collector pins. For MOS transistors, the shared pin can be coupled to either four-terminal (gate, source, drain, body) or five-terminal devices (gate, source, drain, body, and substrate). At least two terminal pins in the.
[0028] Figure 1 The diagram illustrates a test element group containing six test pads 32 (also known as shared pins). If the phase recognition selects the left chip 10, the tester 31 and all (e.g., all six) test pads 32 in the test circuit are connected to the left chip 10 to test it. If the phase recognition selects the right chip 20, the tester 31 and all (e.g., all six) test pads 32 in the test circuit are connected to the right chip 20 to test it.
[0029] In another example, such as Figure 2 As shown, the chip is equipped with a MUX (multiplexer), also known as a multiplexer. The multiplexer performs at least one of the following functions: signal selection, test mode switching, and support for programmable testing. The test pad 32 in the test circuit is electrically connected to the MUX (multiplexer) to control the signal path and support testing and debugging.
[0030] A Multi-User Encoder (MUX) typically plays the following roles: Signal Selector: The MUX can selectively export signals from internal modules to the Test Element Group (TEG) area, or conversely, import test signals from the TEG into the chip's internal modules; this allows for testing or debugging without affecting the main functionality. Test Mode Switching: Switches signal paths between normal and test modes. For example, some modules do not need to be enabled during mass production, but their functionality needs to be verified by turning on the MUX during testing. Support for Programmable Test Architectures: The MUX can be integrated with scan chains, JTAG, or other testability design architectures, providing flexible test point selection.
[0031] In yet another example, such as Figure 3 and Figure 4 As shown, the four chips adjacent to the test element group share the test element group. The four chips are the top left chip, the top right chip, the bottom right chip, and the bottom left chip. The phase angles of the four chips are 0°, 90°, 180°, and 270°. The encoding quadrants of the four chips are the first to the fourth quadrant (Q1 to Q4).
[0032] This invention provides a semiconductor device with a test element group. Several chips share the test element group based on phase recognition, effectively distinguishing the source or location of the chips. The test circuit selects one chip from N chips for testing using the test element group based on the received phase signal, employing a dynamic recognition and selection mechanism. Voltage phase difference is used as the recognition mechanism to distinguish test signals from chips on the left or right. The test circuit is designed within the dicing channel and is automatically removed along with the dicing channel after wafer testing. This increases test UPH (units per hour), simplifies probe cards, and reduces probe card maintenance costs. Sharing the test element group among several chips reduces the number of test pads, reduces wafer area waste, improves testing efficiency, and the test circuit is automatically removed along with the dicing channel after wafer testing. It also reduces dicing channel width and wiring complexity, as the test circuit does not occupy internal chip space, reduces testing time, and reduces post-packaging interference and power consumption risks.
[0033] This invention also provides a testing method for a semiconductor device having a test element group. For example... Figure 1 and Figure 2 As shown, a test element group is set up within the dicing slot; the test element group contains a test circuit, which includes a phase decoder. The phase decoder is the core logic module, responsible for decoding the phase signal and determining which chip should be activated. The test element group is shared by N adjacent chips, where N≥2, and N is an integer; the example given is N=2. The left chip 10 and right chip 20, adjacent to each other in the test element group, share the test element group.
[0034] Test methods for semiconductor devices with test element groups include: S1. The test equipment sends a test signal, which contains phase information used to identify the chip; S2. The test circuit in the test element group receives the test signal; S3. The phase decoder decodes the test signal and selects one chip from the N chips that corresponds to the decoding; S4. The test circuit tests the selected chip; S5. The test results are sent back to the test equipment, and the source chip is marked; S6. The test machine performs tests on the selected chip according to steps S1 to S5. After the test is completed, it switches to the next chip and repeats this process until all chips under test are tested.
[0035] Specifically, in step S1, the test equipment sends a test signal, which contains phase information used to identify the chip; for example, the test signal includes a phase 0° signal and a phase 180° signal, representing two phase-encoded signals from the test equipment, such as the left chip and the right chip respectively.
[0036] S2. The test circuit receives the test signal; S3. The phase decoder decodes the test signal and selects one chip from N chips. In steps S2 and S3, the test circuit uses phase offset or frequency modulation as an identifier to select one chip from N chips based on the received phase signal. For example, the phase recognition logic uses phase offset (such as 0° and 180°) or frequency modulation as an identifier to select the source chip. This can be extended to several chips (such as four-quadrant phase encoding).
[0037] For example, test pad 32 in the test element group is located between the left chip 10 and the right chip 20, serving as a shared test signal interface. The test element group includes a test circuit designed within the cut track, containing test logic. The test circuit includes a phase decoder, which is responsible for determining the signal source based on the voltage phase and selecting the corresponding chip.
[0038] S4. The test circuit tests the selected chip; if the left chip is selected, the test circuit is connected through the solder pad 11 inside the left chip to test the left chip; if the right chip is selected, the test circuit is connected through the solder pad 21 inside the right chip to test the right chip.
[0039] S5. The test results are sent back to the test equipment and the source chip is marked. For the example of N=2, the source chip is one of the left chip and the right chip. For the example of N=4, the source chip is one of the top left chip, the top right chip, the bottom right chip, and the bottom left chip.
[0040] S6. The test machine performs tests on the selected chip according to steps S1 to S5. After the test is completed, it switches to the next chip and repeats this process until all chips under test are tested.
[0041] The semiconductor device with a test element group and the test method thereof provided by this invention can be applied to... High-density sensor arrays (such as image sensors), AI accelerator chip arrays, multi-core SoC test platforms, wafer-level packaging, and chiplet testing. Chiplet testing no longer tests a single chip, but rather a system composed of multiple dies, which may come from different process nodes, different design companies, or even different foundries. The semiconductor device with test element groups and its testing method provided by this invention can also be applied to automated placement processes integrated with EDA tools and several chip dynamic test scheduling algorithms.
[0042] In summary, this invention provides a semiconductor device with a test element group and a testing method thereof, comprising: a substrate, on which multiple chips and dicing grooves are formed, and a test element group is disposed within the dicing grooves; N adjacent chips of the test element group share the test element group, where N≥2, and N is an integer; a test circuit is disposed within the test element group, and the test circuit includes a phase decoder. This invention provides a phase recognition-based method for multiple chips to share a test element group, which can effectively distinguish the source or location of multiple chips; the test circuit selects one chip from the N chips for testing using the test element group based on the received phase signal, employing a dynamic identification and selection mechanism. This simplifies the probe card and reduces probe card maintenance costs. Sharing the test element group among multiple chips reduces the number of test pads, reduces wafer area waste, improves testing efficiency, and automatically removes the test circuit along with the dicing track after wafer testing. It also reduces dicing track width and wiring complexity, as the test circuit does not occupy internal chip space, reduces testing time, and reduces post-packaging interference and power consumption risks.
[0043] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the devices disclosed in the embodiments; relevant details can be found in the method section.
[0044] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A semiconductor device having a test element group, characterized in that, include: A substrate on which a plurality of chips and dicing grooves are formed, wherein a plurality of chips are formed and dicing grooves are located between the chips; A test element group is provided in the dicing groove; the test element group is shared by N adjacent chips, where N≥2 and N is an integer; The test element group is equipped with a test circuit, which includes a phase decoder. The test circuit selects one chip from the N chips based on the received phase signal and uses the test element group for testing.
2. The semiconductor device with a test element group as described in claim 1, characterized in that, The test circuit also includes: several test pads, test devices, and metal wires; the test pads and the test devices are electrically connected through the metal wires.
3. The semiconductor device with a test element group as described in claim 2, characterized in that, The test pads are rectangular or square in shape, and several test pads are spaced apart. The test devices involve various test types, including voltage, current, resistance, and capacitance. During electrical testing, test probes are inserted into the test pads, and different voltages and currents are applied according to different test purposes. At the same time, the electrical signals fed back by the test devices are received to determine the electrical performance of the chip.
4. The semiconductor device with a test element group as described in claim 2, characterized in that, The chip includes a multitasking unit, which performs at least one of the following functions: signal selection, test mode switching, and support for programmable testing; the test pad in the test circuit is electrically connected to the multitasking unit.
5. The semiconductor device with a test element group as described in claim 2, characterized in that, The number of test pads in one of the test element groups is 2 to 8.
6. The semiconductor device with a test element group as described in claim 5, characterized in that, The phase recognition selects one of the chips and connects it to the tester and test pad in the test circuit for testing.
7. The semiconductor device having a test element group as described in claim 1, characterized in that, The test circuit selects a corresponding chip from the N chips by using phase offset or frequency modulation as an identifier based on the received phase signal.
8. The semiconductor device having a test element group as described in claim 1, characterized in that, The test element group consists of two adjacent chips, the left and right chips, which share the test element group.
9. The semiconductor device having a test element group as claimed in claim 1, characterized in that, The four adjacent chips of the test element group share the test element group, and the four chips are the upper left chip, the upper right chip, the lower right chip, and the lower left chip; the phase angles corresponding to the four chips include 0°, 90°, 180°, and 270°; the encoding quadrants corresponding to the four chips include the first to the fourth quadrants.
10. A testing method for a semiconductor device having a test element group, using the semiconductor device according to any one of claims 1 to 9, characterized in that, include: The testing equipment sends a test signal, which contains phase information used to identify the chip; The test circuit in the test element group receives the test signal; The phase decoder decodes the test signal and selects one chip from the N chips that corresponds to the decoding; The test circuit tests the selected chip; The test results are sent back to the test equipment, and the source chip is marked; The testing machine performs the above steps on the selected chip, and after the test is completed, it switches to the next chip, and so on, until all the chips to be tested have been tested.