Subtraction circuit based on voltage-current conversion and power management chip

Abstract

The invention belongs to the technical field of electronic circuits, and provides a subtraction circuit based on voltage-current conversion and a power management chip, the subtraction circuit comprises a reference current source sub-circuit, a differencing sub-circuit and an output sub-circuit; the reference current source sub-circuit is connected with the differencing sub-circuit, and the differencing sub-circuit is connected with the output sub-circuit; the reference current source sub-circuit is used for providing reference current for the differencing sub-circuit, and the reference current is preset based on the current voltage difference range; the differencing sub-circuit is used for obtaining a current difference signal after voltage differencing, voltage-current conversion and current differencing according to the input first voltage, the input second voltage and the reference current; and the output sub-circuit is used for converting the current difference signal and then outputting a voltage output signal to the ground. According to the scheme, the gain adjustment operation is simplified, the differencing error under different voltage differences is effectively reduced, and the differencing precision and the operation convenience and flexibility of the whole circuit are improved.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a subtraction circuit based on voltage-current conversion and a power management chip. Background Technology

[0002] In the field of power management chips, subtraction circuits, as the core module for amplifying and outputting the difference between two input voltages, are widely used in various signal processing scenarios. A typical structure is a single-stage differential amplifier circuit based on operational amplifiers, also known as a differential proportional operational amplifier circuit. This subtraction circuit connects the two input voltages to the inverting and non-inverting inputs of an operational amplifier via resistors, respectively. It utilizes feedback resistors to keep the operational amplifier operating in the linear region. Combining virtual short and virtual open characteristics with the superposition principle, it achieves voltage subtraction. When the input resistors are symmetrical, it can output a signal proportional to the difference between the two input voltages.

[0003] However, existing single-stage differential amplifier circuits have significant limitations in practical applications. First, because the inverting input resistor is fixed at a specific value, the low input resistance results in a non-zero input current, severely limiting the driving capability of the front-end signal source and making it susceptible to the influence of the signal source impedance. Second, gain adjustment is complex, requiring simultaneous adjustment of multiple resistors to maintain a specific proportional relationship, making resistor selection and parameter tuning difficult. Third, the requirement for resistor consistency is extremely high; if there is a deviation between the feedback resistor and the matching resistor, it will lead to a significant increase in output error, making it difficult to meet the requirements of voltage subtraction operations with large voltage differences and high precision.

[0004] It is evident that traditional single-stage differential amplifier circuits suffer from technical problems such as inconvenient and inflexible parameter adjustment and low accuracy. Summary of the Invention

[0005] This invention provides a subtraction circuit and power management chip based on voltage-current conversion to solve the shortcomings of traditional single-stage differential amplifier circuits, such as inconvenient and inflexible parameter adjustment and low accuracy.

[0006] On one hand, the present invention provides a subtraction circuit based on voltage-current conversion, including: a reference current source sub-circuit, a difference sub-circuit, and an output sub-circuit;

[0007] The reference current source sub-circuit is connected to the difference sub-circuit, and the difference sub-circuit is connected to the output sub-circuit;

[0008] The reference current source sub-circuit is used to provide a reference current to the difference sub-circuit, and the reference current is preset based on the current differential pressure range;

[0009] The sub-circuit for calculating the difference is used to obtain a current difference signal by performing voltage difference calculation, voltage-current conversion, and current difference calculation based on the input first voltage and second voltage and the reference current, respectively.

[0010] The output sub-circuit is used to convert the current difference signal and output a voltage signal to ground.

[0011] According to the subtraction circuit based on voltage-current conversion provided by the present invention, the reference current source sub-circuit includes: a first reference current source, a second reference current source, a first MOSFET, a second MOSFET, a third MOSFET, a first transistor, and a first resistor;

[0012] The positive terminals of both the first and second reference current sources are connected to a DC power supply. The negative terminal of the first reference current source is connected to the drain of the second MOSFET. The source of the second MOSFET is connected to the drain of the first MOSFET and the base of the first transistor. The gate and drain of the first MOSFET are shorted together, and the source of the first MOSFET is grounded. The negative terminal of the second reference current source is connected to the drain of the third MOSFET. The gate and drain of the third MOSFET are shorted together, and the source of the third MOSFET is connected to the gate of the second MOSFET and the collector of the first transistor. The emitter of the first transistor is grounded through a first resistor.

[0013] According to the subtraction circuit based on voltage-current conversion provided by the present invention, the sub-circuit for calculating the difference includes: a voltage input module, a voltage difference module, a voltage-current conversion module, and a current difference module;

[0014] The voltage input module is connected to the voltage difference module, the voltage-to-current conversion module is connected to both the voltage difference module and the current difference module, and the current difference module is connected to the output sub-circuit.

[0015] The voltage input module is used to receive the first voltage and the second voltage input;

[0016] The voltage difference module is used to perform voltage difference calculation based on the input first voltage and second voltage and the reference current to obtain a voltage difference signal;

[0017] The voltage-to-current conversion module is used to perform voltage-to-current conversion based on the voltage difference signal to obtain the current signal corresponding to the voltage difference signal;

[0018] The current difference module is used to calculate the difference between the first current and the second current to obtain a current difference signal.

[0019] According to the voltage-current conversion-based subtraction circuit provided by the present invention, the voltage difference calculation module includes: a reference current stabilization submodule and a voltage difference generation submodule;

[0020] The reference current stabilization submodule includes: a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET;

[0021] The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor. The gates and drains of the fourth and fifth MOS transistors are shorted. The gate of the fourth MOS transistor is connected to the voltage difference generation submodule. The drain of the fifth MOS transistor is connected to the drain of the sixth MOS transistor. The source of the sixth MOS transistor is grounded. The gate of the sixth MOS transistor is connected to the reference current source subcircuit.

[0022] According to the voltage-current conversion-based subtraction circuit provided by the present invention, the voltage difference generation submodule includes: a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, a first capacitor, a second capacitor, a second transistor, a third transistor, a second resistor, and a third resistor;

[0023] The seventh and eighth MOS transistors are both connected to the gate of the fourth MOS transistor. The drain of the eighth MOS transistor is connected to the negative terminal of the second capacitor and the drain of the ninth MOS transistor, respectively. The drain of the seventh MOS transistor is connected to the negative terminal of the first capacitor and the drain of the tenth MOS transistor, respectively. The gates of the ninth and tenth MOS transistors are both connected to the reference current source circuit. The source of the ninth MOS transistor is connected to the collector of the second transistor. The emitter of the second transistor is grounded through the second resistor. The source of the tenth MOS transistor is connected to the collector of the third transistor. The emitter of the third transistor is grounded through the third resistor. The bases of the second and third transistors are both connected to the reference current source circuit.

[0024] According to the subtraction circuit based on voltage-current conversion provided by the present invention, the voltage-current conversion module includes: an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, and a fourth resistor;

[0025] The sources of the eleventh and twelfth MOS transistors are both connected to a DC power supply, and the gates of the eleventh and twelfth MOS transistors are both connected to the voltage difference module. The drain of the eleventh MOS transistor is connected to the source of the thirteenth MOS transistor, and the drain of the twelfth MOS transistor is connected to the source of the fourteenth MOS transistor. The drain of the thirteenth MOS transistor is connected to the fourth resistor and the voltage input module, respectively, and the fourth resistor is connected to the voltage input module.

[0026] According to the subtraction circuit based on voltage-current conversion provided by the present invention, the current difference module includes: a first current mirror module and a second current mirror module;

[0027] The first current mirror module is used to acquire the first current;

[0028] The second current mirror module is used to acquire the second current, calculate the difference between the second current and the first current, and output a current difference signal.

[0029] According to the voltage-to-current conversion-based subtraction circuit provided by the present invention, the first current mirror module includes: a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, and a first operational amplifier;

[0030] The drain of the fifteenth MOS transistor is connected to the second current mirror module, the source of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor, the source of the sixteenth MOS transistor is grounded, the source of the fifteenth MOS transistor is connected to the inverting input terminal of the first operational amplifier, the output terminal of the first operational amplifier is connected to the gate of the fifteenth MOS transistor, the non-inverting input terminal of the first operational amplifier is connected to the voltage-to-current conversion module, the gate of the seventeenth MOS transistor is connected to the gate of the sixteenth MOS transistor, the gate and drain of the seventeenth MOS transistor are shorted, and the source of the seventeenth MOS transistor is grounded.

[0031] According to the voltage-to-current conversion-based subtraction circuit provided by the present invention, the second current mirror module includes: an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a second first MOS transistor, and a second operational amplifier;

[0032] The sources of the eighteenth and nineteenth MOS transistors are both connected to the DC power supply VCC. The drain of the eighteenth MOS transistor is connected to the non-inverting input of the second operational amplifier and the source of the twentieth MOS transistor, respectively. The drain of the nineteenth MOS transistor is connected to the source of the second MOS transistor and the inverting input of the second operational amplifier, respectively. The gates of the eighteenth and nineteenth MOS transistors are both connected to the voltage difference module. The gate of the twentieth MOS transistor is connected to the output of the second operational amplifier.

[0033] On the other hand, the present invention also provides a power management chip, including the subtraction circuit based on voltage-current conversion described above.

[0034] The present invention provides a subtraction circuit and power management chip based on voltage-to-current conversion. This circuit comprises a reference current source subcircuit, a difference subcircuit, and an output subcircuit. The reference current source subcircuit provides a reference current to the difference subcircuit. The difference subcircuit, based on the input first and second voltages and the reference current, performs voltage difference calculation, voltage-to-current conversion, and current difference calculation to obtain a current difference signal. The output subcircuit converts the current difference signal and outputs a voltage signal. This scheme uses voltage-to-current conversion, abandoning the method of gain adjustment relying on the proportional relationship of multiple resistors. It converts voltage difference comparison into current difference comparison, simplifying gain adjustment operations and reducing the impact of signal source impedance on common-mode rejection. Furthermore, the reference current in the reference current source subcircuit can be matched and set for different voltage difference scenarios without strictly relying on resistor consistency, effectively reducing the difference error under different voltage differences and improving the overall circuit's difference accuracy, ease of operation, and flexibility. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of an existing single-stage differential amplifier circuit;

[0037] Figure 2 This is one of the structural schematic diagrams of a subtraction circuit based on voltage-current conversion provided in an embodiment of the present invention;

[0038] Figure 3 This is the second schematic diagram of the subtraction circuit based on voltage-current conversion provided in the embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the DC simulation results corresponding to the subtraction circuit based on voltage-current conversion;

[0040] Figure 5 It is voltage V OUT The corresponding output error curve diagram;

[0041] Figure 6 This is a transient simulation diagram of a subtraction circuit based on voltage-current conversion;

[0042] Figure 7 It is different from I ref2 The diagram below shows the circuit error results corresponding to different voltage differences. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0044] This embodiment relates to the field of electronic circuits, specifically applicable to the design of subtraction circuits. In power management chips, the subtraction circuit is a differential amplifier circuit based on operational amplifier design, capable of amplifying and outputting the difference between two input voltages. A typical existing structure is a single-stage differential amplifier circuit, such as... Figure 1 As shown, the two input voltages V IN1 and V IN2 Through resistor R respectively a and resistance R b Connect to both the inverting and non-inverting inputs of operational amplifier A; the non-inverting input of operational amplifier A has a resistor R to ground. c Feedback resistor R f This allows operational amplifier A to operate in the linear region, exhibiting both virtual short and virtual open characteristics.

[0045] Figure 1 The circuit shown is based on the addition and subtraction circuit and operates according to the superposition principle. The input-output relationship of this circuit is as follows:

[0046]

[0047] When the input resistance is symmetrical, such as R a =R b And R f =R c Then the circuit can perform subtraction ratio calculations. If R a =R f Then V satisfies OUT =V IN2 -V IN1 .

[0048] In practical applications, Figure 1 The circuit shown has the following problems:

[0049] First, the input resistance R a The input resistance is relatively small because the input current is not zero for each signal source.

[0050] Second, adjusting the gain requires changing two resistors simultaneously, which is quite difficult. The resistors need to satisfy a specific equality relationship, and the selection and adjustment of the resistors are inconvenient.

[0051] Third, the consistency requirements for resistors are very high, and R must meet the requirements. a =R b And R f =R c If the resistance deviation exceeds 5%, it will lead to a significant increase in output error.

[0052] Based on the above-mentioned technical problems, this embodiment provides a subtraction circuit that can achieve level shifting and voltage-current conversion, meeting the requirements of large pressure difference scenarios. The following describes the circuit in conjunction with... Figures 2 to 7 This invention describes the detailed solution of the subtraction circuit and power management chip based on voltage-to-current conversion provided in the embodiments of the present invention.

[0053] like Figure 2 As shown, the subtraction circuit based on voltage-current conversion provided in this embodiment of the invention specifically includes: a reference current source sub-circuit 110, a difference sub-circuit 120, and an output sub-circuit 130.

[0054] The reference current source circuit 110 is connected to the difference calculation circuit 120, and the difference calculation circuit 120 is connected to the output circuit 130.

[0055] The reference current source circuit 110 is used to provide a reference current with zero temperature drift to the difference circuit 120. The reference current is preset based on the current differential pressure range.

[0056] The sub-circuit 120 is used to obtain the current difference signal by performing voltage difference calculation, voltage-current conversion and current difference calculation respectively based on the input first voltage and second voltage and reference current.

[0057] The output sub-circuit 130 is used to convert the current difference signal and output a voltage signal to ground.

[0058] In one embodiment, such as Figure 3 As shown, the reference current source sub-circuit 110 specifically includes: a first reference current source I REF1 Second reference current source I REF2 The first MOSFET MN4, the second MOSFET MN6, the third MOSFET MN7, the first transistor Q1, and the first resistor R3.

[0059] Among them, the first reference current source I REF1 Second reference current source I REF2 The positive terminals of both are connected to the DC power supply VCC, and the first reference current source I... REF1 The negative terminal of the first transistor MN6 is connected to the drain of the second MOSFET MN6. The source of the second MOSFET MN6 is connected to the drain of the first MOSFET MN4 and the base of the first transistor Q1. The gate and drain of the first MOSFET MN4 are shorted, and the source of the first MOSFET MN4 is grounded. The second reference current source I... REF2The negative terminal of the transistor is connected to the drain of the third MOSFET MN7. The gate and drain of the third MOSFET MN7 are shorted. The source of the third MOSFET MN7 is connected to the gate of the second MOSFET MN6 and the collector of the first transistor Q1. The emitter of the first transistor Q1 is grounded through the first resistor R3.

[0060] like Figure 2 As shown, the sub-circuit 120 for calculating voltage difference includes: a voltage input module 1201, a voltage difference module 1202, a voltage-to-current conversion module 1203, and a current difference module 1204.

[0061] The voltage input module 1201 is connected to the voltage difference module 1202, the voltage-current conversion module 1203 is connected to the voltage difference module 1202 and the current difference module 1204 respectively, and the current difference module 1204 is connected to the output sub-circuit 130.

[0062] The voltage input module 1201 is used to receive the first voltage and the second voltage input.

[0063] The voltage difference module 1202 is used to perform voltage difference calculation based on the input first voltage, second voltage, and reference current to obtain a voltage difference signal.

[0064] The voltage-to-current conversion module 1203 is used to perform voltage-to-current conversion based on the voltage difference signal to obtain the current signal corresponding to the voltage difference signal.

[0065] The current difference module 1204 is used to perform current difference calculation on the first current and the second current to obtain the current difference signal.

[0066] In this embodiment, as Figure 3 As shown, the voltage input module 1201 specifically includes: a first input terminal MOSFET MP1 and a second input terminal MOSFET MP2, wherein the first input terminal MOSFET MP1 is used to input a first voltage V. IN1 The second input terminal MOSFET MP2 is used to input the second voltage V. IN2 .

[0067] In a specific implementation, such as Figure 3 As shown, the voltage difference calculation module includes: a reference current stabilization submodule 210 and a voltage difference generation submodule 220.

[0068] The reference current stabilization submodule 210 specifically includes: the fourth MOSFET MP7, the fifth MOSFET MP14, and the sixth MOSFET MN5.

[0069] In this circuit, the drain of the fourth MOSFET MP7 is connected to the source of the fifth MOSFET MP14, the gate and drain of the fourth MOSFET MP7 are shorted, the gate and drain of the fifth MOSFET MP14 are shorted, the gate of the fourth MOSFET MP7 is connected to the voltage difference generation submodule 220, the drain of the fifth MOSFET MP14 is connected to the drain of the sixth MOSFET MN5, the source of the sixth MOSFET MN5 is grounded, and the gate of the sixth MOSFET MN5 is connected to the gate of the first MOSFET MN4 in the reference current source circuit.

[0070] like Figure 3 As shown, the voltage difference generation submodule 220 specifically includes: a seventh MOSFET MP8, an eighth MOSFET MP9, a ninth MOSFET MN8, a tenth MOSFET MN9, a first capacitor C1, a second capacitor C2, a second transistor Q2, a third transistor Q3, a second resistor R4, and a third resistor R5.

[0071] In this configuration, the positive terminals of the first capacitor C1 and the second capacitor C2, the source of the seventh MOSFET MP8, the source of the eighth MOSFET MP9, and the source of the fourth MOSFET MP7 are all connected to the DC power supply VCC. The seventh MOSFET MP8 and the eighth MOSFET MP9 are both connected to the gate of the fourth MOSFET MP7. The drain of the eighth MOSFET MP9 is connected to the negative terminal of the second capacitor C2 and the drain of the ninth MOSFET MN8, respectively. The drain of the seventh MOSFET MP8 is connected to the negative terminal of the first capacitor C1 and the drain of the tenth MOSFET MN9, respectively. The gates of the ninth MOSFET MN8 and the tenth MOSFET MN9 are connected to the gate of the fourth MOSFET MN7 in the reference current source circuit 110. The source of the ninth MOSFET MN8 is connected to the collector of the second transistor Q2. The emitter of the second transistor Q2 is grounded through the second resistor R4. The source of the tenth MOSFET MN9 is connected to the collector of the third transistor Q3. The emitter of the third transistor Q3 is grounded through the third resistor R5. The bases of the second transistor Q2 and the third transistor Q3 are connected to the base of the first transistor Q1 in the reference current source circuit.

[0072] In a specific implementation, such as Figure 3 As shown, the voltage-to-current conversion module 1203 specifically includes: eleventh MOSFET MP5, twelfth MOSFET MP6, thirteenth MOSFET MP12, fourteenth MOSFET MP13, and fourth resistor R1.

[0073] Among them, the sources of the eleventh MOSFET MP5 and the twelfth MOSFET MP6 are both connected to the DC power supply VCC. The gates of the eleventh MOSFET MP5 and the twelfth MOSFET MP6 are both connected to the drain of the ninth MOSFET MN8 in the voltage difference module. The drain of the eleventh MOSFET MP5 is connected to the source of the thirteenth MOSFET MP12. The drain of the twelfth MOSFET MP6 is connected to the source of the fourteenth MOSFET MP13. The drain of the thirteenth MOSFET MP12 is connected to the fourth resistor R1 and the source of the second input terminal MOSFET MP2.

[0074] In a specific implementation, such as Figure 3 As shown, the current difference module specifically includes: a first current mirror module 230 and a second current mirror module 240.

[0075] The first current mirror module 230 is used to acquire the first current.

[0076] The second current mirror module 240 is used to acquire the second current, calculate the difference between the second current and the first current, and output the current difference signal.

[0077] In this embodiment, as Figure 3 As shown, the first current mirror module 230 specifically includes: the fifteenth MOS transistor MN1, the sixteenth MOS transistor MN2, the seventeenth MOS transistor MN3, and the first operational amplifier A1.

[0078] Specifically, the drain of the fifteenth MOSFET MN1 is connected to the drain of the twentieth MOSFET MP10 in the second current mirror module 240; the source of the fifteenth MOSFET MN1 is connected to the drain of the sixteenth MOSFET MN2; the source of the sixteenth MOSFET MN2 is grounded; the source of the fifteenth MOSFET MN1 is connected to the inverting input of the first operational amplifier A1; the output of the first operational amplifier A1 is connected to the gate of the fifteenth MOSFET MN1; the non-inverting input of the first operational amplifier A1 is connected to the drain of the fourteenth MOSFET MP13 in the voltage-to-current conversion module 1203; the gate of the seventeenth MOSFET MN3 is connected to the gate of the sixteenth MOSFET MN2; the gate and drain of the seventeenth MOSFET MN3 are shorted; and the source of the seventeenth MOSFET MN3 is grounded.

[0079] In this embodiment, as Figure 3 As shown, the second current mirror module 240 specifically includes: the eighteenth MOSFET MP3, the nineteenth MOSFET MP4, the twentieth MOSFET MP10, the second first MOSFET MP11, and the second operational amplifier A2.

[0080] In this configuration, the sources of the eighteenth MOSFET MP3 and the nineteenth MOSFET MP4 are both connected to the DC power supply VCC. The drain of the eighteenth MOSFET MP3 is connected to the non-inverting input of the second operational amplifier A2 and the source of the twentieth MOSFET MP10, respectively. The drain of the nineteenth MOSFET MP4 is connected to the source of the second MOSFET MP11 and the inverting input of the second operational amplifier A2, respectively. The gates of the eighteenth MOSFET MP3 and the nineteenth MOSFET MP4 are both connected to the drain of the tenth MOSFET MN9 in the voltage difference module. The gate of the twentieth MOSFET MP10 is connected to the output of the second operational amplifier A2.

[0081] like Figure 3 As shown, in the output sub-circuit 130, the fifth resistor R2 is connected to the drain of the twentieth MOS transistor MP10 in the second current mirror module 240, and the fifth resistor R2 is grounded.

[0082] Combination Figure 3 The non-inverting and inverting input terminals of the first operational amplifier A1 are the drain voltages of the sixteenth MOSFET MN2 and the seventeenth MOSFET MN3, respectively. This ensures that the drain-source voltages VDS of the two MOSFETs are equal in the current mirror formed by the combination of the sixteenth MOSFET MN2 and the seventeenth MOSFET MN3, thus making the currents flowing through the sixteenth MOSFET MN2 and the seventeenth MOSFET MN3 equal, i.e., I... A =I B .

[0083] The second operational amplifier A2 uses the same principle to make the drain-source voltages of the eighteenth MOSFET MP3 and the nineteenth MOSFET MP4 equal, and the gate voltages of the eighteenth MOSFET MP3 and the nineteenth MOSFET MP4 also equal, so that the current flowing through the eighteenth MOSFET MP3 and the nineteenth MOSFET MP4 is also equal, i.e., I C =I D The gate voltages of the eleventh MOSFET MP5 and the twelfth MOSFET MP6 are provided by the drain voltage of the seventh MOSFET MP8. The current mirror structure formed by the eleventh MOSFET MP5 and the twelfth MOSFET MP6 makes I... B =I E .

[0084] The fourth MOSFET MP7, the seventh MOSFET MP8, and the eighth MOSFET MP9 form a current mirror structure, allowing the seventh MOSFET MP8 and the eighth MOSFET MP9 to carry the same current I. ref1 The second transistor Q2 and the third transistor Q3 are operating in saturation. The first transistor Q1 ensures that the second transistor Q2 and the third transistor Q3 have the same base voltage V. B , Figure 3 China V X Voltage is VB With V BE2 The difference, V BE2 V represents the base and emitter voltage of the second transistor Q2. Y Voltage is V B With V BE3 The difference, V BE3 The voltage between the base and emitter of the third transistor Q3 is given by V. B =I REF2 *R2+V BE1 The voltage magnitudes at nodes X and Y can be obtained as follows:

[0085] V X =I REF2 *R2+V BE1 -V BE2 (2);

[0086] V Y =I REF2 *R2+V BE1 -V BE3 (3);

[0087] In this embodiment, the second transistor Q2 and the third transistor Q3 are BJT transistors of the same process and size, so V BE2 With V BE3 Equal, so that the node voltage V X With V Y They are also equal.

[0088] like Figure 3 As shown, the first input voltage V IN1 Second voltage V IN2 The current flowing through the gates of MOSFET MP1 (first input terminal) and MOSFET MP2 (second input terminal) is respectively:

[0089]

[0090] The current flowing through the second input terminal MOSFET MP2 is:

[0091]

[0092] At the same time, due to satisfying V X =V Y Adjust resistors R4 and R5 so that R4 = R5, then I1 = I2. The first input MOSFET MP1 and the second input MOSFET MP2 of the folded operational amplifier carry the same current. Ignoring the channel length modulation effect, the MOSFET current formula is as follows:

[0093]

[0094] Therefore, it can be concluded that the current of the first input terminal MOSFET MP1 and the second input terminal MOSFET MP2, which are of the same process and size, is only determined by V. GS The gate-source voltage of the MOSFET is determined by the MOSS EFT gate-source voltage, therefore the Vo of the first input MOSFET MP1 and the second input MOSFET MP2 is determined by the MOSFET EFT gate-source voltage. GS Similarly, the gate voltage of the first input MOSFET MP1 is V. IN1 The source voltage is V N The gate voltage of the second input MOSFET MP2 is V. IN2 The source voltage is V P By converting the voltage difference signal into voltages at nodes N and P, we can obtain:

[0095] V GS1 =V IN1 -V N (7);

[0096] V GS2 =V IN2 -V P (8);

[0097] V GS1 =V GS2 (9);

[0098] Furthermore, we can obtain:

[0099] V IN1 -V IN2 =V N -V P (10);

[0100] A fourth resistor R1 is connected between the N and P nodes of the output of the folded operational amplifier. The fourth resistor R1 can separate the current sources above the first input MOSFET MP1 and the second input MOSFET MP2. Figure 3 The current flowing through the fourth resistor R1 can be expressed as:

[0101]

[0102] byI A =I B I C =I D I B =I E It can make the current I diff Further expressed as:

[0103]

[0104] The current through the fifth resistor R2 can be expressed as:

[0105]

[0106] Combining the above equations, we can obtain:

[0107]

[0108] Furthermore, we can obtain:

[0109]

[0110] By adjusting the values ​​of resistors R1 and R2, we can make R1 = 2R2, and thus obtain V. OUT =V IN1 -V IN2 .

[0111] Through the above voltage-to-current conversion, the first voltage V can be converted into a voltage V. IN1 Second voltage V IN2 The difference calculation is converted into a current calculation, and finally the result of the difference is expressed as the voltage output value V above the fifth resistor R2. OUT Place.

[0112] It should be noted that, Figure 3 Second reference current source I REF2 Based on the first resistor R3, the current can be obtained by adjusting the base voltages of the first transistor Q1, the second transistor Q2, and the third transistor Q3, and the gate voltages of the fourth MOSFET MN7, the ninth MOSFET MN8, and the tenth MOSFET MN9; according to the above current calculation formula, the current can be obtained by adjusting the second reference current source I. REF2 The reference current can be used to adjust the currents I1 and I2 flowing through the voltage difference module, thereby achieving low-error difference calculation under different voltage differences.

[0113] at the same time, Figure 3 The drain of the ninth MOSFET MN8 is connected to the gates of the eighteenth MOSFET MP3 and the nineteenth MOSFET MP4 to form a feedback loop; the drain of the tenth MOSFET MN9 is connected to the gates of the eleventh MOSFET MP5 and the twelfth MOSFET MP6 to form a feedback loop; the first capacitor C1 and the second capacitor C2 can effectively suppress high-frequency noise and self-oscillation, ensuring the operational stability of the entire subtraction circuit.

[0114] To verify the beneficial effects of the subtraction circuit based on voltage-current conversion provided in this embodiment, Figure 4 An example is shown showing the DC simulation results corresponding to the subtraction circuit based on voltage-current conversion. Specifically, when the simulation range is set, the first voltage V... IN1 The voltage changes linearly from 3V to 35V.IN2 =1V, the reference current I of the first reference current source ref1 =4uA, the reference current I of the second reference current source ref2 =4uA.

[0115] See Figure 4 The straight line L1 represents V IN1 The voltage, the straight line L2 represents V IN2 The voltage, the straight line L3 represents V IN1 With V IN2 The voltage difference, i.e., voltage V OUT .

[0116] Figure 5 The voltage V is shown OUT The corresponding output error curve, from Figure 4 The DC simulation results shown are Figure 5 As can be seen from the error curves shown, the actual error of the subtraction circuit gradually increases with the increase of the input voltage. The error statistics are shown in Table 1.

[0117] Table 1 Error Statistics

[0118]

[0119]

[0120] As can be seen from Table 1, for scenarios with large pressure differentials, the subtraction circuit based on pressure-current conversion provided in this embodiment has a smaller error.

[0121] Figure 6 The transient simulation diagram of the subtraction circuit based on voltage-current conversion provided in this embodiment is shown, where the horizontal axis represents time, the vertical axis represents voltage, and curve L4 is the first input voltage V. IN1 A step signal from 5V to 10V. Line L5 represents the second input voltage V. IN2 =2V signal, curve L6 represents voltage V OUT The transient response signal, where I ref1 =4uA,I ref2 =4uA, with a response time of ΔT = 10.8388us - 10us = 0.8388us, exhibiting a fast transient response. Therefore, the subtraction circuit based on voltage-current conversion provided in this embodiment can meet the application requirements of high-frequency scenarios.

[0122] Figure 7 Different I were shown ref2 The circuit error conditions corresponding to different voltage differences are as follows. Figure 7 The vertical axis represents voltage error, and the horizontal axis represents voltage (V). IN2 =2V IN1The simulation results show the voltage error from 5V to 65V, i.e., the voltage difference from 3V to 63V. Figure 7 The simulation results show that, under different pressure differentials, I can be adjusted. ref2 The magnitude of the current is determined to achieve voltage difference with low error.

[0123] In summary, the subtraction circuit based on voltage-to-current conversion provided in this embodiment of the invention employs a differential operational amplifier structure, resulting in infinitely large input resistance. This provides high impedance matching at both ends, minimizing the impact of the input source impedance on the circuit's common-mode rejection. Furthermore, the voltage-to-current conversion transforms the voltage difference comparison into a current difference comparison, better meeting the requirements for rapid response. By shifting the input voltage difference onto the ground resistance, detection is easier, and the difference error can be reduced by adjusting the reference current of the second reference current source under different voltage differentials, thus improving the accuracy, stability, and feasibility of the subtraction circuit.

[0124] Based on the same general inventive concept, the present invention also protects a power management chip that includes the voltage-to-current conversion subtraction circuit provided in the above embodiments.

[0125] In power supply systems, power management chips need to monitor the difference between input and output voltages in real time to achieve functions such as overvoltage protection and voltage regulation. The voltage-to-current conversion-based subtraction circuit provided in this embodiment can quickly calculate the voltage difference under different operating conditions. By adjusting the reference current of the second reference current source to adapt to different voltage difference scenarios, it ensures that the voltage difference detection error is extremely small. Simultaneously, its fast transient response can promptly feedback voltage fluctuations, ensuring that the power management chip can quickly regulate voltage changes and preventing power system failures due to lag in voltage difference detection.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A subtraction circuit based on voltage-current conversion, characterized in that, include: Reference current source circuit, difference calculation circuit, and output circuit; The reference current source sub-circuit is connected to the difference sub-circuit, and the difference sub-circuit is connected to the output sub-circuit; The reference current source sub-circuit is used to provide a reference current to the difference sub-circuit, and the reference current is preset based on the current differential pressure range; The sub-circuit for calculating the difference is used to obtain a current difference signal by performing voltage difference calculation, voltage-current conversion, and current difference calculation based on the input first voltage and second voltage and the reference current, respectively. The output sub-circuit is used to convert the current difference signal and output a voltage signal to ground.

2. The subtraction circuit based on voltage-current conversion according to claim 1, characterized in that, The reference current source sub-circuit includes: a first reference current source, a second reference current source, a first MOSFET, a second MOSFET, a third MOSFET, a first transistor, and a first resistor; The positive terminals of both the first and second reference current sources are connected to a DC power supply. The negative terminal of the first reference current source is connected to the drain of the second MOSFET. The source of the second MOSFET is connected to the drain of the first MOSFET and the base of the first transistor. The gate and drain of the first MOSFET are short-circuited, and the source of the first MOSFET is grounded. The negative terminal of the second reference current source is connected to the drain of the third MOSFET. The gate and drain of the third MOSFET are short-circuited, and the source of the third MOSFET is connected to the gate of the second MOSFET and the collector of the first transistor. The emitter of the first transistor is grounded through the first resistor.

3. The subtraction circuit based on voltage-current conversion according to claim 1, characterized in that, The sub-circuit for calculating the difference includes: a voltage input module, a voltage difference module, a voltage-to-current conversion module, and a current difference module; The voltage input module is connected to the voltage difference module, the voltage-to-current conversion module is connected to both the voltage difference module and the current difference module, and the current difference module is connected to the output sub-circuit. The voltage input module is used to receive the first voltage and the second voltage input; The voltage difference module is used to perform voltage difference calculation based on the input first voltage and second voltage and the reference current to obtain a voltage difference signal; The voltage-to-current conversion module is used to perform voltage-to-current conversion based on the voltage difference signal to obtain the current signal corresponding to the voltage difference signal; The current difference module is used to calculate the difference between the first current and the second current to obtain a current difference signal.

4. The subtraction circuit based on voltage-current conversion according to claim 3, characterized in that, The voltage difference calculation module includes: a reference current stabilization submodule and a voltage difference generation submodule; The reference current stabilization submodule includes: a fourth MOSFET, a fifth MOSFET, and a sixth MOSFET; The drain of the fourth MOS transistor is connected to the source of the fifth MOS transistor. The gates and drains of the fourth and fifth MOS transistors are shorted. The gate of the fourth MOS transistor is connected to the voltage difference generation submodule. The drain of the fifth MOS transistor is connected to the drain of the sixth MOS transistor. The source of the sixth MOS transistor is grounded. The gate of the sixth MOS transistor is connected to the reference current source subcircuit.

5. The subtraction circuit based on voltage-current conversion according to claim 4, characterized in that, The voltage difference generation submodule includes: a seventh MOSFET, an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, a first capacitor, a second capacitor, a second transistor, a third transistor, a second resistor, and a third resistor; The seventh and eighth MOS transistors are both connected to the gate of the fourth MOS transistor. The drain of the eighth MOS transistor is connected to the negative terminal of the second capacitor and the drain of the ninth MOS transistor, respectively. The drain of the seventh MOS transistor is connected to the negative terminal of the first capacitor and the drain of the tenth MOS transistor, respectively. The gates of the ninth and tenth MOS transistors are both connected to the reference current source circuit. The source of the ninth MOS transistor is connected to the collector of the second transistor. The emitter of the second transistor is grounded through the second resistor. The source of the tenth MOS transistor is connected to the collector of the third transistor. The emitter of the third transistor is grounded through the third resistor. The bases of the second and third transistors are both connected to the reference current source circuit.

6. The subtraction circuit based on voltage-current conversion according to claim 3, characterized in that, The voltage-to-current conversion module includes: an eleventh MOSFET, a twelfth MOSFET, a thirteenth MOSFET, a fourteenth MOSFET, and a fourth resistor; The sources of the eleventh and twelfth MOS transistors are both connected to a DC power supply, and the gates of the eleventh and twelfth MOS transistors are both connected to the voltage difference module. The drain of the eleventh MOS transistor is connected to the source of the thirteenth MOS transistor, and the drain of the twelfth MOS transistor is connected to the source of the fourteenth MOS transistor. The drain of the thirteenth MOS transistor is connected to the fourth resistor and the voltage input module, respectively, and the fourth resistor is connected to the voltage input module.

7. The subtraction circuit based on voltage-current conversion according to claim 3, characterized in that, The current difference module includes: a first current mirror module and a second current mirror module; The first current mirror module is used to acquire the first current; The second current mirror module is used to acquire the second current, calculate the difference between the second current and the first current, and output a current difference signal.

8. The subtraction circuit based on voltage-current conversion according to claim 6, characterized in that, The first current mirror module includes: a fifteenth MOSFET, a sixteenth MOSFET, a seventeenth MOSFET, and a first operational amplifier; The drain of the fifteenth MOS transistor is connected to the second current mirror module, the source of the fifteenth MOS transistor is connected to the drain of the sixteenth MOS transistor, the source of the sixteenth MOS transistor is grounded, the source of the fifteenth MOS transistor is connected to the inverting input terminal of the first operational amplifier, the output terminal of the first operational amplifier is connected to the gate of the fifteenth MOS transistor, the non-inverting input terminal of the first operational amplifier is connected to the voltage-to-current conversion module, the gate of the seventeenth MOS transistor is connected to the gate of the sixteenth MOS transistor, the gate and drain of the seventeenth MOS transistor are shorted, and the source of the seventeenth MOS transistor is grounded.

9. The subtraction circuit based on voltage-current conversion according to claim 6, characterized in that, The second current mirror module includes: an eighteenth MOSFET, a nineteenth MOSFET, a twentieth MOSFET, a twenty-first MOSFET, and a second operational amplifier; The sources of the eighteenth and nineteenth MOS transistors are both connected to a DC power supply. The drain of the eighteenth MOS transistor is connected to the non-inverting input of the second operational amplifier and the source of the twentieth MOS transistor, respectively. The drain of the nineteenth MOS transistor is connected to the source of the second MOS transistor and the inverting input of the second operational amplifier, respectively. The gates of the eighteenth and nineteenth MOS transistors are both connected to the voltage difference module. The gate of the twentieth MOS transistor is connected to the output of the second operational amplifier.

10. A power management chip, characterized in that, Includes the subtraction circuit based on pressure-current conversion as described in any one of claims 1 to 9.

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