LDO circuit with adaptive PSR lifting and fast transient response

Abstract

The invention provides an LDO (Low Dropout Regulator) circuit with self-adaptive PSR (Power Supply Ratio) boosting and rapid transient response. The LDO circuit comprises a power supply input port, a power supply output port, an error amplifier circuit, a transient enhancement circuit, a PSR boosting circuit, a push-pull buffer circuit, a power tube and a feedback circuit, the in-phase input end and the inverting input end of the error amplifier circuit are respectively connected with the reference voltage and the feedback circuit, and the output end of the error amplifier circuit is connected with the input end of the push-pull buffer circuit; the output end of the push-pull buffer circuit is connected with the grid electrode of the power tube and the PSR boosting circuit. The drain electrode of the power tube MP is connected with the power supply output port, the feedback circuit and the transient enhancement circuit. On the premise that a traditional LDO framework and static power consumption are not changed, the transient enhancement circuit and the PSR boosting circuit are added, the circuit has the high PSR performance, the influence of power noise is small, load current abrupt change can be rapidly detected and fed back to the error amplifier, tail current is changed, then the bandwidth speed is changed, and stable voltage is output.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to an LDO circuit with adaptive PSR enhancement and fast transient response. Background Technology

[0002] The LDO (Low Dropout Linear Regulator) circuit is the core unit that manages the power supply and provides clean and stable voltage to noise-sensitive modules such as RF transceivers, high-precision analog converters, and phase-locked loops.

[0003] Modern SoCs typically employ switching power supplies (DC-DC) for efficient pre-regulation, and the resulting switching ripple is coupled to the output of the LDO through the power supply path. High PSRR (Power Supply Rejection Ratio) is a key indicator of an LDO's ability to suppress this power supply noise; insufficient PSRR will directly interfere with the normal operation of subsequent sensitive circuits. On the other hand, the operating states of digital cores in an SoC (such as CPU / GPU) switch drastically within nanoseconds, causing large and rapid changes in load current. This requires the LDO to have excellent transient response capabilities; otherwise, drastic fluctuations in output voltage (overshoot / undershoot) will cause system logic errors or even hardware damage.

[0004] However, in traditional LDO circuit architectures, there is an inherent design contradiction between high PSRR and fast transient response. High PSRR typically requires a wide-bandwidth error amplifier, but this often introduces stability issues and increases static power consumption; while improving transient response requires strong drive capability and fast feedback mechanism, which also sacrifices power consumption and area. How to better coordinate and optimize high PSRR and transient enhancement techniques has become a hot research direction in the current LDO circuit design field.

[0005] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0006] This invention provides an LDO circuit with adaptive PSR enhancement and fast transient response, aiming to solve the technical problems of high PSRR and poor coordination of transient response in existing LDO circuits.

[0007] The technical solution of the present invention is as follows: An LDO circuit with adaptive PSR boost and fast transient response includes a power input port VIN, a power output port VOUT, an error amplifier circuit, a transient enhancement circuit, a PSR boost circuit, a push-pull buffer circuit, a power transistor MP, and a feedback circuit. The non-inverting input of the error amplifier circuit is connected to a reference voltage Vref, the inverting input of the error amplifier circuit is connected to the feedback voltage point Vfb of the feedback circuit, and the output of the error amplifier circuit is connected to the input of the push-pull buffer circuit. The output of the push-pull buffer circuit is connected to the gate of the power transistor MP and the PSR boost circuit, and the drain of the power transistor MP is connected to the power output port VOUT, the feedback circuit, and the transient enhancement circuit.

[0008] In an optional embodiment of the present invention, the error amplifier circuit includes PMOS transistors PM1, PM2, PM3, PM4, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, and NMOS transistors NM5. The source of PMOS transistor PM1 is connected to the power input port VIN; the gate of PMOS transistor PM1 is connected to the drain of PMOS transistor PM1, the gate of PMOS transistor PM2, and the first end of resistor R2; the drain of PMOS transistor PM1 is connected to the current source input port Ibias, the first end of resistor R2, the gate of PMOS transistor PM1, and the gate of PMOS transistor PM2. The source of the PMOS transistor PM2 is connected to the power input port VIN; the gate of the PMOS transistor PM2 is connected to the gate of the PMOS transistor PM1, the drain of the PMOS transistor PM1, the first end of the resistor R2, and the current source input port Ibias; the drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM5. The source of the PMOS transistor PM3 is connected to the power input port VIN; the gate of the PMOS transistor PM3 is connected to the gate of the PMOS transistor PM4, the drain of the PMOS transistor PM3, and the drain of the NMOS transistor NM1; the drain of the PMOS transistor PM3 is connected to the gate of the PMOS transistor PM3, the gate of the PMOS transistor PM4, and the drain of the NMOS transistor NM1. The source of the PMOS transistor PM4 is connected to the power input port VIN; the gate of the PMOS transistor PM4 is connected to the gate of the PMOS transistor PM3, the drain of the PMOS transistor PM3, and the drain of the NMOS transistor NM1; the drain of the PMOS transistor PM4 is connected to the gate of the PMOS transistor PM6 and the drain of the NMOS transistor NM2. The gate of NMOS transistor NM1 is the non-inverting input terminal of the error amplifier. The drain of NMOS transistor NM1 is connected to the gates of PMOS transistors PM3, PM3, and PM4. The gate of NMOS transistor NM1 is connected to the input reference voltage Vref. The source of NMOS transistor NM1 is connected to the source of NMOS transistor NM2, the drain of NMOS transistor NM3, and the drain of NMOS transistor NM4. The drain of NMOS transistor NM1 is connected to the drain of PMOS transistor PM4 and the gate of PMOS transistor PM6. The gate of the NMOS transistor NM2 is the inverting input terminal of the error amplifier, and the gate of the NMOS transistor NM2 is connected to the feedback voltage point Vfb; the source of the NMOS transistor NM2 is connected to the source of the NMOS transistor NM1, the drain of the NMOS transistor NM3, and the drain of the NMOS transistor NM4. The drain of NMOS transistor NM3 is connected to the source of NMOS transistor NM1, the source of NMOS transistor NM2, and the drain of NMOS transistor NM4; the gate of NMOS transistor NM3 is connected to the drain of NMOS transistor NM5, the gate of NMOS transistor NM5, and the first end of resistor R3; the source of NMOS transistor NM3 is connected to the ground port GND. The drain of NMOS transistor NM4 is connected to the source of NMOS transistor NM1, the source of NMOS transistor NM2, and the drain of NMOS transistor NM3; the gate of NMOS transistor NM4 is connected to the second terminal of capacitor C3; and the source of NMOS transistor NM4 is connected to the ground port GND. The drain of NMOS transistor NM5 is connected to the gate of NMOS transistor NM5, the gate of NMOS transistor NM3, the drain of PMOS transistor PM2, and the first terminal of resistor R3; the gate of NMOS transistor NM5 is connected to the gate of NMOS transistor NM3, the drain of NMOS transistor NM5, and the first terminal of resistor R3; the source of NMOS transistor NM5 is connected to the ground port GND.

[0009] In an optional embodiment of the present invention, the transient enhancement circuit includes the resistor R2, the resistor R3, the capacitor C2, and the capacitor C3; The first end of the resistor R2 is connected to the gate and drain of the PMOS transistor PM1; the second end of the resistor R2 is connected to the first end of the capacitor C2 and the gate of the PMOS transistor PM5. The first terminal of capacitor C2 is connected to the second terminal of resistor R2 and the gate of PMOS transistor PM5; the second terminal of capacitor C2 is connected to the drain of power transistor MP, the second terminal of resistor R3, the first terminal of capacitor C3, the first terminal of resistor Rf1, the voltage output port VOUT, and the first terminal of load resistor RL. The first terminal of capacitor C3 is connected to the drain of power transistor MP, the second terminal of resistor R3, the first terminal of resistor Rf1, and the voltage output port VOUT; the second terminal of capacitor C3 is connected to the gate of NMOS transistor NM4.

[0010] In an optional embodiment of the present invention, the PSR boosting circuit includes PMOS transistor PM5, PMOS transistor PM8, NMOS transistor NM6 and capacitor C1; The source of the PMOS transistor PM5 is connected to the power input port VIN; the gate of the PMOS transistor PM5 is connected to the second terminal of the resistor R2 and the first terminal of the capacitor C2; the drain of the PMOS transistor PM5 is connected to the drain of the NMOS transistor NM6, the source of the PMOS transistor PM8, and the gate of the NMOS transistor NM7. The drain of the NMOS transistor NM6 is connected to the drain of the PMOS transistor PM5, the source of the PMOS transistor PM8, and the gate of the NMOS transistor NM7; the gate of the NMOS transistor NM6 is connected to the drain of the PMOS transistor PM8 and the second terminal of the capacitor C1; the source of the NMOS transistor NM6 is connected to the ground port GND. The drain of the PMOS transistor PM8 is connected to the gate of the NMOS transistor NM6 and the second terminal of the capacitor C1; the gate of the PMOS transistor PM8 is connected to the first terminal of the resistor R1 and the drain of the PMOS transistor PM7; the source of the PMOS transistor PM8 is connected to the drain of the NMOS transistor NM6 and the gate of the NMOS transistor NM7.

[0011] In an optional embodiment of the present invention, the push-pull buffer circuit includes PMOS transistor PM6, PMOS transistor PM7, NMOS transistor NM7 and resistor R1; The source of the PMOS transistor PM6 is connected to the power input port VIN; the gate of the PMOS transistor PM6 is connected to the drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM2; the drain of the PMOS transistor PM6 is connected to the gate of the PMOS transistor PM7, the gate of the power transistor MP, and the drain of the NMOS transistor NM7. The source of the PMOS transistor PM7 is connected to the power input port VIN; the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM6, the gate of the power transistor MP, and the drain of the NMOS transistor NM7; the drain of the PMOS transistor PM7 is connected to the first terminal of the resistor R1 and the gate of the PMOS transistor PM8. The drain of the NMOS transistor NM7 is connected to the drain of the PMOS transistor PM6, the gate of the PMOS transistor PM7, and the gate of the power transistor MP; the gate of the NMOS transistor NM7 is connected to the drain of the NMOS transistor NM6 and the source of the PMOS transistor PM8; the source of the NMOS transistor NM7 is connected to the ground port GND. The first end of the resistor R1 is connected to the drain of the PMOS transistor PM7 and the gate of the PMOS transistor PM8; the second end of the resistor R1 is connected to the ground port GND.

[0012] In an optional embodiment of the present invention, the source of the power transistor MP is connected to the power input port VIN; the gate of the power transistor MP is connected to the drain of the PMOS transistor PM6 and the gate of the PMOS transistor PM7; the drain of the power transistor MP is connected to the first terminal of the feedback resistor Rf1, the second terminal of the capacitor C2, the voltage output port VOUT, and the first terminal of the load resistor RL.

[0013] In an optional embodiment of the present invention, the feedback circuit includes a feedback resistor Rf1, the feedback voltage point Vfb, a feedback resistor Rf2, and a load resistor RL. The first terminal of the feedback resistor Rf1 is connected to the drain of the power transistor MP, the first terminal of the capacitor C2, the voltage output port VOUT, and the first terminal of the load resistor RL; the second terminal of the feedback resistor Rf1 is connected to the feedback voltage point Vfb and the first terminal of the feedback resistor Rf2. The first end of the feedback resistor Rf2 is connected to the second end of the feedback resistor Rf1 and the feedback voltage point Vfb; the second end of the feedback resistor Rf2 is connected to the grounding port GND. The first end of the load resistor RL is connected to the drain of the power transistor MP, the voltage output port VOUT, and the first end of the feedback resistor Rf1; the second end of the load resistor RL is connected to the ground port GND.

[0014] The beneficial effects are as follows: This invention provides an LDO circuit with adaptive PSR boost and fast transient response, including a power input port, a power output port, an error amplifier circuit, a transient enhancement circuit, a PSR boost circuit, a push-pull buffer circuit, a power transistor, and a feedback circuit. The non-inverting and inverting input terminals of the error amplifier circuit are connected to the reference voltage and the feedback circuit, respectively. The output terminal of the error amplifier circuit is connected to the input terminal of the push-pull buffer circuit. The output terminal of the push-pull buffer circuit is connected to the gate of the power transistor and the PSR boost circuit. The drain of the power transistor (MP) is connected to the power output port, the feedback circuit, and the transient enhancement circuit. This invention adds a transient enhancement circuit and a PSR boost circuit without changing the traditional LDO architecture and static power consumption. The circuit has high PSR performance, is less affected by power supply noise, and can quickly detect load current surges and feed them back to the error amplifier, changing the tail current and thus the bandwidth speed, resulting in a stable output voltage. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of an LDO circuit with adaptive PSR enhancement and fast transient response according to the present invention.

[0016] Figure 2 This is a simplified diagram of an LDO circuit with adaptive PSR enhancement and fast transient response according to the present invention.

[0017] Figure 3 This is a schematic diagram illustrating the path for improving the transient response and PSR of the LDO circuit in this invention. Detailed Implementation

[0018] To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0019] It should be noted in advance that in the following description of the present invention, if there are any terms, the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed or operated in a specific orientation. Therefore, they should not be construed as limiting the present invention.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] Throughout this specification, reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the phrase "in one embodiment" or "in some embodiments" appears in various places throughout the specification, and not all references are to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0022] See Figure 1 and Figure 2 This invention provides an LDO circuit with adaptive PSR boost and fast transient response, including a power input port VIN, a power output port VOUT, an error amplifier circuit 10, a transient enhancement circuit 20, a PSR boost circuit 30, a push-pull buffer circuit 40, a power transistor MP50, and a feedback circuit 60; the non-inverting input of the error amplifier circuit 10 is connected to a reference voltage Vref, the inverting input of the error amplifier circuit 10 is connected to the feedback voltage point Vfb of the feedback circuit, and the output of the error amplifier circuit 10 is connected to the input of the push-pull buffer circuit; the output of the push-pull buffer circuit 40 is connected to the gate of the power transistor MP and the PSR boost circuit, and the drain of the power transistor MP50 is connected to the power output port VOUT, the feedback circuit, and the transient enhancement circuit.

[0023] Specifically, the LDO (Low Dropout Linear Regulator) circuit with adaptive PSR boost and fast transient response provided by this invention can utilize easily integrated devices and is suitable for various mainstream BCD processes, facilitating integration. Without altering the basic architecture and static power consumption of a traditional LDO, the addition of transient enhancement and PSR boost circuits results in a higher PSR performance that is less affected by power supply noise. It can quickly detect sudden changes in load current, feeding this information back to the error amplifier to change its tail current, thereby altering the bandwidth and stabilizing the output voltage extremely quickly. This achieves excellent noise suppression capabilities at high frequencies and rapid response to load changes, perfectly meeting the extreme power integrity requirements of next-generation electronic systems.

[0024] See Figure 1In an optional embodiment of the present invention, the error amplifier circuit 10 includes PMOS transistors PM1, PM2, PM3, PM4, NMOS transistors NM1, NM2, NM3, NM4, and NM5; the source of PMOS transistor PM1 is connected to the power input port VIN; the gate of PMOS transistor PM1 is connected to the drain of PMOS transistor PM1, the gate of PMOS transistor PM2, and the first terminal of resistor R2; the drain of PMOS transistor PM1 is connected to the current source input port Ibias, the first terminal of resistor R2, the gate of PMOS transistor PM1, and the first terminal of resistor R2. The gate of PMOS transistor PM2 is connected; the source of PMOS transistor PM2 is connected to the power input port VIN; the gate of PMOS transistor PM2 is connected to the gate of PMOS transistor PM1, the drain of PMOS transistor PM1, the first terminal of resistor R2, and the current source input port Ibias; the drain of PMOS transistor PM2 is connected to the drain of NMOS transistor NM5; the source of PMOS transistor PM3 is connected to the power input port VIN; the gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4, the drain of PMOS transistor PM3, and the drain of NMOS transistor NM1; the drain of PMOS transistor PM3 is connected to the PMOS transistor P... The gate of transistor M3, the gate of PMOS transistor PM4, and the drain of NMOS transistor NM1 are connected; the source of PMOS transistor PM4 is connected to the power input port VIN; the gate of PMOS transistor PM4 is connected to the gate of PMOS transistor PM3, the drain of PMOS transistor PM3, and the drain of NMOS transistor NM1; the drain of PMOS transistor PM4 is connected to the gate of PMOS transistor PM6 and the drain of NMOS transistor NM2; the gate of NMOS transistor NM1 is the non-inverting input terminal of the error amplifier, and the drain of NMOS transistor NM1 is connected to the gate of PMOS transistor PM3, the drain of PMOS transistor PM3, and the gate of PMOS transistor PM4. The NMOS transistor NM1 is connected to the input reference voltage Vref; the source of NMOS transistor NM1 is connected to the source of NMOS transistor NM2, the drain of NMOS transistor NM3, and the drain of NMOS transistor NM4; the drain of NMOS transistor NM1 is connected to the drain of PMOS transistor PM4 and the gate of PMOS transistor PM6; the gate of NMOS transistor NM2 is the inverting input terminal of the error amplifier, and the gate of NMOS transistor NM2 is connected to the feedback voltage point Vfb; the source of NMOS transistor NM2 is connected to the source of NMOS transistor NM1, the drain of NMOS transistor NM3, and the drain of NMOS transistor NM4.The drain of NMOS transistor NM3 is connected to the source of NMOS transistor NM1, the source of NMOS transistor NM2, and the drain of NMOS transistor NM4; the gate of NMOS transistor NM3 is connected to the drain of NMOS transistor NM5, the gate of NMOS transistor NM5, and the first end of resistor R3; the source of NMOS transistor NM3 is connected to the ground port GND; the drain of NMOS transistor NM4 is connected to the source of NMOS transistor NM1, the source of NMOS transistor NM2, and the drain of NMOS transistor NM3; the NM... The gate of NMOS transistor NM4 is connected to the second terminal of capacitor C3; the source of NMOS transistor NM4 is connected to the ground port GND; the drain of NMOS transistor NM5 is connected to the gate of NMOS transistor NM5, the gate of NMOS transistor NM3, the drain of PMOS transistor PM2, and the first terminal of resistor R3; the gate of NMOS transistor NM5 is connected to the gate of NMOS transistor NM3, the drain of NMOS transistor NM5, and the first terminal of resistor R3; the source of NMOS transistor NM5 is connected to the ground port GND.

[0025] In this invention, the tail current of the error amplifier circuit is split into two parallel transistors, NM3 and NM4. NM3 provides a constant bias current, while NM4 improves overshoot voltage. When the output voltage increases due to fluctuations in the load current (i.e., overshoot occurs), this voltage change is transmitted to the gate of the NM4 transistor within the error amplifier through capacitor C3. This causes a sharp increase in the bias current, thereby increasing the unity-gain frequency of the error amplifier and accelerating the feedback loop.

[0026] See Figure 1 In an optional embodiment of the present invention, the transient enhancement circuit 20 includes resistor R2, resistor R3, capacitor C2, and capacitor C3; the first end of resistor R2 is connected to the gate and drain of PMOS transistor PM1; the second end of resistor R2 is connected to the first end of capacitor C2 and the gate of PMOS transistor PM5; the first end of capacitor C2 is connected to the second end of resistor R2 and the gate of PMOS transistor PM5; the second end of capacitor C2 is connected to the drain of power transistor MP, the second end of resistor R3, the first end of capacitor C3, the first end of resistor Rf1, the voltage output port VOUT, and the first end of load resistor RL; the first end of capacitor C3 is connected to the drain of power transistor MP, the second end of resistor R3, the first end of resistor Rf1, and the voltage output port VOUT; the second end of capacitor C3 is connected to the gate of NMOS transistor NM4.

[0027] See Figure 1 In an optional embodiment of the present invention, the PSR boosting circuit 30 includes a PMOS transistor PM5, a PMOS transistor PM8, an NMOS transistor NM6, and a capacitor C1; the source of the PMOS transistor PM5 is connected to the power input port VIN; the gate of the PMOS transistor PM5 is connected to the second terminal of the resistor R2 and the first terminal of the capacitor C2; the drain of the PMOS transistor PM5 is connected to the drain of the NMOS transistor NM6, the source of the PMOS transistor PM8, and the gate of the NMOS transistor NM7; the drain of the NMOS transistor NM6 is connected to the drain of the PMOS transistor PM5 and the PMOS transistor NM6. The source of S-channel transistor PM8 and the gate of NMOS transistor NM7 are connected; the gate of NMOS transistor NM6 is connected to the drain of PMOS transistor PM8 and the second terminal of capacitor C1; the source of NMOS transistor NM6 is connected to the ground port GND; the drain of PMOS transistor PM8 is connected to the gate of NMOS transistor NM6 and the second terminal of capacitor C1; the gate of PMOS transistor PM8 is connected to the first terminal of resistor R1 and the drain of PMOS transistor PM7; the source of PMOS transistor PM8 is connected to the drain of NMOS transistor NM6 and the gate of NMOS transistor NM7.

[0028] The PSR boosting circuit proposed in this invention is an adaptive feedforward path, in which the gain value of the forward path is adjusted according to changes in the load current. This adaptive adjustment enables the circuit to uniformly improve the power supply rejection ratio (PSRR) across the entire load current range. The equivalent impedance R of the PMOS transistor PM8 in the PSR boosting circuit proposed in this invention... PM8 It varies according to the load current, thus achieving a PSR boost across all load currents. Because the gate of the PMOS transistor PM8 is dynamically affected by the voltage across resistor R1, changes in the output current of the low-dropout regulator cause changes in the VGS of the PMOS transistor PM8, which in turn affects R... PM8 The resistance value changes.

[0029] See Figure 1In an optional embodiment of the present invention, the push-pull buffer circuit 40 includes a PMOS transistor PM6, a PMOS transistor PM7, an NMOS transistor NM7, and a resistor R1; the source of the PMOS transistor PM6 is connected to the power input port VIN; the gate of the PMOS transistor PM6 is connected to the drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM2; the drain of the PMOS transistor PM6 is connected to the gate of the PMOS transistor PM7, the gate of the power transistor MP, and the drain of the NMOS transistor NM7; the source of the PMOS transistor PM7 is connected to the power input port VIN; the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM6 and the drain of the power transistor NM7. The gate of transistor MP and the drain of NMOS transistor NM7 are connected; the drain of PMOS transistor PM7 is connected to the first terminal of resistor R1 and the gate of PMOS transistor PM8; the drain of NMOS transistor NM7 is connected to the drain of PMOS transistor PM6, the gate of PMOS transistor PM7, and the gate of power transistor MP; the gate of NMOS transistor NM7 is connected to the drain of NMOS transistor NM6 and the source of PMOS transistor PM8; the source of NMOS transistor NM7 is connected to the ground port GND; the first terminal of resistor R1 is connected to the drain of PMOS transistor PM7 and the gate of PMOS transistor PM8; the second terminal of resistor R1 is connected to the ground port GND.

[0030] See Figure 1 In an optional embodiment of the present invention, the source of the power transistor MP50 is connected to the power input port VIN; the gate of the power transistor MP is connected to the drain of the PMOS transistor PM6 and the gate of the PMOS transistor PM7; the drain of the power transistor MP is connected to the first terminal of the feedback resistor Rf1, the second terminal of the capacitor C2, the voltage output port VOUT, and the first terminal of the load resistor RL.

[0031] See Figure 1In an optional embodiment of the present invention, the feedback circuit 60 includes a feedback resistor Rf1, a feedback voltage point Vfb, a feedback resistor Rf2, and a load resistor RL; the first end of the feedback resistor Rf1 is connected to the drain of the power transistor MP, the first end of the capacitor C2, the voltage output port VOUT, and the first end of the load resistor RL; the second end of the feedback resistor Rf1 is connected to the feedback voltage point Vfb and the first end of the feedback resistor Rf2; the first end of the feedback resistor Rf2 is connected to the second end of the feedback resistor Rf1 and the feedback voltage point Vfb; the second end of the feedback resistor Rf2 is connected to the ground port GND; the first end of the load resistor RL is connected to the drain of the power transistor MP, the voltage output port VOUT, and the first end of the feedback resistor Rf1; the second end of the load resistor RL is connected to the ground port GND.

[0032] To more clearly describe the function of the PSR boosting circuit, based on Figure 3 The expression for the proposed feedforward path can be described as follows:

[0033]

[0034] in A NM6 This is the gain of NMOS transistor NM6; A NM7 This is the gain of NMOS transistor NM7; R PM8 It is the equivalent impedance of PMOS transistor PM8; rds5 It is the drain-source resistance of PMOS transistor PM5. rds6 It is the drain-source resistance of NMOS transistor NM6; It is the transconductance of NMOS transistor NM6.

[0035]

[0036] in μp It is the carrier migration rate of the PMOS transistor; Cox W / L is the gate oxide capacitance of the PMOS transistor; W / L is the width-to-length ratio of the NM8 PMOS transistor. V GS This is the gate-source voltage value of the PMOS transistor NM8; V TH It is the threshold voltage of the PMOS transistor NM8.

[0037] The transient enhancement circuit works as follows: the tail current of the error amplifier circuit is split into two parallel transistors, NM3 and NM4. NM3 provides a constant bias current, while NM4 improves overshoot voltage. When the output voltage increases due to load current fluctuations (i.e., overshoot occurs), this voltage change is transmitted to the gate of the NM4 transistor within the error amplifier through capacitor C3. This causes a sharp increase in the bias current, thereby increasing the unity-gain frequency of the error amplifier and accelerating the feedback loop.

[0038] In summary, this invention improves the power supply rejection ratio (PSR) of a low-dropout linear regulator circuit across the entire operating load current range by adding transient enhancement and PSR boosting circuits without altering the basic architecture and static power consumption of a traditional LDO. The transient enhancement circuit cleverly transmits changes in load current back to the tail current of the error amplifier circuit. When the output voltage increases due to load current fluctuations (i.e., overshoot occurs), this voltage change is transmitted to the gate of the NM4 transistor within the error amplifier through capacitor C3. This causes a sharp increase in bias current, thereby increasing the unity-gain frequency of the error amplifier and accelerating the feedback loop. The PSR boosting circuit is an adaptive feedforward path, where the gain value of the forward path is adjusted according to changes in load current. This adaptive adjustment enables the circuit to uniformly improve the power supply rejection ratio (PSR) across the entire load current range.

[0039] Although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. An LDO circuit with adaptive PSR enhancement and fast transient response, characterized in that, It includes a power input port VIN, a power output port VOUT, an error amplifier circuit, a transient enhancement circuit, a PSR boost circuit, a push-pull buffer circuit, a power transistor MP, and a feedback circuit. The non-inverting input of the error amplifier circuit is connected to the reference voltage Vref, the inverting input of the error amplifier circuit is connected to the feedback voltage point Vfb of the feedback circuit, and the output of the error amplifier circuit is connected to the input of the push-pull buffer circuit. The output of the push-pull buffer circuit is connected to the gate of the power transistor MP and the PSR boost circuit, and the drain of the power transistor MP is connected to the power output port VOUT, the feedback circuit, and the transient enhancement circuit.

2. The LDO circuit with adaptive PSR enhancement and fast transient response according to claim 1, characterized in that, The error amplifier circuit includes PMOS transistors PM1, PM2, PM3, PM4, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, and NMOS transistors NM5. The source of PMOS transistor PM1 is connected to the power input port VIN; the gate of PMOS transistor PM1 is connected to the drain of PMOS transistor PM1, the gate of PMOS transistor PM2, and the first end of resistor R2; the drain of PMOS transistor PM1 is connected to the current source input port Ibias, the first end of resistor R2, the gate of PMOS transistor PM1, and the gate of PMOS transistor PM2. The source of the PMOS transistor PM2 is connected to the power input port VIN; the gate of the PMOS transistor PM2 is connected to the gate of the PMOS transistor PM1, the drain of the PMOS transistor PM1, the first end of the resistor R2, and the current source input port Ibias; the drain of the PMOS transistor PM2 is connected to the drain of the NMOS transistor NM5. The source of the PMOS transistor PM3 is connected to the power input port VIN; the gate of the PMOS transistor PM3 is connected to the gate of the PMOS transistor PM4, the drain of the PMOS transistor PM3, and the drain of the NMOS transistor NM1; the drain of the PMOS transistor PM3 is connected to the gate of the PMOS transistor PM3, the gate of the PMOS transistor PM4, and the drain of the NMOS transistor NM1. The source of the PMOS transistor PM4 is connected to the power input port VIN; the gate of the PMOS transistor PM4 is connected to the gate of the PMOS transistor PM3, the drain of the PMOS transistor PM3, and the drain of the NMOS transistor NM1; the drain of the PMOS transistor PM4 is connected to the gate of the PMOS transistor PM6 and the drain of the NMOS transistor NM2. The gate of NMOS transistor NM1 is the non-inverting input terminal of the error amplifier. The drain of NMOS transistor NM1 is connected to the gates of PMOS transistors PM3, PM3, and PM4. The gate of NMOS transistor NM1 is connected to the input reference voltage Vref. The source of NMOS transistor NM1 is connected to the source of NMOS transistor NM2, the drain of NMOS transistor NM3, and the drain of NMOS transistor NM4. The drain of NMOS transistor NM1 is connected to the drain of PMOS transistor PM4 and the gate of PMOS transistor PM6. The gate of the NMOS transistor NM2 is the inverting input terminal of the error amplifier, and the gate of the NMOS transistor NM2 is connected to the feedback voltage point Vfb; the source of the NMOS transistor NM2 is connected to the source of the NMOS transistor NM1, the drain of the NMOS transistor NM3, and the drain of the NMOS transistor NM4. The drain of NMOS transistor NM3 is connected to the source of NMOS transistor NM1, the source of NMOS transistor NM2, and the drain of NMOS transistor NM4; the gate of NMOS transistor NM3 is connected to the drain of NMOS transistor NM5, the gate of NMOS transistor NM5, and the first end of resistor R3; the source of NMOS transistor NM3 is connected to the ground port GND. The drain of NMOS transistor NM4 is connected to the source of NMOS transistor NM1, the source of NMOS transistor NM2, and the drain of NMOS transistor NM3; the gate of NMOS transistor NM4 is connected to the second terminal of capacitor C3; and the source of NMOS transistor NM4 is connected to the ground port GND. The drain of NMOS transistor NM5 is connected to the gate of NMOS transistor NM5, the gate of NMOS transistor NM3, the drain of PMOS transistor PM2, and the first terminal of resistor R3; the gate of NMOS transistor NM5 is connected to the gate of NMOS transistor NM3, the drain of NMOS transistor NM5, and the first terminal of resistor R3; the source of NMOS transistor NM5 is connected to the ground port GND.

3. The LDO circuit with adaptive PSR enhancement and fast transient response according to claim 2, characterized in that, The transient enhancement circuit includes resistor R2, resistor R3, capacitor C2, and capacitor C3; The first end of the resistor R2 is connected to the gate and drain of the PMOS transistor PM1; the second end of the resistor R2 is connected to the first end of the capacitor C2 and the gate of the PMOS transistor PM5. The first terminal of capacitor C2 is connected to the second terminal of resistor R2 and the gate of PMOS transistor PM5; the second terminal of capacitor C2 is connected to the drain of power transistor MP, the second terminal of resistor R3, the first terminal of capacitor C3, the first terminal of resistor Rf1, the voltage output port VOUT, and the first terminal of load resistor RL. The first terminal of capacitor C3 is connected to the drain of power transistor MP, the second terminal of resistor R3, the first terminal of resistor Rf1, and the voltage output port VOUT; the second terminal of capacitor C3 is connected to the gate of NMOS transistor NM4.

4. The LDO circuit with adaptive PSR enhancement and fast transient response according to claim 3, characterized in that, The PSR boost circuit includes PMOS transistor PM5, PMOS transistor PM8, NMOS transistor NM6 and capacitor C1; The source of the PMOS transistor PM5 is connected to the power input port VIN; the gate of the PMOS transistor PM5 is connected to the second terminal of the resistor R2 and the first terminal of the capacitor C2; the drain of the PMOS transistor PM5 is connected to the drain of the NMOS transistor NM6, the source of the PMOS transistor PM8, and the gate of the NMOS transistor NM7. The drain of the NMOS transistor NM6 is connected to the drain of the PMOS transistor PM5, the source of the PMOS transistor PM8, and the gate of the NMOS transistor NM7; the gate of the NMOS transistor NM6 is connected to the drain of the PMOS transistor PM8 and the second terminal of the capacitor C1; the source of the NMOS transistor NM6 is connected to the ground port GND. The drain of the PMOS transistor PM8 is connected to the gate of the NMOS transistor NM6 and the second terminal of the capacitor C1; the gate of the PMOS transistor PM8 is connected to the first terminal of the resistor R1 and the drain of the PMOS transistor PM7; the source of the PMOS transistor PM8 is connected to the drain of the NMOS transistor NM6 and the gate of the NMOS transistor NM7.

5. The LDO circuit with adaptive PSR enhancement and fast transient response according to claim 4, characterized in that, The push-pull buffer circuit includes PMOS transistor PM6, PMOS transistor PM7, NMOS transistor NM7 and resistor R1; The source of the PMOS transistor PM6 is connected to the power input port VIN; the gate of the PMOS transistor PM6 is connected to the drain of the PMOS transistor PM4 and the drain of the NMOS transistor NM2; the drain of the PMOS transistor PM6 is connected to the gate of the PMOS transistor PM7, the gate of the power transistor MP, and the drain of the NMOS transistor NM7. The source of the PMOS transistor PM7 is connected to the power input port VIN; the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM6, the gate of the power transistor MP, and the drain of the NMOS transistor NM7; the drain of the PMOS transistor PM7 is connected to the first terminal of the resistor R1 and the gate of the PMOS transistor PM8. The drain of the NMOS transistor NM7 is connected to the drain of the PMOS transistor PM6, the gate of the PMOS transistor PM7, and the gate of the power transistor MP; the gate of the NMOS transistor NM7 is connected to the drain of the NMOS transistor NM6 and the source of the PMOS transistor PM8; the source of the NMOS transistor NM7 is connected to the ground port GND. The first end of the resistor R1 is connected to the drain of the PMOS transistor PM7 and the gate of the PMOS transistor PM8; the second end of the resistor R1 is connected to the ground port GND.

6. The LDO circuit with adaptive PSR enhancement and fast transient response according to claim 5, characterized in that, The source of the power transistor MP is connected to the power input port VIN; the gate of the power transistor MP is connected to the drain of the PMOS transistor PM6 and the gate of the PMOS transistor PM7; the drain of the power transistor MP is connected to the first terminal of the feedback resistor Rf1, the second terminal of the capacitor C2, the voltage output port VOUT, and the first terminal of the load resistor RL.

7. The LDO circuit with adaptive PSR enhancement and fast transient response according to claim 6, characterized in that, The feedback circuit includes a feedback resistor Rf1, a feedback voltage point Vfb, a feedback resistor Rf2, and a load resistor RL; The first terminal of the feedback resistor Rf1 is connected to the drain of the power transistor MP, the first terminal of the capacitor C2, the voltage output port VOUT, and the first terminal of the load resistor RL; the second terminal of the feedback resistor Rf1 is connected to the feedback voltage point Vfb and the first terminal of the feedback resistor Rf2. The first end of the feedback resistor Rf2 is connected to the second end of the feedback resistor Rf1 and the feedback voltage point Vfb; the second end of the feedback resistor Rf2 is connected to the grounding port GND. The first end of the load resistor RL is connected to the drain of the power transistor MP, the voltage output port VOUT, and the first end of the feedback resistor Rf1; the second end of the load resistor RL is connected to the ground port GND.

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