Uci e-based debug information recording method, storage medium, and artificial intelligence chip

Abstract

The application provides a UCIe-based debugging information recording method, a storage medium and an artificial intelligence chip. The debugging information recording method comprises the following steps: setting the format of a debugging chain by a direct memory access module; updating the debugging chain by the direct memory access module; and sending the debugging chain to at least one of a memory bus and a control bus by the direct memory access module, wherein the debugging chain comprises a start mark, timestamp register information and an end mark, and further comprises at least one debugging register information or at least one error transmission information. The debugging information recording method, the computer readable storage medium and the artificial intelligence chip can effectively record debugging information.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a UCIe-based debugging information recording method, storage medium, and artificial intelligence chip. Background Technology

[0002] In existing inter-chip communication systems, the recording of debug information is incomplete. The main reason is that traditional systems use static registers to store debug information, so earlier debug information is overwritten by subsequent debug information. However, in more complex error scenarios, insufficient debug information can drastically increase the complexity of error analysis, leading to low debugging efficiency and difficulty in locating the root cause of errors.

[0003] In addition, since the existing debugging method uses static debug log registers to store debug information, some debug log registers in the existing system have a fixed size and debug log content after the hardware is manufactured, which makes it impossible to dynamically adjust them according to the actual error scenario. Summary of the Invention

[0004] This invention relates to a UCIe-based debugging information recording method, a computer-readable storage medium, and an artificial intelligence chip, which can effectively record debugging information.

[0005] According to an embodiment of the present invention, a UCIe-based debug information recording method includes the following steps: setting the format of the debug chain through a direct access module; updating the debug chain through the direct access module; and sending the debug chain to at least one of the memory bus and the control bus through the direct access module. The debug chain includes a start flag, timestamp register information, and an end flag, and also includes at least one debug register information or at least one error transmission information.

[0006] In the debugging information recording method according to an embodiment of the present invention, the starting identifier includes the index information of the debugging chain.

[0007] In the debugging information recording method according to an embodiment of the present invention, the end marker includes information on the quantity of at least one error transmission information.

[0008] In the debugging information recording method according to an embodiment of the present invention, at least one of the debugging register information includes physical layer debugging register information, adaptation layer debugging register information, and protocol layer debugging register information.

[0009] In the debugging information recording method according to an embodiment of the present invention, at least one error transmission information includes error transmission information belonging to at least one of a read operation, a write operation, and an atomic operation.

[0010] In the debugging information recording method according to an embodiment of the present invention, the direct access module is implemented in the UCIe protocol layer.

[0011] The debugging information recording method according to an embodiment of the present invention further includes: allocating at least one of the memory bus address space and the control bus address space to the direct access module; and setting the address overlay mode of the direct access module.

[0012] In the debugging information recording method according to an embodiment of the present invention, the address overwrite mode includes a first address overwrite mode. In the first address overwrite mode, when the address space allocated to the direct access module is full, the sending of requests for new debug chains is stopped.

[0013] In the debugging information recording method according to an embodiment of the present invention, the address overwrite mode includes a second address overwrite mode. In the second address overwrite mode, when the address space allocated to the direct access module is full, a new debugging chain is sent from the starting address of the address space allocated to the direct access module to overwrite the previous debugging chain.

[0014] In the debugging information recording method according to an embodiment of the present invention, the address overwrite mode includes a third address overwrite mode. In the third address overwrite mode, the direct access module specifies the length of the debug chain. When the address space allocated to the direct access module is full, the debug chain continues to be sent from the starting address of the address space allocated to the direct access module to overwrite previous data. When the address space allocated to the direct access module is not full and the debug chain has been sent completely, the request to send a new debug chain is stopped.

[0015] According to an embodiment of the present invention, a computer-readable storage medium is used to store a computer program. The computer program is executed by a processor to implement the steps of the above-described debugging information recording method.

[0016] According to an embodiment of the present invention, a UCIe-based artificial intelligence chip includes a first chip and a second chip. The artificial intelligence chip also includes a storage module and a processor. The artificial intelligence chip stores multiple algorithms. The processor is coupled to the storage module. The processor is used to execute the multiple algorithms to implement a Direct Memory Access (DMI) module in the protocol layer of the first and second chips within the UCIe framework. The DMI module is used to set the format of a debug chain and to update the debug chain. The DMI module is used to send the debug chain to at least one of the memory bus and the control bus. The debug chain includes a start flag, timestamp register information, and an end flag, and also includes at least one debug register information or at least one error transmission information.

[0017] Based on the above, the UCIe-based debugging information recording method, computer-readable storage medium, and artificial intelligence chip of the present invention can dynamically set the debugging chain through the direct access module and send the debugging chain to at least one of the memory bus and the control bus to realize the debugging information recording function that can be flexibly changed according to the actual application scenario.

[0018] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of the present invention;

[0020] Figure 2 This is a flowchart of a debugging information recording method according to an embodiment of the present invention;

[0021] Figure 3 This is a schematic diagram of the debugging chain according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the debugging chain according to an embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the debugging chain according to an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the debugging chain according to an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram illustrating the allocation of address space according to an embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram illustrating the allocation of address space according to an embodiment of the present invention;

[0027] Figure 9 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention.

[0028] Explanation of icon numbers

[0029] 100: Data transmission system;

[0030] 101: The memory bus of the first chip;

[0031] 102: The memory bus of the second chip;

[0032] 103: Memory bus;

[0033] 104: Control bus;

[0034] 110: UCIe protocol layer;

[0035] 111: Direct Access Module;

[0036] 112: First data transmission module;

[0037] 113: Second data transmission module;

[0038] 120: UCIe adapter layer;

[0039] 130: UCIe physical layer;

[0040] 300: First debug chain;

[0041] 400: Second debug chain;

[0042] 500: 3rd debug chain;

[0043] 600: 4th debug chain;

[0044] 710_1: Debug chain of timestamp t1_1;

[0045] 710_2: Debug chain of timestamp t1_2;

[0046] 710_N: Debug chain of timestamp t1_N;

[0047] 810_1: Debug chain of timestamp t2_1;

[0048] 810_2: Debug chain of timestamp t2_2;

[0049] 810_K: Debug chain of timestamp t2_K;

[0050] 310: First starting marker;

[0051] 410: Second starting marker;

[0052] 510: The third starting marker;

[0053] 610: The fourth starting marker;

[0054] 320: End marker for the first section;

[0055] 420: End marker for the second part;

[0056] 520: End marker for the 3rd section;

[0057] 620: End marker for the 4th section;

[0058] 331: Information from the 1st_1st timestamp register;

[0059] 332: Information from the 1st and 2nd timestamp registers;

[0060] 431: Information from the 2_1st timestamp register;

[0061] 432: Information from the 2_2nd timestamp register;

[0062] 531: Information from the 3_1st timestamp register;

[0063] 532: Information from the 3rd_2nd timestamp register;

[0064] 631: Information from the 4_1st timestamp register;

[0065] 632: Information from the 4_2nd timestamp register;

[0066] 340_a: Debug register information for 1_a;

[0067] 340_b: Debug register information for 1_b;

[0068] 540_a: Debug register information for 2_a;

[0069] 540_b: Debug register information for part 2_b;

[0070] 640_1: Debug register information (3_1);

[0071] 640_M: Debug register information for the 3_Mth generation;

[0072] 350_1: Error transmission information No. 11_1 from the first core to the second core;

[0073] 350_R: Error transmission information of the 11th R from the first core to the second core;

[0074] 450_1: Error transmission information 21_1 from the first core to the second core;

[0075] 450_R: Error transmission information for the 21st R stage from the first core to the second core;

[0076] 360_1: Error transmission information 12_1 from the second core to the first core;

[0077] 360_S: Error transmission information from the second core to the first core, 12_S later;

[0078] 460_1: Error transmission information 22_1 from the second core to the first core;

[0079] 460_S: Error transmission information from the second core to the first core, 22_S.

[0080] 700: Memory line bus address space;

[0081] 800: Control bus address space;

[0082] 900: Artificial intelligence chip;

[0083] 910: First chip;

[0084] 920: Second core. Detailed Implementation

[0085] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0086] Figure 1 This is a schematic diagram of a data transmission system according to an embodiment of the present invention. (See reference) Figure 1 The data transmission system 100 includes a first chiplet and a second chiplet. The first and second chiplets are used to implement die-to-die communication based on the Universal Chiplet Interconnect Express (UCIe) protocol. The data transmission system 100 also includes a processor and a storage module. The storage module is used to store multiple algorithms. The processor is coupled to the storage module and is used to execute the multiple algorithms, for example, in... Figure 1 The UCIe protocol layer 110 shown implements a direct access module 111. The data transmission system 100 includes a first-core memory bus 101, a second-core memory bus 102, a memory bus 103, a control bus 104, a UCIe protocol layer 110, a UCIe adaptation layer 120, and a UCIe physical layer 130. The UCIe protocol layer 110, UCIe adaptation layer 120, and UCIe physical layer 130 are implemented between the first-core memory bus 101 and the second-core memory bus 102. The direct access module 111 of the UCIe protocol layer 110 can be used to implement the debugging information recording function of the main data path between the first-core memory bus 101 and the second-core memory bus 102, and can send the recording results of the debugging information to at least one of the memory bus 103 and the control bus 104.

[0087] The UCIe protocol layer 110 and the UCIe adaptation layer 120 are connected via an FDI (Flit-aware Die-to-Die Interface) interface. Downstream on the chip side, the UCIe protocol layer 110 is connected to the chip's NOC (Network on Chip) interface. Based on this, the UCIe protocol layer 110 also includes a first data transmission module 112 and a second data transmission module 113. The first data transmission module 112 converts data packets from the packet format required by the NOC interface into Flit (cell) format packets and sends them to the FDI interface. The second data transmission module 113 decodes Flit format packets received by the FDI interface into packets in the packet format required by the NOC interface and sends them to the NOC interface.

[0088] Processors may include, for example, a central processing unit (CPU) or other programmable general-purpose or special-purpose microprocessor, digital signal processor (DSP), programmable controller, application-specific integrated circuit (ASIC), programmable logic device (PLD), other similar processing devices, or combinations thereof.

[0089] Storage modules may include, for example, random access memory (RAM), non-volatile memory, hard disk drive (HDD), or solid state drive (SSD). Random access memory may include, for example, dynamic random access memory (DRAM) or static random access memory (SRAM). Non-volatile memory may include, for example, flash memory or read-only memory (ROM).

[0090] Figure 2 This is a flowchart of a debugging information recording method according to an embodiment of the present invention. (See reference) Figure 1 as well as Figure 2The data transmission system 100 can execute the following steps S210 to S230. In step S210, the direct access module 111 sets the format of the debug chain. In this embodiment, during the initialization process, the direct access module 111 can set a suitable debug chain format according to actual usage requirements. In this embodiment, the debug chain includes a start flag, timestamp register information, and an end flag, and also includes at least one debug register information or at least one error transmission information. Detailed implementation of the debug chain format will be provided below. Figures 3 to 6 The following embodiments will be used to illustrate this in detail. The Direct Memory Access (DMI) module 111 can be selectively sent to at least one of the memory bus 103 and the control bus 104, thereby allocating the corresponding address space. Furthermore, the DMI module 111 can determine the address overlay mode according to actual usage requirements, and a detailed implementation of the debug chain format will be provided below. Figures 7 to 8 The following examples will be used to illustrate this in detail.

[0091] In step S220, the Direct Access Module 111 updates the debug chain. During actual use, the Direct Access Module 111 can obtain debug information from at least one of the UCIe protocol layer 110, UCIe adaptation layer 120, and UCIe physical layer 130, and record it in the debug chain. In step S230, the Direct Access Module 111 sends the debug chain to at least one of the memory bus 103 and control bus 104. Therefore, even if one of the memory bus 103 and control bus 104 is damaged, the Direct Access Module 111 can still send the debug chain to the other bus, so that the system can still be debugged and located.

[0092] Figure 3 This is a schematic diagram of a debugging chain according to an embodiment of the present invention. (See reference) Figure 3 In one embodiment, the direct access module 111 can establish such... Figure 3The first debug chain 300 is shown. The first debug chain 300 includes a first start identifier 310, a first end identifier 320, first timestamp register information (including first_1 timestamp register information 331 and first_2 timestamp register information 332), first_a debug register information 340_a to first_b debug register information 340_b, error transmission information 350_1 from the first chip to the second chip (first_1 to first_2) (first_R to first_2), and error transmission information 360_1 from the second chip to the first chip (second_1 to second_2) (second_S to first_2), where a, b, R, and S can be 0 or positive integers. It should be noted that the first debug chain 300 may include only one debug register data (corresponding to one debug register information) or only one error transmission message.

[0093] In this embodiment, the first start identifier 310 includes index information of the first debug chain 300, indicating which debug chain the first debug chain 300 is. The first end identifier 320 includes information on the number of error transmissions. In one embodiment, the index information and the number of error transmissions may each be 32 bits of data, but the invention is not limited thereto. In this embodiment, the first_1 timestamp register information 331 and the first_2 timestamp register information 332 can, for example, be used to indicate the start and end times of the first debug chain 300. Therefore, the index information in the first start identifier 310 facilitates software calibration to ensure the correctness of the currently processed debug chain, and also helps to accurately determine the position of the debug chain together with the timestamp.

[0094] In this embodiment, the first_a debug register information 340_a to the first_b debug register information 340_b can be selected based on different UCIe designs or different actual usage scenarios to determine which registers are placed in the first debug chain 300. The system can select the start position (i.e., the first_a debug register 340_a) and the end position (i.e., the first_b debug register 340_b) of the debug register information to select only a portion of the debug register information to be serialized into the first debug chain 300 (i.e., for example, if there are 1 to M debug registers, where M is a positive integer, the debug register information of the 5th to 10th consecutive debug registers can be selected to be stored). In this way, it is easier to filter out the required debug register information, thereby avoiding the occupation of actual storage address space by unhelpful debug register information.

[0095] Additionally, debug register information 340_a (first type) to 340_b (second type) may include at least one of the physical layer debug register information, adaptation layer debug register information, and protocol layer debug register information. In practical use, debug register information from certain layers can be selected according to actual needs. For example, if the number of transmissions of erroneous transmission information is incorrect, only the protocol layer debug register information can be selected. Alternatively, if a link establishment error occurs, only the physical layer debug register information can be selected.

[0096] In this embodiment, the number of error transmission information 350_1 (11_1) to 11_R (11_R) from the first core to the second core, and the number of error transmission information 360_1 (12_1) to 12_S (12_S) from the second core to the first core, can be 0 to multiple. These are error transmission information that the Direct Memory Access Module 111 may cache during a single debug chain transmission, and the number of error transmission information is stored in the first end marker 320. In other words, if the Direct Memory Access Module 111 does not receive any error transmission information within a timestamp interval, the number of error transmission information is 0. Furthermore, the first debugging chain 300 can also store only the 11_1 error transmission information 350_1 to the 11_R error transmission information 350_R from the first core to the second core, or only the 12_1 error transmission information 360_1 to the 12_S error transmission information 360_S from the second core to the first core, depending on actual usage requirements.

[0097] Furthermore, the types of the error transmission information 350_1 (11_1) to 350_R (11_R) from the first core to the second core, and the error transmission information 360_1 (12_1) to 360_S (12_S) from the second core to the first core, include, for example, error transmission information belonging to at least one of read operations, write operations, and atomic operations. Moreover, the error transmission information 350_1 (11_1) to 350_R (11_R) from the first core to the second core, and the error transmission information 360_S (12_1) to 360_S (12_S) from the second core to the first core, may include, for example, error transmission information indicating no response after a timeout following request transmission or error transmission information indicating an error status.

[0098] Figure 4 This is a schematic diagram of a debugging chain according to an embodiment of the present invention. (See reference) Figure 1 and Figure 4In one embodiment, the direct access module 111 can establish such... Figure 4 The second debug chain 400 is shown. The second debug chain 400 includes a second start identifier 410, a second end identifier 420, second timestamp register information (including second_1 timestamp register information 431 and second_2 timestamp register information 432), error transmission information 450_1 from the first chip to the second chip (21_1 error transmission information 450_1 to 21_R error transmission information 450_R), and error transmission information 460_1 from the second chip to the first chip (22_1 error transmission information 460_1 to 22_S error transmission information 460_S). In other words, the direct access module 111 can also establish, according to actual usage requirements, such as... Figure 4 The second debug chain 400 shown does not include debug register information, but only contains timestamps and error transmission information.

[0099] Figure 5 This is a schematic diagram of a debugging chain according to an embodiment of the present invention. (See reference) Figure 1 and Figure 5 In one embodiment, the direct access module 111 can establish such... Figure 5 The third debug chain 500 is shown. The third debug chain 500 includes a third start identifier 510, a third end identifier 520, third timestamp register information (including third_1 timestamp register information 531 and third_2 timestamp register information 532), and second_a debug register information 540_a to second_b debug register information 540_b. In other words, the direct access module 111 can also establish, according to actual usage requirements, such as... Figure 5 The third debug chain 500 shown does not include error transmission information, but only contains timestamps and debug register information. Furthermore, the debug register information 540_a (2_a) to 540_b (2_b) can be one of the following register types: filtered physical layer debug register information, adaptation layer debug register information, and protocol layer debug register information.

[0100] Figure 6 This is a schematic diagram of a debugging chain according to an embodiment of the present invention. (See reference) Figure 1 and Figure 6 In one embodiment, the direct access module 111 can establish such... Figure 6The fourth debug chain 600 is shown. The fourth debug chain 600 includes a fourth start identifier 610, a fourth end identifier 620, fourth timestamp register information (including fourth_1 timestamp register information 631 and fourth_2 timestamp register information 632), and third_1 debug register information 640_1 to third_M debug register information 640_M. In other words, the direct access module 111 can also establish, according to actual usage requirements, such as... Figure 6 The fourth debug chain 600 shown does not include error transmission information, but only contains timestamps and debug register information. Furthermore, the third_1 debug register information 640_1 to the third_M debug register information 640_M can be a complete debug register information chain, and can be one of the following register types: filtered physical layer debug register information, adaptation layer debug register information, and protocol layer debug register information.

[0101] Figure 7 This is a schematic diagram of address space allocation according to an embodiment of the present invention. Figure 8 This is a schematic diagram illustrating the allocation of address space according to an embodiment of the present invention. (Reference) Figure 1 , Figure 7 as well as Figure 8 To accommodate various debugging needs, the data transmission system 100 can be allocated as follows: Figure 7 The memory line bus address space 700 shown and as follows Figure 8 At least one of the control bus address spaces 800 shown is assigned to the Direct Memory Access Module 111, and the address overwrite mode of the Direct Memory Access Module 111 is set. The Direct Memory Access Module 111 can send debug chains to the memory bus 103 or the control bus 104. Therefore, when the memory bus 103 or the control bus 104 fails and becomes inaccessible, the Direct Memory Access Module 111 can send debug chains to another bus so that the system can still be debugged.

[0102] In addition, such as Figure 7As shown, the memory line bus address space 700 can store N debug chains, such as debug chain 710_1 for timestamp t1_1, debug chain 710_2 for timestamp t1_2, ..., debug chain 710_N for timestamp t1_N, where N is a positive integer. The system determines how many debug chains at different times can be stored in the memory line bus address space 700 based on the space occupied by each debug chain and the memory line bus address space allocated to the direct memory access module 111. For example, assuming the address space allocated to the direct memory access module 111 is 4MB (Megabyte), and the space occupied by a single debug chain is 4KB (Kilobyte), then a maximum of 1024 debug chains can be stored in this 4MB space (i.e., 4MB / 4KB = 1024).

[0103] like Figure 8 As shown, the Direct Memory Access (DMI) module 111 can also store debug chains in the control bus address space 800. The control bus address space 800 can store K debug chains, such as debug chain 810_1 for timestamp t2_1, debug chain 810_2 for timestamp t2_2, ..., debug chain 810_K for timestamp t2_K, where K is a positive integer. The system determines how many debug chains at different times can be stored in the control bus address space 800 based on the space occupied by each debug chain and the control bus address space allocated to the DMI module 111.

[0104] However, continuing with the above example, if the number of debug chains exceeds 1024 in actual use, the direct access module 111 can perform subsequent processing according to the set address overwrite mode. This address overwrite mode may include, for example, at least one of a first address overwrite mode, a second address overwrite mode, and a third address overwrite mode.

[0105] In detail, in the first address overwrite mode, when the address space allocated to the direct access module 111 is full, the system will stop sending requests for new debug chains.

[0106] In the second address overwrite mode, when the address space allocated to the direct access module 111 is full, the system continues sending the new debug chain from the starting address of the address space allocated to the direct access module 111 (e.g., resending from low address to high address) to overwrite the previous debug chain. In other words, for example... Figure 7 As shown, the debug chain of the next timestamp after the debug chain 710_N of timestamp t1_N will overwrite the address space of the debug chain 710_1 of timestamp t1_1 to continue storing.

[0107] In the third address overwrite mode, the direct access module 111 can first specify the length of the debug chain. When the address space allocated to the direct access module 111 is full, the system continues sending the debug chain from the starting address of the address space allocated to the direct access module 111 to overwrite previous data. In other words, for example... Figure 7 As shown, if the debug chain 710_N of timestamp t1_N exceeds the allocated address space, the excess portion of the debug chain 710_N of timestamp t1_N will overwrite the address space of the debug chain 710_1 of timestamp t1_1 to continue storage. Furthermore, when the address space allocated to the direct access module is not full and the debug chain has been sent completely, requests for new debug chains are stopped. In other words, for example... Figure 7 As shown, if the debug chain 710_N of timestamp t1_N has been recorded and the address space allocated to the direct access module 111 has not been filled, the system will still stop sending requests for new debug chains.

[0108] Figure 9 This is a schematic diagram of an artificial intelligence chip according to an embodiment of the present invention. (See reference) Figure 9 In one embodiment, the artificial intelligence chip 900 may include a first chip 910 and a second chip 920. The first chip 910 and the second chip 920 are used to achieve inter-chip communication based on a general-purpose chip interconnect technology. The first chip 910 and the second chip 920 may be configured as follows: Figure 1 The data transmission system 100 is shown. For details regarding the implementation methods and technical details of the first chip 910 and the second chip 920, please refer to the descriptions of the above embodiments. Furthermore, the data transmission method between the first chip 910 and the second chip 920 can also refer to the processes of the above embodiments, thus providing sufficient teaching, suggestions, and implementation instructions. In addition, in another embodiment, the number of chips in the artificial intelligence chip 900 is not limited to... Figure 9 The first core 910 and the second core 920 are shown.

[0109] In one embodiment, the artificial intelligence chip 900 can be any one of a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose graphics processing unit (GPGPU).

[0110] In summary, the UCIe-based debugging information recording method, computer-readable storage medium, and artificial intelligence chip of this invention enable highly flexible debugging chains, allowing for the selection of appropriate debugging information formats based on actual usage requirements. Furthermore, it can compress invalid information throughout the debugging chain, thereby reducing its length and effectively increasing the density of useful information. Moreover, compared to existing technologies that can only read static registers for debugging, the UCIe-based debugging information recording method, computer-readable storage medium, and artificial intelligence chip of this invention can send real-time dynamic debugging information to at least one of the memory address bus and control bus via a direct access module, achieving unlimited recording of debugging information. The recorded content can also be set according to different actual usage requirements, thus realizing a convenient and highly flexible UCIe-based debugging function.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for recording debugging information based on UCIe, characterized in that, include: The debug chain format is set through the direct access module; The debug chain is updated through the direct access module, and debug information is obtained from at least one of the UCIe protocol layer, UCIe adaptation layer and UCIe physical layer and recorded in the debug chain. as well as, The debug chain is sent to at least one of the memory bus and the control bus via the direct access module. The debug chain includes a start flag, timestamp register information, and an end flag, and also includes at least one debug register information or at least one error transmission information.

2. The debugging information recording method based on UCIe according to claim 1, characterized in that, The starting identifier includes the index information of the debug chain.

3. The debugging information recording method based on UCIe according to claim 1, characterized in that, The end indicator includes information on the number of the at least one erroneous transmission information.

4. The debugging information recording method based on UCIe according to claim 1, characterized in that, The at least one debug register information includes at least one of physical layer debug register information, adaptation layer debug register information, and protocol layer debug register information.

5. The debugging information recording method based on UCIe according to claim 1, characterized in that, The type of the at least one error transmission information includes error transmission information belonging to at least one of read operations, write operations, and atomic operations.

6. The debugging information recording method based on UCIe according to claim 1, characterized in that, The direct access module is implemented in the UCIe protocol layer.

7. The debugging information recording method based on UCIe according to claim 1, characterized in that, Also includes: Allocate at least one of the memory bus address space and the control bus address space to the direct access module; as well as Configure the address overwrite mode of the direct access module.

8. The debugging information recording method based on UCIe according to claim 7, characterized in that, The address overwrite mode includes a first address overwrite mode. In the first address overwrite mode, when the address space allocated to the direct access module is full, the sending of new debug chain requests stops.

9. The debugging information recording method based on UCIe according to claim 8, characterized in that, The address overwrite mode includes a second address overwrite mode. In the second address overwrite mode, when the address space allocated to the direct access module is full, a new debug chain is sent from the starting address of the address space allocated to the direct access module to overwrite the previous debug chain.

10. The debugging information recording method based on UCIe according to claim 9, characterized in that, The address overwrite mode includes a third address overwrite mode. In the third address overwrite mode, the direct access module specifies the length of the debug chain. When the address space allocated to the direct access module is full, the debug chain continues to be sent from the starting address of the address space allocated to the direct access module to overwrite previous data. When the address space allocated to the direct access module is not full and the debug chain has been sent, the request to send the new debug chain is stopped.

11. A computer-readable storage medium for storing a computer program, characterized in that, The computer program is executed by a processor to implement the steps of the UCIe-based debugging information recording method according to any one of claims 1 to 10.

12. An artificial intelligence chip based on UCIe, comprising a first chip and a second chip, characterized in that, The artificial intelligence chip also includes: A storage module for storing multiple algorithms; and, A processor, coupled to the storage module, is configured to execute the plurality of algorithms to implement a direct access module in the UCIe protocol layer of the first and second chips. The direct access module is used to set the format of the debug chain, and to update the debug chain by obtaining debug information from at least one of the UCIe protocol layer, UCIe adaptation layer, and UCIe physical layer, and recording it in the debug chain. The direct access module is used to send the debug chain to at least one of the memory bus and the control bus. The debug chain includes a start flag, timestamp register information, and an end flag, and also includes at least one debug register information or at least one error transmission information.

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