Accelerator card emulation methods, devices, equipment, storage media and software products

Abstract

This application discloses an accelerator card simulation method, apparatus, device, storage medium, and program product, relating to the field of accelerator card technology. The method includes obtaining multiple execution instructions corresponding to a target task; determining a first mapping relationship between the multiple execution instructions and multiple thread bundles of the target task; determining a second mapping relationship between the multiple thread bundles and multiple processors, the second mapping relationship including the identifiers of the multiple processors and the identifier of at least one thread bundle corresponding to each processor; and determining the predicted execution time of the target task by the accelerator card based on the first mapping relationship, the second mapping relationship, and the operating parameters of the multiple processors. The above method can improve simulation accuracy.

Description

Technical Field

[0001] This application relates to the field of accelerator card technology, and in particular to an accelerator card emulation method, apparatus, equipment, storage medium and program product. Background Technology

[0002] Graphics Processing Unit (GPU) simulation includes functional-level simulation and behavioral-level performance simulation.

[0003] Behavioral performance simulation aims to predict GPU performance metrics, such as GPU latency. However, current GPU behavioral performance simulations primarily rely on experience and fixed latency, resulting in poor simulation accuracy. Summary of the Invention

[0004] This application provides an accelerator card simulation method, apparatus, device, storage medium, and program product to at least solve the problem of poor simulation accuracy in related technologies.

[0005] Firstly, this application provides an accelerator card emulation method, wherein the accelerator card includes multiple processors, and the method includes:

[0006] Obtain multiple execution instructions corresponding to the target task;

[0007] Determine the initial mapping relationship between multiple execution instructions and multiple thread bundles of the target task;

[0008] A second mapping relationship is determined between multiple thread bundles and multiple processors. The second mapping relationship includes the identifiers of the multiple processors and the identifier of at least one thread bundle corresponding to each processor.

[0009] Based on the first mapping relationship, the second mapping relationship, and the operating parameters of multiple processors, the predicted duration for the accelerator card to execute the target task is determined.

[0010] Secondly, this application provides an accelerator card emulation device, characterized in that the accelerator card includes multiple processors, and the device includes an acquisition module and a determination module, wherein:

[0011] The acquisition module is used to acquire multiple execution instructions corresponding to the target task;

[0012] The determination module is used to determine the first mapping relationship between multiple execution instructions and multiple thread bundles of the target task;

[0013] The determining module is further configured to determine a second mapping relationship between multiple thread bundles and multiple processors, the second mapping relationship including the identifiers of the multiple processors and the identifier of at least one thread bundle corresponding to each processor;

[0014] The determination module is also used to determine the predicted duration of the accelerator card's execution of the target task based on the first mapping relationship, the second mapping relationship, and the operating parameters of multiple processors.

[0015] Thirdly, this application provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the accelerator card emulation methods described in the first aspect.

[0016] Fourthly, this application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the accelerator card emulation methods described in the first aspect.

[0017] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the accelerator card emulation methods described in the first aspect.

[0018] The technical solution provided in this application allows an electronic device to acquire multiple execution instructions corresponding to a target task; determine a first mapping relationship between the multiple execution instructions and multiple thread bundles of the target task; determine a second mapping relationship between the multiple thread bundles and multiple processors, the second mapping relationship including the identifiers of the multiple processors and the identifier of at least one thread bundle corresponding to each processor; and determine the predicted execution time of the target task by the accelerator card based on the first mapping relationship, the second mapping relationship, and the operating parameters of the multiple processors. This method achieves the purpose of behavioral-level performance simulation of the accelerator card and improves simulation accuracy. Attached Figure Description

[0019] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a Hopper architecture GPU.

[0021] Figure 2 A flowchart illustrating the accelerator card emulation method provided in this application embodiment. Figure 1 ;

[0022] Figure 3 A flowchart illustrating the accelerator card emulation method provided in this application embodiment. Figure 2 ;

[0023] Figure 4A flowchart illustrating the accelerator card emulation method provided in this application embodiment. Figure 3 ;

[0024] Figure 5 A flowchart illustrating the accelerator card emulation method provided in this application embodiment. Figure 4 ;

[0025] Figure 6 This is a schematic diagram of the structure of an accelerator card simulation device provided in an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of another accelerator card simulation device provided in an embodiment of this application;

[0027] Figure 8 A schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0029] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0030] To facilitate understanding, the technical terms and background technology provided in the embodiments of this application will be explained first.

[0031] 1. GPU Hardware Architecture: The hardware architecture of a GPU typically consists of multiple Streaming Multiprocessors (SMs). Each SM contains several Compute Unified Device Architecture (CUDA) cores for parallel execution of arithmetic and logic operation instructions. To achieve high concurrency, the GPU uses warps as the smallest scheduling unit. A warp typically consists of 32 threads, all of which execute the same instructions within the same clock cycle in a Single Instruction Multiple Threads (SIMT) manner. CUDA-programmed code is translated into instructions by the compiler, which are then loaded and executed by the GPU, a process similar to that of a Central Processing Unit (CPU). These instructions typically include Arithmetic Logic Unit (ALU) instructions and memory access instructions. ALU instructions primarily perform floating-point or integer addition, subtraction, multiplication, and division operations, representing the main workload for computationally intensive tasks such as matrix addition and matrix multiplication. Memory access instructions mainly include Load (LoaD, LD) instructions and Store (STore, ST) instructions. LD and ST instructions are responsible for transferring data between the GPU's multi-level memory hierarchy. The GPU's memory architecture is similar to that of the CPU, including L1 cache, L2 cache, and Global Memory. The access latency varies significantly between these different levels. When data hits the L1 or L2 cache, the latency is relatively low; however, when accessing Global Memory, it incurs a large delay, thus becoming one of the performance bottlenecks in GPU execution.

[0032] The following is combined Figure 1 This section provides an illustrative description of the GPU hardware architecture based on the Hopper architecture.

[0033] Figure 1 This is a schematic diagram of a Hopper architecture GPU. Please refer to [link / reference]. Figure 1 A GPU consists of multiple task engines (SMs), a shared L2 cache and global video memory, a network of SMs, a task engine, a command buffer, and memory-mapped I / O (MMIO).

[0034] For any given SM, the SM includes an Inst Cache, a Warp Scheduler, a Dispatch Unit, a CUDA Core, a Tensor Core, a Load / Store Unit (LD / ST Unit), a Register File, a Level 1 Cache and Shared Memory (SMEM), a Translation Lookaside Buffer (TLB), and a Tensor Memory Accelerator (TMA).

[0035] The instruction cache is configured to store the instruction stream that will be executed by the Warp. The Warp scheduler is configured to manage and schedule multiple Warps. The dispatch unit is configured to dispatch instructions to be executed to the corresponding execution unit. For example, computational instructions are dispatched to the CUDA core or Tensor core, and memory access instructions are dispatched to the load / store unit. Computational instructions can be floating-point add (FADD) instructions, and memory access instructions can be LD instructions, etc.

[0036] The CUDA core is configured to execute basic integer and single-precision floating-point arithmetic instructions, such as the FADD instruction. The Tensor core is configured to perform specialized matrix multiplication and addition operations, particularly suitable for artificial intelligence tasks. The load / store unit is configured to execute load and store instructions. In response to a load instruction dispatched by the dispatch unit, the load / store unit reads data from the memory hierarchy into the register file; or in response to a store instruction, writes data from the register file back to the memory hierarchy.

[0037] The register file provides exclusive, high-speed storage resources for each thread residing within the SM. Both the compute unit and the load / store unit interact directly with the register file.

[0038] Level 1 cache and shared memory, as a programmable high-speed memory shared by all threads within the SM, are used to implement thread cooperation and data exchange within a thread block. Simultaneously, it serves to cache access to global video memory.

[0039] The second-level cache, shared by all SMs, is used to cache access to global video memory and reduce access latency.

[0040] Global video memory, as the main memory of the GPU, is used to store large-scale working datasets and computation results.

[0041] The TLB is configured to cache the mapping between virtual addresses and physical addresses. When a load / memory unit executes a memory access instruction, it first queries the TLB to quickly obtain the physical address, thereby greatly reducing address translation latency.

[0042] TMA is configured to serve large-scale matrix operations in the Tensor Core. TMA can efficiently manage and aggregate access requests for large blocks of tensor data in global memory. By reducing transaction overhead and cooperating with shared memory to achieve asynchronous data copying, it efficiently transfers data from global memory to shared memory, thereby ensuring that the Tensor Core's computational pipeline can receive a continuous supply of data and avoids stagnation due to data waiting.

[0043] SM-to-SM networks are used to enable direct communication between different SMs.

[0044] The task engine and command buffer are used to manage the computational tasks received by the GPU.

[0045] The task engine comprises a thread generator, a ComputeUnified Device Architecture Application Programming Interface (CUDA API), and control registers. The thread generator generates corresponding thread blocks based on the control register configuration. The CUDA API handles device management, memory allocation, and data transfer. The control registers store kernel execution parameters, including grid dimension, block dimension, kernel entry address, and resource allocation information.

[0046] The CUDA API can initiate computation tasks, which are then compiled by the compiler into a Parallel Thread Execution (PTX) intermediate representation, ultimately generating Streaming Assemblage (SASS) native instructions. These SASS instructions are configured through the task engine's control registers and loaded into the SM's instruction cache, completing the transition from software instructions to hardware execution.

[0047] Figure 1The workflow of the SM (Software Controller) is as follows: Thread blocks are allocated to the SM, and the corresponding threads are generated by the Thread Generator. The Warp scheduler fetches instructions from the instruction cache and issues them through the dispatch unit. For example, the FADD instruction is dispatched to the CUDA core for execution, and the LD instruction is dispatched to the load / store unit for execution. When the load / store unit executes the LD instruction, it first checks the L1 cache and shared memory. If a cache miss occurs, it requests further access to the L2 cache or global memory after address translation via the TLB, ultimately loading the data into the register file. The compute unit retrieves operands from the register file, performs the computation, and writes the result back to the register file. Direct data transfer between the GPU and the host or other GPUs can be achieved through the copy engine and high-speed hub.

[0048] 2. GPU Simulation Technology: As a crucial tool for architecture verification and performance prediction, GPU simulation technology has become a core component in the GPU design, verification, and application optimization process. Through simulation, researchers and engineers can not only evaluate the feasibility, performance bottlenecks, and optimization potential of architecture designs under conditions where the hardware has not yet been actually manufactured or where its internal operation is difficult to observe directly, but also predict GPU performance in architecture simulations, enabling performance evaluation of computing clusters. Currently, GPU simulation can be broadly categorized into two types: functional simulation and behavioral performance simulation.

[0049] 3. Functional-level simulation: Functional-level simulation is mainly used to verify the correctness of GPU hardware logic, ensuring that instruction execution flow, register read / write behavior, and thread scheduling strategies conform to design specifications. This type of simulation is typically used for logic verification and relative performance comparison of GPU functional modules. However, to accurately reflect the device's performance characteristics in a real operating environment, such as latency, bandwidth usage, and resource contention, full-process modeling at clock-level precision is required, along with complex calculations performed based on the clock frequency. While this method offers high precision, it incurs enormous computational overhead, essentially replacing the actual chip with a software implementation running at a very low clock frequency, making it unsuitable for large-scale applications.

[0050] 4. Behavioral Performance Simulation: Behavioral performance simulation introduces quantitative modeling of hardware characteristics such as computing, storage, and interconnect. Unlike functional simulation, which relies on clock precision for cycle-by-cycle simulation, behavioral performance simulation, by abstracting performance models and combining them with specific algorithms or inference logic, can directly calculate and output key indicators such as GPU runtime latency, thereby significantly improving simulation efficiency while maintaining reasonable accuracy. This type of method can provide reliable performance prediction data for applications such as deep learning training, scientific computing simulation, and data analysis, and is particularly suitable for performance potential assessment and bottleneck location in large-scale parallel training / inference systems in scale-up systems.

[0051] Currently, GPU behavioral performance simulation mainly relies on experience and uses fixed delays, resulting in poor simulation accuracy.

[0052] In view of this, the embodiments of this application propose the following concept: the execution instructions corresponding to the target task are allocated to the corresponding processors, and the execution time of the GPU to execute the target task is predicted by combining the execution instructions and the processor's running parameters, thereby achieving the purpose of performing GPU behavioral-level performance simulation and improving the simulation accuracy.

[0053] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] Figure 2 A flowchart illustrating the accelerator card emulation method provided in this application embodiment. Figure 1 The execution subject of this method can be an electronic device or an accelerator card emulation device installed within an electronic device. The accelerator card emulation device can be implemented through software or a combination of hardware and software. The following explanation uses an electronic device as the execution subject. Please refer to... Figure 2 The method may include:

[0055] S201. Obtain multiple execution instructions corresponding to the target task.

[0056] This embodiment provides an accelerator card emulation method, wherein the accelerator card includes multiple processors. For example, the accelerator card can be a GPU or a programmable controller, and the processors can be SMs, etc.

[0057] The target task can be any task that can be performed using an accelerator card. For example, the target task could be rendering a game frame or editing and outputting a video clip.

[0058] The multiple execution instructions corresponding to the target task can be the machine code that the accelerator card needs to execute when performing the target task. The execution instructions can be in SASS format.

[0059] In this embodiment, the electronic device can obtain the code corresponding to the target task and compile the code to obtain multiple execution instructions corresponding to the target task; alternatively, the electronic device can also obtain multiple pre-compiled execution instructions corresponding to the target task from other electronic devices. This embodiment does not limit this.

[0060] S202. Determine the first mapping relationship between multiple execution instructions and multiple thread bundles of the target task.

[0061] The number of thread bundles for the target task can be determined based on the thread bundle size of the accelerator card and the number of threads in the target task. Methods for determining the number of thread bundles for the target task can be found in relevant technical documents and will not be elaborated upon here.

[0062] Thread bundles can also be called warps.

[0063] In this embodiment, the electronic device can divide multiple execution instructions into at least one target instruction set. The execution instructions in the same target instruction set have the same instruction function, and the execution instructions in different target instruction sets have different instruction functions. Among multiple thread bundles, the thread bundle corresponding to the execution instructions in each target instruction set is determined. Based on the thread bundle corresponding to the execution instructions in each target instruction set, a first mapping relationship is determined. The first mapping relationship includes the identifiers of multiple thread bundles, the identifiers of the execution instructions with different instruction functions corresponding to each thread bundle, and the number of execution instructions with each instruction function.

[0064] For any given thread bundle, the thread bundle identifier is used to uniquely identify that thread bundle. For example, the thread bundle identifier can be the name of the thread bundle, or the thread bundle number, etc.

[0065] For any given instruction, an instruction identifier is used to uniquely identify that instruction. For example, the instruction identifier can be the instruction's name or its number.

[0066] For example, the instruction function can be integer arithmetic, floating-point arithmetic, first-level memory access, or global memory access, etc.

[0067] When at least one target instruction set is determined, the electronic device can divide multiple execution instructions into at least one initial instruction set. The execution instructions in the same initial instruction set have the same instruction category, while the execution instructions in different initial instruction sets have different instruction categories, which can be computational, memory access, or control. For any initial instruction set, based on the instruction function, the execution instructions in the initial instruction set are divided into at least one target instruction set. Determining multiple target instruction sets includes: the target instruction set corresponding to each initial instruction set.

[0068] Specifically, multiple execution instructions can first be divided into at least one initial instruction set according to the instruction category. Then, the execution instructions in each initial instruction set can be divided into corresponding target instruction sets according to the instruction function. Finally, it can be determined that at least one target instruction set includes the target instruction set corresponding to each initial instruction set.

[0069] For example, multiple execution instructions can be divided into a set of initial instructions for computation, a set of initial instructions for memory access, and a set of initial instructions for control.

[0070] For example, the initial instruction set for computation can be divided into multiple corresponding target instruction sets. The target instruction sets corresponding to the initial instruction set for computation can include: integer arithmetic target instruction sets, floating-point arithmetic target instruction sets, and special mathematical function target instruction sets, etc.

[0071] For example, the initial set of memory access instructions can be divided into multiple corresponding target instruction sets. The target instruction sets corresponding to the initial set of memory access instructions can be: a first-level memory access target instruction set, a second-level memory access target instruction set, and a global memory access target instruction set, etc.

[0072] For example, the initial instruction set of the control class can be divided into multiple corresponding target instruction sets. The target instruction sets corresponding to the initial instruction set of the control class can be: conditional branch target instruction sets, unconditional jump target instruction sets, and synchronization target instruction sets, etc.

[0073] For ease of understanding, Table 1 is used as an example to illustrate the initial instruction set and the target instruction set.

[0074] Table 1

[0075]

[0076] It should be noted that the initial instruction set and target instruction set shown in Table 1 are merely illustrative examples and do not constitute a limitation on the technical solutions provided in the embodiments of this application. In actual implementation, the number of initial instruction sets may be more or less, and the number of target instruction sets may also be more or less.

[0077] It should be noted that electronic devices can classify multiple execution instructions into at least one target instruction set based on the instruction category and function of each instruction. Alternatively, electronic devices can use a pre-defined classification model to classify multiple execution instructions into at least one target instruction set. Using a pre-defined classification model to classify multiple execution instructions into at least one target instruction set can improve the efficiency of determining the target instruction set, thereby determining the simulation efficiency of the accelerator card. The pre-defined classification model can be a pre-trained model used to determine the target instruction set based on the execution instructions.

[0078] The method for determining the thread bundle corresponding to the instructions to be executed in each target instruction set is the same. In this embodiment, taking any target instruction set as an example, the method for determining the thread bundle corresponding to the instructions to be executed in each target instruction set will be described.

[0079] For any target instruction set, the electronic device can determine the correlation between each execution instruction in the target instruction set and multiple thread bundles through a preset model, thereby obtaining multiple correlations corresponding to each execution instruction in the target instruction set; for any execution instruction in the target instruction set, the thread bundle corresponding to the target correlation is determined as the thread bundle corresponding to the execution instruction, and the target correlation is the maximum value among the multiple correlations corresponding to the execution instruction.

[0080] The preset model can be a pre-trained probabilistic model used to determine the correlation between the executed instructions and the thread bundle.

[0081] Specifically, for any one execution instruction in the target instruction set, the correlation between the execution instruction and each of the multiple thread bundles can be determined through a preset model, resulting in multiple correlations; the maximum target correlation can be determined among the multiple correlations; and the thread bundle corresponding to the target correlation can be determined as the thread bundle corresponding to the execution instruction.

[0082] In this embodiment, a first mapping relationship can be used to indicate multiple thread bundles, the execution instructions for different instruction functions corresponding to each thread bundle, and the number of execution instructions for each instruction function. This embodiment does not limit the specific form of the first mapping relationship, as long as it can indicate the execution instructions for different instruction functions corresponding to each thread bundle and the number of execution instructions for each instruction function. For example, the first mapping relationship can be in key-value pair form or table form, etc.

[0083] For ease of understanding, Table 2 will be used as an example to illustrate the first mapping relationship.

[0084] Table 2

[0085]

[0086] It should be noted that Table 2 is only an illustrative example of the mapping relationship between thread bundles and execution instructions, and does not constitute a limitation on the technical solutions provided in the embodiments of this application. In specific implementation, the first mapping relationship may include more or fewer thread bundle identifiers, and each thread bundle identifier may also correspond to more or fewer execution instruction identifiers.

[0087] S203. Determine a second mapping relationship between multiple thread bundles and multiple processors. The second mapping relationship includes the identifiers of the multiple processors and the identifier of at least one thread bundle corresponding to each processor.

[0088] For any given processor, a processor identifier can be used to uniquely identify that processor. For example, a processor identifier can be a processor number or a processor device identifier.

[0089] For any given thread bundle, the thread bundle identifier can be used to uniquely identify that thread bundle. For example, the thread bundle identifier can be the thread bundle number, etc.

[0090] In this embodiment, the electronic device can determine a second mapping relationship between multiple thread bundles and multiple processors based on the number of processors and the allocation strategy in the accelerator card.

[0091] This embodiment does not limit the allocation strategy; it can be set according to actual needs during implementation. For example, the allocation strategy can be a load balancing strategy, which aims to maintain a balanced load across processors as much as possible. Another example is a user-configured static strategy to meet specific simulation needs.

[0092] It should be noted that in practice, some large matrix multiplication operations require multiple thread bundles to be executed collaboratively across processors. In this embodiment, the large matrix can be first split according to the processor's computing power and equivalently performed on multiple thread bundles. Each execution instruction can be limited to a single processor, thereby facilitating simulation calculations.

[0093] This embodiment does not limit the specific form of the second mapping relationship, as long as it can indicate multiple processors and the thread bundles corresponding to each processor. For example, the second mapping relationship can be in the form of key-value pairs or tables, etc.

[0094] For ease of understanding, Table 3 will be used as an example to illustrate the second mapping relationship.

[0095] Table 3

[0096]

[0097] As shown in Table 3, the second mapping relationship indicates that the thread bundle corresponding to processor A may include thread bundle a, thread bundle b, and thread bundle e, while the thread bundle corresponding to processor B may include thread bundle c and thread bundle d.

[0098] S204. Based on the first mapping relationship, the second mapping relationship, and the operating parameters of multiple processors, determine the predicted duration for the accelerator card to execute the target task.

[0099] The predicted execution time of the target task by the accelerator card can also be called the predicted latency of the target task by the accelerator card.

[0100] In this embodiment, the electronic device can determine the correspondence between multiple processors and multiple execution instructions based on the first mapping relationship and the second mapping relationship; for any processor, the execution duration corresponding to the processor is determined based on the processor's operating parameters and the execution instructions corresponding to the processor; the predicted duration for the accelerator card to execute the target task is determined to be the sum of the execution durations corresponding to multiple processors.

[0101] Specifically, the execution instructions corresponding to each processor can be determined based on the first and second mapping relationships. For any given processor, the execution time of the corresponding execution instructions can be determined. Furthermore, the predicted execution time of the target task by the accelerator card can be determined as the sum of the execution times of multiple processors.

[0102] In this embodiment, after determining the first mapping relationship between the execution instruction and the thread bundle, the execution instruction corresponding to the processor is determined based on the first mapping relationship and the second mapping relationship between the thread bundle and the processor. This can make the correspondence between the execution instruction and the processor more accurate.

[0103] The accelerator card simulation method provided in this embodiment can acquire multiple execution instructions corresponding to a target task; determine a first mapping relationship between the multiple execution instructions and multiple thread bundles of the target task; determine a second mapping relationship between the multiple thread bundles and multiple processors, the second mapping relationship including the identifiers of the multiple processors and the identifier of at least one thread bundle corresponding to each processor; and determine the predicted execution time of the target task by the accelerator card based on the first mapping relationship, the second mapping relationship, and the operating parameters of the multiple processors. Through the above method, the purpose of behavioral-level performance simulation of the accelerator card can be achieved, and the simulation accuracy can be improved.

[0104] Based on the above embodiments, the method for determining the execution time corresponding to each processor is the same. Below, in conjunction with... Figure 3 Taking any processor in the accelerator card as an example, this paper explains the method for determining the execution time of the processor.

[0105] Figure 3A flowchart illustrating the accelerator card emulation method provided in this application embodiment. Figure 2 The execution subject of this method can be an electronic device or an accelerator card emulation device installed within an electronic device. The accelerator card emulation device can be implemented through software or a combination of hardware and software. The following explanation uses an electronic device as the execution subject. Please refer to... Figure 3 The method may include:

[0106] S301. According to the preset processing granularity, the execution instructions corresponding to the processor are divided into at least one processing unit.

[0107] The processing unit includes at least one execution instruction.

[0108] The default processing granularity can be at the thread bundle level or the instruction execution level. For example, the default processing granularity can be a single thread bundle or a default number of execution instructions.

[0109] It should be noted that the maximum preset processing granularity in this embodiment is a single thread bundle. To further improve simulation accuracy, the preset processing granularity can be reduced, and the entire execution flow can be divided into shorter processing units. For example, the preset processing granularity can be set to a preset number of execution instructions, where the preset number is less than the number of execution instructions in a single thread bundle.

[0110] S302. For any processing unit, determine the execution time of the processing unit based on the execution instructions included in the processing unit and the operating parameters of the processor.

[0111] It should be noted that the method for determining the execution time of each processing unit is the same. This embodiment takes any one processing unit as an example to illustrate the method for determining the execution time of the processing unit.

[0112] In this embodiment, the electronic device can determine the computation time of the processing unit based on the processor's operating parameters and the computational execution instructions included in the processing unit; determine the memory access time of the processing unit based on the processor's operating parameters and the memory access execution instructions included in the processing unit; and determine the larger value of the computation time and the memory access time as the execution time of the processing unit; wherein, the execution instructions included in the processing unit include: computational execution instructions included in the processing unit and memory access execution instructions included in the processing unit.

[0113] Specifically, the computation time of computation-type instructions and the memory access time of memory access instructions in the processing unit can be determined, and the larger value of the computation time and the memory access time can be determined as the execution time of the processing unit.

[0114] It should be noted that accelerator computation and memory access are inherently parallel. To model this parallelism, this embodiment uses the larger of the computation time and memory access time for any processing unit, rather than their sum. This reflects the partial overlap between computation and memory access. Furthermore, by pre-setting the processing granularity, the error in the execution time of the determined computation unit in this embodiment will be smaller.

[0115] It should be noted that in this embodiment, the processor's operating parameters are considered when determining the execution duration of the processing unit. This allows for different simulations to be performed for different accelerator cards, resulting in high simulation adaptability.

[0116] S303. Determine that the execution time corresponding to the processor is the sum of the execution times of each processing unit corresponding to the processor.

[0117] In this embodiment, after determining the execution time of each processing unit, the execution time corresponding to the processor can be updated until the execution time of all processing units corresponding to the processor is determined.

[0118] The accelerator card simulation method provided in this embodiment can divide the execution instructions corresponding to the processor into at least one processing unit according to a preset processing granularity. For any processing unit, the execution time of the processing unit can be determined based on the execution instructions included in the processing unit and the processor's operating parameters. The execution time corresponding to the processor can be determined as the sum of the execution times of all processing units corresponding to the processor. Through the above method, the purpose of determining the execution time corresponding to the processor can be achieved.

[0119] Based on any of the above embodiments, the method for determining the computation time of each processing unit is the same. The following is in conjunction with... Figure 4 Taking any processing unit as an example, the method for determining the execution time of a processing unit will be explained.

[0120] Figure 4 A flowchart illustrating the accelerator card emulation method provided in this application embodiment. Figure 3 The execution subject of this method can be an electronic device or an accelerator card emulation device installed within an electronic device. The accelerator card emulation device can be implemented through software or a combination of hardware and software. The following explanation uses an electronic device as the execution subject. Please refer to... Figure 4 The method may include:

[0121] S401. For any computation-type execution instruction included in the processing unit, determine the computation time of the computation-type execution instruction based on the computation data corresponding to the computation-type execution instruction and the processor's operating parameters.

[0122] In this embodiment, the electronic device can divide the computational data corresponding to the computational execution instructions into multiple data blocks according to the maximum data input volume supported by the processor; determine the computation time of a single data block according to the number of processor cores and the computation time required for each core to perform a computation; and determine the computation time of the computational execution instructions according to the computation time of a single data block. The processor's operating parameters include: the maximum data input volume supported by the processor, the number of processor cores, and the computation time required for each core to perform a computation.

[0123] Specifically, the computation data corresponding to computation-type execution instructions can be divided into multiple data blocks, and the size of the data block can be the maximum amount of data input supported by the processor; the computation time of a single data block can be determined; and the computation time of the computation-type execution instructions can be determined based on the number of multiple data blocks and the computation time of a single data block.

[0124] The maximum amount of data input supported by the processor, as well as the number of computing cores of the processor, can be determined based on the specific accelerator card.

[0125] The processor's computing cores can be either CUDA cores or Tensor cores.

[0126] The computation time required for a processor's core to perform a single calculation can be obtained in advance through benchmarking, which will not be elaborated here. For example, benchmarking can include fine-grained benchmarking of accelerator cards.

[0127] Assume the computation data corresponding to the computational execution instructions includes a first matrix and a second matrix, where the first matrix has a dimension of . The dimension of the second matrix is Then multiple data blocks satisfy the following formula:

[0128]

[0129] in, Let M, K, and N be the total number of data blocks, where M, K, and N are all integers greater than or equal to 1. The instruction-level operation dimension of the processor. This indicates the rounding up operation.

[0130] The computation time for a single data block satisfies the following formula:

[0131]

[0132] in, The computation time for a single data block. The instruction-level operation dimension of the processor. This is the minimum computational dimension of the processor. The number of computing cores in the processor. The time required for computation of the core execution unit.

[0133] The computation time of computation-based execution instructions satisfies the following formula:

[0134]

[0135] in, The computation time for the execution instructions of the computation class. The total number of multiple data blocks. The computation time for a single data block. This is the utilization rate coefficient.

[0136] S402. The computation time of the processing unit is determined to be the sum of the computation times of the execution instructions of each computation class included in the processing unit.

[0137] In this embodiment, the computation time of each computation class execution instruction in the processing unit can be determined by the method in S401, and the sum of the computation times of each computation class execution instruction in the processing unit can be determined as the computation time of the processing unit.

[0138] The accelerator card emulation method provided in this embodiment can determine the computation time of any computation-type execution instruction included in the processing unit based on the computation data corresponding to the computation-type execution instruction and the processor's operating parameters. It can also determine that the computation time of the processing unit is the sum of the computation times of all computation-type execution instructions included in the processing unit. Through this method, the purpose of determining the computation time of the processing unit can be achieved.

[0139] Based on any of the above embodiments, the method for determining the memory access time of each processing unit is the same. The following is in conjunction with... Figure 5 Taking any processing unit as an example, the method for determining the memory access time of the processing unit is explained.

[0140] Figure 5 A flowchart illustrating the accelerator card emulation method provided in this application embodiment. Figure 4 The execution subject of this method can be an electronic device or an accelerator card emulation device installed within an electronic device. The accelerator card emulation device can be implemented through software or a combination of hardware and software. The following explanation uses an electronic device as the execution subject. Please refer to... Figure 5 The method may include:

[0141] S501. For any memory access instruction included in the processing unit, determine the memory access duration of the memory access instruction based on the memory access address corresponding to the memory access instruction and the processor's operating parameters.

[0142] In this embodiment, the electronic device can determine the storage location corresponding to the memory access instruction based on the memory access address corresponding to the memory access instruction. The storage location is a level 1 cache, a level 2 cache, or global memory. The read / write duration corresponding to the storage location is determined as the memory access duration of the memory access instruction. The processor's operating parameters include the read / write duration corresponding to the level 1 cache, the read / write duration corresponding to the level 2 cache, and the read / write duration corresponding to the global memory.

[0143] The read / write times for the L1 cache, L2 cache, and global memory can be obtained in advance through benchmarking, which will not be elaborated here. For example, a benchmark could be a parallel pointer chasing (P-chase) memory access benchmark.

[0144] For example, if the storage location corresponding to a memory access instruction is a level 1 cache, then the memory access duration of the memory access instruction can be the read / write duration corresponding to the level 1 cache.

[0145] For example, if the storage location corresponding to a memory access instruction is a level 2 cache, then the memory access time of the memory access instruction can be the read / write time corresponding to the level 2 cache.

[0146] For example, if the memory access instruction corresponds to the global memory, then the memory access time of the memory access instruction can be the read / write time corresponding to the global memory.

[0147] Specifically, the memory access time of memory access instructions satisfies the following formula:

[0148]

[0149] in, This represents the memory access duration of the i-th memory access instruction in the processing unit. This refers to the read / write time corresponding to the first-level cache. This refers to the read / write time corresponding to the second-level cache. This refers to the read / write time corresponding to the global memory. , This indicates an address alignment operation. This is the memory address corresponding to the i-th memory access instruction in the processing unit. This refers to the cache range of the L1 cache corresponding to the i-th memory access instruction in the processing unit. This refers to the cache range of the L2 cache corresponding to the i-th memory access instruction in the processing unit. This refers to the storage area of ​​the global memory.

[0150] In this embodiment, if the storage location is a level 2 cache, the cache range of the level 1 cache is updated; if the storage location is a global memory, the cache range of the level 1 cache and the cache range of the level 2 cache are updated.

[0151] Specifically, updating the cache range of the first-level cache includes: updating the cache range of the first-level cache to: the starting position is the starting position of the memory access address and the range length is the preset first-level range length; updating the cache range of the second-level cache includes: updating the cache range of the second-level cache to: the starting position is the starting position of the memory access address and the range length is the preset second-level range length.

[0152] S502. The memory access time of the processing unit is determined to be the sum of the memory access times of all memory access instruction types included in the processing unit.

[0153] In this embodiment, the memory access duration of each memory access type execution instruction in the processing unit can be determined by the method in S501, and the sum of the memory access durations of each memory access type execution instruction in the processing unit can be determined as the memory access duration of the processing unit.

[0154] The accelerator card emulation method provided in this embodiment can determine the memory access duration of any memory access instruction included in the processing unit based on the memory access address corresponding to the memory access instruction and the processor's operating parameters. The memory access duration of the processing unit can be determined as the sum of the memory access durations of all memory access instructions included in the processing unit. Through this method, the purpose of determining the memory access duration of the processing unit can be achieved.

[0155] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0156] Figure 6 This is a schematic diagram of an accelerator card emulation device provided in an embodiment of this application. The accelerator card includes multiple processors, and the accelerator card emulation device 10 includes an acquisition module 11 and a determination module 12, wherein:

[0157] The acquisition module 11 is used to acquire multiple execution instructions corresponding to the target task;

[0158] The determining module 12 is used to determine a first mapping relationship between multiple execution instructions and multiple thread bundles of the target task;

[0159] The determining module 12 is further configured to determine a second mapping relationship between multiple thread bundles and multiple processors, the second mapping relationship including the identifiers of the multiple processors and the identifier of at least one thread bundle corresponding to each processor;

[0160] The determining module 12 is also used to determine the predicted duration of the accelerator card executing the target task based on the first mapping relationship, the second mapping relationship, and the operating parameters of multiple processors.

[0161] The accelerator card simulation device provided in this embodiment can execute the accelerator card simulation method in any of the above method embodiments. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0162] In one possible implementation, the determining module 12 is specifically used for:

[0163] Multiple execution instructions are divided into at least one target instruction set. Execution instructions in the same target instruction set have the same instruction function, while execution instructions in different target instruction sets have different instruction functions.

[0164] Among multiple thread bundles, determine the thread bundle corresponding to the instruction to be executed in each target instruction set;

[0165] Based on the thread bundles corresponding to the execution instructions in each target instruction set, a first mapping relationship is determined. The first mapping relationship includes the identifiers of multiple thread bundles, the identifiers of the execution instructions for different instruction functions corresponding to each thread bundle, and the number of execution instructions for each instruction function.

[0166] In one possible implementation, the determining module 12 is specifically used for:

[0167] Multiple execution instructions are divided into at least one initial instruction set. Execution instructions in the same initial instruction set have the same instruction category, while execution instructions in different initial instruction sets have different instruction categories, which can be computational, memory access, or control.

[0168] For any initial instruction set, based on the instruction function, the execution instructions in the initial instruction set are divided into corresponding target instruction sets;

[0169] Determining at least one target instruction set includes: the target instruction set corresponding to each initial instruction set.

[0170] In one possible implementation, for any set of target instructions, the determining module 12 is specifically used for:

[0171] By using a pre-defined model, the correlation between each execution instruction in the target instruction set and multiple thread bundles is determined, thereby obtaining multiple correlations corresponding to each execution instruction in the target instruction set.

[0172] For any execution instruction in the target instruction set, the thread bundle corresponding to the target relevance is determined as the thread bundle corresponding to the execution instruction, and the target relevance is the maximum value among multiple relevance values ​​corresponding to the execution instruction.

[0173] In one possible implementation, the determining module 12 is specifically used for:

[0174] Based on the first mapping relationship and the second mapping relationship, determine the correspondence between multiple processors and multiple execution instructions;

[0175] For any given processor, the execution time is determined based on the processor's operating parameters and the corresponding execution instructions.

[0176] The predicted execution time of the target task by the accelerator card is determined to be the sum of the execution times of the multiple processors.

[0177] In one possible implementation, the determining module 12 is specifically used for:

[0178] According to the preset processing granularity, the execution instructions corresponding to the processor are divided into at least one processing unit, and the processing unit includes at least one execution instruction;

[0179] For any given processing unit, the execution time of the processing unit is determined based on the execution instructions included in the processing unit and the processor's operating parameters.

[0180] The execution time corresponding to the processor is determined to be the sum of the execution times of each processing unit corresponding to the processor.

[0181] In one possible implementation, the determining module 12 is specifically used for:

[0182] The computation time of a processing unit is determined based on the processor's operating parameters and the computational instructions executed by the processing unit.

[0183] The memory access duration of the processing unit is determined based on the processor's operating parameters and the memory access type of instructions executed by the processing unit.

[0184] The larger of the computation time and memory access time is determined as the execution time of the processing unit;

[0185] The processing unit includes execution instructions such as computational execution instructions and memory access execution instructions.

[0186] In one possible implementation, the determining module 12 is specifically used for:

[0187] For any computation-type execution instruction included in the processing unit, the computation time of the computation-type execution instruction is determined based on the computation data corresponding to the computation-type execution instruction and the processor's operating parameters;

[0188] The computation time of a processing unit is determined to be the sum of the computation times of all computational instructions executed by the processing unit.

[0189] In one possible implementation, the determining module 12 is specifically used for:

[0190] Based on the maximum amount of data input supported by the processor, the computation data corresponding to the computational execution instructions is divided into multiple data blocks;

[0191] The computation time for a single data block is determined based on the number of processor cores and the time required for each core to perform a computation.

[0192] The computation time of computation-type execution instructions is determined based on the computation time of a single data block.

[0193] The processor's operating parameters include: the maximum amount of data input supported by the processor, the number of processor cores, and the time required for each processor core to perform a computation.

[0194] In one possible implementation, the computation data corresponding to the computation class execution instructions includes a first matrix and a second matrix, where the first matrix has a dimension of . The dimension of the second matrix is Multiple data blocks satisfy:

[0195]

[0196] in, Let M, K, and N be the total number of data blocks, where M, K, and N are all integers greater than or equal to 1. The instruction-level operation dimension of the processor. This indicates the rounding up operation.

[0197] In one possible implementation, the computation time for a single data block satisfies:

[0198]

[0199] in, The computation time for a single data block. The instruction-level operation dimension of the processor. This is the minimum computational dimension of the processor. The number of computing cores in the processor. The time required for computation of the core execution unit.

[0200] In one possible implementation, the computation time of the computation class's execution instructions satisfies:

[0201]

[0202] in, The computation time for the execution instructions of the computation class. The total number of multiple data blocks. The computation time for a single data block. This is the utilization rate coefficient.

[0203] In one possible implementation, the determining module 12 is specifically used for:

[0204] For any memory access instruction included in the processing unit, the memory access duration of the memory access instruction is determined based on the memory access address corresponding to the memory access instruction and the processor's operating parameters.

[0205] The memory access time of the processing unit is determined to be the sum of the memory access times of all memory access instruction types executed within the processing unit.

[0206] In one possible implementation, the determining module 12 is specifically used for:

[0207] Based on the memory access address corresponding to the memory access instruction, determine the storage location corresponding to the memory access instruction. The storage location can be the L1 cache, L2 cache, or global memory.

[0208] The read / write duration corresponding to the storage location is determined as the memory access duration of the memory access instruction.

[0209] The processor's operating parameters include: read / write time for L1 cache, read / write time for L2 cache, and read / write time for global memory.

[0210] In one possible implementation, the memory access time of memory access instruction execution satisfies:

[0211]

[0212] in, This represents the memory access duration of the i-th memory access instruction in the processing unit. This refers to the read / write time corresponding to the first-level cache. This refers to the read / write time corresponding to the second-level cache. This refers to the read / write time corresponding to the global memory. , This indicates an address alignment operation. This is the memory address corresponding to the i-th memory access instruction in the processing unit. This refers to the cache range of the L1 cache corresponding to the i-th memory access instruction in the processing unit. This refers to the cache range of the L2 cache corresponding to the i-th memory access instruction in the processing unit. This refers to the storage area of ​​the global memory.

[0213] Figure 7 This is a schematic diagram of another accelerator card simulation device provided in an embodiment of this application. Figure 6 Based on this, the accelerator card emulation device 10 also includes an update module 13, wherein:

[0214] If the storage location is a second-level cache, the update module 13 is used to update the cache range of the first-level cache;

[0215] If the storage location is global memory, the update module 13 is used to update the cache range of the first-level cache and the cache range of the second-level cache.

[0216] In one possible implementation, update module 13 is specifically used for:

[0217] Update the L1 cache range to: the starting position is the starting position of the memory access address, and the range length is the preset L1 range length.

[0218] In one possible implementation, update module 13 is specifically used for:

[0219] Update the L2 cache range to: start position is the start position of the memory access address, range length is the preset L2 range length.

[0220] The accelerator card simulation device provided in this embodiment can execute the accelerator card simulation method in any of the above method embodiments. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0221] Figure 8 A schematic diagram of the structure of the electronic device provided in this application. Figure 8 As shown, the electronic device 50 provided in this embodiment includes at least one processor 501 and a memory 502. Optionally, the electronic device 50 further includes a communication component 503. The processor 501, memory 502, and communication component 503 are connected via a bus.

[0222] In the specific implementation process, at least one processor 501 executes computer execution instructions stored in memory 502, causing at least one processor 501 to execute the above-described accelerator card emulation method embodiment.

[0223] The specific implementation process of processor 501 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0224] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0225] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0226] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0227] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the accelerator card emulation method at runtime.

[0228] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0229] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the accelerator card emulation method.

[0230] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described accelerator card emulation method embodiments.

[0231] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0232] The above provides a detailed description of the accelerator card emulation method, apparatus, device, storage medium, and program product provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An acceleration card emulation method, characterized by, The accelerator card includes a plurality of processors, and the method includes: obtaining a plurality of execution instructions corresponding to a target task; determining a first mapping relationship between the plurality of execution instructions and a plurality of thread bundles of the target task; determining a second mapping relationship between the plurality of thread bundles and the plurality of processors, the second mapping relationship including identifiers of the plurality of processors and identifiers of at least one thread bundle corresponding to each processor identifier; determining a predicted duration for the accelerator card to execute the target task according to the first mapping relationship, the second mapping relationship, and running parameters of the plurality of processors; The determination of the first mapping relationship between the plurality of execution instructions and the plurality of thread bundles of the target task includes: dividing the plurality of execution instructions into at least one target instruction set, the execution instructions in the same target instruction set having the same instruction function, and the execution instructions in different target instruction sets having different instruction functions; determining, among the plurality of thread bundles, a thread bundle corresponding to the execution instructions in each target instruction set; determining the first mapping relationship according to the thread bundle corresponding to the execution instructions in each target instruction set, the first mapping relationship including identifiers of the plurality of thread bundles, identifiers of the execution instructions of different instruction functions corresponding to each thread bundle, and the number of execution instructions of each instruction function; The division of the plurality of execution instructions into at least one target instruction set includes: dividing the plurality of execution instructions into at least one initial instruction set, the execution instructions in the same initial instruction set having the same instruction category, and the execution instructions in different initial instruction sets having different instruction categories, the instruction category being a calculation category, a memory access category, or a control category; for any initial instruction set, dividing the execution instructions in the initial instruction set into a corresponding target instruction set based on instruction function; The determination of the at least one target instruction set includes the target instruction set corresponding to each initial instruction set.

2. The method of claim 1, wherein, For any target instruction set, determining, among the plurality of thread bundles, a thread bundle corresponding to the execution instructions in the target instruction set includes: determining, by a preset model, a relevance of each execution instruction in the target instruction set to the plurality of thread bundles, to obtain a plurality of relevances corresponding to each execution instruction in the target instruction set; for any execution instruction of the target instruction set, determining a thread bundle corresponding to a target relevance as the thread bundle corresponding to the execution instruction, the target relevance being the maximum value in the plurality of relevances corresponding to the execution instruction.

3. The method of claim 1, wherein, The determination of the predicted duration for the accelerator card to execute the target task according to the first mapping relationship, the second mapping relationship, and the running parameters of the plurality of processors includes: determining a correspondence between the plurality of processors and the plurality of execution instructions according to the first mapping relationship and the second mapping relationship; for any processor, determining an execution duration corresponding to the processor according to the running parameters of the processor and the execution instructions corresponding to the processor; determining the predicted duration for the accelerator card to execute the target task as the sum of the execution durations corresponding to the plurality of processors.

4. The method of claim 3, wherein, The execution duration of the processor is determined according to the running parameters of the processor and the execution instructions corresponding to the processor, and the execution duration of the processor comprises: The execution instructions corresponding to the processor are divided into at least one processing unit according to a preset processing granularity, and the processing unit comprises at least one execution instruction; The execution duration of the processing unit is determined according to the execution instructions included in the processing unit and the running parameters of the processor; The execution duration of the processor is determined as the sum of the execution durations of each processing unit corresponding to the processor.

5. The method of claim 4, wherein, The execution duration of the processing unit is determined according to the execution instructions included in the processing unit and the running parameters of the processor, and the execution duration of the processing unit comprises: The calculation duration of the processing unit is determined according to the running parameters of the processor and the calculation-type execution instructions included in the processing unit; The memory access duration of the processing unit is determined according to the running parameters of the processor and the memory access-type execution instructions included in the processing unit; If the calculation duration is greater than the memory access duration, the calculation duration is determined as the execution duration of the processing unit; If the memory access duration is greater than the calculation duration, the memory access duration is determined as the execution duration of the processing unit; The execution instructions included in the processing unit comprise the calculation-type execution instructions included in the processing unit and the memory access-type execution instructions included in the processing unit.

6. The method of claim 5, wherein, The calculation duration of the processing unit is determined according to the running parameters of the processor and the calculation-type execution instructions included in the processing unit, and the calculation duration of the calculation-type execution instruction comprises: The calculation duration of the calculation-type execution instruction is determined according to the calculation data corresponding to the calculation-type execution instruction and the running parameters of the processor; The calculation duration of the processing unit is determined as the sum of the calculation durations of each calculation-type execution instruction included in the processing unit.

7. The method of claim 6, wherein, The calculation duration of the calculation-type execution instruction is determined according to the running parameters of the processor and the calculation data corresponding to the calculation-type execution instruction, and the calculation duration of the calculation-type execution instruction comprises: The calculation data corresponding to the calculation-type execution instruction is divided into a plurality of data blocks according to the maximum data input supported by the processor; The calculation duration of a single data block is determined according to the number of calculation cores of the processor and the duration required for a calculation unit of the calculation core to perform a calculation; The calculation duration of the calculation-type execution instruction is determined according to the calculation duration of the single data block; The running parameters of the processor comprise the maximum data input supported by the processor, the number of calculation cores of the processor, and the duration required for a calculation unit of the calculation core to perform a calculation.

8. The method of claim 7, wherein, The computing class execution instruction corresponds to computing data including a first matrix and a second matrix, the first matrix has a dimension of , the second matrix has a dimension of , and the plurality of data blocks satisfy: Wherein the is the total number of the plurality of data blocks, M, K and N are all integers greater than or equal to 1, is the instruction level operation dimension of the processor, represents a rounding up operation.

9. The method of claim 7, wherein, The calculation duration of the single data block satisfies: Wherein the is a calculation duration of the single data block, is an instruction level operation dimension of the processor, is a minimum operation dimension of the processor, is a number of calculation cores of the processor, is a duration required for the calculation core execution unit calculation.

10. The method of claim 7, wherein, The calculation duration of the calculation-type execution instruction satisfies: Wherein, the is the computing duration of executing instructions for the computing class, the is the total number of the plurality of data blocks, the is the computing duration of the single data block, the is the utilization coefficient.

11. The method of claim 5, wherein, The memory access duration of the processing unit is determined according to the running parameters of the processor and the memory access-type execution instructions included in the processing unit, and the memory access duration of the memory access-type execution instruction comprises: According to the memory address corresponding to the memory type execution instruction and the running parameter of the processor, the memory time length of the memory type execution instruction is determined. The memory time length of the processing unit is determined as the sum of the memory time lengths of each memory type execution instruction included in the processing unit.

12. The method of claim 11, wherein, According to the memory address corresponding to the memory type execution instruction and the running parameter of the processor, the memory time length of the memory type execution instruction is determined. According to the memory address corresponding to the memory type execution instruction, the storage location corresponding to the memory type execution instruction is determined, and the storage location is a level one cache, a level two cache, or a global memory. The read-write time length corresponding to the storage location is determined as the memory time length of the memory type execution instruction. The running parameter of the processor includes the read-write time length corresponding to the level one cache, the read-write time length corresponding to the level two cache, and the read-write time length corresponding to the global memory.

13. The method of claim 12, wherein, The memory time length of the memory type execution instruction satisfies: wherein, is a memory access duration of an i-th memory access type instruction in the processing unit, is a read-write duration corresponding to the level one cache, is a read-write duration corresponding to the level two cache, is a read-write duration corresponding to the global memory, , represents an address alignment operation, is a memory access address corresponding to the i-th memory access type instruction in the processing unit, is a cache interval of the level one cache corresponding to the i-th memory access type instruction in the processing unit, is a cache interval of the level two cache corresponding to the i-th memory access type instruction in the processing unit, is a storage interval of the global memory.

14. The method according to claim 12 or 13, characterized in that, The method further includes: If the storage location is the level two cache, the cache interval of the level one cache is updated. If the storage location is the global memory, the cache interval of the level one cache and the cache interval of the level two cache are updated.

15. The method of claim 14, wherein, The cache interval of the level one cache is updated by: The cache interval of the level one cache is updated to an interval with a starting position being the starting position of the memory address and an interval length being a preset level one interval length. The cache interval of the level two cache is updated by: The cache interval of the level two cache is updated to an interval with a starting position being the starting position of the memory address and an interval length being a preset level two interval length.

16. An acceleration card emulation apparatus, comprising: The accelerator card includes a plurality of processors, and the device includes an acquisition module and a determination module, wherein: The acquisition module is configured to acquire a plurality of execution instructions corresponding to a target task. The determination module is configured to determine a first mapping relationship between the plurality of execution instructions and a plurality of thread bundles of the target task. The determination module is further configured to determine a second mapping relationship between the plurality of thread bundles and the plurality of processors, the second mapping relationship including an identifier of the plurality of processors and an identifier of at least one thread bundle corresponding to each processor. The determination module is further configured to determine a predicted time length for the accelerator card to execute the target task according to the first mapping relationship, the second mapping relationship, and a running parameter of the plurality of processors. The determination module is specifically configured to divide the plurality of execution instructions into at least one target instruction set, execution instructions in a same target instruction set having a same instruction function, and execution instructions in different target instruction sets having different instruction functions. In the plurality of thread bundles, a thread bundle corresponding to an execution instruction in each target instruction set is determined. The first mapping relationship is determined according to thread bundles corresponding to execution instructions in each target instruction set, and the first mapping relationship includes identifiers of the plurality of thread bundles, identifiers of execution instructions of different instruction functions corresponding to each thread bundle, and numbers of execution instructions of each instruction function; The determining module is specifically configured to divide the plurality of execution instructions into at least one initial instruction set, execution instructions in a same initial instruction set have a same instruction category, execution instructions in different initial instruction sets have different instruction categories, the instruction category is a calculation category, a memory access category, or a control category, for any initial instruction set, the execution instructions in the initial instruction set are divided into corresponding target instruction sets based on instruction functions, and the at least one target instruction set includes target instruction sets corresponding to each initial instruction set.

17. An electronic device, comprising: Comprise: a memory for storing a computer program; a processor for implementing the method in any one of claims 1 to 15 when executing the computer program.

18. A computer-readable storage medium, characterized in that, The computer program is stored in the computer readable storage medium, and when the computer program is executed by the processor, the method in any one of claims 1 to 15 is implemented.

19. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the method in any one of claims 1 to 15. The computer program is executed by the processor to implement the method in any one of claims 1 to 15.

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