Analog signal selector and channel configuration method thereof, and safety protection circuit

Abstract

The application relates to the technical field of integrated circuits, and discloses an analog signal selector, a channel configuration method thereof and a safety protection circuit, which are applied to the analog signal selector. The analog signal selector comprises N analog transmission gates, and the safety protection circuit comprises N protection units. Each protection unit corresponds to one analog transmission gate. Each protection unit comprises: a logic detection module, an input end of the logic detection module being coupled to N-1 enable signals except for the enable signal corresponding to the protection unit; a delay module, an input end of the delay module being coupled to an output end of the logic detection module, the delay module being configured to delay the rising edge of the input signal and keeping transparent to the falling edge; and a logic output module, a first input end of the logic output module being coupled to the enable signal corresponding to the protection unit, a second input end of the logic output module being coupled to an output end of the delay module, and an output end of the logic output module outputting a safety enable signal to the corresponding analog transmission gate.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a safety protection circuit, an analog signal selector channel configuration method, an analog signal selector, and a microcontroller chip. Background Technology

[0002] In general-purpose microcontroller units (MCUs), the analog multiplexer (AMUX) is a very important circuit module. It is often used for input channel selection in on-chip analog-to-digital converters (ADCs) and comparators (CMPs), as well as for switching test channels in on-chip test circuits.

[0003] When performing this multiple input signal selection function, the analog signal selector can only allow one input to be selected at a time to achieve the input analog signal selection function; alternatively, all transmission gates can be disabled to achieve the function of shutting off the input and output. If multiple transmission gates are enabled at the same time, the output will be driven by multiple input analog signal sources simultaneously. Its level value will be affected by factors such as the voltage and output impedance of the multiple input analog signal sources, deviating from the expected value and becoming difficult to control. Moreover, since analog signals are bidirectional signals, the multiple input analog signal sources that are turned on will pull and interfere with each other through the transmission gates, thereby disrupting the working state of the circuits that generate each input analog signal source. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. Therefore, the first objective of this invention is to propose a safety protection circuit that supports channel configuration and fast switching, eliminates the sensitivity of analog signal selectors to software misconfiguration, avoids the serious consequences of simultaneous conduction of transmission gates of multiple analog signal selectors, eliminates race conditions during channel switching of analog signal selectors, prevents mutual interference between multiple input analog signal sources during channel switching from endangering system security, improves the channel switching efficiency of analog signal selectors, and reduces the resource consumption of the kernel and bus.

[0005] The second objective of this invention is to provide a method for configuring analog signal selector channels.

[0006] The third objective of this invention is to provide an analog signal selector.

[0007] The fourth objective of this invention is to provide a microcontroller chip.

[0008] To achieve the above objectives, a first aspect of the present invention provides a safety protection circuit applied to an analog signal selector. The analog signal selector includes N analog transmission gates, which are controlled by N corresponding enable signals. The safety protection circuit includes N protection units, each corresponding to one analog transmission gate. Each protection unit includes: a logic detection module, the input of which is coupled to N-1 other enable signals besides its own enable signal, for detecting whether the other N-1 enable signals include a valid signal; a delay module, the input of which is coupled to the output of the logic detection module, configured to delay the rising edge of its input signal and remain transparent to the falling edge; and a logic output module, the first input of which is coupled to its own enable signal, the second input of which is coupled to the output of the delay module, and the output of which outputs a safety enable signal to the corresponding analog transmission gate.

[0009] In addition, the safety protection circuit according to the above embodiments of the present invention may also have the following additional technical features:

[0010] According to some embodiments of the present invention, the logic detection module is an N-1 input NOR gate.

[0011] According to some embodiments of the present invention, the logic output module is an AND gate.

[0012] According to some embodiments of the present invention, the delay time of the delay module is not less than the duration during which the two analog transmission gates are simultaneously turned on when the analog signal selector performs channel switching.

[0013] According to some embodiments of the present invention, the analog signal selector includes N channels, each channel corresponding to an enable signal.

[0014] According to an embodiment of the present invention, a safety protection circuit is applied to an analog signal selector. The analog signal selector includes N analog transmission gates, which are controlled by N corresponding enable signals. The safety protection circuit includes N protection units, each corresponding to one analog transmission gate. Each protection unit includes: a logic detection module, the input of which is coupled to N-1 other enable signals besides its own enable signal, for detecting whether the other N-1 enable signals include a valid signal; a delay module, the input of which is coupled to the output of the logic detection module, configured to delay the rising edge of its input signal and remain transparent to the falling edge; and a logic output module, the first input of which is coupled to its own enable signal, the second input of which is coupled to the output of the delay module, and the output of which outputs a safety enable signal to the corresponding analog transmission gate. Therefore, this circuit can support channel configuration and fast switching, eliminate the sensitivity of analog signal selectors to software misconfiguration, avoid the serious consequences of multiple analog signal selector transmission gates being turned on simultaneously, eliminate the race conditions during channel switching of analog signal selectors, avoid mutual interference between multiple input analog signal sources during channel switching that could endanger system security, improve the channel switching efficiency of analog signal selectors, and reduce the resource consumption of the core and bus.

[0015] The second objective of this invention is to propose an analog signal selector channel configuration method that supports channel configuration and fast switching, eliminates the sensitivity of analog signal selectors to software misconfiguration, avoids the serious consequences of multiple analog signal selector transmission gates being simultaneously turned on, eliminates race conditions during channel switching of analog signal selectors, prevents mutual interference between multiple input analog signal sources during channel switching from endangering system security, improves the channel switching efficiency of analog signal selectors, and reduces the resource consumption of the kernel and bus.

[0016] To achieve the above objectives, a second aspect of the present invention provides an analog signal selector channel configuration method applied to the aforementioned security protection circuit. The method includes: receiving N enable signals generated by a selection decoding logic circuit; for the i-th channel, monitoring the status of the other N-1 enable signals besides the i-th enable signal; when the other N-1 enable signals do not include a valid signal, generating a high-level signal; performing rising edge delay processing on the high-level signal to obtain a delayed high-level signal; performing a logical AND operation between the i-th enable signal and the delayed high-level signal to generate the i-th valid security enable signal to control the opening of the i-th analog transmission gate.

[0017] In addition, the analog signal selector channel configuration method according to the above embodiments of the present invention may also have the following additional technical features:

[0018] According to some embodiments of the present invention, the above-described analog signal selector channel configuration method further includes: immediately turning off the analog transmission gate corresponding to the j-th channel in response to switching from the j-th channel to the k-th channel; and turning on the analog transmission gate corresponding to the k-th channel after a preset delay time.

[0019] According to some embodiments of the present invention, the above-described analog signal selector channel configuration method further includes: when two or more valid signals are detected among the N enable signals, the security enable signal is switched from valid to invalid, thereby shutting down all analog transmission gates.

[0020] An analog signal selector channel configuration method according to an embodiment of the present invention includes: receiving N enable signals generated based on a selection decoding logic circuit; for the i-th channel, monitoring the status of the other N-1 enable signals besides the i-th enable signal; when the other N-1 enable signals do not include a valid signal, generating a high-level signal; performing rising edge delay processing on the high-level signal to obtain a delayed high-level signal; performing a logical AND operation between the i-th enable signal and the delayed high-level signal to generate the i-th valid security enable signal to control the opening of the i-th analog transmission gate. Therefore, this method can support channel configuration and fast switching functions, eliminate the sensitivity of the analog signal selector to software misconfiguration, avoid the serious consequences of multiple analog signal selector transmission gates being simultaneously turned on, eliminate race conditions during channel switching of the analog signal selector, prevent mutual interference between multiple input analog signal sources during channel switching from endangering system security, improve the channel switching efficiency of the analog signal selector, and reduce the resource consumption of the kernel and bus.

[0021] To achieve the above objectives, a third aspect of the present invention provides an analog signal selector, comprising N analog transmission gates and a selection decoding logic circuit. The selection decoding logic circuit generates N enable signals according to the configuration of the channel selection register. The present invention also includes the aforementioned security protection circuit. The input terminal of the security protection circuit is coupled to the N enable signals output by the selection decoding logic circuit, and the N security enable signals output by the output terminal of the security protection circuit control the on and off states of the N analog transmission gates, respectively.

[0022] The analog signal selector according to embodiments of the present invention can support channel configuration and fast switching functions, eliminate the sensitivity of the analog signal selector to software misconfiguration, avoid the serious consequences caused by the simultaneous conduction of transmission gates of multiple analog signal selectors, eliminate the race conditions during channel switching of the analog signal selector, avoid mutual interference between multiple input analog signal sources during channel switching that could endanger system security, improve the channel switching efficiency of the analog signal selector, and reduce the resource consumption of the kernel and bus.

[0023] To achieve the above objectives, a fourth aspect of the present invention provides a microcontroller chip that integrates the aforementioned analog signal selector.

[0024] The microcontroller chip according to embodiments of the present invention can support channel configuration and fast switching functions, eliminate the sensitivity of analog signal selectors to software misconfiguration, avoid the serious consequences caused by the simultaneous conduction of transmission gates of multiple analog signal selectors, eliminate the competition hazards in the channel switching process of analog signal selectors, avoid mutual interference between multiple input analog signal sources during channel switching that could endanger system security, improve the channel switching efficiency of analog signal selectors, and reduce the resource consumption of the core and bus.

[0025] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0026] Figure 1 This is a block diagram of a safety protection circuit in the related art according to some embodiments of the present invention;

[0027] Figure 2 This is a schematic diagram of the channel switching timing of an analog signal selector in the related art according to some embodiments of the present invention;

[0028] Figure 3 A block diagram of a safety protection circuit according to some embodiments of the present invention;

[0029] Figure 4 This is a flowchart of an analog signal selector channel configuration method according to some embodiments of the present invention;

[0030] Figure 5 This is a schematic diagram of the channel switching timing of an analog signal selector according to some embodiments of the present invention;

[0031] Figure 6 This is a block diagram of a microcontroller chip according to some embodiments of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0033] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this invention should have the ordinary meaning understood by those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] As mentioned in the background section, analog signal selectors are crucial circuit modules in general-purpose microcontrollers, commonly used for input channel selection in on-chip analog-to-digital converters and comparators, and for switching test channels in on-chip test circuits. (Reference) Figure 1 The diagram below is a block illustration of a safety protection circuit in the related art according to some embodiments of the present invention. The analog signal selector consists of N analog transmission gates, each processing one of the N analog signals from analog signal 1 to analog signal N. Each of the N analog transmission gates is controlled by a corresponding enable signal, and the specific enable status is configured by the analog signal selector channel selection register. After configuring the analog signal selector channel selection register, by selecting the decoding logic circuit (which can also be transparent logic), one of the N transmission gates can be enabled, allowing that analog signal to pass through that gate and form an output analog signal N+1, which is then transmitted to the next stage circuit.

[0035] When performing this multiple input signal selection function, the analog signal selector can only allow one input to be selected at a time to achieve the input analog signal selection function; alternatively, all transmission gates can be disabled to achieve the function of shutting off the input and output. If multiple transmission gates are enabled at the same time, the output will be driven by multiple input analog signal sources simultaneously. Its level value will be affected by factors such as the voltage and output impedance of the multiple input analog signal sources, deviating from the expected value and becoming difficult to control. Moreover, since analog signals are bidirectional signals, the multiple input analog signal sources that are turned on will pull and interfere with each other through the transmission gates, thereby disrupting the working state of the circuits that generate each input analog signal source.

[0036] In implementing this invention, the applicant discovered that, as mentioned above, analog signal selector channel selection and switching are performed by configuring the analog signal selector channel selection register. For a common 32-bit MCU, the core executes a single program instruction to configure the analog signal selector channel selection register and simultaneously set the state of each of the N (N less than or equal to 32) analog transmission gates. However, configuring the analog signal selector channel selection register often faces some security risks. On the one hand, in order to complete the relevant application functions, the analog signal selector channel selection register often needs to be configured repeatedly in the user program. This makes the analog signal selector channel selection register prone to misconfiguration, which in turn causes multiple analog transmission gates in the analog signal selector to be turned on at the same time. This will cause the analog output of the analog signal selector to deviate from the expected value, and the multiple connected analog input signals will pull and interfere with each other, destroy their respective circuit states, and even cause the system to be locked in the reset state, making it impossible to further correct the configuration of the analog signal selector channel selection register. On the other hand, even if there is no misconfiguration, and each configuration only enables one channel, for example, switching from a single analog channel 1 to a single analog channel 2, during the switching process, due to non-ideal factors such as the non-strict flipping of each bit signal output by the analog signal selector channel selection register, the non-strict flipping of each enable signal output by the selection decoding logic circuit, the unequal path transmission time required for each enable signal to reach the corresponding analog transmission gate, and the need for a certain turn-off time for the analog transmission gate to turn off, it is still unavoidable that there will be a short period of time when analog transmission gate 1 and analog transmission gate 2 are turned on at the same time.

[0037] refer to Figure 2 This is a schematic diagram of the channel switching timing of an analog signal selector in the related art according to some embodiments of the present invention. During this period, a race condition is formed, and input analog signal 1 and input analog signal 2 will still strongly interfere with each other in a pull-to-pull manner. In actual MCU circuits, some of the N input analog signals of the analog signal selector often come from sensitive circuits such as on-chip reference sources, voltage detection sampling points, and critical internal circuit test points. Even a brief interference can often lead to serious consequences such as system clock lockout and system cold reset. Even after the interference ends, because the normal working state of the circuits that generate input analog signal 1 and input analog signal 2 has been disrupted, it may be difficult to restore them to their normal levels.

[0038] To mitigate the aforementioned risks associated with analog signal selector channel configuration and switching, common methods include: firstly, optimizing user programs to reduce the probability of misconfigured channel selection registers, although this cannot completely eliminate misconfiguration; secondly, using software methods to stagger the conduction configuration time of the two channels. Taking switching from analog channel 1 to analog channel 2 as an example, staggering the configuration time of the two channels requires: the MCU kernel executing the first program instruction to configure the analog signal selector channel selection register and disable analog transmission gate 1; then executing the second program instruction to reconfigure the analog signal selector channel selection register and enable analog transmission gate 2. Considering that each kernel instruction fetch, execution, and bus transmission requires several clock cycles, this method significantly reduces the efficiency of analog signal selector channel switching, thus severely impacting the working efficiency of analog-to-digital converters, comparators, and test circuits using analog signal selector circuits, and consuming more kernel and bus resources.

[0039] The following description, with reference to the accompanying drawings, describes the safety protection circuit, analog signal selector channel configuration method, analog signal selector, and microcontroller chip proposed in the embodiments of the present invention.

[0040] refer to Figure 3 This is a block diagram of a safety protection circuit according to some embodiments of the present invention.

[0041] The safety protection circuit of this invention is applied to analog signal selectors, analog signal selector channel selection registers, and system buses.

[0042] Furthermore, the system bus is a set of common communication paths connecting the major components inside a computer system (such as the central processing unit, memory, and input / output device interfaces). The system bus is a transmission medium made of wires used to transmit data, addresses, and control signals between components.

[0043] Furthermore, the analog signal selector includes N analog transmission gates, each processing one of the N analog signals from analog signal 1 to analog signal N. These N analog transmission gates are controlled by corresponding N enable signals, and the specific enabling configuration is determined by the analog signal selector channel selection register. After configuring the analog signal selector channel selection register, by selecting the decoding logic circuit (which can also be transparent logic), one of the N analog transmission gates can be enabled, allowing that analog signal to pass through that gate and form an output analog signal N+1, which is then passed to the next stage circuit.

[0044] Specifically, the analog signal selector includes N channels, each channel corresponding to an enable signal.

[0045] Furthermore, the safety protection circuit includes N protection units, each of which corresponds to an analog transmission gate. Alternatively, protection unit 1 corresponds to analog transmission gate 1, and protection unit 2 corresponds to analog transmission gate 2.

[0046] Specifically, each protection unit includes a logic detection module, a delay module, and a logic output module. That is, the safety protection circuit consists of N logic detection modules, N delay modules, and N logic output modules.

[0047] Specifically, the logic detection module is an N-1 input NOR gate. The input terminal of the logic detection module is connected to the output enable signal of the selection decoding logic circuit. The input terminal of the logic detection module is coupled to N-1 other enable signals besides its own corresponding enable signal. The logic detection module can detect whether the other N-1 enable signals include a valid signal. For example, the N-1 input terminals of the logic detection module 3 are respectively connected to enable signal 1, enable signal 2, enable signal 4, ..., enable signal N-1, and enable signal N.

[0048] Specifically, the delay module is a rising edge delay unit, which is a unit that provides delay. The input of the delay module is coupled to the output of the logic detection module. The delay module can delay the rising edge of its input signal and remain transparent to the falling edge. The delay time provided by the rising edge is used to cover the duration during which the two analog transmission gates are simultaneously turned on in the timing sequence when the analog signal selector is switching channels.

[0049] Specifically, the logic output module is an AND gate. The first input of the logic output module is coupled to its corresponding enable signal, and the second input is coupled to the output of the delay module. The output of the logic output module outputs a safety enable signal to the corresponding analog transmission gate, forming an output analog signal N+1 that is then passed to the next stage circuit. The safety enable signal output by the logic output module can directly control the analog transmission gate within the analog signal selector. For example, the two inputs of logic output module N are connected to the output enable signal N of the selection decoding logic circuit and the output of delay module N, respectively. The output of logic output module N is a safety enable signal, connected to the enable terminal of analog transmission gate N within the analog signal selector.

[0050] In summary, the safety protection circuit according to embodiments of the present invention is applied to an analog signal selector. The analog signal selector includes N analog transmission gates, which are controlled by corresponding N enable signals. The safety protection circuit includes N protection units, each corresponding to one analog transmission gate. Each protection unit includes: a logic detection module, the input of which is coupled to N-1 other enable signals besides its own enable signal, for detecting whether the other N-1 enable signals include a valid signal; a delay module, the input of which is coupled to the output of the logic detection module, configured to delay the rising edge of its input signal and remain transparent to the falling edge; and a logic output module, the first input of which is coupled to its own enable signal, the second input of which is coupled to the output of the delay module, and the output of which outputs a safety enable signal to the corresponding analog transmission gate. Therefore, this circuit can support channel configuration and fast switching, eliminate the sensitivity of analog signal selectors to software misconfiguration, avoid the serious consequences of multiple analog signal selector transmission gates being turned on simultaneously, eliminate the race conditions during channel switching of analog signal selectors, avoid mutual interference between multiple input analog signal sources during channel switching that could endanger system security, improve the channel switching efficiency of analog signal selectors, and reduce the resource consumption of the core and bus.

[0051] like Figure 4 As shown, the analog signal selector channel configuration method of this embodiment of the invention may include the following steps:

[0052] S401 receives N enable signals generated based on the selection decoding logic circuit.

[0053] Specifically, the configuration is performed by the analog signal selector channel selection register. After the analog signal selector channel selection register is configured, the configuration information is sent to the selection decoding logic circuit (which can also be transparent logic). The selection decoding logic circuit generates N enable signals and sends the N enable signals to the safety protection circuit. The safety protection circuit receives the N enable signals generated by the selection decoding logic circuit. Specifically, each of the N protection units receives the corresponding N enable signals generated by the selection decoding logic circuit.

[0054] S402, for the i-th channel, monitor the status of the other N-1 enable signals besides the i-th enable signal.

[0055] For example, when switching from analog channel 1 to analog channel 2, for the second channel, monitor the status of the other N-1 enable signals besides the second enable signal. That is, monitor the status of enable signal 1, enable signal 3, enable signal 4, ..., enable signal N-1, and enable signal N.

[0056] S403 generates a high-level signal when the other N-1 enable signals do not include a valid signal.

[0057] For example, when enable signals 1, 3, 4, ..., N-1, and enable signal N does not contain a valid signal, a high-level signal is generated, enabling the logic detection module. The logic detection module then outputs a high-level signal and sends it to the delay module. When enable signals 1, 3, 4, ..., N-1, and enable signal N contains a valid signal, a low-level signal is generated, disabling the logic detection module.

[0058] S404 performs rising edge delay processing on the high-level signal to obtain a delayed high-level signal.

[0059] For example, when the delay module receives a high-level signal from the logic detection module, the delay module performs rising edge delay processing on the high-level signal so that the delay module delays the rising edge of its input signal to obtain a delayed high-level signal.

[0060] S405 performs a logical AND operation between the i-th enable signal and the delayed high-level signal to generate the i-th valid security enable signal, thereby controlling the opening of the i-th analog transmission gate.

[0061] For example, the second enable signal is logically ANDed with the delayed high-level signal to generate a high-level signal, which enables the logic output module. The logic output module then generates a second valid safety enable signal to control the opening of the second analog transmission gate.

[0062] Here, a valid signal can refer to a signal with a level value of "1", excluding signals with a level value of "0". For example, when you want to control the analog transmission gate 2 to open, enable signal 2 generates a signal with a level value of "1". When the level values ​​of enable signals 1, 3, 4, ..., N-1, and N are all "0", a signal with a level value of "1" will be generated. At this time, NOR gate 2 is turned on, and NOR gate 2 also outputs a signal with a level value of "1" to rising edge delay unit 2. Rising edge delay unit 2 performs rising edge delay processing on the signal with a level value of "1", and obtains a delayed signal with a level value of "1". At this time, the signal with a level value of "1" generated by enable signal 2 and the delayed signal with a level value of "1" will combine to generate a signal with a level value of "1", which will turn on AND gate 2. AND gate 2 outputs a safety enable signal 2 with a level value of "1", so that the analog transmission gate 2 is turned on.

[0063] For example, taking the control of opening the third analog transmission gate as an example, a high-level signal is generated for the third enable signal. The states of enable signals 1, 2, 4, ..., N-1, and N are monitored. When none of the enable signals 1, 2, 4, ..., N-1, and N contain a valid signal, a high-level signal is generated, enabling the logic detection module. The logic detection module outputs a high-level signal and sends it to the delay module. The delay module receives the high-level signal from the logic detection module and performs rising edge delay processing on the high-level signal to obtain a delayed high-level signal. The third enable signal and the delayed high-level signal are then logically ANDed to generate a high-level signal, enabling the logic output module. The logic output module generates a third valid safety enable signal to control the opening of the third analog transmission gate, allowing analog signal 3 to pass through analog transmission gate 3 and output a signal to the next stage circuit.

[0064] Therefore, with the help of this circuit, the present invention can, on the one hand, eliminate the various uncertainties caused by misconfiguration of the analog signal selector channel selection register, and on the other hand, when switching analog signal selector channels, only one program instruction needs to be executed by the kernel to configure N (N is less than or equal to the kernel bit width) analog transmission gates to complete the safe switching between any two of them, avoiding the race conditions that exist during the channel switching process.

[0065] In some embodiments of the present invention, the above-described analog signal selector channel configuration method further includes: in response to switching from channel j to channel k, immediately turning off the analog transmission gate corresponding to channel j; and after a preset delay time, turning on the analog transmission gate corresponding to channel k.

[0066] Specifically, in the initial state, the analog signal selector channel selection register defaults to disabling the analog signal selector. In the initial state, when the analog signal selector channel selection register is correctly configured to enable a specific analog transmission gate, that gate immediately conducts, completing the channel selection function. When configuring the analog signal selector channel selection register to switch between any two channels, for example, refer to... Figure 5 This is a schematic diagram of the analog signal selector channel switching timing according to some embodiments of the present invention. Switching from channel 1 to channel 2 only requires configuring the analog signal selector channel selection register once. The analog transmission gate corresponding to channel 1 will immediately turn off. After the circuit waits for the safety delay time provided by the delay module 2, it automatically enables analog transmission gate 2, thus avoiding race conditions. When configuring the analog signal selector channel selection register to turn off any currently enabled channel N, analog transmission gate N immediately turns off.

[0067] In some embodiments of the present invention, the above-described analog signal selector channel configuration method further includes: when two or more valid signals are detected among the N enable signals, the security enable signal is switched from valid to invalid, thereby shutting down all analog transmission gates.

[0068] Specifically, when two or more valid signals are detected among the N enable signals, that is, when a misconfiguration of the analog signal selector channel selection register causes multiple analog transmission gates in the analog signal selector to be set to the on state, the safety protection circuit will immediately identify the misconfiguration, change the safety enable signal from valid to invalid, shut down all analog transmission gates, and restore the analog signal selector circuit to its initial state.

[0069] Therefore, this invention solves the problems of analog signal selector channel selection registers being easily misconfigured, resulting in multiple analog transmission gates being enabled simultaneously, causing mutual interference between multiple input analog signal sources, and the output analog signal deviating from the expected value, affecting chip functionality and security; and the existence of race conditions during analog signal selector channel switching, which can easily lead to mutual interference between multiple input analog signal sources, affecting chip functionality and security. Common techniques use software methods to stagger the conduction configuration time of consecutive channels, which reduces circuit efficiency and consumes more kernel and bus resources. This circuit supports channel configuration and fast switching, eliminates the sensitivity of analog signal selectors to software misconfiguration, avoids the serious consequences of multiple analog signal selector transmission gates being simultaneously activated, eliminates race conditions during analog signal selector channel switching, and prevents mutual interference between multiple input analog signal sources during channel switching from endangering system security. Furthermore, channel switching only requires the kernel to configure the AMUX channel selection register once, improving the channel switching efficiency of analog signal selectors, reducing kernel and bus resource consumption, and can be automatically implemented in hardware after the function is enabled, without excessive software intervention.

[0070] In summary, the analog signal selector channel configuration method according to embodiments of the present invention includes: receiving N enable signals generated based on a selection decoding logic circuit; for the i-th channel, monitoring the status of the other N-1 enable signals besides the i-th enable signal; when the other N-1 enable signals do not include a valid signal, generating a high-level signal; performing rising edge delay processing on the high-level signal to obtain a delayed high-level signal; performing a logical AND operation between the i-th enable signal and the delayed high-level signal to generate the i-th valid security enable signal to control the opening of the i-th analog transmission gate. Therefore, this method can support channel configuration and fast switching functions, eliminate the sensitivity of the analog signal selector to software misconfiguration, avoid the serious consequences of multiple analog signal selector transmission gates being simultaneously turned on, eliminate race conditions during channel switching of the analog signal selector, prevent mutual interference between multiple input analog signal sources during channel switching from endangering system security, improve the channel switching efficiency of the analog signal selector, and reduce the resource consumption of the kernel and bus.

[0071] It should be noted that the above description describes some embodiments of the present invention. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than that shown in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0072] Corresponding to the above embodiments, the present invention also proposes an analog signal selector, including N analog transmission gates and a selection decoding logic circuit. The selection decoding logic circuit is used to generate N enable signals according to the configuration of the channel selection register, and also includes the aforementioned security protection circuit. The input terminal of the security protection circuit is coupled to the N enable signals output by the selection decoding logic circuit, and the N security enable signals output by the output terminal of the security protection circuit control the on and off of the N analog transmission gates respectively.

[0073] The analog signal selector according to embodiments of the present invention can support channel configuration and fast switching functions, eliminate the sensitivity of the analog signal selector to software misconfiguration, avoid the serious consequences caused by the simultaneous conduction of transmission gates of multiple analog signal selectors, eliminate the race conditions during channel switching of the analog signal selector, avoid mutual interference between multiple input analog signal sources during channel switching that could endanger system security, improve the channel switching efficiency of the analog signal selector, and reduce the resource consumption of the kernel and bus.

[0074] To achieve the above objectives, a microcontroller chip is proposed in a fourth aspect of the present invention.

[0075] like Figure 6 As shown, the microcontroller chip 600 of the present invention integrates the above-mentioned analog signal selector.

[0076] The microcontroller chip according to embodiments of the present invention can support channel configuration and fast switching functions, eliminate the sensitivity of analog signal selectors to software misconfiguration, avoid the serious consequences caused by the simultaneous conduction of transmission gates of multiple analog signal selectors, eliminate the competition hazards in the channel switching process of analog signal selectors, avoid mutual interference between multiple input analog signal sources during channel switching that could endanger system security, improve the channel switching efficiency of analog signal selectors, and reduce the resource consumption of the core and bus.

[0077] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Rather, the steps depicted in the flowchart may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0078] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this invention should have the ordinary meaning understood by those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0079] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A safety protection circuit applied to an analog signal selector, the analog signal selector comprising N analog transmission gates, the N analog transmission gates being controlled by corresponding N enable signals, characterized in that, The security protection circuit includes N protection units, each protection unit corresponding to one analog transmission gate, and each protection unit includes: A logic detection module, wherein the input terminal of the logic detection module is coupled to N-1 other enable signals besides its own corresponding enable signal, and is used to detect whether the other N-1 enable signals include a valid signal; The delay module, whose input is coupled to the output of the logic detection module, is configured to delay the rising edge of its input signal and remain transparent to the falling edge. Specifically, when the output signal of the logic detection module changes from low to high, it outputs a high level after a preset delay; when the output signal of the logic detection module changes from high to low, it immediately outputs a low level. The logic output module has a first input terminal coupled to its corresponding enable signal, a second input terminal coupled to the output terminal of the delay module, and an output terminal of the logic output module outputting a safety enable signal to the corresponding analog transmission gate.

2. The safety protection circuit according to claim 1, characterized in that, The logic detection module is an N-1 input NOR gate.

3. The safety protection circuit according to claim 1, characterized in that, The logic output module is an AND gate.

4. The safety protection circuit according to claim 1, characterized in that, The delay time of the delay module is not less than the duration during which the two analog transmission gates are simultaneously turned on when the analog signal selector performs channel switching.

5. The safety protection circuit according to claim 1, characterized in that, The analog signal selector includes N channels, each channel corresponding to an enable signal.

6. A method for configuring analog signal selector channels, characterized in that, The method, applied to the safety protection circuit as described in any one of claims 1-5, comprises: Receive N enable signals generated based on the selection decoding logic circuit; For the i-th channel, monitor the status of the other N-1 enable signals besides the i-th enable signal; When none of the other N-1 enable signals are valid, and the i-th enable signal is valid, a high-level signal is generated; The high-level signal is subjected to rising edge delay processing to obtain a delayed high-level signal, including: when the output signal of the logic detection module changes from low level to high level, a high level is output after a preset time; when the output signal of the logic detection module changes from high level to low level, a low level is output immediately. The i-th enable signal and the delayed high-level signal are logically ANDed to generate the i-th valid security enable signal, which controls the opening of the i-th analog transmission gate.

7. The analog signal selector channel configuration method according to claim 6, characterized in that, The method further includes: In response to switching from channel j to channel k, the analog transmission gate corresponding to channel j is immediately turned off; After a preset delay time, the analog transmission gate corresponding to the k-th channel is activated.

8. The analog signal selector channel configuration method according to claim 6, characterized in that, When two or more valid signals are detected among the N enable signals, the security enable signal remains invalid or becomes invalid, thereby shutting down all the analog transmission gates.

9. An analog signal selector, comprising N analog transmission gates and a selection decoding logic circuit, wherein the selection decoding logic circuit is used to generate N enable signals according to the configuration of a channel selection register, characterized in that, It also includes the safety protection circuit as described in any one of claims 1 to 4; The input terminal of the security protection circuit is coupled to the N enable signals output by the selection decoding logic circuit, and the N security enable signals output by the output terminal of the security protection circuit control the conduction and deactivation of the N analog transmission gates respectively.

10. A microcontroller chip, characterized in that, It integrates the analog signal selector as described in claim 9.

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