A low-latency inter-CPU communication hardware implementation method and device

Abstract

The application discloses a low-delay CPU intercommunication hardware implementation method and device, and relates to the technical field of computers. The method comprises the following steps: receiving initialization configuration information from a sending CPU, wherein the initialization configuration information comprises a starting address and a space size of a memory of the sending CPU, and a starting address and a space size of a memory of a receiving CPU; monitoring a sending tail pointer updated by the sending CPU, and determining whether to read to-be-sent data from the memory of the sending CPU to an internal cache of a hardware communication module based on the initialization configuration information, the sending tail pointer and a sending head pointer maintained by the hardware communication module; monitoring a receiving head pointer updated by the receiving CPU, and determining whether to write to-be-written data in the internal cache to the memory of the receiving CPU based on the initialization configuration information, the receiving head pointer and a receiving tail pointer maintained by the hardware communication module; and the hardware communication module adopts a direct memory access mode to transmit data between the memory of the sending CPU and the memory of the receiving CPU.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a low-latency inter-CPU communication hardware implementation method and device. BACKGROUND

[0002] In multi-core processors and heterogeneous computing systems, efficient data communication between CPU cores is a key factor to improve the overall performance of the system.

[0003] Currently, the mainstream inter-CPU communication methods include shared memory, serial port, DMA and Ethernet, but in the scenarios of low latency and low CPU occupation, these methods all have inherent defects. Specifically, the shared memory method can avoid the overhead of the network protocol stack, but it usually relies on CPU participation in data copying, thereby increasing the delay. More importantly, the synchronization operation in the communication process still needs the frequent intervention of the CPU, and in the scenario of frequent communication of short messages, the synchronization overhead may even exceed the data handling itself, becoming the main source of delay and CPU resource consumption. The serial port transmission method has the advantages of low cost, low power consumption and relative simplicity, but its bandwidth is low and it is difficult to carry large data streams. The DMA transmission method can realize data handling without CPU, but it is usually designed for general purposes, and the programming and configuration overhead is large, and it is not suitable for frequently initiated and small data volume communication tasks. In addition, the general DMA usually does not directly maintain the buffer state of the communication parties, and needs to rely on the CPU to manage the initiation and completion of data transmission through interrupts or polling, introducing delay and CPU occupation problems. The Ethernet transmission method is more suitable for cross-device or more complex systems, but it is not suitable for different CPUs within the same system, because its complexity and cost are relatively high. SUMMARY

[0004] In view of the high latency, high CPU occupation, difficulty in carrying large data streams, and high complexity and cost of the prior art, the present application provides a low-latency inter-CPU communication hardware implementation method and device. The method introduces an independent hardware communication module to build a direct data path between the sending CPU and the receiving CPU. Based on the double-pointer cooperative monitoring data transmission mechanism, zero-copy communication is realized without CPU participation in specific data transmission and synchronization operation.

[0005] The present application achieves the above-mentioned purposes through the following technical solutions:

[0006] A low-latency inter-CPU communication hardware implementation method, comprising:

[0007] receiving initialization configuration information from the sending CPU; the initialization configuration information includes the starting address and space size of the sending CPU memory , and the starting address and space size of the receiving CPU memory ;

[0008] Monitoring the sending tail pointer updated by the sending CPU , and determining whether to read the data to be sent from the sending CPU memory to the internal cache of the hardware communication module based on the initialization configuration information, the sending tail pointer and the sending head pointer maintained by the hardware communication module .

[0009] Monitoring the receiving head pointer updated by the receiving CPU , and determining whether to write the data to be written in the internal cache of the hardware communication module to the receiving CPU memory based on the initialization configuration information, the receiving head pointer and the receiving tail pointer maintained by the hardware communication module .

[0010] The hardware communication module is arranged between the sending CPU and the receiving CPU and is configured to transmit data between the sending CPU memory and the receiving CPU memory in a direct memory access mode.

[0011] As a preferred scheme of the present application, the determination of whether to read the data to be sent from the sending CPU memory to the internal cache of the hardware communication module comprises:

[0012] Comparing the sending tail pointer with the sending head pointer .

[0013] When the sending tail pointer is not equal to the sending head pointer , it is determined that there is data to be sent.

[0014] When it is determined that there is data to be sent, the amount of data to be sent is calculated according to the sending tail pointer and the sending head pointer , and it is judged whether there is enough available space in the internal cache of the hardware communication module to accommodate the data to be sent.

[0015] When there is enough available space in the internal cache of the hardware communication module, the data to be sent is read from the sending CPU memory to the internal cache of the hardware communication module based on the amount of data to be sent and the starting address of the sending CPU memory, and the sending head pointer is updated.

[0016] As a preferred scheme of the present application, the calculation of the amount of data to be sent comprises:

[0017] When the sending tail pointer is greater than the sending head pointer , the amount of data to be sent is for:

[0018] ;

[0019] When sending the tail pointer Less than the send header pointer At that time, the amount of data to be sent for:

[0020] .

[0021] As a preferred embodiment of the present invention, determining whether there is sufficient available space in the internal buffer of the hardware communication module to accommodate the data to be sent includes:

[0022] Obtain the total capacity A of the internal buffer of the hardware communication module;

[0023] Get the cumulative amount of data B = CD that has been read from the sending CPU memory into the internal cache of the hardware communication module but has not yet been written to the receiving CPU memory; where C is the total amount of data that has been read from the sending CPU memory into the internal cache of the hardware communication module obtained by the read counter maintained by the hardware communication module, and D is the total amount of data that has been written to the receiving CPU memory obtained by the write counter maintained by the hardware communication module.

[0024] Calculate the current available space E=AB, and compare the current available space E with the amount of data to be read. ;

[0025] If the current available space E is greater than or equal to the amount of data to be read If so, it is determined that there is enough available space in the internal buffer of the hardware communication module to accommodate the data to be sent.

[0026] As a preferred embodiment of the present invention, determining whether to write the data to be written in the internal cache of the hardware communication module to the receiving CPU memory includes:

[0027] Compare receive head pointer With the tail pointer ;

[0028] When the receiver head pointer With the tail pointer If they are not equal, it is determined that there is space to be written;

[0029] When it is determined that there is space to be written, based on the receive head pointer With the tail pointer Calculate the amount of space to be written. ;

[0030] Based on the amount of space to be written The system reads the starting address of the receiving CPU memory, writes the data to be written from the internal cache of the hardware communication module into the receiving CPU memory, and updates the receiving tail pointer. .

[0031] As a preferred embodiment of the present invention, the calculation of the amount of space to be written is described. include:

[0032] When the receiver head pointer Less than the tail pointer At that time, the amount of space to be written for:

[0033] ;

[0034] When the receiver head pointer Greater than the tail pointer At that time, the amount of space to be written for:

[0035] ;

[0036] The amount of space to be written The starting address of the receiving CPU memory is used to write the data to be written from the internal cache of the hardware communication module to the receiving CPU memory, including:

[0037] Get the cumulative amount of data B = CD that has been read from the sending CPU memory into the internal cache of the hardware communication module but has not yet been written to the receiving CPU memory; where C is the total amount of data that has been read from the sending CPU memory into the internal cache of the hardware communication module obtained by the read counter maintained by the hardware communication module, and D is the total amount of data that has been written to the receiving CPU memory obtained by the write counter maintained by the hardware communication module.

[0038] Determine the actual amount of data to be written. ;

[0039] Based on the actual amount of data to be written The starting address of the receiving CPU memory is used to write the data to be written from the internal cache of the hardware communication module to the receiving CPU memory.

[0040] As a preferred embodiment of the present invention, the monitoring of the transmit tail pointer updated by the transmit CPU is described. and the monitoring of the receiver head pointer updated by the receiving CPU. This can be achieved in the following ways:

[0041] Monitor the write operations of the corresponding preset pointer registers in the hardware communication module.

[0042] As a preferred embodiment of the present invention, the bandwidth and timing configuration of the bus between the hardware communication module and the CPU are dynamically adjusted according to the data transmission requirements determined by the amount of data to be sent and the amount of space to be written.

[0043] A hardware implementation device for low-latency inter-CPU communication, comprising:

[0044] A configuration receiving unit is configured to receive initialization configuration information from the sending CPU; the initialization configuration information includes the starting address and size of the sending CPU's memory. And the starting address and size of the CPU memory to be received. ;

[0045] The data processing unit is used to monitor the transmit tail pointer updated by the transmit CPU. And based on the initialization configuration information, send the tail pointer and the send head pointer maintained by the hardware communication module Determine whether to read the data to be sent from the sending CPU memory into the internal cache of the hardware communication module;

[0046] The receiving data processing unit is used to monitor the receive head pointer updated by the receiving CPU. Based on the initialization configuration information and the received header pointer and the receive tail pointer maintained by the hardware communication module Determine whether to write the data to be written from the internal cache of the hardware communication module to the receiving CPU memory;

[0047] The hardware communication module is located between the sending CPU and the receiving CPU and is configured to transmit data between the sending CPU memory and the receiving CPU memory via direct memory access.

[0048] As a preferred embodiment of the present invention, it further includes:

[0049] The bus control unit is used to dynamically adjust the bandwidth and timing configuration of the bus between the device and the CPU based on the data transmission requirements determined by the amount of data to be sent and the amount of space to be written.

[0050] The beneficial effects of this invention are as follows: By introducing a hardware communication module and adopting a data transmission mechanism based on direct memory access, a direct path is established between the sending CPU and the receiving CPU memory, completely bypassing the traditional software protocol stack. Simultaneously, this module can actively monitor the pointer state updated by the CPU, and immediately initiate transmission once the data is ready, effectively eliminating random delays caused by operating system scheduling and software processing, achieving highly deterministic, extremely low end-to-end latency. Based on the initialized memory address information, this module can directly read data from the sending memory, temporarily cache it internally, and then directly write it to the receiving memory, establishing the shortest data transmission path between the application layer and the communication layer, completely avoiding the data copy overhead between kernel mode and user mode, achieving true zero-copy communication. This module can autonomously determine whether to read or write data based on the pointer state. Under this mechanism, the CPU only needs to update the head and tail pointers when the data is ready or processing is complete, while the specific data handling, buffer management, and transmission synchronization are all autonomously completed by the hardware communication module, reducing the occupation of CPU computing resources. The entire communication process is completed independently by the hardware communication module, and its behavior is not affected by operating system scheduling, interrupt load, or other software tasks. This pure hardware implementation ensures excellent timing determinism and operational reliability in the communication process, providing performance advantages that software solutions cannot match for application scenarios with high real-time requirements. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0052] Figure 1 A schematic diagram of a system architecture for inter-CPU data transmission based on a hardware communication module provided by the present invention;

[0053] Figure 2 A flowchart illustrating a hardware implementation method for low-latency inter-CPU communication provided by the present invention;

[0054] Figure 3 This is a flowchart provided in an embodiment of the present invention for determining whether to read data to be sent from the sending CPU memory to the internal cache of the hardware communication module;

[0055] Figure 4 This is a flowchart provided in an embodiment of the present invention for determining whether to write the data to be written in the internal cache to the receiving CPU memory;

[0056] Figure 5A modular schematic diagram of a hardware implementation device for low-latency inter-CPU communication provided by the present invention;

[0057] Figure 6 A simulation diagram illustrating how the sending CPU directly transmits data to the receiving CPU in the conventional transmission method provided by this invention.

[0058] Figure 7 This is a simulation diagram illustrating how the hardware communication module provided by the present invention is responsible for data transmission between the sending CPU and the receiving CPU. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the described embodiments of the present invention are within the scope of protection of the present invention.

[0060] Currently, mainstream inter-CPU communication methods each have their advantages and disadvantages. Shared memory can avoid network protocol stack overhead, but the data copying process relying on the CPU increases latency, and synchronization operations require frequent CPU intervention. In frequent short message communication, the synchronization overhead may exceed data transfer, becoming the main cause of latency and CPU resource consumption. Serial port transmission is low-cost, low-power, and simple, but its bandwidth is low, making it difficult to handle large data streams. DMA can transfer data without CPU intervention, but it is designed for general purposes, has high programming and configuration overhead, and is not suitable for frequently initiated communication tasks with small data volumes. It also requires CPU management of transmission, introducing latency and CPU usage issues. Ethernet is suitable for cross-device or complex systems, but not for different CPUs within the same system, due to its high complexity and cost. To address the above problems, this invention proposes a hardware implementation method and apparatus for low-latency inter-CPU communication. This method introduces a hardware communication module, which is configured to transfer data between the sending CPU and the receiving CPU memory via direct memory access, thereby bypassing the traditional software protocol stack processing flow. At the same time, this module actively monitors the updated pointer state of the CPU and initiates transmission immediately after the data is ready, effectively eliminating random delays caused by operating system scheduling and software processing. Based on the memory address information configured during initialization, this module directly reads data from the sender's memory, temporarily caches it internally, and then writes it to the receiver's memory. This establishes the shortest data transmission path between the application layer and the communication layer, achieving zero-copy communication. Furthermore, this module autonomously determines data read / write operations based on pointer states. The CPU only updates the pointer after generating new data or completing a read / write operation, without participating in the actual data transfer process, thus reducing the CPU's computational resource consumption.

[0061] likeFigure 1 The diagram shows a system architecture for inter-CPU data transmission based on a hardware communication module provided by this invention. This system architecture mainly consists of a sending CPU, a receiving CPU, and a hardware communication module that implements the core communication functions. The hardware communication module acts as an independent communication proxy, connected to both the sending CPU and the receiving CPU.

[0062] The workflow and data flow are as follows: Once the transmitting CPU is ready to send data, it updates the transmit tail pointer. Upon detecting the pointer update, the hardware communication module actively acts as the bus master, reading data from the transmitting CPU's memory into its internal cache. This frees the transmitting CPU from heavy data transfer tasks, significantly reducing CPU overhead. Subsequently, the hardware communication module writes the data temporarily stored in its cache into the receiving CPU's memory. After processing the data, the receiving CPU updates the receive head pointer to notify the hardware communication module that there is new free space in its memory.

[0063] The entire communication process is driven by the hardware communication module through monitoring and maintaining the send tail pointer and receive head pointer, realizing efficient and autonomous data transmission without the need for direct intervention from the sending CPU and receiving CPU.

[0064] In this invention, the hardware communication module is named the LLIPC (Low Latency Interprocessor Communication) module and adopts a direct memory access method to realize data transmission between the sending CPU memory and the receiving CPU memory.

[0065] like Figure 2 The illustration shows an embodiment of the present invention, which provides a hardware implementation method for low-latency inter-CPU communication. Executed by an LLCPC module, the method includes:

[0066] S1, Receive initialization configuration information from the sending CPU. This initialization configuration information includes the starting address and size of the sending CPU's memory. And the starting address and size of the CPU memory to be received. .

[0067] Furthermore, this step is used to initialize and start the LLCPC module. After obtaining the relevant initialization configuration information, the module stores this information in its internal configuration register, completing the preparation work for establishing the communication channel. This step lays a solid foundation for subsequent data transmission, which is entirely executed autonomously by the module.

[0068] After completing the initial configuration, the LLCPC module then enters the data readiness monitoring and autonomous reading phase.

[0069] S2, monitor the transmit tail pointer updated by the transmitting CPU. And based on the initialization configuration information, send the tail pointer and the transmit header pointer maintained by the LLCPC module This determines whether to read the data to be sent from the sending CPU memory into the internal cache of the LLCPC module.

[0070] The LLIPC module monitors the data readiness status of the sending CPU in the following ways:

[0071] The LLIPC module continuously monitors its internal transmit tail pointer register. When the transmit CPU generates new data to be transmitted, it updates this register via a bus write operation. The LLIPC module captures this write operation and uses the written value as the new transmit tail pointer value.

[0072] The LLIPC module learns the tail pointer. After the update, the tail pointer will be sent. With its own maintained send header pointer A comparison is made to determine if there is data to be sent. For example... Figure 3 As shown, the judgment logic is as follows:

[0073] S21, Compare the transmit tail pointer With the send header pointer .

[0074] S22, when sending the tail pointer With the send header pointer If they are not equal, it is determined that there is data to be sent.

[0075] S23, when it is determined that there is data to be sent, according to the tail pointer With the send header pointer It calculates the amount of data to be sent and determines whether there is enough available space in the internal buffer of the LLCPC module to accommodate the data to be sent.

[0076] The calculation of the amount of data to be sent includes:

[0077] When sending the tail pointer Greater than the send header pointer At that time, the amount of data to be sent for:

[0078] .

[0079] When sending the tail pointer Less than the send header pointer At that time, the amount of data to be sent for:

[0080] .

[0081] To ensure smooth data flow, the LLCPC module needs to determine whether its internal buffer has sufficient available space to accommodate the data to be sent before initiating a read operation. The determination process is as follows:

[0082] Get the total capacity A of the internal cache of the LLIPC module.

[0083] Obtain the cumulative amount of data B that has been read from the sending CPU memory into the internal cache of the LLCPC module but has not yet been written to the receiving CPU memory. Where B = CD, C is the total amount of data read from the sending CPU into the internal cache of the LLCPC module obtained by the read counter maintained by the LLCPC module, and D is the total amount of data written to the receiving CPU memory obtained by the write counter maintained by the LLCPC module.

[0084] Calculate the current available space E=AB, and compare the current available space E with the amount of data to be read. .

[0085] If the current available space E is greater than or equal to the amount of data to be read If so, it is determined that there is enough available space in the internal buffer of the LLIPC module to accommodate the data to be sent.

[0086] If the current available space E is less than the amount of data to be read If so, it is determined that there is not enough available space in the internal buffer of the LLIPC module to accommodate the data to be sent.

[0087] S24, when there is enough available space in the internal buffer of the LLCPC module, based on the amount of data to be sent and the starting address of the sending CPU memory, the data to be sent is read from the sending CPU memory into the internal buffer of the LLCPC module, and the sending head pointer is updated. .

[0088] Furthermore, if the conditions of data readiness and sufficient cache space are met, the LLCPC module will automatically initiate direct memory access operations:

[0089] Based on the amount of data to be sent The starting address of the transmit head pointer and the transmit CPU memory are used to calculate the exact physical address of the data to be read. The data to be transmitted is then read from the transmit CPU memory into the internal buffer of the LLCPC module. After reading is complete, the LLCPC module updates its maintained transmit head pointer. This indicates that the data has been successfully retrieved. Simultaneously, the read counter increments. .

[0090] If the condition of data readiness but insufficient buffer space is met, the actual amount of data to be read is E. Based on the actual amount of data to be read (E), the send head pointer, and the starting address of the sending CPU memory, the accurate physical address of the data to be read is calculated. The data to be sent is read from the sending CPU memory into the internal buffer of the LLCPC module. After the read is complete, the LLCPC module updates its maintained send head pointer. This indicates that the data has been successfully retrieved. Simultaneously, the read counter increments by E.

[0091] After the data is successfully read and temporarily stored in the internal cache, the LLCPC module executes the readiness monitoring and data writing process on the receiving side in parallel.

[0092] S3, monitor the receiver head pointer updated by the receiving CPU. Based on the initialization configuration information and the received header pointer and the receive tail pointer maintained by the LLCPC module This determines whether to write the data to be written from the internal cache of the LLIPC module to the receiving CPU memory.

[0093] Furthermore, the LLCPC module detects when the receiving CPU is ready to receive new data by monitoring the state of the receive head pointer, specifically as follows:

[0094] The LLIPC module monitors write operations to its internal receive head pointer register. When the receive CPU finishes processing existing data and its memory buffer becomes free, it notifies the LLIPC module by updating this register value. The LLIPC module captures this write operation to know that the receive side is ready.

[0095] like Figure 4 As shown, the LLCPC module learns the receive head pointer After the update, the head pointer will be received. With its own maintained receive tail pointer A comparison is made to determine whether to write the data to be written from the LLIPC module's internal cache to the receiving CPU memory, including:

[0096] S31, Compare Receive Header Pointer With the tail pointer .

[0097] S32, when receiving the head pointer With the tail pointer If they are not equal, it is determined that there is space to be written.

[0098] S33, upon determining that there is space to be written, based on the receiver head pointer... With the tail pointer Calculate the amount of space to be written. .

[0099] Among them, the amount of space to be written is calculated. include:

[0100] When the receiver head pointer Less than the tail pointer At that time, the amount of space to be written for:

[0101] ;

[0102] When the receiver head pointer Greater than the tail pointer At that time, the amount of space to be written for:

[0103] .

[0104] S34, based on the amount of space to be written The system reads the starting address of the receiving CPU memory, writes the data from the internal cache of the LLCPC module into the receiving CPU memory, and updates the receiving tail pointer. .

[0105] Among them, based on the amount of space to be written The starting address of the receiving CPU memory is specified, and data from the internal cache of the LLCPC module is written to the receiving CPU memory, including:

[0106] Get the cumulative amount of data B = CD that has been read from the sending CPU memory into the internal cache of the hardware communication module but has not yet been written to the receiving CPU memory; where C is the total amount of data that has been read from the sending CPU memory into the internal cache of the hardware communication module obtained by the read counter maintained by the hardware communication module, and D is the total amount of data that has been written to the receiving CPU memory obtained by the write counter maintained by the hardware communication module.

[0107] Determine the actual amount of data to be written. .

[0108] Furthermore, to avoid overflow, the amount of space to be written is taken. The smaller value between the writable data volume B and the actual data volume to be written will be used. .

[0109] Based on the actual amount of data to be written The starting address of the receiving CPU memory is determined, and the data to be written in the internal cache of the LLCPC module is written to the receiving CPU memory.

[0110] Furthermore, based on the starting address of the received CPU memory and the receiving tail pointer and the actual amount of data to be written The exact target physical address of the data to be written is calculated. Through the bus master device interface, the data to be written is batch-written from the internal cache of the LLCPC module to the corresponding location in the receiving CPU memory. After the writing is complete, the LLCPC module updates its maintained receive tail pointer. This indicates that the new data has been successfully delivered. Simultaneously, the write counter value H increases. .

[0111] To maximize transmission efficiency, the LLCPC module has the ability to dynamically adjust its bus interface behavior:

[0112] The bandwidth and timing configuration of the bus between the LLIPC module and the CPU are dynamically adjusted according to the data transmission requirements determined by the amount of data to be sent and the amount of space to be written.

[0113] Furthermore, the LLCPC module predicts the scale of the upcoming transmission based on the amount of data to be read and the amount of space to be written calculated in the current step. Based on this prediction, the LLCPC module dynamically adjusts the bus interconnecting with the CPU, such as the AXI bandwidth utilization strategy and timing parameters like burst transmission length and interleaving degree.

[0114] Thus, for large-scale data transmission, a high-bandwidth, long-burst mode is configured to improve throughput; for short messages, a low-latency, short-burst mode is used to complete them quickly. This dynamic adjustment mechanism ensures optimal transmission efficiency and resource utilization under different communication loads.

[0115] like Figure 5 As shown, another embodiment of the present invention provides a hardware implementation device for low-latency inter-CPU communication. This device is an LLCPC module, located between the sending CPU and the receiving CPU, and configured to transfer data between the sending CPU memory and the receiving CPU memory via direct memory access.

[0116] The device includes a configuration receiving unit, a transmit data processing unit, a receive data processing unit, and a bus control unit. Details are as follows:

[0117] The configuration receiving unit is used to receive initialization configuration information from the sending CPU. This initialization configuration information includes the starting address and size of the sending CPU's memory. And the starting address and size of the CPU memory to be received. .

[0118] Furthermore, this unit is responsible for interacting with the sending CPU to establish the communication context. This unit typically contains a set of configuration registers accessible to the CPU, used to store initialization configuration information from the sending CPU.

[0119] The data processing unit is used to monitor the transmit tail pointer updated by the transmit CPU. And based on the initialization configuration information, send the tail pointer and the transmit header pointer maintained by the LLCPC module This determines whether to read the data to be sent from the sending CPU memory into the internal cache of the LLCPC module.

[0120] Furthermore, this unit is responsible for actively acquiring the data to be transmitted from the transmitting CPU memory. This is done by monitoring the transmit tail pointer. Register write operations detect when new data is ready. Compare the send tail pointer. With the send header pointer To determine if the data is ready, the system simultaneously checks the available space in the LLCPC module's internal buffer to ensure operational feasibility. When the conditions are met, the system, acting as the bus master, initiates a data read, moving the data to be read from the transmitting CPU's memory to the LLCPC module's internal buffer and updating the transmit head pointer. .

[0121] The receiving data processing unit is used to monitor the receive head pointer updated by the receiving CPU. Based on the initialization configuration information and the received header pointer and the receive tail pointer maintained by the LLCPC module This determines whether to write the data to be written from the internal cache of the LLIPC module to the receiving CPU memory.

[0122] Furthermore, this unit works in conjunction with the data transmission processing unit to ensure timely delivery of data to the receiving CPU. This is achieved by monitoring the receiver head pointer. The register write operation detects available free space on the receiving CPU. The receive head pointer is compared. With the tail pointer This is used to determine writable space. When the conditions are met, the device, acting as the bus master, initiates a data write operation, moving the data to be written from the internal cache of the LLCPC module to the receiving CPU memory and updating the receiving tail pointer. .

[0123] The bus control unit is used to dynamically adjust the bandwidth and timing configuration of the bus between the device and the CPU based on the data transmission requirements determined by the amount of data to be sent and the amount of space to be written.

[0124] Furthermore, this unit is responsible for optimizing bus transmission efficiency. For large-scale data transmission, it is automatically configured to a long burst transmission mode to improve throughput; for short message communication, it adopts a low-latency short burst mode, thereby achieving dynamic optimization of transmission efficiency.

[0125] To verify the performance advantages of the LLIPC module of this invention, a comparative test was designed in this embodiment to quantitatively analyze the differences in transmission latency and CPU overhead between the traditional CPU direct transmission scheme and the scheme of this invention under the same working conditions.

[0126] During the test, eight double-word data packets were sent simultaneously, and the transmission times of the following two schemes were compared:

[0127] 1. Comparative approach: The sending CPU directly transmits data to the receiving CPU.

[0128] 2. The solution of this invention: The LLCPC module is responsible for transmitting data between the sending and receiving CPUs.

[0129] The key signals to be considered in the test are defined as follows:

[0130] ahb_hsel: Selection signal, '1' indicates selection.

[0131] ahb_hwrite: Read / write signal, '1' indicates write, '0' indicates read.

[0132] ahb_hwdata[31:0]: The data value written.

[0133] ahb_hrdata[31:0]: The data value read.

[0134] axi_wdata[31:0]: The data written.

[0135] axi_wvalid: '1' indicates that the written data is valid.

[0136] axi_wlast: '1' indicates the last data transmitted in this transfer.

[0137] axi_bvalid: '1' indicates that the CPU has acknowledged the data being written.

[0138] Transmission duration is defined as the time interval from when the sender sends the first data to when the receiver confirms receipt of the last data.

[0139] Figure 6 This is the timing sequence for direct data transfer via a traditional CPU. By monitoring the falling edges of `ahb_hsel` and `ahb_hwrite`, eight double-word data entries (ab_0000 to ab_0007) can be captured from the T_CPU. On the R_CPU side, when the `axi_wvalid` signal is valid, the corresponding `axi_wdata` is the data being written. The T_CPU needs to perform eight independent write operations. Correspondingly, the R_CPU generates eight `axi_bvalid` acknowledgment signals. Figure 6The two dashed vertical lines indicate two points in time: T_CPU started reading data at 301050.08234ns, and R_CPU received the written data at 301604.567246ns. The distance between the two dashed vertical lines represents the time taken to transmit these 8 double-word data: 301604.567246ns - 301050.08234ns = 554.484906ns.

[0140] Figure 7 The timing diagram for transmitting the same 8 double-word data using the scheme of this invention is as follows: The LLIPC module actively reads data ahb_hrdata[31:0] from the memory of T_CPU and then transmits it to R_CPU. The LLIPC module is designed to process multiple data in batches at once. Although it reads data from T_CPU 8 times, when writing to R_CPU, it only sets axi_wlast to '1' when transmitting the last data ab_0007, indicating that it considers this transmission as a complete batch operation. This significantly reduces protocol overhead compared to some CPU transmission methods that require data-by-data confirmation. Because it is a single batch write, R_CPU only generates an axi_bvalid confirmation signal once, greatly simplifying the communication process. Figure 7 The two dashed vertical lines indicate two key moments: the LLIPC module started reading data from T_CPU at 301206.233114ns, and R_CPU received the written data at 301409.568015ns. The distance between the two dashed vertical lines represents the time taken to transmit these eight identical double-word data sequences: 301409.568015ns - 301206.233114ns = 203.334901ns. It should also be noted that... Figure 7 The part circled in black in the upper right corner represents the subsequent operations performed by the LLIPC module after reading ab_0000 to ab_0007 from T_CPU, and is unrelated to evaluating the transmission time of these 8 double-word data.

[0141] A direct comparison of the test results of the two schemes reveals that, for transmitting the same 8 double-word data, the comparative scheme took 554.484906 ns, while the scheme of the present invention took only 203.334901 ns, resulting in a reduction of transmission latency of approximately 63%. This comparative experimental result clearly demonstrates the significant effect of the present invention in reducing communication latency.

[0142] More importantly, in this invention, the role of T_CPU is greatly simplified. It no longer needs to actively perform eight transfer operations, but only needs to update the pointer after the data is ready. The LLIPC module will actively and autonomously complete all eight data read and write operations. This frees T_CPU from heavy communication tasks, allowing it to focus on core tasks such as computation, thereby significantly improving the overall execution efficiency of the system.

[0143] Therefore, this embodiment demonstrates through rigorous experimental comparison that the solution of the present invention can not only significantly reduce the end-to-end latency of data transmission, but also effectively offload the communication burden of the CPU, providing key hardware-level performance support for high real-time and high-concurrency applications.

[0144] In summary, this invention proposes a low-latency hardware implementation method and apparatus for inter-CPU communication. This method introduces an independent LLCPC module, establishing a direct data path between the sending and receiving CPUs. Based on a dual-pointer collaborative monitoring data transmission mechanism, zero-copy communication is achieved without CPU involvement in specific data transmission and synchronization operations. Specifically, by introducing the LLCPC module and employing a direct memory access-based data transmission mechanism, a direct path is established between the sending and receiving CPU memory, completely bypassing the traditional software protocol stack. Simultaneously, this module actively monitors the updated pointer state of the CPU and initiates transmission immediately once data is ready, effectively eliminating random delays caused by operating system scheduling and software processing, achieving highly deterministic, extremely low end-to-end latency. Based on the initialized memory address information, this module can directly read data from the sending memory, temporarily cache it internally, and then directly write it to the receiving memory, establishing the shortest data transmission path between the application layer and the communication layer, completely avoiding data copy overhead between kernel mode and user mode, and achieving true zero-copy communication. This module can autonomously determine whether to read or write data based on the pointer state. Under this mechanism, the CPU only needs to update the head and tail pointers when the data is ready or processed, while the actual data handling, buffer management, and transmission synchronization are all handled autonomously by the hardware module, reducing the CPU's computational resource consumption. The entire communication process is completed independently by the LLCPC module, and its behavior is unaffected by operating system scheduling, interrupt load, or other software tasks. This pure hardware implementation ensures excellent timing determinism and operational reliability in the communication process, providing performance advantages that software solutions cannot match for applications with high real-time requirements.

[0145] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A hardware implementation method for low-latency inter-CPU communication, characterized in that, include: Receive initialization configuration information from the sending CPU; the initialization configuration information includes the starting address and size of the sending CPU's memory. And the starting address and size of the CPU memory to be received. ; Monitor the transmit tail pointer updated by the transmitting CPU. And based on the initialization configuration information, send the tail pointer and the send head pointer maintained by the hardware communication module Determine whether to read the data to be sent from the sending CPU memory into the internal cache of the hardware communication module; The step of determining whether to read the data to be sent from the transmitting CPU memory into the internal cache of the hardware communication module includes: Compare the tail pointers to send With the send header pointer ; When sending the tail pointer With the send header pointer If they are not equal, it is determined that there is data to be sent; When it is determined that there is data to be sent, the tail pointer is used as a reference. With the send header pointer Calculate the amount of data to be sent and determine whether there is enough available space in the internal buffer of the hardware communication module to accommodate the data to be sent; When there is sufficient available space in the internal buffer of the hardware communication module, the data to be sent is read from the sending CPU memory into the internal buffer of the hardware communication module based on the amount of data to be sent and the starting address of the sending CPU memory, and the sending header pointer is updated. ; Monitor the receiver head pointer updated by the receiving CPU. Based on the initialization configuration information and the received header pointer and the receive tail pointer maintained by the hardware communication module Determine whether to write the data to be written from the internal cache of the hardware communication module to the receiving CPU memory; The step of determining whether to write the data to be written in the internal cache to the receiving CPU memory includes: Compare receive head pointer With the tail pointer ; When the receiver head pointer With the tail pointer If they are not equal, it is determined that there is space to be written. When it is determined that there is space to be written, based on the receive head pointer With the tail pointer Calculate the amount of space to be written. ; Based on the amount of space to be written The system reads the starting address of the receiving CPU memory, writes the data to be written from the internal cache of the hardware communication module into the receiving CPU memory, and updates the receiving tail pointer. ; The hardware communication module is located between the sending CPU and the receiving CPU and is configured to transmit data between the sending CPU memory and the receiving CPU memory via direct memory access.

2. The hardware implementation method for low-latency inter-CPU communication according to claim 1, characterized in that, The calculation of the amount of data to be sent includes: When sending the tail pointer Greater than the send header pointer At that time, the amount of data to be sent for: ； When sending the tail pointer Less than the send header pointer At that time, the amount of data to be sent for: 。 3. The hardware implementation method for low-latency inter-CPU communication according to claim 2, characterized in that, The step of determining whether there is enough available space in the internal buffer of the hardware communication module to accommodate the data to be sent includes: Obtain the total capacity A of the internal buffer of the hardware communication module; Get the cumulative amount of data B = CD that has been read from the sending CPU memory into the internal cache of the hardware communication module but has not yet been written to the receiving CPU memory; where C is the total amount of data that has been read from the sending CPU memory into the internal cache of the hardware communication module obtained by the read counter maintained by the hardware communication module, and D is the total amount of data that has been written to the receiving CPU memory obtained by the write counter maintained by the hardware communication module. Calculate the current available space E=AB, and compare the current available space E with the amount of data to be read. ; If the current available space E is greater than or equal to the amount of data to be read If so, it is determined that there is enough available space in the internal buffer of the hardware communication module to accommodate the data to be sent.

4. The hardware implementation method for low-latency inter-CPU communication according to claim 1, characterized in that, The calculation of the amount of space to be written include: When the receiver head pointer Less than the tail pointer At that time, the amount of space to be written for: ； When the receiver head pointer Greater than the tail pointer At that time, the amount of space to be written for: ； The amount of space to be written The starting address of the receiving CPU memory is used to write the data to be written from the internal cache of the hardware communication module to the receiving CPU memory. This includes: obtaining the cumulative amount of data B=CD that has been read from the sending CPU memory into the internal cache of the hardware communication module but not yet written to the receiving CPU memory; where C is the total amount of data read from the sending CPU memory into the internal cache of the hardware communication module obtained by the read counter maintained by the hardware communication module, and D is the total amount of data written to the receiving CPU memory obtained by the write counter maintained by the hardware communication module; and determining the actual amount of data to be written. Based on the actual amount of data to be written The starting address of the receiving CPU memory is used to write the data to be written from the internal cache of the hardware communication module to the receiving CPU memory.

5. The hardware implementation method for low-latency inter-CPU communication according to claim 1, characterized in that, The monitoring is performed by updating the transmit tail pointer via the transmit CPU. and the monitoring of the receiver head pointer updated by the receiving CPU. This can be achieved in the following ways: Monitor the write operations of the corresponding preset pointer registers in the hardware communication module.

6. The hardware implementation method for low-latency inter-CPU communication according to claim 1, characterized in that, The bandwidth and timing configuration of the bus between the hardware communication module and the CPU are dynamically adjusted according to the data transmission requirements determined by the amount of data to be sent and the amount of space to be written.

7. A hardware implementation apparatus for low-latency inter-CPU communication, comprising a hardware implementation method for low-latency inter-CPU communication according to any one of claims 1 to 6, characterized in that, include: A configuration receiving unit is configured to receive initialization configuration information from the sending CPU; the initialization configuration information includes the starting address and size of the sending CPU's memory. And the starting address and size of the CPU memory to be received. ; The data processing unit is used to monitor the transmit tail pointer updated by the transmit CPU. And based on the initialization configuration information, send the tail pointer and the send head pointer maintained by the hardware communication module Determine whether to read the data to be sent from the sending CPU memory into the internal cache of the hardware communication module; The receiving data processing unit is used to monitor the receive head pointer updated by the receiving CPU. Based on the initialization configuration information and the received header pointer and the receive tail pointer maintained by the hardware communication module Determine whether to write the data to be written from the internal cache of the hardware communication module to the receiving CPU memory; The hardware communication module is located between the sending CPU and the receiving CPU and is configured to transmit data between the sending CPU memory and the receiving CPU memory via direct memory access.

8. The hardware implementation apparatus for low-latency inter-CPU communication according to claim 7, characterized in that, Also includes: The bus control unit is used to dynamically adjust the bandwidth and timing configuration of the bus between the hardware communication module and the CPU based on the data transmission requirements determined by the amount of data to be sent and the amount of space to be written.

Images