Sensitive amplifiers, amplifier circuits, and chips based on current source offset compensation

Abstract

This invention relates to the field of dynamic random access memory (DRAM) circuit design technology, specifically to a sensitive amplifier, amplifier circuit, and chip based on current source compensation for offset. The invention provides a sensitive amplifier based on current source compensation for offset, comprising: six NMOS transistors MN1~MN6 and four PMOS transistors MP1~MP4. This invention does not use a capacitor-compensated sensitive amplifier; instead, it provides a stable current to the diode connection formed by the latch transistors by multiplexing pre-charge transistors as a current source, thereby achieving offset voltage compensation and effectively mitigating the sensitivity of offset voltage to compensation time while avoiding excessive circuit area overhead. This invention solves the problems of excessive area overhead and sensitivity of offset voltage to offset compensation time in existing sensitive amplifier compensation schemes.

Description

Technical Field

[0001] This invention relates to the field of dynamic random access memory (DRAM) circuit design technology, and more specifically, to: 1. a sensitive amplifier based on current source compensation for offset; 2. an amplifier circuit constructed based on the sensitive amplifier; and 3. a sensitive amplifier chip designed based on the sensitive amplifier. Background Technology

[0002] Sensitive amplifiers (SAs) are commonly used devices in DRAM read operations. They are responsible for amplifying the weak charge signals in the DRAM and converting them into logic levels "0" or "1".

[0003] It is well known that the smaller the input voltage difference of the switching amplifier (SA), the more prone it is to offset in the SA, leading to reading errors. Therefore, several compensation schemes for the SA have emerged: 1. Constructing the SA using capacitor compensation, but this suffers from the problem of excessive area overhead due to large capacitor usage; 2. Constructing the SA using diode connection compensation, but this suffers from the problem of the compensation effect being sensitive to offset compensation time. Summary of the Invention

[0004] Therefore, it is necessary to address the problems of excessive area overhead and sensitivity of offset voltage to offset compensation time in existing SA compensation schemes by providing sensitive amplifiers, amplifier circuits, and chips based on current source compensation for offset.

[0005] This invention is achieved using the following technical solution:

[0006] In a first aspect, the present invention provides a sensitive amplifier based on current source compensation for offset, comprising: 6 NMOS transistors MN1~MN6 and 4 PMOS transistors MP1~MP4.

[0007] The gate of MN1 is connected to the reference bit line BLT, the source is connected to the pull-down signal SAN1, and the drain is connected to the drain of MN3, the drain of MN6, the drain of MP1, the gate of MP2, and the drain of MP3; the gate of MN2 is connected to the reference bit line BLB, the source is connected to the pull-down signal SAN2, and the drain is connected to the drain of MN4, the drain of MN5, the drain of MP2, the gate of MP1, and the drain of MP4; the source of MN3 is connected to BLT, and the gate is connected to the compensation signal OB; the source of MN4 is connected to BLB, and the gate is connected to OB; the source of MN5 is connected to BLT, and the gate is connected to the strobe signal ISO1; the source of MN6 is connected to BLB, and the gate is connected to the strobe signal ISO2; the source of MP1 is connected to the pull-up signal SAP1; the source of MP2 is connected to the pull-up signal SAP2; the gate of MP3 is connected to the gate voltage signal BLEQ1, and the source is connected to the control signal VEQ; the gate of MP4 is connected to the gate voltage signal BLEQ2, and the source is connected to VEQ.

[0008] The operating timing sequence of the sensitive amplifier includes: pre-charge stage, offset compensation stage, charge sharing stage, pre-sensing amplification stage, and main sensing stage. MP3~MP4 act as pre-charge tubes in the pre-charge stage and as current source tubes in the offset compensation stage, and are connected with MN1~MN2 to form diodes to achieve offset compensation.

[0009] This method or process for implementing a current source-based offset-compensated sensitive amplifier is based on an embodiment of the present disclosure.

[0010] In a second aspect, the present invention discloses an amplifier circuit, comprising: a DRAM memory cell one, a DRAM memory cell two, and a sensitive amplifier based on current source compensation offset as disclosed in the first aspect.

[0011] DRAM memory cell one is used to store 0 or 1. DRAM memory cell two is used to store 0 or 1.

[0012] A sensitive amplifier based on current source compensation offset is used to read DRAM memory cell one or DRAM memory cell two.

[0013] This type of amplifier circuit is implemented according to the method or process of an embodiment of this disclosure.

[0014] Thirdly, the present invention discloses a sensitive amplifier chip that adopts the circuit layout of a sensitive amplifier based on current source compensation for offset as disclosed in the first aspect.

[0015] The implementation of this sensitive amplifier chip is based on the method or process of embodiments of this disclosure.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1. This invention designs a 10T DRAM sensitive amplifier, which does not use capacitor compensation SA, but instead uses a pre-charge tube multiplexed as a current source to provide a stable current to the diode connection formed by the latch tube, thereby achieving offset voltage compensation and effectively mitigating the sensitivity of offset voltage to compensation time while avoiding excessive circuit area overhead.

[0018] 2. This invention designs a 10T DRAM sensitive amplifier, which achieves pre-amplification of the bit line voltage difference by multiplexing the pre-charge tube into a current source and forming a common source amplifier with the latch tube as the current source load, thus ensuring the accuracy of amplification. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 The circuit diagram of the sensitive amplifier based on current source compensation offset provided in Embodiment 1 of the present invention;

[0021] Figure 2 Based on Figure 1 The circuit diagram of the amplifier circuit constructed from the sensitive amplifier;

[0022] Figure 3 for Figure 2 The circuit state diagram of the amplifier circuit in the pre-charge stage;

[0023] Figure 4 for Figure 2 The circuit state diagram of the amplifier circuit in the offset compensation stage;

[0024] Figure 5 for Figure 2 The circuit state diagram of the amplifier circuit in the charge sharing stage;

[0025] Figure 6 for Figure 2 The circuit state diagram of the amplifier circuit in the pre-induction amplification stage;

[0026] Figure 7 for Figure 2 The circuit state diagram of the amplifier circuit in the main induction stage;

[0027] Figure 8 for Figure 2 Timing diagram of the amplifier circuit;

[0028] Figure 9 This is a comparison diagram of simulation experiments provided in Embodiment 2 of the present invention;

[0029] Figure 10 The figure shows the simulation results provided in Embodiment 2 of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] It should be noted that when a component is said to be "installed on" another component, it can be directly on the other component or it may be in a component that is centered on it. When a component is said to be "set on" another component, it can be directly set on the other component or it may also be in a component that is centered on it. When a component is said to be "fixed to" another component, it can be directly fixed to the other component or it may also be in a component that is centered on it.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] Example 1

[0034] First, see Figure 1 This is a circuit diagram of a sensitive amplifier based on current source compensation for offset provided in Embodiment 1.

[0035] In terms of the number of MOS transistors, the current source-compensated offset sensitive amplifier is designed for 10T and is suitable for DRAM. It includes: 6 NMOS transistors MN1~MN6 and 4 PMOS transistors MP1~MP4.

[0036] The specific connection relationships are as follows:

[0037] The gate of MN1 is connected to the reference bit line BLT, the source is connected to the pull-down signal SAN1, and the drain is connected to the drain of MN3, the drain of MN6, the drain of MP1, the gate of MP2, and the drain of MP3; the gate of MN2 is connected to the reference bit line BLB, the source is connected to the pull-down signal SAN2, and the drain is connected to the drain of MN4, the drain of MN5, the drain of MP2, the gate of MP1, and the drain of MP4; the source of MN3 is connected to BLT, and the gate is connected to the compensation signal OB; the source of MN4 is connected to BLB, and the gate is connected to OB; the source of MN5 is connected to BLT, and the gate is connected to the strobe signal ISO1; the source of MN6 is connected to BLB, and the gate is connected to the strobe signal ISO2; the source of MP1 is connected to the pull-up signal SAP1; the source of MP2 is connected to the pull-up signal SAP2; the gate of MP3 is connected to the gate voltage signal BLEQ1, and the source is connected to the control signal VEQ; the gate of MP4 is connected to the gate voltage signal BLEQ2, and the source is connected to VEQ.

[0038] For a current source-based offset-compensated sensitive amplifier, its operating timing sequence includes: pre-charge phase (PCG), offset compensation phase (OC), charge sharing phase (CS), pre-sensing amplification phase (PS), and main sensing phase (MS).

[0039] A current-source offset-compensated sensitive amplifier is used for read amplification of DRAM memory cells. Therefore, a current-source offset-compensated sensitive amplifier can be used to construct... Figure 2 The amplifier circuit shown.

[0040] See Figure 2 The amplifier circuit includes: DRAM memory cell one, DRAM memory cell two, and a sensitive amplifier based on current source compensation for offset.

[0041] DRAM memory cell one is used to store 0 or 1. DRAM memory cell two is used to store 0 or 1. A sensitive amplifier based on current source offset compensation is used to read DRAM memory cell one or DRAM memory cell two.

[0042] DRAM memory cell one and DRAM memory cell two can adopt a common 1T1C design. That is, DRAM memory cell one includes: one NMOS transistor N0 and one capacitor C0; the drain of N0 is connected to BLT, and the gate is connected to the word line WL0; the first terminal of C0 is connected to the source of N0, and the second terminal is connected to ground VSS. DRAM memory cell two includes: one N1 and one capacitor C1; the drain of N1 is connected to BLB, and the gate is connected to the word line WL1; the first terminal of C1 is connected to the source of N1, and the second terminal is connected to ground VSS.

[0043] It is important to note that WL0 and WL1 should not be turned on at the same time to avoid reading errors by the sensitive amplifier based on current source compensation offset.

[0044] The timing of the sensitive amplifier based on current source offset compensation is explained in detail below, based on the amplifier circuit:

[0045] 1. See Figure 3 During the pre-charging phase:

[0046] BLEQ1 and BLEQ2 are placed in VSS (i.e., MP3 and MP4 are turned on and act as pre-charge tubes), OB, ISO1, and ISO2 are placed in 3×VDD / 2 (i.e., MN3, MN4, MN5, and MN6 are turned on), SAP1, SAN1, SAP2, and SAN2 are placed in VDD / 2, and VEQ is placed in VDD / 2; BLT and BLB are pre-charged to VDD / 2 (i.e., VEQ charges BLT through MP3 and MN3, and charges BLB through MP4 and MN4).

[0047] Where VDD represents the power supply voltage.

[0048] 2. See Figure 4 During the dysfunction compensation phase:

[0049] BLEQ1 and BLEQ2 are set to VG (where VG represents the voltage value within [0, Vth], and Vth is the threshold voltage of the PMOS transistor, making MP3~MP4 act as current source transistors), ISO1, ISO2, SAP1, SAN1, SAP2, and SAN2 are set to 0 (i.e., MN5 and MN6 are turned off), OB is set to 3×VDD / 2 (i.e., MN3 and MN4 are turned on), and VEQ is set to VDD.

[0050] Therefore, the drain and gate of MN1 and the drain and gate of MN2 are connected, thus forming a diode connection between MN1 and MN2. MP3 forms a current source under the action of VEQ and BLEQ1 and acts on MN1, while MP4 forms a current source under the action of VEQ and BLEQ2 and acts on MN2. That is, the mismatch caused by the different threshold voltages of MN1 and MN2 will be compensated by the constant current provided by the current source based on the diode connection, thereby storing the mismatch voltage on BLB and BLT to achieve offset compensation.

[0051] It should be noted that the value of VG depends on the output current of MP3~MP4; and the output current of MP3~MP4 must meet the following requirement: after offset compensation, the drain of MN1, the drain of MN2, BLT, and BLB can still be near VDD / 2.

[0052] In summary, MP3~MP4 act as current source transistors during the offset compensation stage and are connected to MN1~MN2 to form diodes to achieve offset compensation.

[0053] 3. During the charge sharing phase:

[0054] See Figure 5 If DRAM memory cell one is read, then OB is set to 0 (i.e., MN3 and MN4 are off), BLEQ2 and SAP2 are set to VDD (i.e., MP3 is off), WL0 is set to 3×VDD / 2 (i.e., N0 is on), VEQ remains at VDD, ISO1, ISO2, SAP1, SAN1, and SAN2 remain at VSS (i.e., MN5 and MN6 are off), BLEQ1 remains at VG, and C0 shares charge with BLT (i.e., a voltage change value ΔV is generated in BLT). BLT ).

[0055] If DRAM memory cell two is read, then OB is set to 0 (i.e., MN3 and MN4 are off), BLEQ1 and SAP1 are set to VDD (i.e., MP3 is off), WL1 is set to 3×VDD / 2 (i.e., N1 is on), VEQ remains at VDD, ISO1, ISO2, SAP2, SAN1, and SAN2 remain at VSS (i.e., MN5 and MN6 are off), BLEQ2 remains at VG, and C1 shares charge with BLB (i.e., when BLB generates a voltage change value ΔV). BLB ).

[0056] 4. During the pre-induction amplification stage:

[0057] See Figure 6 If DRAM memory cell one is read, ISO2 is set to 3×VDD / 2 (i.e., MN6 is on), OB, ISO1, SAP1, SAN1, and SAN2 remain at 0 (i.e., MN3, MN4, and MN5 are off), BLEQ2, SAP2, and VEQ remain at VDD (i.e., MP4 is off), and BLEQ1 remains at VG.

[0058] Therefore, we have: ΔV BLT The signal enters from the gate of MN1 and exits from the drain of MN1. MP3 acts as a current source load, meaning that MN1 and MP3 form a common-source amplifier with a current source load, thus causing BLB to correspond to ΔV. BLT The polarity is reversed to amplify the voltage difference between BLT and BLB, thus preventing large voltage differences.

[0059] If DRAM memory cell 2 is read, ISO1 is set to 3×VDD / 2 (i.e., MN5 is on), OB, ISO2, SAP2, SAN1, and SAN2 remain at 0 (i.e., MN3, MN4, and MN6 are off), BLEQ1, SAP1, and VEQ remain at VDD (i.e., MP3 is off), and BLEQ2 remains at VG.

[0060] Therefore, we have: ΔV BLB The signal enters from the gate of MN2 and exits from the drain of MN2. MP4 acts as a current source load. That is, MN2 and MP4 form a common-source amplifier with a current source load, thus BLT corresponds to ΔV. BLB The polarity is reversed to amplify the voltage difference between BLB and BLT, thus preventing large voltage differences.

[0061] In summary, during the pre-sensing amplification stage, MP3~MP4 selects one as the current source transistor according to the reading needs and forms a common source amplifier with the corresponding MN1 or MN2 to achieve large-scale prevention.

[0062] 5. During the main sensing stage:

[0063] See Figure 7If DRAM memory cell one is read, ISO1 is set to 3×VDD / 2 (i.e., MN5 is on), BLEQ1 and SAP1 are set to VDD (i.e., MP3 is off), VEQ is set to VSS, ISO2 is kept at 3×VDD / 2 (i.e., MN6 is on), BLEQ2 and SAP2 are kept at VDD (i.e., MP4 is off), and SAN1 and SAN2 are kept at VSS. MP1, MN1, MN2, and MP2 form a cross-coupled inverter and amplify the voltage difference between BLT and BLB.

[0064] If DRAM memory cell 2 is read, ISO2 is set to 3×VDD / 2 (i.e., MN6 is on), BLEQ2 and SAP2 are set to VDD (i.e., MP4 is off), VEQ is set to VSS, ISO1 is kept at 3×VDD / 2 (i.e., MN5 is on), BLEQ1 and SAP1 are kept at VDD (i.e., MP3 is off), and SAN1 and SAN2 are kept at VSS. MP1, MN1, MN2, and MP2 form a cross-coupled inverter and amplify the voltage difference between BLT and BLB.

[0065] To facilitate understanding of the above stages, a timing diagram of each signal at each stage is drawn, taking the reading of DRAM memory cell one as an example. Figure 8 As shown.

[0066] Furthermore, this embodiment 1 also discloses a sensitive amplifier chip, which adopts the circuit layout of the sensitive amplifier based on current source compensation for offset disclosed above. The chip-packaged form makes it easier to promote and apply the aforementioned circuit.

[0067] This sensitive amplifier chip has 12 pins: pin 1 is used to connect to BLT; pin 2 is used to connect to BLB; pin 3 is used to connect to ISO1; pin 4 is used to connect to ISO2; pin 5 is used to connect to SAP1; pin 6 is used to connect to SAP2; pin 7 is used to connect to BLEQ1; pin 8 is used to connect to BLEQ2; pin 9 is used to connect to VEQ; pin 10 is used to connect to OB; pin 11 is used to connect to SAN1; and pin 12 is used to connect to SAN2.

[0068] Of course, the sensitive amplifier based on current source compensation for offset can also be designed as a module—if designed as a module, the corresponding pins can be designed as terminals.

[0069] Example 2

[0070] In this embodiment 2, a Monte Carlo simulation experiment was conducted at room temperature to verify the effectiveness of the sensitive amplifier based on current source compensation for offset proposed in embodiment 1.

[0071] 1. A sensitive amplifier based on current source offset compensation (i.e., Figure 9Curve 1) and the existing sensitive amplifier that uses diode connection for compensation (i.e. Figure 9 (See curve 2) for the variation of offset voltage under different compensation times. The comparison results are shown in [reference needed]. Figure 9 .

[0072] Depend on Figure 9 It is known that existing sensitive amplifiers using diode connection compensation have a significant impact on offset voltage at different compensation times; the offset voltage first decreases and then increases sharply with increasing compensation time—that is, the offset voltage is sensitive to compensation time. However, sensitive amplifiers based on current source compensation mitigate the sensitivity of offset voltage to compensation time, achieving a gradual decrease in offset voltage with increasing compensation time, and reaching near-convergence.

[0073] 2. Multiple simulations were performed on the sensitive amplifier based on current source offset compensation to examine its offset voltage distribution. See the results below. Figure 10 .

[0074] Depend on Figure 10 It can be seen that the mean offset voltage is -729.4μV and the standard deviation is 6.678mV, which is considered to be at a relatively good level.

[0075] Thus, the above simulation experiments have verified the effectiveness and superiority of the sensitive amplifier based on current source compensation for offset proposed in Example 1.

[0076] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A current source based offset compensated sense amplifier characterized by, Comprise: 6 NMOS transistors MN1~MN6, 4 PMOS transistors MP1~MP4; The gate of MN1 is connected with the reference bit line BLT, the source is connected with the pull-down signal SAN1, and the drain is connected with the drain of MN3, the drain of MN6, the drain of MP1, the gate of MP2, and the drain of MP3; The gate of MN2 is connected with the reference bit line BLB, the source is connected with the pull-down signal SAN2, and the drain is connected with the drain of MN4, the drain of MN5, the drain of MP2, the gate of MP1, and the drain of MP4; The source of MN3 is connected with BLT, and the gate is connected with the compensation signal OB; The source of MN4 is connected with BLB, and the gate is connected with OB; The source of MN5 is connected with BLT, and the gate is connected with the gate signal ISO1; The source of MN6 is connected with BLB, and the gate is connected with the gate signal ISO2; The source of MP1 is connected with the pull-up signal SAP1; The source of MP2 is connected with the pull-up signal SAP2; The gate of MP3 is connected with the gate voltage signal BLEQ1, and the source is connected with the control signal VEQ; The gate of MP4 is connected with the gate voltage signal BLEQ2, and the source is connected with VEQ; The working timing of the sensitive amplifier comprises, in sequence, a pre-charge stage, a offset compensation stage, a charge sharing stage, a pre-sensing amplification stage, and a main sensing stage; MP3~MP4 act as pre-charge tubes in the pre-charge stage, act as current source tubes in the offset compensation stage, and are diode-connected with MN1~MN2 to realize offset compensation.

2. An amplification circuit, characterized by, Comprise: A DRAM storage unit one for storing 0 or 1; A DRAM storage unit two for storing 0 or 1; And The sensitive amplifier based on current source offset compensation as claimed in claim 1 is used for reading the DRAM storage unit one or the DRAM storage unit two.

3. The amplification circuit of claim 2, wherein The DRAM storage unit one comprises: 1 NMOS tube N0 and 1 capacitor C0; The drain of N0 is connected with BLT, and the gate is connected with the word line WL0; The first end of C0 is connected with the source of N0, and the second end is connected with the ground VSS; The DRAM storage unit two comprises: 1 N1 and 1 capacitor C1; The drain of N1 is connected with BLB, and the gate is connected with the word line WL1; The first end of C1 is connected with the source of N1, and the second end is connected with the ground VSS; Wherein, WL0 and WL1 are not opened at the same time.

4. The amplification circuit of claim 3, wherein In the pre-charge stage, BLEQ1 and BLEQ2 are set to VSS, OB, ISO1, ISO2 are set to 3×VDD / 2, SAP1, SAN1, SAP2, SAN2 are set to VDD / 2, and VEQ is set to VDD / 2; BLT and BLB are pre-charged to VDD / 2; Wherein, VDD represents the power voltage.

5. The amplification circuit of claim 4, wherein, In the offset compensation stage, BLEQ1 and BLEQ2 are set to VG, ISO1, ISO2, SAP1, SAN1, SAP2, and SAN2 are set to 0, OB is set to 3×VDD / 2, VEQ is set to VDD; MN1~MN2 are diode-connected, MP3 forms a current source under the action of VEQ and BLEQ1 and acts on MN1, MP4 forms a current source under the action of VEQ and BLEQ2 and acts on MN2, and offset compensation is realized. Wherein, VG represents a voltage value within [0, Vth]; Vth is the threshold voltage of the PMOS tube.

6. The amplification circuit of claim 5, wherein, In the charge sharing stage: If reading DRAM memory cell one, OB is set to 0, BLEQ2, SAP2 are set to VDD, WL0 is set to 3×VDD / 2, VEQ remains VDD, ISO1, ISO2, SAP1, SAN1, SAN2 remain VSS, BLEQ1 remains VG, C0 shares charge with BLT; If reading DRAM memory cell two, OB is set to 0, BLEQ1, SAP1 are set to VDD, WL1 is set to 3×VDD / 2, VEQ remains VDD, ISO1, ISO2, SAP2, SAN1, SAN2 remain VSS, BLEQ2 remains VG, C1 shares charge with BLB.

7. The amplification circuit of claim 6, wherein, In the pre-sense stage: MP3~MP4 are selected as current source tubes according to reading needs, and form common source amplifiers with corresponding MN1 or MN2 to realize pre-sense.

8. The amplification circuit of claim 7, wherein, In the pre-sense stage: If reading DRAM memory cell one, ISO2 is set to 3×VDD / 2, OB, ISO1, SAP1, SAN1, SAN2 remain 0, BLEQ2, SAP2, VEQ remain VDD, BLEQ1 remains VG; MN1, MP3 form a common source amplifier with current source as load, and pre-sense the voltage difference between BLT and BLB; If reading DRAM memory cell two, ISO1 is set to 3×VDD / 2, OB, ISO2, SAP2, SAN1, SAN2 remain 0, BLEQ1, SAP1, VEQ remain VDD, BLEQ2 remains VG, MN2, MP4 form a common source amplifier with current source as load, and pre-sense the voltage difference between BLB and BLT.

9. The amplification circuit of claim 8, wherein, In the main sense stage: If reading DRAM memory cell one, ISO1 is set to 3×VDD / 2, BLEQ1, SAP1 are set to VDD, VEQ is set to VSS, ISO2 remains 3×VDD / 2, BLEQ2, SAP2 remain VDD, SAN1, SAN2 remain VSS; MP1, MN1, MN2, MP2 form a cross-coupled inverter, and amplify the voltage difference between BLT and BLB; If reading DRAM memory cell two, ISO2 is set to 3×VDD / 2, BLEQ2, SAP2 are set to VDD, VEQ is set to VSS, ISO1 remains 3×VDD / 2, BLEQ1, SAP1 remain VDD, SAN1, SAN2 remain VSS; MP1, MN1, MN2, MP2 form a cross-coupled inverter, and amplify the voltage difference between BLT and BLB.

10. A sensitive amplifier chip, characterized by The sensitive amplifier comprises the sensitive amplifier as claimed in claim 1. The sensitive amplifier comprises the sensitive amplifier as claimed in claim 1.

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