Hybrid bonding method of bare chip and wafer and preparation method of semiconductor chip

Abstract

The invention discloses a bare chip and wafer hybrid bonding method and a semiconductor chip preparation method, and the bonding method comprises the steps: cutting a to-be-cut wafer into a plurality of bare chips; the bare chip comprises a first surface and a second surface opposite to the first surface, and the first surface of the bare chip is provided with a first bonding layer; all the bare chips are simultaneously grabbed from the second surfaces of the bare chips, and all the bare chips are placed on the surface of the carrying disc in the mode that the first bonding layers of all the bare chips face the carrying disc; each bare chip is sequentially grabbed from the second surface of the bare chip, and the bare chips are placed on the bearing wafer in the mode that the first bonding layers of the bare chips face the third surface of the bearing wafer; the third surface of the bearing wafer is provided with a second bonding layer; and bonding the bare chip with the bearing wafer. According to the invention, the bonding quality of the bare chip and the bearing wafer is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a hybrid bonding method for dies and wafers and a method for fabricating semiconductor chips. Background Technology

[0002] Die-to-wafer hybrid bonding is an advanced 3D integration technology that enables high-density electrical interconnects and physical isolation within a very small space. With the surge in high-bandwidth memory (HBM), 3D NAND flash memory, and the number of stacked logic chips, die-to-wafer hybrid bonding technology is penetrating from HBM and 3D NAND into logic chips, sensors, and other fields.

[0003] Currently, in the die-to-wafer bonding process, particle defects are easily introduced into the bonding surface of the die, resulting in poor bonding strength between the die and the wafer, ultimately leading to a decrease in product yield. Summary of the Invention

[0004] This invention provides a hybrid bonding method for bare dies and wafers and a method for fabricating semiconductor chips, in order to solve the problem of poor bonding quality between bare dies and wafers.

[0005] In a first aspect, the present invention provides a hybrid bonding method for bare dies and wafers, wherein the bonding method includes:

[0006] The wafer to be cut is cut into multiple bare dies; each bare die includes a first surface and a second surface opposite to the first surface, and a first bonding layer is provided on the first surface of the bare die.

[0007] All the bare dies are simultaneously picked up from the second surface of the bare die, and all the bare dies are placed on the surface of the carrier disk with the first bonding layer of all the bare dies facing the carrier disk;

[0008] Each die is sequentially picked up from the second surface of the die and placed on the carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer;

[0009] The bare die is bonded to the carrier wafer.

[0010] Optionally, before simultaneously grasping all the bare dies from the second surface of the die and placing all the bare dies on the carrier disk surface with the first bonding layer of all the bare dies facing the carrier disk, the method further includes:

[0011] Provide a carrier tray, clean the carrier tray, and fix the carrier tray on the carrier tray holder;

[0012] The carrier disk is cut into multiple carrier areas, and each carrier area corresponds to a bare die.

[0013] Clean the cut carrier tray;

[0014] All bare dies are simultaneously picked up from the second surface of the die and placed on the carrier disk with the first bonding layer of all the dies facing the carrier disk, including:

[0015] All dies are simultaneously picked up from the second surface of the die and placed in their respective carrier areas with the first bonding layer of all dies facing the carrier disk.

[0016] Optionally, simultaneously gripping all the bare dies from their second surface and placing them on the carrier disk with the first bonding layers of all the dies facing the carrier disk, includes:

[0017] All dies are simultaneously picked up from the second surface of the die and placed on the surface of the silicon carrier with the first bonding layer of all dies facing the silicon carrier.

[0018] Optionally, before dicing the wafer to be diced into multiple bare dies, the process further includes:

[0019] A first dielectric layer is formed on the fourth surface of the wafer to be diced; the fourth surface of the wafer to be diced includes a plurality of first metal pads;

[0020] The first dielectric layer is etched to form a plurality of first vias, each of which corresponds to a first metal pad and exposes the first metal pad.

[0021] A first bonding metal is formed in the first through-hole; the side of the first bonding metal away from the fourth surface is flush with the side of the first dielectric layer away from the fourth surface; the first dielectric layer and the first bonding metal form a full-surface bonding layer;

[0022] The wafer to be diced is diced into multiple bare dies; each bare die includes a first surface and a second surface opposite to the first surface, and the first surface of the bare die is provided with a first bonding layer, including:

[0023] The wafer to be cut and the full-surface bonding layer are cut into multiple bare dies; a first dielectric layer and a first bonding metal are disposed on the first surface of the bare die as the first bonding layer.

[0024] Optionally, after forming the first bonding metal within the first through-hole, the method further includes:

[0025] The fifth surface of the wafer to be cut is thinned; the fifth surface is positioned opposite to the fourth surface.

[0026] The wafer to be cut is placed on a wafer holder, and a protective layer is formed on the side of the first dielectric layer and the first bonding metal away from the fourth surface;

[0027] After dicing the wafer to be diced and the full-surface bonding layer into multiple bare dies, the process also includes:

[0028] Remove the protective layer;

[0029] Plasma activation treatment is performed on the side of the first dielectric layer and the first bonded metal away from the fourth surface;

[0030] The first dielectric layer and the side of the first bonding metal away from the fourth surface are cleaned.

[0031] Optionally, the wafer to be diced is diced into multiple bare dies, including:

[0032] Laser grooving is performed on the wafer to be cut;

[0033] Plasma cutting technology is used to cut the wafer to be cut in the laser-grooved area.

[0034] Optionally, before sequentially picking up each die from its second surface and placing it on the carrier wafer with its first bonding layer facing the third surface of the carrier wafer, the process includes:

[0035] A second dielectric layer is formed on the third surface of the wafer; the third surface of the wafer includes a plurality of second metal pads;

[0036] The second dielectric layer is etched to form multiple second vias, each of which corresponds to a second metal pad and exposes the second metal pad.

[0037] A second bonding metal is formed in the second via; the side of the second bonding metal away from the third surface is flush with the side of the second dielectric layer away from the third surface; the second dielectric layer and the second bonding metal together form the second bonding layer.

[0038] Optionally, after forming the second bonding metal within the second through-hole, the method further includes:

[0039] Plasma activation treatment is performed on the side of the second bonding metal and the second dielectric layer that is away from the third surface;

[0040] The side of the second bonding metal and the second dielectric layer away from the third surface is cleaned.

[0041] Optionally, the entire die is simultaneously gripped from the second surface of the die, including:

[0042] Use a sticky blue film to simultaneously grab all the bare wafers from the second surface of the wafer;

[0043] Each die is sequentially picked up from the second surface of the die, including:

[0044] Use a sticky blue film or a vacuum nozzle to sequentially pick up each die from the second surface of the die.

[0045] Secondly, the present invention provides a bonding structure for a bare die and a wafer, wherein the bonding structure for the bare die and the wafer is prepared by the bonding method for a bare die and a wafer provided in any embodiment of the present invention.

[0046] Thirdly, the present invention provides a method for fabricating a semiconductor chip, wherein the method for fabricating a semiconductor chip includes the bonding method of a bare die and a wafer provided in any embodiment of the present invention.

[0047] The technical solution of this invention involves dicing a wafer into multiple bare dies, then simultaneously grasping all the dies from their second surface (i.e., from the fifth surface of the wafer to be diced), placing them on a carrier disk with their first bonding layer facing down. The carrier disk can be cleaned through processes such as acid washing and water washing to ensure its surface is free of any impurities. Each die to be bonded to the carrier wafer is then sequentially grasped from its second surface and aligned to its corresponding position on the carrier wafer, thus completing the bonding between the die and the carrier wafer without needing to flip the die before placing it on the carrier wafer. In this invention, the dies are grasped from their second surface during the grasping process, avoiding contact with the first bonding layer on the first surface of the die. Furthermore, the carrier disk that comes into contact with the first bonding layer on the first surface of the die during bonding is free of any impurities, thus preventing particle defects or other contamination from being introduced to the bonding surface of the die. This invention effectively improves the bonding quality between the die and the carrier wafer, further increasing product yield.

[0048] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 This is a flowchart of a bonding method between a bare die and a wafer provided in an embodiment of the present invention;

[0051] Figures 2-5This is a schematic diagram of the structure corresponding to each step in a bonding method for a bare die and a wafer provided in an embodiment of the present invention;

[0052] Figure 6 This is a schematic diagram of a bonding interface between a bare die and a carrier wafer provided in an embodiment of the present invention;

[0053] Figure 7 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention;

[0054] Figure 8 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention;

[0055] Figure 9 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention;

[0056] Figures 10-13 This is a schematic diagram of some steps in another bonding method for a bare die and a wafer provided in an embodiment of the present invention;

[0057] Figure 14 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention;

[0058] Figure 15 This is a schematic diagram of some steps in another bonding method for a bare die and a wafer provided in an embodiment of the present invention;

[0059] Figure 16 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention;

[0060] Figure 17 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention;

[0061] Figures 18-20 This is a schematic diagram of some steps in another bonding method for a bare die and a wafer provided in an embodiment of the present invention;

[0062] Figure 21 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention;

[0063] Figure 22 This is a flowchart of another bonding method for a bare die and a wafer provided in an embodiment of the present invention. Detailed Implementation

[0064] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0065] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0066] Figure 1 This is a flowchart of a bonding method between a bare die and a wafer provided in an embodiment of the present invention. Figures 2-5 This is a schematic diagram of the structure corresponding to each step in a bonding method for a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the bonding methods include:

[0067] S100: The wafer to be cut is cut into multiple bare dies; each bare die includes a first surface and a second surface opposite to the first surface, and the first surface of the bare die is provided with a first bonding layer.

[0068] Specifically, Figure 2 This is a schematic diagram of a wafer 10 to be cut, which has a full-surface bonding layer 20 provided in an embodiment of the present invention. Figure 3 yes Figure 2 A schematic diagram of the cross-sectional structure after cutting along the dotted line AB, as shown below. Figure 2 and Figure 3 As shown, a wafer 10 to be diced is first provided. The wafer 10 can be a wafer that has completed front-end processing (FEOL), mid-end processing (MEOL), and back-end processing (BEOL). That is, the wafer 10 to be diced can include electronic devices such as transistors, capacitors, and resistors. The wafer 10 to be diced can also include interconnect layers, dielectric layers, and other film layers, and interconnection between devices is achieved through interconnect layers. The wafer 10 to be diced can include a fourth surface 101 and a fifth surface 102. The fourth surface 101 of the wafer 10 to be diced can be provided with a full-surface bonding layer 20.

[0069] The wafer 10 to be diced is diced into multiple dies 11. During the dicing of the wafer 10, the full-surface bonding layer 20 of the fourth surface 101 of the wafer 10 is also diced. The die 11 may include a first surface 111 and a second surface 112. After the front bonding layer 20 is diced, it can serve as a first bonding layer 21 located on the first surface 111 of the die 11. The die 11 can be bonded to the carrier wafer through the first bonding layer 21.

[0070] S110: Grab all the bare dies from the second surface of the bare die at the same time, and place all the bare dies on the surface of the carrier disk with the first bonding layer of all the bare dies facing the carrier disk.

[0071] Specifically, such as Figures 2-4 As shown, a carrier disk 12 is provided. The carrier disk 12 can be cleaned by acid washing, water washing and other cleaning processes to ensure that the surface of the carrier disk 12 is free of any impurities.

[0072] After the wafer 10 to be diced is divided into multiple bare dies 11, all the bare dies 11 are simultaneously picked up from the second surface 112 of the multiple bare dies 11, that is, from the fifth surface 102 of the wafer 10 to be diced, and placed on the carrier disk 12 with the first bonding layer 21 of all the bare dies 11 facing downwards. The first bonding layer 21 of all the bare dies 11 is in contact with the surface of the carrier disk 12, and the second surface 112 of all the bare dies 11 is facing upwards.

[0073] S120: Grab each die sequentially from the second surface of the die and place the die on the carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer.

[0074] Specifically, such as Figure 5 As shown, a carrier wafer 13 is provided. The carrier wafer 13 can be placed on a bonding device. The carrier wafer 13 is a wafer that needs to be bonded to the bare die 11. The carrier wafer 13 can be a wafer that has undergone front-end processing (FEOL), mid-end processing (MEOL), and back-end processing (BEOL). Alternatively, the carrier wafer 13 can be a silicon wafer that has not undergone any fabrication process. The front-end processing (FEOL), mid-end processing (MEOL), and back-end processing (BEOL) can be performed on the carrier wafer 13 after bonding with the bare die 11. The carrier wafer 13 may include a third surface 103 and a sixth surface 104. The third surface 103 of the carrier wafer 13 may be provided with a second bonding layer 14.

[0075] Each die 11 that needs to be bonded to the carrier wafer 13 is sequentially picked up from the second surface 112 of the die 11 and placed on the corresponding position on the carrier wafer 13 by alignment. Specifically, the first bonding layer 21 of the die 11 is aligned with the second bonding layer 14 of the third surface 103 of the carrier wafer 13 when the die 11 is placed on the corresponding position on the carrier wafer 13.

[0076] S130: Bond the bare die to the carrier wafer.

[0077] Specifically, such as Figure 5 As shown, after placing all the bare dies 11 that need to be bonded to the carrier wafer 13 at the corresponding positions on the carrier wafer 13, the bonding equipment performs the bonding operation on the bare dies 11 and the carrier wafer 13.

[0078] Figure 6 This is a schematic diagram of a bonding interface between a bare die and a carrier wafer provided in an embodiment of the present invention. Figure 6 It can be seen that there are no bubbles at the bonding interface between the bare die 11 and the carrier wafer 13, indicating that no particle defects were introduced into the bonding surface of the bare die 11 during the bonding process, which improved the overall wafer reconstruction yield after the bare die 11 and the carrier wafer 13 were bonded.

[0079] The technical solution of this invention involves dicing the wafer 10 to be diced into multiple bare dies 11, then simultaneously grasping all the bare dies 11 from their second surface 112 (i.e., from the fifth surface 102 of the wafer 10 to be diced), placing all the bare dies 11 with their first bonding layer 21 facing downwards on a carrier disk 12. The carrier disk 12 can be cleaned through processes such as acid washing and water washing to ensure that its surface is free of any impurities. Then, each bare die 11 that needs to be bonded to a carrier wafer 13 is sequentially grasped from its second surface 112, and aligned and placed on the corresponding position on the carrier wafer 13, thereby completing the bonding between the bare die 11 and the carrier wafer 13 without flipping the bare die 11 before placing it on the carrier wafer 13. In the technical solution of this invention, during the gripping of the bare die 11, it is gripped from the second surface 112 of the bare die 11, without contacting the first bonding layer 21 located on the first surface 111 of the bare die 11. Furthermore, the carrier disk 12, which contacts the first bonding layer 21 on the first surface 111 of the bare die 11 during the bonding process, is free from any impurities. Therefore, the bonding surface of the bare die 11 will not introduce contamination such as particle defects. This invention effectively improves the bonding quality between the bare die 11 and the carrier wafer 13, further improving product yield.

[0080] Optionally, based on the above embodiments, Figure 7 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the bonding methods include:

[0081] S200: The wafer to be cut is cut into multiple bare dies; each bare die includes a first surface and a second surface opposite to the first surface, and the first surface of the bare die is provided with a first bonding layer.

[0082] S210: Provide a carrier tray, clean the carrier tray, and fix the carrier tray on the carrier tray holder.

[0083] Specifically, such as Figure 4 As shown, a carrier disk 12 is provided; exemplarily, the carrier disk 12 can be a silicon carrier disk. The entire carrier disk 12 is cleaned through processes such as acid washing and water washing to ensure that the surface of the carrier disk 12 is free of any impurities. For example, the carrier disk 12 can be cleaned using the RCA standard.

[0084] S220: The carrier disk is cut into multiple carrier areas, and each carrier area corresponds to a bare die.

[0085] Specifically, such as Figures 2-4 As shown, the carrier tray 11, fixed on the carrier tray holder, is cut into multiple bearing areas 121 according to the dimensions of each bare wafer 11, with vertical sidewalls and flat surfaces for placing the bare wafers 11. Each bearing area 121 can hold one bare wafer 11, and the size of the bearing area 121 can be the same as the size of the corresponding bare wafer 11, or the size of the bearing area 121 can be slightly larger than the size of the corresponding bare wafer 11.

[0086] S230: Clean the cut carrier disc.

[0087] Specifically, such as Figure 4 As described above, after the carrier disk 12 is cut into multiple carrier areas 121, the carrier disk 12 is then cleaned. For example, the carrier disk 12 can be cleaned according to RCA standards to ensure that the carrier disk 12 is free of any impurities or contamination.

[0088] S240: Grab all the bare dies from the second surface of the die simultaneously and place all the bare dies in the corresponding carrier area with the first bonding layer of all the bare dies facing the carrier disk.

[0089] Specifically, such as Figures 2-4 As shown, after the wafer 10 to be diced is divided into multiple bare dies 11, all the bare dies 11 are simultaneously picked up from the second surface 112 of the multiple bare dies 11, that is, from the fifth surface 102 of the wafer 10 to be diced, so that the first bonding layer 21 of all the bare dies 11 is facing down on the corresponding bearing area 121 of the carrier 12. The first bonding layer 21 of all the bare dies 11 is in contact with the surface of the corresponding bearing area 121 of the carrier 12, and the second surface 112 of all the bare dies 11 is facing up.

[0090] S250: Each die is sequentially picked up from the second surface of the die and placed on the carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer.

[0091] S260: Bonds the die to the carrier wafer.

[0092] Optionally, based on the above embodiments, Figure 8 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the bonding methods include:

[0093] S300: The wafer to be cut is cut into multiple bare dies; each bare die includes a first surface and a second surface opposite to the first surface, and the first surface of the bare die is provided with a first bonding layer.

[0094] S310: Grab all the bare dies from the second surface of the die at the same time, and place all the bare dies on the surface of the silicon carrier with the first bonding layer of all the bare dies facing the silicon carrier.

[0095] Specifically, such as Figures 2-4 As shown, the carrier disk 12 can be a silicon carrier disk, which can be subjected to RCA standard cleaning. After the silicon carrier disk is cut into multiple carrier areas 121, it is cleaned again. For example, the silicon carrier disk can be subjected to RCA standard cleaning again to ensure that the silicon carrier disk is free of any impurities. In the technical solution of this embodiment of the invention, the carrier disk 12 is made of silicon material, and the standard RCA cleaning of the silicon carrier disk can achieve the ultra-clean standard required by the semiconductor industry. All bare dies 11 are simultaneously picked up from the second surface 112 of the bare die 11, and all bare dies 11 are placed on the corresponding carrier areas 121 with the first bonding layer 21 of all bare dies 11 facing the carrier disk 12. Since the silicon carrier disk has reached the ultra-clean standard, after the first bonding layer 21 of the bare die 11 comes into contact with the surface of the silicon carrier disk, the bonding surface of the bare die 11 will not introduce any impurities, thereby effectively improving the bonding quality between the bare die 11 and the carrier wafer 13, and further improving the product yield.

[0096] S320: Grab each die sequentially from the second surface of the die and place the die on the carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer.

[0097] S330: Bonds the die to the carrier wafer.

[0098] Optionally, based on the above embodiments, Figure 9 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention. Figures 10-13This is a schematic diagram of some steps in another bonding method for a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 9 As shown, the bonding methods include:

[0099] S400: A first dielectric layer is formed on the fourth surface of the wafer to be diced; the fourth surface of the wafer to be diced includes a plurality of first metal pads.

[0100] Specifically, such as Figure 10 As shown, after the front-end process (FEOL), middle-end process (MEOL) and back-end process (BEOL) are completed, the fourth surface 101 of the wafer to be cut 10 may include a plurality of first metal pads 15. After the wafer to be cut 10 is subsequently cut into a plurality of bare dies 11, the first metal pad 15 of the first surface 111 of each bare die 11 may be the contact point for the bare die 11 to connect with the outside.

[0101] A first dielectric layer 201 is formed on the fourth surface 101 of the wafer 10 to be cut. For example, the first dielectric layer 201 may include a silicon dioxide layer.

[0102] S410: Etch the first dielectric layer to form a plurality of first vias, each of which corresponds to a first metal pad and exposes the first metal pad.

[0103] Specifically, such as Figure 11 As shown, the first dielectric layer 201 is etched to form a first through hole 203. The first through hole 203 can be set one-to-one with the first metal pad 15, and the first through hole 203 exposes the corresponding first metal pad 15.

[0104] S420: A first bonding metal is formed in the first through hole; the side of the first bonding metal away from the fourth surface is flush with the side of the first dielectric layer away from the fourth surface; the first dielectric layer and the first bonding metal form a full-surface bonding layer.

[0105] Specifically, such as Figure 12 As shown, a first bonding metal 202 is deposited within the first via 203. For example, the first bonding metal 202 may include copper. After forming the first bonding metal 202, the side of the first dielectric layer 201 and the first bonding metal 202 away from the wafer 10 to be diced can be chemically mechanically polished, so that the side of the first bonding metal 202 away from the fourth surface 101 is flush with the side of the first dielectric layer 201 away from the fourth surface 101. The first dielectric layer 201 located on the fourth surface 101 of the wafer 10 to be diced and all the first bonding metals 202 can constitute a full-surface bonding layer 20.

[0106] S430: The wafer to be cut and the full-surface bonding layer are cut into multiple bare dies; the first dielectric layer and the first bonding metal disposed on the first surface of the bare die serve as the first bonding layer.

[0107] Specifically, such as Figure 13 As shown, the entire bonding layer 20 of the wafer 10 to be cut and the fourth surface 101 is then cut to cut the wafer 10 into multiple bare dies 11. The first dielectric layer 201 of the first surface 111 of the bare die 11 and multiple first bonding metals 202 constitute the first bonding layer 21. Each bare die 11 can achieve mixed bonding with the carrier wafer through the first bonding layer 21.

[0108] S440: Grab all the bare dies from the second surface of the die simultaneously and place all the bare dies on the surface of the carrier disk with the first bonding layer of all the bare dies facing the carrier disk.

[0109] S450: Each die is sequentially picked up from the second surface of the die and placed on the carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer.

[0110] S460: Bonds the die to the carrier wafer.

[0111] Optionally, based on the above embodiments, Figure 14 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention. Figure 15 This is a schematic diagram of some steps in another bonding method for a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 14 As shown, the preparation method includes:

[0112] S500: A first dielectric layer is formed on the fourth surface of the wafer to be cut; the fourth surface of the wafer to be cut includes a plurality of first metal pads.

[0113] S510: Etch the first dielectric layer to form a plurality of first vias, each of which corresponds to a first metal pad and exposes the first metal pad.

[0114] S520: A first bonding metal is formed in the first through hole; the side of the first bonding metal away from the fourth surface is flush with the side of the first dielectric layer away from the fourth surface; the first dielectric layer and the first bonding metal form a full-surface bonding layer.

[0115] S530: Thinning treatment is performed on the fifth surface of the wafer to be cut; the fifth surface is set opposite to the fourth surface.

[0116] Specifically, such as Figure 15As shown, after forming a full-surface bonding layer 20 on the fourth surface 101 of the wafer 10 to be cut, the fifth surface 102 of the wafer 10 to be cut is thinned. For example, the overall thickness of the wafer 10 to be cut can be reduced to 200um.

[0117] S540: Place the wafer to be cut on the wafer holder and form a protective layer on the side of the first dielectric layer and the first bonding metal away from the fourth surface.

[0118] Specifically, such as Figure 15 As shown, the thinned wafer 10 is fixed on a wafer holder. The wafer holder can surround the sides of the wafer 10 to be cut, fixing the wafer 10 in place. After the wafer 10 is subsequently cut into multiple dies 11, the wafer holder can keep the multiple dies 11 in place, and the multiple dies 11 still form the shape of the wafer 10 to be cut. A protective layer 30 is formed on the side of the first dielectric layer 201 and the first bonding metal 202 away from the fourth surface 101. When the wafer 10 is cut, the protective layer 30 can protect the first dielectric layer 201 and the first bonding metal 202 from damage.

[0119] S550: The wafer to be cut and the full-surface bonding layer are cut into multiple bare dies; the first dielectric layer and the first bonding metal disposed on the first surface of the bare die serve as the first bonding layer.

[0120] S560: Remove the protective layer.

[0121] S570: Plasma activation treatment is performed on the side of the first dielectric layer and the first bonded metal away from the fourth surface.

[0122] Specifically, such as Figure 13 As shown, after removing the first protective layer, plasma activation is performed on the side of the first dielectric layer 201 and the first bonding metal 202 away from the fourth surface 101. The plasma activation process can clean and activate the side of the first dielectric layer 201 and the first bonding metal 202 away from the fourth surface 101, increase their surface energy, and further improve the bonding quality between the side of the first dielectric layer 201 and the first bonding metal 202 away from the fourth surface 101 and the supporting wafer.

[0123] S580: Clean the first dielectric layer and the side of the first bonded metal away from the fourth surface.

[0124] Specifically, such as Figure 13As shown, the side of the first dielectric layer 201 and the first bonding metal 202 away from the fourth surface 101 is cleaned to remove various contaminants from the side of the first dielectric layer 201 and the first bonding metal 202 away from the fourth surface 101, thereby ensuring the bonding quality between the side of the first dielectric layer 201 and the first bonding metal 202 away from the fourth surface 101 and the carrier wafer.

[0125] Optionally, based on the above embodiments, Figure 16 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 16 As shown, the bonding methods include:

[0126] S600: Laser grooving is performed on the wafer to be cut.

[0127] Specifically, such as Figure 1 and Figure 2 As shown, a laser can be used to scan along the scribe lines between the bare dies 11 in the wafer 10 to be cut, thereby realizing laser grooving on the wafer 10 to be cut.

[0128] S610: Using plasma cutting technology, the wafer to be cut is cut in the laser grooving area, and the wafer to be cut is cut into multiple bare dies; the bare die includes a first surface and a second surface opposite to the first surface, and the first surface of the bare die is provided with a first bonding layer.

[0129] Specifically, such as Figure 1 and Figure 2 As shown, deep reactive ion etching (DRIE) is used to deeply etch along the laser-grooved path, completely separating the bare die 11 from the wafer 10 to be cut. Plasma dicing is a dry etching process with narrow kerfs, smooth sidewalls, and no mechanical stress.

[0130] S620: Grab all the bare dies from the second surface of the die at the same time, and place all the bare dies on the surface of the carrier disk with the first bonding layer of all the bare dies facing the carrier disk.

[0131] S630: Each die is sequentially picked up from the second surface of the die and placed on the carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer.

[0132] S640: Bonds the die to the carrier wafer.

[0133] Optionally, based on the above embodiments, Figure 17 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention. Figures 18-20This is a schematic diagram of some steps in another bonding method for a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 17 As shown, the bonding methods include:

[0134] S700: The wafer to be cut is cut into multiple bare dies; each bare die includes a first surface and a second surface opposite to the first surface, and the first surface of the bare die is provided with a first bonding layer.

[0135] S710: Grab all the bare dies from the second surface of the die simultaneously and place all the bare dies on the surface of the carrier disk with the first bonding layer of all the bare dies facing the carrier disk.

[0136] S720: A second dielectric layer is formed on the third surface of the wafer; the third surface of the wafer includes a plurality of second metal pads.

[0137] Specifically, such as Figure 18 As shown, the third surface 103 of the carrier wafer 13 may include a plurality of second metal pads 16, which may be contact points for connecting the carrier wafer 13 to the outside. A second dielectric layer 141 is formed on the third surface 103 of the carrier wafer 13. Exemplarily, the second dielectric layer 141 may include a silicon dioxide layer.

[0138] S730: Etch the second dielectric layer to form multiple second vias, each of which corresponds to a second metal pad and exposes the second metal pad.

[0139] Specifically, such as Figure 19 As shown, the second dielectric layer 141 is etched to form a second via 143. The second via 143 can be set one-to-one with the second metal pad 16, and the second via 143 exposes the corresponding second metal pad 16.

[0140] S740: A second bonding metal is formed in the second through hole; the side of the second bonding metal away from the third surface is flush with the side of the second dielectric layer away from the third surface; the second dielectric layer and the second bonding metal together form the second bonding layer.

[0141] Specifically, such as Figure 20 As shown, a second bonding metal 142 is deposited within the second via 143. Exemplarily, the second bonding metal 142 may include copper. After forming the second bonding metal 142, the sides of the second dielectric layer 141 and the second bonding metal 142 away from the supporting wafer 13 can be chemically mechanically polished, such that the side of the second bonding metal 142 away from the third surface 103 is flush with the side of the second dielectric layer 141 away from the third surface 103. The second dielectric layer 141 located on the third surface 103 of the supporting wafer 13 and all the second bonding metals 142 can constitute the second bonding layer 14.

[0142] like Figure 13 and Figure 20 As shown, when the bare die 11 is bonded to the carrier wafer 13, the first dielectric layer 201 is bonded to the second dielectric layer 141, and the first bonding metal 202 is bonded to the second bonding metal 142, thereby realizing the hybrid bonding of the bare die 11 and the carrier wafer 13.

[0143] S750: Each die is sequentially picked up from the second surface of the die and placed on the carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer.

[0144] S760: Bonds the die to the carrier wafer.

[0145] Optionally, based on the above embodiments, Figure 21 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 21 As shown, the bonding methods include:

[0146] S800: The wafer to be cut is cut into multiple bare dies; each bare die includes a first surface and a second surface opposite to the first surface, and the first surface of the bare die is provided with a first bonding layer.

[0147] S810: Grab all the bare dies from the second surface of the die simultaneously and place all the bare dies on the surface of the carrier disk with the first bonding layer of all the bare dies facing the carrier disk.

[0148] S820: A second dielectric layer is formed on the third surface of the wafer; the third surface of the wafer includes a plurality of second metal pads.

[0149] S830: Etch the second dielectric layer to form multiple second vias, each of which corresponds to a second metal pad and exposes the second metal pad.

[0150] S840: A second bonding metal is formed in the second through hole; the side of the second bonding metal away from the third surface is flush with the side of the second dielectric layer away from the third surface; the second dielectric layer and the second bonding metal together form the second bonding layer.

[0151] S850: Plasma activation treatment is performed on the side of the second bonding metal and the second dielectric layer away from the third surface.

[0152] Specifically, such as Figure 13 and Figure 20As shown, the side of the second bonding metal 142 and the second dielectric layer 141 away from the third surface 103 is subjected to plasma activation treatment. The plasma activation treatment can clean and activate the side of the second bonding metal 142 and the second dielectric layer 141 away from the third surface 103, increase its surface energy, and further improve the bonding quality between the side of the second bonding metal 142 and the second dielectric layer 141 away from the third surface 103 and the first dielectric layer 201 of the bare die 11 and the side of the first bonding metal 202 away from the fourth surface 101.

[0153] S860: Clean the side of the second bonding metal and the second dielectric layer away from the third surface.

[0154] Specifically, such as Figure 13 and Figure 20 As shown, the side of the second bonding metal 142 and the second dielectric layer 141 away from the third surface 103 is cleaned to remove various contaminants from the side of the second bonding metal 142 and the second dielectric layer 141 away from the third surface 103, thereby ensuring the bonding quality between the side of the second bonding metal 142 and the second dielectric layer 141 away from the third surface 103 and the first dielectric layer 201 of the bare die 11 and the side of the first bonding metal 202 away from the fourth surface 101.

[0155] S870: Each die is sequentially picked up from the second surface of the die and placed on the carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer.

[0156] S880: Bonds the die to the carrier wafer.

[0157] Optionally, based on the above embodiments, Figure 22 This is a flowchart of another bonding method between a bare die and a wafer provided in an embodiment of the present invention, as shown below. Figure 22 As shown, the bonding methods include:

[0158] S900: The wafer to be cut is cut into multiple bare dies; each bare die includes a first surface and a second surface opposite to the first surface, and the first surface of the bare die is provided with a first bonding layer.

[0159] S910: Use a sticky blue film to simultaneously grab all the bare dies from the second surface of the die; and place all the bare dies on the surface of the carrier disk with the first bonding layer of all the bare dies facing the carrier disk.

[0160] Specifically, such as Figures 2-4As shown, after the wafer 10 to be diced is cut into multiple bare dies 11, tools such as adhesive blue film or rubber suction nozzles are used to simultaneously pick up all the bare dies 11 from their second surface 112, i.e., from their fifth surface 102, so that the first bonding layer 21 of all the bare dies 11 is facing down on the carrier tray 12. The first bonding layer 21 of all the bare dies 11 is in contact with the surface of the carrier tray 12, and the second surface 112 of all the bare dies 11 is facing up.

[0161] S920: Each die is sequentially picked up from the second surface of the die using an adhesive blue film or a vacuum nozzle. The die is then placed on the carrier wafer with its first bonding layer facing the third surface of the carrier wafer, where a second bonding layer is disposed.

[0162] Specifically, such as Figure 5 As shown, tools such as adhesive blue film or rubber nozzles are used to sequentially pick up each die 11 that needs to be bonded to the carrier wafer 13 from the second surface 112 of the die 11, and place the die 11 on the corresponding position of the carrier wafer 13 by alignment. Specifically, the first bonding layer 21 of the die 11 faces the second bonding layer 14 of the third surface 103 of the carrier wafer 13 when placing the die 11 on the corresponding position of the carrier wafer 13.

[0163] In the technical solution of this invention embodiment, when it is necessary to grasp the bare die 11 during the bonding process, a tool such as an adhesive blue film or a rubber suction nozzle is used to grasp it from the second surface 112 of the bare die 11, so as to avoid the adhesive blue film or rubber suction nozzle coming into contact with the bonding surface of the bare die 11.

[0164] S930: Bonds the bare die to the carrier wafer.

[0165] This invention provides a bonding structure between a bare die and a wafer, wherein the bonding structure is prepared by the bonding method of the bare die and wafer provided in any of the above embodiments of this invention, and has the beneficial effects of the bonding method of the bare die and wafer provided in any of the above embodiments of this invention.

[0166] This invention provides a method for fabricating a semiconductor chip, wherein the method includes the bonding method of bare die and wafer provided in any of the above embodiments of this invention, and has the beneficial effects of the bonding method of bare die and wafer provided in any of the above embodiments of this invention.

[0167] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0168] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A hybrid bonding method of a die and a wafer, characterized by, The method comprises the following steps: cutting a wafer to be cut into a plurality of dies; the dies comprise a first surface and a second surface opposite to the first surface, and the first surface of the dies is provided with a first bonding layer; simultaneously grabbing all the dies from the second surface of the dies and placing all the dies on the surface of a carrier wafer with the first bonding layer of all the dies facing the carrier wafer; sequentially grabbing each of the dies from the second surface of the dies and placing the dies on a third surface of a carrier wafer with the first bonding layer of the dies facing the third surface of the carrier wafer; the third surface of the carrier wafer is provided with a second bonding layer; bonding the dies and the carrier wafer.

2. The die and wafer hybrid bonding method according to claim 1, wherein, Before simultaneously grabbing all the dies from the second surface of the dies and placing all the dies on the surface of the carrier wafer with the first bonding layer of all the dies facing the carrier wafer, the method further comprises the following steps: providing the carrier wafer, cleaning the carrier wafer, and fixing the carrier wafer on a carrier wafer fixing frame; cutting the carrier wafer into a plurality of carrier regions, wherein the carrier regions correspond to the dies one by one; cleaning the carrier wafer after cutting; simultaneously grabbing all the dies from the second surface of the dies and placing all the dies on the surface of the carrier wafer with the first bonding layer of all the dies facing the carrier wafer, comprising: simultaneously grabbing all the dies from the second surface of the dies and placing all the dies on the corresponding carrier regions with the first bonding layer of all the dies facing the carrier regions.

3. The die and wafer hybrid bonding method according to claim 1, wherein, simultaneously grabbing all the dies from the second surface of the dies and placing all the dies on the surface of the carrier wafer with the first bonding layer of all the dies facing the carrier wafer, comprising: simultaneously grabbing all the dies from the second surface of the dies and placing all the dies on the surface of a silicon carrier wafer with the first bonding layer of all the dies facing the silicon carrier wafer.

4. The die and wafer hybrid bonding method of claim 1, wherein, Before cutting the wafer to be cut into a plurality of dies, the method further comprises the following steps: forming a first dielectric layer on a fourth surface of the wafer to be cut; the fourth surface of the wafer to be cut comprises a plurality of first metal pads; etching the first dielectric layer to form a plurality of first through holes, wherein the first through holes correspond to the first metal pads one by one, and the first through holes expose the first metal pads; forming a first bonding metal in the first through holes; one side of the first bonding metal away from the fourth surface is flush with one side of the first dielectric layer away from the fourth surface; the first dielectric layer and the first bonding metal serve as an integral bonding layer; cutting the wafer to be cut into a plurality of dies; the dies comprise a first surface and a second surface opposite to the first surface, and the first surface of the dies is provided with a first bonding layer, comprising: cutting the wafer to be cut and the integral bonding layer into a plurality of dies; the first dielectric layer and the first bonding metal provided on the first surface of the dies serve as the first bonding layer.

5. The die and wafer hybrid bonding method according to claim 4, wherein, After forming the first bonding metal in the first through holes, the method further comprises the following steps: a fifth surface of the wafer to be cut is thinned; the fifth surface is arranged opposite to the fourth surface; the wafer to be cut is placed on a wafer fixing frame, and a protective layer is formed on a side of the first dielectric layer and the first bonding metal away from the fourth surface; after the wafer to be cut and the full-area bonding layer are cut into a plurality of dies, the method further comprises: removing the protective layer; the side of the first dielectric layer and the first bonding metal away from the fourth surface is subjected to a plasma activation treatment; the side of the first dielectric layer and the first bonding metal away from the fourth surface is subjected to a cleaning treatment.

6. The die and wafer hybrid bonding method of claim 1, wherein, cutting a wafer to be cut into a plurality of dies, comprising: laser grooving the wafer to be cut; cutting the wafer to be cut in the laser-grooved region by using a plasma cutting technique.

7. The die and wafer hybrid bonding method of claim 1, wherein, grabbing each of the dies from the second surface of the die in sequence, and placing the dies on a carrier wafer with the first bonding layer of the die facing the third surface of the carrier wafer before the dies are placed on the carrier wafer, comprising: forming a second dielectric layer on the third surface of the carrier wafer; the third surface of the carrier wafer comprises a plurality of second metal pads; etching the second dielectric layer to form a plurality of second through holes, the second through holes corresponding one-to-one to the second metal pads, and the second through holes exposing the second metal pads; forming a second bonding metal in the second through holes; a side of the second bonding metal away from the third surface is flush with a side of the second dielectric layer away from the third surface; the second dielectric layer and the second bonding metal serve as the second bonding layer.

8. The die and wafer hybrid bonding method according to claim 7, wherein, after the second bonding metal is formed in the second through holes, the method further comprises: subjecting the second bonding metal and the side of the second dielectric layer away from the third surface to a plasma activation treatment; subjecting the second bonding metal and the side of the second dielectric layer away from the third surface to a cleaning treatment.

9. The die and wafer hybrid bonding method of claim 1, wherein, grabbing all the dies from the second surface of the die simultaneously, comprising: grabbing all the dies from the second surface of the die simultaneously using an adhesive blue film; grabbing each of the dies from the second surface of the die in sequence, comprising: grabbing each of the dies from the second surface of the die in sequence using an adhesive blue film or a vacuum suction nozzle.

10. A method of manufacturing a semiconductor chip, characterized by, a hybrid bonding method comprising the die and the wafer according to any one of claims 1-9.

Images