An on-chip adjustable segmented linear quantization analog-to-digital converter based on memcapacitor array

Abstract

The application discloses an on-chip adjustable segmented linear quantization analog-digital converter based on a memcapacitor array, which comprises a memcapacitor array, an input signal conversion circuit, a control circuit, a linear quantization circuit and an on-chip adjustment circuit, the memcapacitor array is used for constructing a nonlinear characteristic according to a memcapacitor memory value, determining a nonlinear segment where an input signal is located and providing a reference voltage for the linear quantization circuit; the input signal conversion circuit is used for receiving and sampling an original input signal; the control circuit is used for controlling quantization, buffering or outputting digital codes in a quantization process by using a logic circuit; the linear fine quantization circuit is used for receiving the reference voltage from the memcapacitor array and performing uniform quantization on the input signal in a segment; and the on-chip adjustment circuit is used for implementing gating adjustment on the memcapacitor array; and the transfer characteristic can be freely regulated according to specific application scenarios and accuracy requirements, so that an ideal effect can be obtained.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and more particularly to an on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as a bridge between the analog and digital worlds, converting analog signals with continuous time and values ​​into discrete digital signals. ADCs are mainly classified into several types: Flash, SAR, Pipeline, and Sigma-Delta, each suitable for different application scenarios and accuracy requirements. Among them, SAR ADCs utilize circuitry to achieve successive approximations of signal magnitudes, enabling medium to high accuracy with relatively few circuit resources. Furthermore, due to the fact that most of their components are digital circuits, their power consumption is relatively low, making them widely used in various sensors.

[0003] Traditional ADCs mostly employ uniform quantization, where the input signal is uniformly distributed across the full-scale range (FSR). However, in some applications, such as quantizing neuronal electrical signals, temperature signals, and speech signals, the amplitude of the signal of interest is not uniformly distributed but rather concentrated in a small portion of the range in a specific manner. If uniform quantization is used, the conversion accuracy in data-dense regions will be low, and the quantization noise will be excessive. In sparse regions, although the quantization noise is less, the amount of data is also less, resulting in low conversion efficiency. For example, the electrical signal of human nerve cells mainly consists of a large-amplitude effective signal and a small-amplitude ineffective part. If uniform quantization is still used, the high-amplitude effective signal will be poorly reproduced, and the low-amplitude ineffective part will be assigned useless quantization levels, leading to a decrease in signal-to-noise ratio. Piecewise linear ADCs achieve a piecewise approximation of the nonlinear transfer characteristics, making them more suitable for quantizing signals with non-uniform amplitude distributions. However, the transfer characteristics of existing piecewise linear ADCs are determined by the circuit and cannot be freely adjusted. Summary of the Invention

[0004] To address the aforementioned problem of the inability to freely adjust the transfer characteristics of piecewise linear ADCs, the present invention aims to provide an on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array, which can freely adjust the transfer characteristics according to specific application scenarios and accuracy requirements to achieve ideal results.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] This invention provides an on-chip adjustable segmented linear quantization analog-to-digital converter based on a memory container array, including a memory container array, an input signal conversion circuit, a control circuit, a linear quantization circuit, and an on-chip adjustment circuit. The control circuit is connected to the input signal conversion circuit, the memory container array, and the linear quantization circuit. The on-chip adjustment circuit is connected to the memory container array, and the memory container array is connected to the linear quantization circuit.

[0007] The memory capacitor array uses multiple memory capacitors and switches to achieve charge redistribution, and constructs nonlinear characteristics based on the memory capacitance value of the memory capacitors to determine the nonlinear segment in which the input signal is located.

[0008] The input signal conversion circuit is used to receive and sample and hold the original input signal, and perform amplitude conversion;

[0009] The control circuit is used to buffer and store the quantized digital code, and to control the quantization process according to the preset algorithm of the logic circuit.

[0010] The linear quantization circuit is used to receive a reference voltage from the memory array and perform uniform quantization on the input signal within a nonlinear segment.

[0011] The on-chip adjustment circuit performs gating adjustment on the memory container array through the coordinated operation of the gating array and the address gating unit.

[0012] Preferably, the memory capacitor array and the linear quantization circuit constitute a two-stage quantization structure, wherein the memory capacitor array is the first stage, providing a reference voltage to the linear quantization circuit after determining the nonlinear segment in which the signal is located;

[0013] The linear quantization circuit is the second stage, and the number of linear quantization intervals is the same within each nonlinear segment. If the length of the nonlinear segment is... The number of linear quantization intervals is The linear quantization interval size is Their relationship satisfies:

[0014] ;

[0015] The linear quantization circuit determines the length of the nonlinear segment in which the signal is located using a reference voltage provided by the memory capacitor array. and divide it into A number of intervals of the same size.

[0016] Preferably, the on-chip adjustable piecewise linear quantization analog-to-digital converter based on memory container array uses a SAR structure to implement quantization, and the control circuit includes a comparator unit, a SAR register, a decoder, and an output register.

[0017] The comparator unit is used to connect to the input voltage and compare the reference voltage node with the input voltage;

[0018] The SAR register is used to temporarily store the digital code generated during the successive approximation process, realize the successive approximation algorithm and control the circuit to complete the successive approximation quantization.

[0019] The decoder is used to convert the binary segment bit digital code output by the SAR register into thermometer code for the memory container array;

[0020] The output register buffers and combines the high-order and low-order digital codes to control the output of the final digital code.

[0021] Preferably, the comparator unit contains one comparator; the SAR register outputs a total of M+N bits of digital code, where M is the number of bits in the segment code and N is the number of bits in the intra-segment code; the number of bits M in the segment code is equal to the number of bits in the non-uniform coarse quantization implemented based on the memory container array, and is located in the high M bits of the final digital code output by the output register; the number of bits N in the intra-segment code is equal to the number of bits in the uniform fine quantization implemented based on the linear quantization circuit, and is located in the low N bits of the final digital code output by the output register; the SAR register includes 2(M+N+1) D flip-flops; N and the number of linear quantization intervals. Relationship satisfaction .

[0022] Preferably, the memory container array includes a total of Each memory container comprises two memory container array units, and each memory container array unit includes... Each memory container is used to generate the starting reference voltage of the nonlinear segment interval where the signal is located. and endpoint reference voltage The relationship between the two is as follows: The linear quantization circuit receives a starting reference voltage. and endpoint reference voltage Determine the length of the nonlinear segment containing the input signal. It satisfies the following relationship: .

[0023] Preferably, the linear quantization circuit includes a binary capacitor digital-to-analog converter composed of (N+1) capacitors, wherein the reference voltage terminal of the binary capacitor digital-to-analog converter receives the starting reference voltage from the memory capacitor array. and endpoint reference voltage And under the control of the SAR register, a reference voltage is generated at the starting point. and endpoint reference voltage Feedback voltage used for successive approximation within the interval If the SAR register outputs the binary segment code as The feedback voltage generated by the linear quantization circuit for: .

[0024] Preferably, the on-chip adjustment circuit includes a gating array and an address gating unit; wherein the gating array is connected to the memory container array, and the address gating unit is connected to the gating array.

[0025] Preferably, the gating array unit includes One MOSFET.

[0026] This invention provides an on-chip adjustable piecewise linear quantization analog-to-digital converter (ADC) based on a memcell array. Through the on-chip adjustment circuit, the capacitance value of the memcell array can be finely adjusted, enabling the ADC to be adjusted to different quantization types when facing different types of signals. Appropriate quantization intervals can be applied to signals with different amplitude distributions. This not only reduces quantization noise in the main signal region of interest through non-uniform quantization, but also improves the versatility and configurability of the ADC. Specifically:

[0027] 1) The quantization circuit in this invention is a two-stage structure, with the first-stage memcell array providing a reference voltage for the second-stage linear quantization circuit. This enables the realization of equal-number, uniform-size linear quantization intervals within each nonlinear quantization interval, based on a low effective bit count nonlinear quantization, thereby achieving piecewise linear quantization.

[0028] 2) The two-level quantization circuit in this invention has a simple structure and can achieve piecewise linear quantization with approximately high-precision nonlinear quantization characteristics with fewer circuit components, and can achieve a larger dynamic range.

[0029] 3) In this invention, the first and second stages of the quantization circuit are relatively independent. The nonlinear quantization characteristics are determined by the first stage memory array. The segment endpoints can be flexibly changed by adjusting the memory array. The linear quantization interval within the nonlinear segment will be automatically redistributed by the second stage through the reference voltage, realizing flexible on-chip adjustment of segmented linear quantization. Attached Figure Description

[0030] Figure 1 This is a block diagram of the on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array as described in this invention;

[0031] Figure 2 This is a schematic diagram of the analog-to-digital converter described in a specific embodiment of the present invention;

[0032] Figure 3 This is a circuit schematic diagram of the analog-to-digital converter described in a specific embodiment of the present invention;

[0033] Figure 4 This is a timing diagram of the analog-to-digital converter described in a specific embodiment of the present invention;

[0034] Figure 5 This is the transfer characteristic curve corresponding to Embodiment 1 of the present invention;

[0035] Figure 6 This is the transfer characteristic curve corresponding to Embodiment 2 of the present invention;

[0036] Figure 7 This is the quantization result diagram corresponding to Embodiment 2 of the present invention;

[0037] Figure 8 This is the transfer characteristic curve corresponding to Embodiment 3 of the present invention;

[0038] Figure 9 This is the quantization result diagram corresponding to Embodiment 3 of the present invention;

[0039] Figure 10 This is the transfer characteristic curve corresponding to Embodiment 4 of the present invention;

[0040] Figure 11 This is the quantization result diagram corresponding to Embodiment 4 of the present invention;

[0041] Figure 12 This is the transfer characteristic curve corresponding to Embodiment 5 of the present invention;

[0042] Figure 13 This is the quantization result diagram corresponding to Embodiment 5 of the present invention;

[0043] Figure 14 This is the quantization result diagram corresponding to Embodiment 6 of the present invention;

[0044] Figure 15 This is the quantization result diagram corresponding to Embodiment 7 of the present invention;

[0045] Figure 16 This is the transfer characteristic curve corresponding to Comparative Example 1 of the present invention;

[0046] Figure 17 This is the transfer characteristic curve corresponding to Comparative Example 2 of the present invention;

[0047] Figure 18 This is the quantization result diagram corresponding to Comparative Example 2 of this invention. Detailed Implementation

[0048] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0049] Please see Figure 1This invention provides an on-chip adjustable segmented linear quantization analog-to-digital converter based on a memory container array, including a memory container array 100, an input signal conversion circuit 200, a control circuit 300, a linear quantization circuit 400, and an on-chip adjustment circuit 500. The control circuit 300 is connected to the input signal conversion circuit 200, the memory container array 100, and the linear quantization circuit 400. The on-chip adjustment circuit 500 is connected to the memory container array 100, and the memory container array 100 is connected to the linear quantization circuit 400.

[0050] The memory capacitor array 100 uses multiple memory capacitors and switches to achieve charge redistribution, and constructs nonlinear characteristics based on the memory capacitance value of the memory capacitors to determine the nonlinear segment in which the input signal is located.

[0051] The input signal conversion circuit 200 is used to receive and sample and hold the original input signal, and perform amplitude conversion;

[0052] The control circuit 300 is used to buffer and store the quantized digital code, and to control the quantization process according to the preset algorithm of the logic circuit.

[0053] The linear quantization circuit 400 is used to receive a reference voltage from the memory capacitor array 100 and perform uniform quantization within a nonlinear segment on the input signal.

[0054] The on-chip adjustment circuit 500 performs gating adjustment on the memory container array 100 through the coordinated operation of the gating array and the address gating unit.

[0055] In one embodiment, the memory capacitor array 100 and the linear quantization circuit 400 constitute a two-stage quantization structure. The memory capacitor array 100 is the first stage, providing a reference voltage to the linear quantization circuit 400 after determining the nonlinear segment in which the signal resides. The linear quantization circuit 400 is the second stage, where the number of linear quantization intervals is the same within each nonlinear segment. If the length of the nonlinear segment is... The number of linear quantization intervals is The linear quantization interval size is Their relationship satisfies: The linear quantization circuit 400 determines the length of the nonlinear segment in which the signal is located by using the reference voltage provided by the memory capacitor array 100. and divide it into A number of intervals of the same size.

[0056] Please see Figure 2The on-chip adjustable piecewise linear quantization analog-to-digital converter based on memory container array uses a SAR structure to implement quantization. In one embodiment, the control circuit 300 includes a comparator unit 301, a SAR register 302, a decoder 303, and an output register 304.

[0057] The comparator unit 301 is used to connect to the input voltage and compare the reference voltage node with the input voltage.

[0058] The SAR register 302 is used to temporarily store the digital code generated during the successive approximation process, realize the successive approximation algorithm and control the circuit to complete the successive approximation quantization.

[0059] The decoder 303 is used to convert the binary segment bit digital code output by the SAR register 302 into thermometer code for the memory container array 100.

[0060] The output register 304 buffers and combines the high-order and low-order digital codes to control the output of the final digital code.

[0061] In one embodiment, the comparator unit contains one comparator; the SAR register 302 outputs a total of M+N bits of digital code, where M is the number of bits in the segment code and N is the number of bits in the intra-segment code; the number of bits M in the segment code is equal to the number of bits in the non-uniform coarse quantization implemented based on the memory container array 100, and is located in the high M bits of the final digital code output by the output register 304; the number of bits N in the intra-segment code is equal to the number of bits in the uniform fine quantization implemented based on the linear quantization circuit 400, and is located in the low N bits of the final digital code output by the output register 304; the SAR register includes 2(M+N+1) D flip-flops; N and the number of linear quantization intervals. Relationship satisfaction ;

[0062] In one embodiment, the memory container array 100 includes a total of Each memory container comprises two memory container array units, and each memory container array has 100 units. Each memory container is used to generate the starting reference voltage of the nonlinear segment interval where the signal is located. and endpoint reference voltage The relationship between the two is as follows: The linear quantization circuit 400 receives a starting reference voltage. and endpoint reference voltage Determine the length of the nonlinear segment containing the input signal. It satisfies the following relationship: .

[0063] In one embodiment, the linear quantization circuit 400 includes a binary capacitor digital-to-analog converter composed of (N+1) capacitors, wherein the reference voltage terminal of the binary capacitor digital-to-analog converter receives a starting reference voltage from the memory capacitor array 100. and endpoint reference voltage And under the control of the SAR register, a reference voltage is generated at the starting point. and endpoint reference voltage Feedback voltage used for successive approximation within the interval If the SAR register outputs the binary segment code as The feedback voltage generated by the linear quantization circuit 400 for: .

[0064] In one embodiment, the on-chip adjustment circuit 500 includes a gating array and an address gating unit; wherein the gating array is connected to the memory container array 100, and the address gating unit is connected to the gating array.

[0065] In one embodiment, the gating array unit includes One MOSFET.

[0066] This embodiment provides an 8-bit on-chip adjustable piecewise linear quantization SAR analog-to-digital converter based on a memory container, and the implementation method is as follows: Figure 3 As shown.

[0067] exist Figure 3 In the middle, the binary capacitor digital-to-analog converter on the right, composed of capacitors, corresponds to the linear quantization circuit 400; the memory capacitor array 100 consists of two coarse quantization digital-to-analog converters, which are used to provide the segment start reference voltage for the fine quantization circuit. and paragraph end reference voltage Each coarse quantization digital-to-analog converter (DAC) consists of a memory capacitor, a switch, and a unity-gain buffer (UBG). The control circuit 300 consists of a decoder, a comparator, and a SAR logic. The SAR logic outputs an 8-bit binary code, where the high 4 bits are the segment code, which is converted into a thermometer code by the decoder to control the memory capacitor array to complete coarse quantization, generating the start and end voltages of the segment. The low 4 bits are the intra-segment code, which controls the fine quantization process. The sample-and-hold function of the input signal conversion circuit 200 is implemented by a capacitor array and a switch circuit. The on-chip adjustment circuit 500 consists of a gating array and an address gating. The gating array is composed of a MOS transistor array and is connected to the memory capacitor array 100. The address gating is connected to the gating array. When the DAC performs signal quantization, all the MOS transistors controlled by the address gating are in the on state. The MOS transistor array is only in the blocked state when the capacitance of the memory capacitor array needs to be adjusted.

[0068] In this embodiment, the encoding correspondence and the control rules of the switches used are as follows: The eight-bit binary code of the SAR register is B0 to B7 from the least significant bit to the most significant bit; among them, B4 to B7 are segment codes with a bit length M=4, which are converted into thermometer codes T1 to T16 by the decoder to control the switches of the memory array. When T1 to T16 are 0, the corresponding switch is connected to the negative terminal reference voltage of the circuit. When the value is 1, the switch is connected to the positive terminal of the circuit reference voltage. The input signal of the analog-to-digital converter described in this embodiment The range is from 0V to 1V, therefore Grounding is 0V. The relative voltage is 1V; B0 to B3 are segment codes with a bit depth N=4. When the value is 0, the corresponding switch is connected to... When taking 1, the corresponding switch is connected. The voltage level at the upper plate of the binary capacitor array in a linear quantization circuit. From the input signal The feedback voltage generated during the quantization process by the linear quantization circuit Decision, satisfaction .

[0069] The SAR register first samples the input signal. In this state, the coarse quantization level formed by the memory container array does not operate, and the switch... , , and Access .switch Input signal Since the SAR register outputs are all zero, all switches of the binary capacitor array in the linear quantization circuit are now connected to the input signal. At this point, let the total capacitance of the capacitor array in parallel be... Then the charge stored in the capacitor array at this time Charge is conserved during subsequent quantization, thereby enabling the sampling of the input signal.

[0070] After the input signal is sampled, signal quantization begins. , disconnect, , Access , disconnect, A unity-gain buffer is connected to form a two-stage analog-to-digital converter. SAR logic controls the circuit to quantize the signal from high to low bits using a successive approximation method. First, the memory capacitor array is controlled to complete coarse quantization. At this time, the upper plate of the binary capacitor array in the linear quantization circuit is floating, and the voltage level at this point is... The charge is ,have:

[0071] ;

[0072] And because of the conservation of charge In this embodiment ,have to:

[0073] ;

[0074] Therefore, in the coarse quantization process This is equal to the voltage generated by the memory capacitor array. With respect to the magnitude of the input signal The comparator determines the difference by making successive comparisons. The polarity of the signal can be used to determine the nonlinear segment interval in which the signal is located.

[0075] Once the 4-bit segment code is determined, the analog-to-digital converter enters the fine quantization stage. At this point, the capacitor array selects the appropriate input based on the B0~B3 output from the SARlogic. or If access is set The total capacitance at that location is Remaining access The total capacitance at that location is ,have + Then the charge at the upper plate of the capacitor array at this time for:

[0076] ;

[0077] And because of the conservation of charge, , ,but:

[0078] ;

[0079] In this embodiment, the binary capacitor array contains N+1=5 capacitors, and the first term in the above equation is the feedback voltage generated by the linear quantization circuit. Define access The weights of the n capacitors at point n are: Then at this time for: .

[0080] B0~B3 control the closing of the control switch, thereby controlling the voltage generated by the binary capacitor array in the linear quantization circuit. Thus achieving and Fine-grained quantization between ranges; binary capacitor arrays have binary weights, specifically, if The capacitance values ​​controlled by B0~B3 are as follows: 2 4 8 The weights are as follows: , , , Therefore, if the values ​​of binary code B0~B3 are... Access Weight of capacitor And because the length of the non-linear paragraph is Number of linear quantization intervals The linear quantization interval size is obtained. The feedback voltage generated by the linear quantization circuit for: .

[0081] Under the aforementioned quantization state, the two coarse quantization digital-to-analog converters respectively generate the start and end voltages of the nonlinear segment containing the input signal, thereby enabling the fine quantization interval to be... and Evenly distributed between them; after quantization, the switch... , , and All connected This enables the discharge and reset of the capacitor and memory array.

[0082] The timing diagram of the entire quantization process is as follows: Figure 4As shown, a single quantization requires 11 cycles: the first cycle is for resetting, the second cycle is for sampling, the third to seventh cycles are for 4-bit non-uniform coarse quantization, and the last four cycles are for uniform fine quantization.

[0083] To enable on-chip adjustments to the memcached array, the memcached containers can enter read / write states. Before performing on-chip adjustments, the memcached containers must first be... , , and All connected , Connected to a unity-gain buffer, it enables the reset of the memcached memory and capacitor array. Termination to read / write control terminal ,Will Termination to read / write control terminal In this state, the address selector will first select the MOSFET at the bottom terminal of the specified memory capacitor, while all other MOSFETs will be blocked. The selected memory capacitor will be connected to the control terminals at both ends. With control terminal The read / write capability allows for the control of the relative magnitudes of the signals at both ends to adjust the capacitance value of the memory capacitor. Furthermore, the output current can be measured after applying a read voltage to determine the adjusted capacitance state, thereby enabling precise capacitance control of the memory capacitor.

[0084] Taking the least significant memory cell in the memory cell array as an example, when reading the capacitor, first input the address of the memory cell. After the address selector decodes the address, it pulls the port signal of the corresponding MOSFET on the bus high, thereby enabling the least significant memory cell. A DC read voltage that does not change the state of the memory capacitor is applied to the MOS transistor connected to the terminal. Simultaneously, a small AC voltage signal is used to stimulate the device. By measuring the AC current signal obtained from the device's response to the AC voltage, the circuit admittance is calculated, and the capacitance value of the device under that DC voltage is obtained through mathematical transformation. If the capacitance of the memory capacitor is less than the desired adjustment capacitance, then... Terminal grounding, by A pulse signal is input to the terminal to increase the capacitance value. If the capacitance of the memory container is greater than the desired capacitance at this time, then... Terminal grounding, by A pulse signal is input to the terminal to lower the capacitance value. After adjustment, the current state is detected by reading the capacitance. The above process is repeated until the capacitance value of the memory container is adjusted to the desired value. Further, the above process is repeated, and each memory container is adjusted by the address selector until all memory containers in the memory container array are adjusted to the target state.

[0085] Since the quantization interval of the aforementioned analog-to-digital converter (ADC) is non-uniform, while its final output binary digital code is still uniformly distributed, to restore the signal, an inverse nonlinear transformation corresponding to the transfer characteristics of the ADC is required. The quantization result output by the ADC is then restored to the linearly proportional binary digital code corresponding to the original signal value using a lookup table. If the inverse nonlinear transformation is not performed and the signal is directly output, the ADC will also perform a nonlinear mapping of the input signal according to the transfer characteristics determined by the memory array while quantizing.

[0086] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0087] Example 1

[0088] In this embodiment, the 8-bit memory container-based on-chip adjustable piecewise linear quantization SAR analog-to-digital converter is configured in uniform quantization mode, where the interval between each piece is equal. Figure 5 The figure shows the transfer characteristic curve of the analog-to-digital converter under this condition. The quantization interval is equal, which proves that the on-chip adjustable piecewise linear quantization SAR analog-to-digital converter can be configured to uniform quantization mode.

[0089] Example 2

[0090] In this embodiment, the 8-bit memory-capable-based on-chip adjustable piecewise linear quantization SAR analog-to-digital converter is configured in small-signal quantization mode. In this mode, the quantization interval for small-amplitude signals is small, and the quantization interval for large-amplitude signals is large. Figure 6 The curve shows the transfer characteristic of the analog-to-digital converter under this condition. The curve exhibits logarithmic characteristics. A linear signal is input as the excitation to the analog-to-digital converter in this mode. Figure 7 For the corresponding input signal and output result, more quantization bits are allocated to small-amplitude signals in this mode, proving that the on-chip adjustable piecewise linear quantization SAR analog-to-digital converter can be configured to a quantization mode that is more sensitive to small-amplitude signals.

[0091] Example 3

[0092] In this embodiment, the 8-bit memory container-based on-chip adjustable piecewise linear quantization SAR analog-to-digital converter is configured in large-signal quantization mode. In this mode, the analog-to-digital converter has a large quantization interval for small-amplitude signals and a small quantization interval for large-amplitude signals. Figure 8 The transfer characteristic curve of the analog-to-digital converter under this condition is given by inputting a linear signal as excitation to the analog-to-digital converter in this mode. Figure 9 For the corresponding input signal and output result, the large-amplitude signal is assigned more quantization bits in this mode, proving that the on-chip adjustable piecewise linear quantization SAR analog-to-digital converter can be configured to a quantization mode that is more sensitive to large-amplitude signals.

[0093] Example 4

[0094] In this embodiment, the 8-bit memory container-based on-chip adjustable piecewise linear quantization SAR analog-to-digital converter is configured to use a smaller quantization interval for intermediate amplitude signals and a larger quantization interval for large and small amplitude signals. Figure 10 The transfer characteristic curve of the analog-to-digital converter under this condition is given by inputting a linear signal as excitation to the analog-to-digital converter in this mode. Figure 11 For the corresponding input signal and output result, in this mode, the intermediate amplitude signal is assigned more quantization bits, and the signals with larger or smaller amplitudes are assigned lower quantization precision. This proves that the on-chip adjustable piecewise linear quantization SAR analog-to-digital converter can be configured to a quantization mode that is relatively sensitive to intermediate amplitude signals and insensitive to larger or smaller amplitude signals.

[0095] Example 5

[0096] In this embodiment, the 8-bit memory container-based on-chip adjustable piecewise linear quantization SAR analog-to-digital converter is configured to use a larger quantization interval for intermediate amplitude signals and a smaller quantization interval for large and small amplitude signals. Figure 12 The transfer characteristic curve of the analog-to-digital converter under this condition is given by inputting a linear signal as excitation to the analog-to-digital converter in this mode. Figure 13 For the corresponding input signal and output result, in this mode, the intermediate amplitude signal is assigned fewer quantization bits, while the larger or smaller amplitude signal is assigned higher quantization precision. This proves that the on-chip adjustable piecewise linear quantization SAR analog-to-digital converter can be configured to a quantization mode that is relatively sensitive to larger or smaller amplitude signals and less sensitive to medium amplitude signals.

[0097] Example 6

[0098] In this embodiment, the 8-bit memory container-based on-chip adjustable piecewise linear quantization SAR analog-to-digital converter is configured in uniform quantization mode, and a sinusoidal signal is input as excitation to the analog-to-digital converter in this mode. Figure 14 For the corresponding input signal and output result, the amplitude of each value of the sine signal is uniformly quantized in this mode.

[0099] Example 7

[0100] In this embodiment, the 8-bit memory container-based on-chip adjustable piecewise linear quantization SAR analog-to-digital converter is configured to use a smaller quantization interval for intermediate amplitude signals and a larger quantization interval for large and small amplitude signals. A sinusoidal signal is input as excitation to the analog-to-digital converter in this mode. Figure 15For the corresponding input signal and output result, the quantization of the larger or smaller amplitude of the sine signal is relatively coarse in this mode, while the quantization accuracy is higher as the amplitude is closer to 1 / 2.

[0101] Comparative Example 1

[0102] This comparative example retains the first-stage memcached array of the quantization circuit but removes the second-stage linear quantization circuit, thus outputting only a 4-bit segment code. In this comparative example, the memcached array is configured in uniform quantization mode. Figure 16 The transfer characteristic curve of the analog-to-digital converter under this condition is shown below. Figure 5 In comparison, the transfer characteristic curve of the analog-to-digital converter in this comparative example is coarser, and the output accuracy is lower. If M is the number of bits in the segment code of the SAR register output digital code, and N is the number of bits in the intra-segment code of the SAR register output digital code, in this embodiment M=4 and N=4, to achieve a similar 8-bit quantization effect as in Example 1 using the single-level structure in this example, more power is required. The presence of one capacitor demonstrates that a two-stage quantization circuit can achieve higher accuracy and a greater dynamic range with fewer circuit components.

[0103] Comparative Example 2

[0104] This comparative example retains the first-stage memcached array of the quantization circuit but removes the second-stage linear quantization circuit, thus outputting only a 4-bit segment code. In this comparative example, the memcached array is configured in small-signal quantization mode, where the analog-to-digital converter (ADC) has a small quantization interval for small-amplitude signals and a large quantization interval for large-amplitude signals. Figure 17 The transfer characteristic curve of the analog-to-digital converter under this condition is given by inputting a linear signal as excitation to the analog-to-digital converter in this mode. Figure 18 For the corresponding input signal and output result, the same Figure 6 and Figure 7 In comparison, the transfer characteristic curve of the analog-to-digital converter in this comparative example is coarser, resulting in lower output accuracy. To achieve a similar 8-bit quantization effect as in Example 2 using the single-stage structure in this example would not only consume more capacitors, but also prevent the remaining capacitors from automatically adjusting the quantization interval according to the size of the nonlinear segment when the memory array is reconfigured to other modes, making it difficult to achieve freely adjustable piecewise linear quantization characteristics. This demonstrates that a two-stage quantization circuit can consume fewer circuit components and achieve piecewise linear quantization characteristics with accuracy advantages, while ensuring on-chip adjustability of the nonlinear segment endpoints.

[0105] This invention can be applied to multiple fields such as image and audio sensors, temperature sensors, and brain-computer interface sensors. It provides a method for flexibly changing the transfer function of a piecewise linear analog-to-digital converter (ADC). The piecewise linear quantization ADC achieved using a two-stage SAR ADC offers suitable accuracy and power consumption, making it widely applicable. While the ADC typically uses a weighted capacitor array, the fixed capacitance value of the array prevents adjustment of the transfer function for different scenarios. A memristor is a novel memory element proposed after the memristor, belonging to the category of nonlinear dynamic capacitors. Its capacitance value is determined by historical voltage or charge state, exhibiting non-volatile memory characteristics. Practical devices achieve capacitance control through various methods, including utilizing electron tunneling, embedded memristor materials, and ion migration modulation. Taking memristors utilizing electron tunneling as an example, this type of memristor incorporates two or more embedded metal layers with a spacing much smaller than the plate spacing of a planar capacitor. Under an applied voltage, electrons tunnel between the embedded metal layers, accumulating a certain amount of non-zero charge and generating a built-in electric field opposite to the external electric field. This affects the overall dielectric constant of the planar capacitor. By applying voltage excitations of different polarities, the electric field between the embedded metal layers can be changed, thereby controlling the capacitance of the entire capacitor. Furthermore, the tunneling current between the embedded metal layers has a highly nonlinear exponential dependence on the applied excitation, thus providing a natural threshold for distinguishing between the pulse strength during programming and the signal strength during reading. Memristors also offer smaller dimensions, and their fabrication processes are compatible with CMOS processes, potentially leading to higher circuit integration. By applying the aforementioned characteristics of memory containers, this invention enables the adjustment of piecewise linear quantization characteristics under different scenarios, thereby achieving piecewise linear quantization of signals.

[0106] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of the present invention are included within the scope of protection of the present invention.

Claims

1. An on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array, characterized in that: It includes a memory container array, an input signal conversion circuit, a control circuit, a linear quantization circuit, and an on-chip adjustment circuit. The control circuit is connected to the input signal conversion circuit, the memory container array, and the linear quantization circuit. The on-chip adjustment circuit is connected to the memory container array, and the memory container array is connected to the linear quantization circuit. The memory capacitor array uses multiple memory capacitors and switches to achieve charge redistribution, and constructs nonlinear characteristics based on the memory capacitance value of the memory capacitors to determine the nonlinear segment in which the input signal is located. The input signal conversion circuit is used to receive and sample and hold the original input signal, and perform amplitude conversion; The control circuit is used to buffer and store the quantized digital code, and to control the quantization process according to the preset algorithm of the logic circuit. The linear quantization circuit is used to receive a reference voltage from the memory array and perform uniform quantization on the input signal within a nonlinear segment. The on-chip adjustment circuit performs gating adjustment on the memory container array through the coordinated operation of the gating array and the address gating unit.

2. The on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array as described in claim 1, characterized in that: The memory capacitor array and the linear quantization circuit constitute a two-stage quantization structure. The memory capacitor array is the first stage, which provides a reference voltage to the linear quantization circuit after determining the nonlinear segment in which the signal is located. The linear quantization circuit is the second stage, and the number of linear quantization intervals is the same within each nonlinear segment. If the length of the nonlinear segment is... The number of linear quantization intervals is The linear quantization interval size is Their relationship satisfies: ； The linear quantization circuit determines the length of the nonlinear segment in which the signal is located using a reference voltage provided by the memory capacitor array. and divide it into A number of intervals of the same size.

3. The on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array as described in claim 2, characterized in that: The on-chip adjustable piecewise linear quantization analog-to-digital converter based on memory container array uses a SAR structure to implement quantization, and the control circuit includes a comparator unit, a SAR register, a decoder, and an output register. The comparator unit is used to connect to the input voltage and compare the reference voltage node with the input voltage; The SAR register is used to temporarily store the digital code generated during the successive approximation process, realize the successive approximation algorithm and control the circuit to complete the successive approximation quantization. The decoder is used to convert the binary segment code portion of the SAR register output into thermometer code for controlling the memory container array; The output register buffers and combines the high-order and low-order digital codes to control the output of the final digital code.

4. The on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array as described in claim 3, characterized in that: The comparator unit contains one comparator; The SAR register outputs a total of M+N bits of digital code, where M is the number of bits in the segment code and N is the number of bits in the intra-segment code; The number of bits M of the segment code is equal to the number of bits of the non-uniform coarse quantization implemented based on the memory container array, and it is located in the high M bits of the final digital code output by the output register. The number of bits N in the segment code is equal to the number of bits in the uniform fine quantization implemented based on the linear quantization circuit, and it is located in the lower N bits of the final digital code output by the output register. The SAR register includes 2(M+N+1) D flip-flops; N and the number of linear quantization intervals Relationship satisfaction .

5. The on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array as described in claim 4, characterized in that: The memory container array includes a total of Each memory container comprises two memory container array units, and each memory container array unit includes... Each memory container is used to generate the starting reference voltage of the nonlinear segment interval where the signal is located. and endpoint reference voltage The relationship between the two is as follows: ; The linear quantization circuit receives a starting reference voltage. and endpoint reference voltage Determine the length of the nonlinear segment containing the input signal. It satisfies the following relationship: .

6. The on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array as described in claim 5, characterized in that: The linear quantization circuit includes a binary capacitor digital-to-analog converter (DAC) consisting of (N+1) capacitors. The reference voltage terminal of the binary capacitor DAC receives the starting reference voltage from the memory capacitor array. and endpoint reference voltage And under the control of the SAR register, a reference voltage is generated at the starting point. and endpoint reference voltage The feedback voltage used for successive approximation within the interval; If the SAR register outputs the binary segment internal code as The feedback voltage generated by the linear quantization circuit for: .

7. The on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array as described in claim 4, characterized in that: The on-chip adjustment circuit includes a gating array and an address gating unit; wherein the gating array is connected to the memory container array, and the address gating unit is connected to the gating array.

8. The on-chip adjustable piecewise linear quantization analog-to-digital converter based on a memory container array as described in claim 7, characterized in that: The gating array includes One MOSFET.

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