Continuous time linear equalizer and high speed serial communication receiver thereof

Abstract

The application provides a continuous time linear equalizer and a high-speed serial communication receiver thereof, and belongs to the technical field of integrated circuits, and comprises: a plurality of differential input pairs with different input common-mode voltage ranges; an input selection circuit configured to alternatively enable one of all the differential input pairs as a target differential input pair; a differential load circuit coupled to an output end of a differential input stage module and having an adjustable equivalent impedance; and a load control circuit configured to determine load configuration information in response to an input mode selection signal and adjust the equivalent impedance of the differential load circuit according to the load configuration information. The application establishes a linkage mechanism of input stage switching and load impedance adjustment through the input mode selection signal, automatically calls corresponding calibration parameters to eliminate the offset voltage in different modes while expanding the input common-mode voltage range, and significantly improves the adaptability and signal transmission quality of the high-speed interface circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a continuous time linear equalizer applied to a high speed serial link (SerDes) receiving end and a high speed serial communication receiver. BACKGROUND

[0002] In a high speed communication system, the analog front-end circuit of the receiving end is responsible for compensating and recovering the signal attenuated by the channel. With the evolution of semiconductor process nodes and the diversification of interface protocol standards, the common mode voltage (Common Mode Voltage) of the signal output by the transmitter driver presents a differentiated distribution characteristic, which puts forward strict physical layer requirements for the signal processing capability of the receiving end circuit under different voltage environments.

[0003] In the prior art, in order to compensate for the high frequency loss of the channel, a differential amplification circuit based on source degeneration technology is usually used to realize the continuous time linear equalizer (CTLE) function. The typical circuit architecture includes a differential input stage, a source degeneration network and a load stage. In the circuit design stage, based on the established process library and the preset application scenario, the designer usually uses a metal-oxide-semiconductor field effect transistor of a specific polarity to construct a differential input pair, for example, an N-channel Metal-Oxide-Semiconductor (NMOS) transistor pair or a P-channel Metal-Oxide-Semiconductor (PMOS) transistor pair. In operation, the input signal drives the differential input pair to convert the voltage signal into a current signal, and establishes an output voltage through the load stage, while the offset voltage caused by the device manufacturing process deviation is calibrated through the trimming circuit at the load end.

[0004] However, the circuit using the above architecture has inherent limitations in actual physical characteristics. First, the linear amplification of the transistor is highly dependent on the bias relationship between the gate-source voltage and the threshold voltage, and the transistor of a specific polarity can only work in the saturation region within a specific common-mode voltage interval. When the common-mode voltage of the input signal deviates from the conduction threshold or working interval of the specific transistor, the transconductance efficiency of the transistor will be nonlinearly attenuated or even cut off, resulting in the circuit failing to maintain the expected gain and bandwidth characteristics. Second, since the DC offset voltage of the transistor is derived from the random mismatch of physical parameters such as device size and doping concentration, this mismatch characteristic is strictly bound to its physical structure. The existing trimming circuit usually fixes the compensation of the load based on a single configuration parameter. When the working state of the circuit or the working point of the core device changes, the original compensation parameter no longer corresponds to the current mismatch characteristic, resulting in a residual DC voltage deviation at the output end, which further causes the closure of the signal eye diagram. SUMMARY

[0005] In view of the technical problems in the prior art that the working range of the input common-mode voltage of the continuous-time linear equalizer is limited, different voltage domain input signals cannot be compatible, and the DC offset voltage cannot be adaptively eliminated under different working conditions, thereby causing the signal transmission quality to decrease, the present application provides a continuous-time linear equalizer and a high-speed serial communication receiver.

[0006] In a first aspect, the present application provides a continuous-time linear equalizer, comprising:

[0007] a differential input stage module, comprising a plurality of differential input pairs with different input common-mode voltage ranges;

[0008] an input selection circuit configured to selectively enable one of all the differential input pairs as a target differential input pair for current work in response to an input mode selection signal;

[0009] a differential load circuit coupled to the output end of the differential input stage module, the differential load circuit having an adjustable equivalent impedance;

[0010] a load control circuit configured to determine load configuration information corresponding to the target differential input pair in response to the input mode selection signal, and adjust the equivalent impedance of the differential load circuit according to the load configuration information.

[0011] In a possible implementation, the differential input pairs are two, including a first differential input pair and a second differential input pair.

[0012] In a possible implementation, the first differential input pair is composed of PMOS transistors, and the second differential input pair is composed of NMOS transistors.

[0013] The input common-mode voltage range of the first differential input pair is higher than that of the second differential input pair.

[0014] In a possible implementation, the load control circuit comprises a storage unit;

[0015] The storage unit is configured to store a calibration code corresponding to each of the differential input pairs respectively;

[0016] The load control circuit is configured to read the storage unit, take the calibration code corresponding to the target differential input pair as the load configuration information, and adjust the equivalent impedance of the differential load circuit according to the load configuration information.

[0017] In a possible implementation, the storage unit comprises a first register group and a second register group, and the load control circuit further comprises a multiplexer;

[0018] The first register group stores a first calibration code corresponding to the first differential input pair, and the second register group stores a second calibration code corresponding to the second differential input pair;

[0019] The multiplexer is controlled by the input mode selection signal to switch output between the first register group and the second register group.

[0020] In a possible implementation, the differential load circuit comprises a variable resistance array;

[0021] The load configuration information is used to adjust the resistance value of the variable resistance array, so that when the differential signal input into the continuous-time linear equalizer is zero, the differential output voltage of the continuous-time linear equalizer is substantially zero.

[0022] In a possible implementation, the continuous-time linear equalizer further comprises:

[0023] A configurable equalization network coupled in a signal amplification path of the continuous-time linear equalizer, configured to adjust its equivalent impedance in response to an equalization control signal, to set low-frequency gain and high-frequency gain in frequency response characteristics of the CTLE.

[0024] In a possible implementation, the configurable equalization network comprises a resistance array and / or a capacitance array:

[0025] The resistance array comprises a plurality of resistance elements controlled to be accessed by a first switch;

[0026] The capacitance array comprises a plurality of capacitance elements controlled to be accessed by a second switch;

[0027] The equalization control signal adjusts the equivalent impedance by controlling the on-off state of the first switch and / or the second switch.

[0028] In a possible implementation, the continuous-time linear equalizer has a first gain in a frequency band lower than the use frequency; and has a second gain higher than the first gain in a frequency band higher than the use frequency.

[0029] In a possible implementation, the continuous-time linear equalizer further comprises a transmission gate structure.

[0030] The transmission gate structure is coupled between a signal input pad of the continuous-time linear equalizer and the differential input stage module.

[0031] The transmission gate structure is configured to provide a signal path when the continuous-time linear equalizer is in an active state, and to provide a high-impedance isolation or electrostatic discharge protection path when the continuous-time linear equalizer is in an inactive state.

[0032] In a possible implementation, the transmission gate structure comprises an NMOS transmission tube and a PMOS transmission tube connected in parallel.

[0033] The input selection circuit controls the on-off of the signal path by controlling the gate voltage of the NMOS transmission tube and the PMOS transmission tube.

[0034] In a possible implementation, the input mode selection signal, the load configuration information, and the equalization control signal are all digital signals that can be configured by software programming.

[0035] In a second aspect, the present application provides a high-speed serial communication receiver comprising the continuous-time linear equalizer according to any one of the first aspect.

[0036] Compared with the prior art, the continuous-time linear equalizer and the high-speed serial communication receiver provided by the present application have the following beneficial effects:

[0037] (1) The present application breaks the limitation of a single transistor type on the input voltage range by setting multiple differential input pairs with different input common-mode voltage ranges and using an input selection circuit to enable one of them, so that the continuous-time linear equalizer can adapt to different input common-mode voltages, significantly improving the versatility of the circuit and the compatibility with upstream drivers.

[0038] (2) The application innovatively establishes a linkage mechanism of input mode selection and load impedance adjustment, and the load control circuit can automatically call the load configuration information (such as calibration code) matched with the target differential input according to the current input mode selection signal. This linkage mechanism ensures that no matter which input mode is switched to, the load control circuit can obtain accurate DC offset calibration for the device characteristics in the mode, thereby ensuring that the output end always maintains DC balance, effectively preventing eye closure and reducing the bit error rate.

[0039] (3) The application realizes flexible programming of frequency response characteristics, input mode and load calibration through a fully digital control mode, such as register configuration, and further improves the reliability and flexibility of system integration in cooperation with the high-isolation and electrostatic protection functions provided by the transmission gate structure. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0041] Figure 1 is a schematic diagram of the CTLE circuit structure commonly used in the prior art.

[0042] Figure 2 is a schematic diagram of the CTLE circuit structure provided by the application.

[0043] Figure 3 is a schematic diagram of the overall architecture of the CTLE provided by the application.

[0044] Figure 4 is a schematic diagram of the connection relationship between the load control circuit and the differential load circuit provided by the application.

[0045] Figure 5 is a schematic diagram of the structure of the high-speed serial communication receiver provided by the application. DETAILED DESCRIPTION

[0046] In order to make the purpose, technical solutions and advantages of the application clearer, the technical solutions in the application will be described clearly and completely below in combination with the drawings in the application. Obviously, the described embodiments are some embodiments of the application, not all embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0047] It should be noted that in the description of the present application, the terms "comprising", "containing" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article or device comprising the element. The terms "upper", "lower", "front", "back" and the like indicate the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. Unless otherwise specified and limited, the terms "mounting", "connecting", "connecting" should be broadly understood, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0048] The terms "first", "second", and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, and do not limit the number of objects, for example, the first object can be one or more. In addition, "and / or" means at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in a "or" relationship.

[0049] In a high-speed serial communication system, the signal will be affected by the attenuation and distortion of the channel during transmission, resulting in a decrease in signal quality and an increase in error rate. This attenuation is particularly severe at high frequencies, because the physical characteristics of the channel (such as cables, backplane wiring) will exhibit the characteristics of a low-pass filter. The role of CTLE is to compensate for the attenuation of the channel and restore the integrity of the signal. Simply put, CTLE can be regarded as a reverse filter, which not only enhances high-frequency signals, but also moderately attenuates low-frequency signals, thereby offsetting the adverse effects of the channel, which enables the receiving end to more accurately recover the original data.

[0050] Skin effect refers to the phenomenon that the current density exponentially decays with the depth of the conductor when the alternating current flows in the conductor. In a semiconductor, the current of a high-frequency signal (such as a radio frequency, microwave) will concentrate in a thin layer on the surface of the material, resulting in a significant reduction of the current density inside the conductor. CTLE is mainly used to solve the problem that the high-frequency attenuation is greater than the low-frequency attenuation of the signal in the transmission process due to the skin effect and dielectric loss. This frequency-dependent loss will cause the signal pulses to spread and overlap with each other, resulting in inter-symbol interference (ISI), which causes the eye diagram at the receiving end to close and the bit error rate to rise. CTLE is essentially an analog high-pass filter (or its frequency response has a peaking characteristic), which compensates for the high-frequency loss of the channel by providing higher gain for high-frequency components than for low-frequency components in the signal, so that the frequency response of the entire transmission link becomes flat, thereby reducing ISI and reopening the eye diagram. The value of CTLE lies in its pure analog implementation, which can process high-speed signals in real time without digital sampling, and has relatively low power consumption. However, it will also amplify high-frequency noise. Therefore, CTLE is often used in combination with digital equalization technologies such as decision feedback equalizer (DFE) to form a hybrid equalization scheme to achieve better overall performance.

[0051] Figure 1 is a schematic diagram of a CTLE circuit structure commonly used in the prior art, as shown in Figure 1 , the differential pair differential input transistors M1, M2 usually use NMOS transistors to receive differential input signals V in+ and V in- . Current sources M3, M4 provide bias current for the differential pair. The source degeneration network composed of source degeneration resistance R s and source degeneration capacitance C s determines the equalization characteristics of the CTLE and adjusts the gain compensation range. Among them, R s affects the degree of low-frequency attenuation, C s affects the degree of high-frequency enhancement. The load resistance R L is located at the output end and affects the output voltage V out .

[0052] According to Figure 1 , the key to understanding the working principle of the CTLE commonly used in the prior art lies in understanding this frequency-dependent impedance composed of source degeneration resistance R s and source degeneration capacitance C s :

[0053] 1) In the low-frequency / direct current (DC) working state, that is, when the input signal frequency is very low, or even a direct current signal, C sThe impedance is extremely high, equivalent to an open circuit, at which point the current can only flow through R. s Therefore, the total impedance of the source degenerate network is R. s The resistance value of R. s The presence of this effect creates a negative feedback effect, significantly reducing the circuit's voltage gain. This can be understood as a portion of the input signal's energy being consumed by R. s This limits the amplification capability. Therefore, in low-frequency / DC operation, the gain of CTLE is relatively low, and this gain is determined by R. s and R L The ratio is roughly determined in order to attenuate low-frequency components.

[0054] 2) In high-frequency operating mode, i.e. when the input signal frequency is very high, C s The impedance becomes very small, approaching a short circuit, at which point R s C s The circuit is "short-circuited" or "bypassed." Current will preferentially flow through the Cs path, which has extremely low impedance. Therefore, the total impedance of the source-degraded network is approximately zero, and the CTLE is equivalent to an ideal differential amplifier without source degradation. Thus, in high-frequency operation, the CTLE's gain reaches its maximum value and is almost unaffected by R. s and C s The gain is mainly influenced by the transistor's own transconductance (gm) and load resistance R. L The decision was made to enhance (or not attenuate) the high-frequency components.

[0055] 3) In the mid-frequency transition region, i.e., as the input signal frequency changes from low to high, C s The impedance gradually decreases from infinity to zero. Therefore, the total impedance of the source degenerate network also smoothly decreases from R... s Reducing it to zero causes the total gain of CTLE to smoothly transition from a low-gain state to a high-gain state as the input signal frequency increases. The inflection point frequency at which this gain begins to rise (called the zero point) is f. zero By R s and C s The product determines: f zero ≈1 / (2 R s C s ).

[0056] In summary, Figure 1 The working principle of the existing CTLE can be summarized as follows: it can be regarded as a special amplifier, and its gain curve exhibits the characteristics of a high-pass filter that attenuates low frequencies and allows high frequencies to pass. Through R... s The low-frequency portion of the attenuated signal is attenuated through C.s In high frequency, bypass R s , so that the high frequency signal obtains the maximum gain. In high-speed communication, the transmission channel (such as a cable) itself is like a low-pass filter, which can seriously attenuate the high frequency components of the signal. This CTLE circuit can indeed provide an opposite frequency response, actively boosting (or compensating) the high frequency components attenuated by the channel, while keeping the low frequency components from being amplified too much, ultimately enabling the signal at the receiving end to recover a clearer waveform, thereby compensating for channel loss and reducing bit error rate.

[0057] However, the existing CTLE has very obvious disadvantages, mainly manifested in the following points:

[0058] 1) The input common-mode voltage range depends on the designed input tube type, and the applicable range is limited.

[0059] NMOS transistors need their gate (input) voltage to be higher than their source voltage by a certain threshold voltage to be turned on. At the same time, in order to ensure that it works in the amplification state, the input voltage cannot be too high, otherwise it will squeeze the voltage space of the output end. This leads to the fact that the NMOS transistor input stage is more suitable for processing input signals with lower DC level. However, if PMOS is used as the input tube in design, the situation is the opposite. PMOS transistors are more suitable for processing input signals with higher DC level (close to the power supply voltage VDD). Therefore, once the input tube type is selected as NMOS input tube or PMOS input tube in design, this CTLE can only efficiently process signals within a certain voltage range.

[0060] In a complex chip system (SoC), different functional modules may be designed by different teams or come from different IP suppliers. The DC bias (common-mode voltage) of their output signals may be various. If a CTLE can only receive input signals in the range of 0.2V~0.6V, for example, when the upstream module outputs an input signal of 0.9V, the CTLE cannot normally interface with it.

[0061] Therefore, the design of hardware fixation leads to the lack of flexibility and universality of the existing CTLE at the electrical interface level, which cannot become a widely reusable IP module.

[0062] 2) Increasing bandwidth often requires increasing current, which consumes more power.

[0063] The bandwidth of CTLE (which can be understood as the highest signal frequency it can handle) ∝1 / (R Cload), which is related to several factors, of which the most important is the R C time constant of the output node. Among them, Cload is the total capacitance of the output end (including the input capacitance and parasitic capacitance of the next stage circuit).

[0064] To achieve higher bandwidth (i.e. to process faster input signals), one direct method is to reduce the load resistance R L However, the gain of the circuit is approximately equal to gm x R L , where gm (transconductance) is the amplification capability of the input transistor. When R L is reduced to increase the bandwidth, the gain will decrease. To maintain sufficient gain, gm must be increased. However, the gm of a transistor is closely related to the bias current flowing through it (provided by M3, M4), and usually gm is proportional to the current. Therefore, to increase gm, the operating current of the entire circuit must be increased, which means higher power consumption.

[0065] 3) Compensation does not set adaptive algorithm, affected by the three major variables (process, voltage and temperature, PVT) of chip performance is greatly affected.

[0066] Specifically, there are microscopic physical deviations in the manufacturing process of the chip. Even on the same wafer, the characteristics of the transistors in this corner and the transistors in that corner may be slightly different. This will cause Figure 1 R s , C s , R L in the actual value and the characteristics of the transistor deviate from the design value.

[0067] The supply voltage of the chip is not absolutely constant, and there will be fluctuations, and the change of the supply voltage will directly affect the operating point and current of the transistor, thereby changing the gain and frequency response of the CTLE. In addition, affected by the chip manufacturing process, it will also cause the gain of the CTLE to drift to some extent. In addition, the chip will generate heat when working, and the environmental temperature will also change, and the temperature will significantly change the mobility of the transistor and the resistance value of the resistor, which will also cause the equalization characteristics of the CTLE to drift.

[0068] The CTLE used in the prior art as shown in Figure 1 is generally a static circuit, whose characteristics are determined by physical elements, and there is no sensing and feedback mechanism to cope with changes caused by PVT.

[0069] 4) Offset affects eye pattern shape. The eye pattern is a pattern formed by superimposing a large number of digital signal waveforms on an oscilloscope. The area in the middle of the eye pattern shape represents the margin of signal decision. The larger and clearer the eye, the better the signal quality and the stronger the anti-interference ability.

[0070] Offset is an unwanted DC voltage difference at the differential output terminal. Its effect on the eye pattern mainly reflects in:

[0071] Offset causes the entire eye to shift in the vertical direction. The originally symmetric "1" and "0" levels become asymmetric. This reduces the voltage margin for decision. The receiver is more likely to make a mistake when distinguishing between high and low levels.

[0072] Horizontal closure (increase jitter): The shift in voltage causes the time at which the input signal crosses the decision threshold (zero level) to shift. This uncertainty in time is called deterministic jitter. It reduces the time margin for decision (i.e. eye width).

[0073] The height and width of the eye diagram are key measures of communication system performance, with eye height representing noise immunity and eye width representing jitter immunity. Offset squeezes the eye shape from both dimensions, making the eye smaller. A very small eye means that the system is very fragile, and any additional noise or jitter can cause data transmission errors, i.e. a sharp increase in bit error rate (BER).

[0074] Figure 2 is the circuit structure schematic diagram of the CTLE provided by the present application, as Figure 2 shown, in view of the above problems existing in the prior art, the present application provides a new CTLE, which mainly makes the following improvements:

[0075] (1) By using a digital control signal (REG_IN_SEL signal) to control the input selection switch Tgate, a certain differential input pair with different input common mode voltage range can be selected as the input stage.

[0076] For example, considering that PMOS transistors and NMOS transistors have different characteristics, PMOS transistors are more suitable for processing signals close to the power supply voltage, while NMOS transistors are more suitable for processing signals close to the ground voltage. By selecting the appropriate input type, the dynamic range of the input signal can be maximized, improving the performance of the CTLE.

[0077] (2) By configuring the equalization network (controlled by REG_R_SEL and REG_C_SEL), the equalization characteristics of the CTLE can be flexibly adjusted to adapt to different channel conditions. This adjustability allows the CTLE to maintain optimal performance in different operating environments.

[0078] Specifically, by adjusting the values of REG_R_SEL and REG_C_SEL, the frequency response curve of the CTLE can be changed to better match the channel characteristics. When the channel characteristics change, the equalization effect can be optimized by reconfiguring the values of REG_R_SEL and REG_C_SEL, thereby improving signal quality.

[0079] (3) By controlling the value of the adjustable load resistance through TRIM_CODEP and TRIM_CODEN, the offset of the input link can be eliminated.

[0080] Specifically, by adjusting the values of TRIM_CODEP and TRIM_CODEN, the output voltage of the CTLE can be changed to be closer to the expected value. This can reduce the bit error rate and improve the reliability of the CTLE.

[0081] (4) The values of REG_R_SEL and REG_C_SEL can be configured by software according to the channel characteristics to change the zero point position and achieve adaptive compensation effect.

[0082] Specifically, the software configuration of REG_R_SEL and REG_C_SEL allows the CTLE to dynamically adjust according to the actual channel conditions without manual adjustment of hardware parameters. This greatly simplifies the system design and debugging process and improves the flexibility of the CTLE.

[0083] The following will be described in detail in combination with the contents shown in Figures 2-5 The continuous time linear equalizer and high-speed serial communication receiver provided by the present application.

[0084] Figure 3 The overall architecture of the CTLE provided by the present application is shown in Figure 3 The continuous time linear equalizer provided by the present application mainly includes but is not limited to:

[0085] A differential input stage module including a plurality of differential input pairs with different input common mode voltage ranges;

[0086] An input selection circuit configured to selectively enable one of all the differential input pairs as a target differential input pair currently working in response to an input mode selection signal;

[0087] A differential load circuit coupled to the output end of the differential input stage module, the differential load circuit having an adjustable equivalent impedance;

[0088] A load control circuit configured to determine load configuration information corresponding to the target differential input pair in response to the input mode selection signal, and adjust the equivalent impedance of the differential load circuit according to the load configuration information.

[0089] The CTLE provided by the present application can be integrated as an independent analog IP core in various system on chip (SoC) systems, or as a front-end module of a high-speed serial communication receiver (such as a SerDes receiver).

[0090] The differential input stage module is a functional unit that integrates multiple differential input pairs, such as... Figure 3 The differential input pairs shown are 1, 2, and N. "Multiple" here refers to two or more pairs. Each differential input pair is used to convert the input differential voltage signal into a differential current signal.

[0091] Different differential input pairs have different input common-mode voltage ranges, meaning that each differential input pair maintains normal amplification characteristics within a different common-mode voltage range. For example, differential input pair 1 can effectively handle input signals close to the high supply voltage (VDD), while differential input pair 2 can effectively handle input signals close to the low supply voltage (GND or VSS). This difference in input common-mode voltage range can be achieved by using transistors with different conductivity types (e.g., PMOS and NMOS transistors), transistors with different threshold voltages, or transistors with different physical sizes, thus enabling the entire differential input stage module to cover a wider voltage operating range.

[0092] An input selection circuit is a hardware circuit that selects the input path. Its physical implementation can be a multiplexer, an array of analog switches, or a bias current guiding circuit controlled by logic gates. The control terminal of the input selection circuit receives an input mode selection signal. This signal can be an instruction signal—a digital code written to an internal register by an external processor via a bus—or a level signal provided by an upstream circuit, informing the input selection circuit which differential input pair should be selected for operation.

[0093] In this embodiment, the input selection circuit is configured to respond to the input mode selection signal, meaning that when the logic state of the input mode selection signal changes, the input selection circuit will perform a corresponding switching action.

[0094] The specific switching action includes: selectively activating one of all differential input pairs as the target differential input pair for current operation. Activating a differential input pair can be achieved by directing the main bias current to the selected target differential input pair while simultaneously cutting off the bias current of the other unselected differential input pairs, thus ensuring that only one set of differential input pairs is consuming static power and processing signals at any given time.

[0095] The differential load circuit is coupled to the output of the differential input stage module. This coupling can be a direct electrical connection; for example, the drain output of the differential input stage module can be directly connected to the input of the differential load circuit. The function of the differential load circuit is to convert the differential current signal output from the differential input stage module into a differential voltage signal.

[0096] It is noted that the differential load circuit has an adjustable equivalent impedance, which can be changed according to an external control signal. As shown in Figure 3 , it can contain a variable resistance array inside. The adjustment of the equivalent impedance can be achieved by selectively connecting or disconnecting parallel resistive elements through a digitally controlled switch array.

[0097] The load control circuit is a functional part of the digital control and calibration logic as shown in Figure 3 , which is configured to respond to an input mode selection signal, i.e. its working logic is associated with the input mode selection signal. When the load control circuit receives the input mode selection signal, it will perform the action of determining the load configuration information corresponding to the target differential input pair.

[0098] Here, the way to determine the load configuration information can be: in a pre-set look-up table or memory, according to the value of the input mode selection signal as the address or index, find the pre-stored load configuration information matching the mode.

[0099] The load configuration information here is a set of information used to characterize and set the target state of the differential load circuit, which can take various forms.

[0100] In one possible implementation, the load configuration information can be an analog voltage signal or an analog current signal, which is generated by a digital-to-analog converter (DAC) inside the load control circuit, and directly controls the on-resistance of an active load (such as a MOS transistor working in the linear region).

[0101] In another possible implementation, the load configuration information is a set of digital codes, such as binary codes, which represent the desired load impedance value.

[0102] As an optional embodiment, the determined load configuration information can also be physical configuration state information. After determining the load configuration information, the load control circuit performs the action of adjusting the equivalent impedance of the differential load circuit according to the load configuration information. The adjustment method used can be that the load control circuit applies the load configuration information (such as digital codes) as a control signal to the control terminal of the differential load circuit (such as a variable resistance array), drives the switch array therein to switch, and thus accurately adjusts the equivalent impedance of the differential load circuit to the value corresponding to the load configuration information.

[0103] The CTLE provided by the application can automatically and adaptively adjust the load impedance while switching the input differential pair to adapt to different input common-mode voltages, so as to compensate for the inherent offset voltage introduced by different differential input pairs, and ensure the signal integrity of the circuit in a wide voltage input range.

[0104] As an optional embodiment, the differential input pair is two, including: a first differential input pair and a second differential input pair.

[0105] The number of differential input pairs is two, which is a preferred technical choice after weighing the performance, area overhead and control logic complexity of the circuit. Specifically, in the current mainstream high-speed serial interface standards, such as PCIe, USB, Ethernet, etc., although the protocol versions are various, the output common-mode voltage of the physical layer transmission driver can be generally classified into two categories: one is a high common-mode level close to the high power voltage VDD, and the other is a low common-mode level close to the ground GND. Therefore, by using two differential input pairs optimized for these two voltage intervals, most application scenarios can be covered with minimal hardware resource cost, which has high engineering practice value and commercial value.

[0106] As understood by those skilled in the art, the differential input pair is not limited to two, and in other embodiments, three or more differential input pairs can be set according to more complex application requirements. For example, an additional third differential input pair composed of zero threshold voltage (Zero-VT) transistors can be added to efficiently process intermediate common-mode voltages between high and low levels. Or, in a system requiring an extremely low power standby mode, a fourth differential input pair with sub-threshold (Sub-threshold) design can be added, which is slower but has extremely low static power consumption. These are all within the protection scope of the application.

[0107] In an optional embodiment, by setting the first differential input pair and the second differential input pair as two core paths, the basic framework for the circuit to achieve wide-range input adaptation is formed. This dual-path design is the key to solving the technical pain point of limited input range of traditional CTLE. Furthermore, a circuit implementation scheme that achieves the best balance between performance coverage and resource consumption is also realized.

[0108] As an optional embodiment, in order to efficiently construct two input paths with significantly different input common-mode voltage ranges, the most basic and complementary device types in CMOS technology are adopted: the first differential input pair is composed of PMOS transistors, while the second differential input pair is composed of NMOS transistors.

[0109] As shown in FIG. 1, the PMOS differential input pair and the NMOS differential input pair are arranged in parallel, and the gate terminals of both are commonly connected to receive the differential signal of the external input, while the drain terminals of both are commonly connected to the subsequent differential load circuit. Figure 2

[0110] The technical principle of this design is rooted in the basic physical characteristics of MOS transistors. The conduction of an NMOS transistor requires its gate voltage to be significantly higher than its source voltage, so it is suitable for processing low common-mode level signals close to ground (GND). When the common-mode voltage of the input signal is in the low level range of, for example, 0.2V to 0.6V, the transistors of the NMOS differential input pair can easily maintain in the saturation region, providing stable and large enough transconductance (gm) to ensure effective amplification of the signal.

[0111] On the contrary, the conduction of a PMOS transistor requires its gate voltage to be significantly lower than its source voltage. In typical circuit design, the source of the PMOS differential input pair is usually connected to the high power supply voltage VDD, so it is suitable for processing high common-mode level signals close to VDD. When the common-mode voltage of the input signal is in the high level range of, for example, 0.8V to 1.2V, the PMOS differential input pair can enter its optimal working state, also providing ideal signal amplification performance.

[0112] Based on the above physical principles, the complementary design of PMOS transistors and NMOS transistors in this embodiment naturally leads to the input common-mode voltage range of the first differential input pair being higher than that of the second differential input pair. This is not simply a device stacking, but by deeply understanding the physical characteristics of the devices, the optimal working intervals of the two types of transistors are ingeniously combined together, thereby expanding the effective input voltage window of the entire CTLE from a single narrow range to a wide range covering from low level to high level.

[0113] Those skilled in the art can understand that there are not only one way to achieve different input common-mode ranges. In other embodiments, two differential input pairs of the same conduction type (for example, both NMOS) but with different threshold voltages can also be used. For example, a standard threshold voltage NMOS differential input pair and a low threshold voltage NMOS differential input pair can be combined, and the optimized working intervals of the two will also be different, which can also achieve the purpose of widening the input common-mode voltage range.​

[0114] In summary, the embodiment directly and efficiently solves the fundamental problem of limited input voltage range of the CTLE circuit in the prior art by using PMOS transistors and NMOS transistors to construct two differential input pairs respectively. When the input mode selection signal (REG_IN_SEL) is switched, the circuit can select the physical path most suitable for the current input signal common mode level to work, ensuring that the signal amplification stage works in the most efficient and linear state under any supported input mode, providing high-quality input for subsequent signal processing.

[0115] Based on the content of the embodiment, as an optional embodiment, the load control circuit includes a storage unit;

[0116] The storage unit is used to store a calibration code corresponding to each of the differential input pairs respectively;

[0117] The load control circuit is configured to read the storage unit, take the calibration code corresponding to the target differential input pair as the load configuration information, and adjust the equivalent impedance of the differential load circuit according to the load configuration information.

[0118] Considering that two differential input pairs with different physical characteristics are used, one of the technical challenges that must be faced is that due to inherent and random process variations in the manufacturing process, the two different differential input pairs will each introduce a DC offset that is completely independent in size and direction. Therefore, simply using a set of fixed calibration parameters according to the prior art cannot accurately compensate for the offset under the two modes at the same time.

[0119] To solve this technical problem, the present application proposes an innovative solution, the load control circuit includes a storage unit. The function of this storage unit is to establish and keep a respective exclusive calibration code for the two differential input pairs with different physical characteristics.

[0120] The calibration code is a specific digital embodiment of the load configuration information in this embodiment. The calibration code can be a set of digital codes, which are obtained by iterative calculation through a closed-loop feedback algorithm during the calibration phase of the final test or power-on initialization of the system. For example, when the NMOS differential input pair is enabled, the calibration algorithm will find a set of digital codes that can accurately zero the output offset voltage of the differential input pair, and define it as "Group A Code"; similarly, when switching to the PMOS differential input pair, the algorithm is run again independently to obtain another set of completely different digital codes, and define it as "Group B Code".

[0121] As shown in FIG. 1, in the real-time working phase, the load control circuit is configured to read the storage unit and use the calibration code corresponding to the target differential input pair as the load configuration information to adjust the equivalent impedance of the differential load circuit. The input mode selection signal REG IN SEL shown in FIG. 1 not only controls the transmission gate Tgate switch to select the physical input path, but also is sent to the load control circuit. The logic inside the load control circuit will accurately take out the corresponding calibration code from the storage unit according to the value of REG IN SEL (for example, '0' represents the NMOS mode and '1' represents the PMOS mode), that is, '0' corresponds to Group A Code and '1' corresponds to Group B Code. Figure 2 Figure 2 The specific physical implementation of the storage unit is also diverse. In an optional embodiment of the present application, the storage unit is composed of a set of programmable registers. This SRAM unit-based implementation has very high flexibility in the system, allowing software to rewrite and update the calibration code at any time.

[0122] In other possible embodiments, the storage unit can also be a non-volatile memory (NVM), such as a fuse or an eFuse. This method is suitable for scenarios where the calibration code does not need to be changed after being determined, and can be burned in one time before shipment, thereby reducing the chip area and the complexity of power-on initialization.

[0123] In addition, the storage unit can also be a shared memory block in the system on chip, and the load control circuit accesses the memory block through an internal bus interface to obtain the calibration code.

[0124] In addition, the storage unit can also be a shared memory block in the system on chip, and the load control circuit accesses the memory block through an internal bus interface to obtain the calibration code.

[0125] ​By introducing the storage unit of mode binding, the application acknowledges and respects the independence of different physical device mismatches, no longer tries to open two different "locks" with a "universal key", but accurately matches a special "key" (the respective calibration code) for each "lock" (PMOS pair and NMOS pair). The design of "special code for special use" ensures that the DC operating point of the CTLE can be accurately calibrated to the best state no matter which input mode it works in, thereby providing the signal with the maximum dynamic range and eye diagram margin, greatly improving the robustness and signal transmission quality of the entire link.

[0126] Based on the content of the above embodiment, as an optional embodiment, the storage unit includes a first register group and a second register group, and the load control circuit further includes a multiplexer;

[0127] The first register group stores a first calibration code corresponding to the first differential input pair, and the second register group stores a second calibration code corresponding to the second differential input pair.

[0128] The multiplexer is controlled by the input mode selection signal to switch output between the first register group and the second register group.

[0129] Figure 4 is a schematic diagram of the connection relationship between the load control circuit provided by the application and the differential load circuit, as Figure 4 shown, in order to realize independent storage and fast switching of the calibration codes in PMOS mode and NMOS mode, the storage unit is specifically a first register group (denoted as register group A) and a second register group (denoted as register group B), and the load control circuit further includes a multiplexer (Multiplexer) as a core selector.

[0130] In the specific implementation of the circuit, the first register group (register group A) is specially used for storing a first calibration code corresponding to the first differential input pair (PMOS mode). Similarly, the second register group (register group B) is specially used for storing a second calibration code corresponding to the second differential input pair (NMOS mode). The two register groups are physically independent storage units and can be written by software through a standard configuration bus (such as an APB bus), so as to fix the Group A Code and the Group B Code obtained in the test phase in the circuit.

[0131] The key of the circuit architecture provided by the present embodiment lies in the introduction of the multiplexer, as Figure 4As shown, two parallel multi-bit data input ports of the multiplexer are connected to the outputs of register group A and register group B respectively. The selection control end of the multiplexer directly receives the input mode selection signal from outside.

[0132] When the CTLE circuit needs to work, the multiplexer is controlled by the input mode selection signal to switch the output between the first register group and the second register group. The specific process can be as follows:

[0133] When the logic level of the input mode selection signal indicates that the PMOS mode is enabled (for example, the signal is logic '1'), the logic gate inside the multiplexer automatically opens the path to register group A, and the corresponding calibration code (denoted as the first calibration code) is transmitted to the output end.

[0134] Conversely, when the input mode selection signal indicates that the NMOS mode is enabled (for example, the signal is logic '0'), the multiplexer immediately switches to open the path to register group B, and the corresponding calibration code (denoted as the second calibration code) is selected to the output end.

[0135] Finally, the selected digital code output from the multiplexer is converted into the final load configuration information and directly sent to the control port of the differential load circuit to accurately set the equivalent impedance thereof.

[0136] The embodiment adopts a digital circuit design of double register groups plus a multiplexer, realizing high speed and high reliability of calibration code switching. Since the multiplexer is a pure combinational logic circuit, the delay of selection switching is extremely low (usually in nanoseconds), which can ensure that the corresponding calibration code can take effect immediately within the same clock cycle of input mode switching, meeting the demand of high-speed dynamic switching. Meanwhile, compared with other possible analog selection schemes, this standardized and fully digital implementation has better noise immunity and predictability, greatly simplifying the design, simulation and verification process of the circuit.

[0137] Those skilled in the art can understand that there are other equivalent circuit forms to realize the same selection logic. For example, two groups of tri-state buffers can be used to replace the multiplexer, and the outputs of the two groups of buffers are connected in parallel, and the enable ends of the two groups of buffers are controlled by the input mode selection signal to be mutually exclusive, which can also achieve the effect of two-to-one output. These equivalent replacements all fall within the scope of embodiments of the present application.

[0138] As an optional embodiment, the differential load circuit can further include a variable resistance array; and the load configuration information is used to adjust the resistance value of the variable resistance array, so that when the differential signal input into the CTLE is zero, the differential output voltage of the CTLE is substantially zero.

[0139] Optionally, the differential load circuit is implemented as a pair of variable resistance arrays symmetrically connected between the output of the differential amplifier and the power supply or ground.

[0140] Specifically, in the differential load circuit part, each side of the variable resistance array is composed of a plurality of parallel resistance branches. Each resistance branch can contain a fixed resistance element and a switch (such as a MOS switch) controlled by a digital signal. This structure allows the equivalent resistance value of the entire differential load circuit to be finely adjusted by digital control.

[0141] When the load control circuit determines the final load configuration information (such as Group A Code or Group B Code) according to the input mode selection signal, each bit of the digital code will be sent to the control end of the corresponding switch in the variable resistance array. By changing the value of the digital code, the on-off combination of different switches in the variable resistance array can be controlled.

[0142] For example, when a bit is '1', the corresponding switch is closed and the branch resistance is connected in parallel to the circuit; when a bit is '0', the corresponding switch is open and the branch resistance is removed from the circuit. The total equivalent resistance value of the circuit is the parallel connection of all the on-branch resistances. By binary weighting or thermometer coding design of the parallel resistance element value, linear and monotonic adjustment of the equivalent resistance value of the variable resistance array can be achieved.

[0143] It is important to emphasize that the ultimate goal of the above fine adjustment of the resistance value of the variable resistance array is to make the differential output voltage of the CTLE circuit essentially zero when the differential signal input to the CTLE circuit is zero. This is a crucial performance indicator that directly affects the eye diagram quality of the signal.

[0144] In an ideal case, when the differential input is zero (i.e. IN_P = IN_N), the current flowing through both sides of the differential amplifier should be exactly equal. At this time, if the load resistances on both sides are also exactly equal, the differential output voltage will naturally be zero. However, due to random deviations in manufacturing processes, the two transistors in the differential input pair cannot be completely symmetrical. This mismatch will cause the currents on both sides to be unequal even at zero input, resulting in a non-zero differential output voltage on the load, which is called offset.

[0145] The present application can actively and asymmetrically change the load size of both sides by fine-tuning the equivalent resistance value of one side or both sides of the differential load, so as to accurately offset the influence caused by the asymmetric current of the input stage. For example, if the current on the left side of the input stage is too large, the resistance value of the left load is slightly increased or the resistance value of the right load is slightly decreased, so that the voltage drops (I R) of both sides are restored to balance.

[0146] The load configuration information is repeatedly adjusted by the closed-loop calibration algorithm, and the differential output is monitored until the optimal combination code that makes the differential output closest to zero is found, and the optimal combination code is stored.

[0147] In the embodiment, the variable resistance array is used as the differential load, and the digital load configuration information is used for fine-tuning. Essentially, a post-compensation mechanism is provided, which provides an efficient, accurate and easy-to-digital-control correction method for solving the inevitable physical mismatch problem of the front-end input stage, and ensures that the CTLE circuit can have a clean and symmetric DC output operating point in any working mode, thereby providing the maximum dynamic range and signal-to-noise ratio for subsequent signal processing.

[0148] As an optional embodiment, a preferred structure for enhancing the core equalization function of the CTLE circuit is further provided. In order to enable the circuit to flexibly compensate for different degrees of high-frequency loss caused by different physical channels, the embodiment further integrates a configurable equalization network in the CTLE circuit.

[0149] Reference Figure 2 and Figure 3 As shown, the configurable equalization network can be a resistance-capacitance (RC) network coupled in the signal amplification path of the CTLE circuit. The coupling mode adopted is to connect the configurable equalization network in the form of source degeneration across the two source terminals of the differential input pair, so as to realize the functions of high-frequency enhancement and low-frequency suppression.

[0150] In actual operation, the configurable equalization network configuration is adjusted in response to an equalization control signal. The equalization control signal, like the input mode selection signal and the load configuration information described above, is also from the digital control and calibration logic shown in Figure 3 which can also be a digital code configured by software programming.

[0151] For example, the equalization control signals used include REG_R_SEL and REG_C_SEL, where REG_R_SEL is a multi-bit digital code, each bit of which controls the switch of a resistive element, and these switches determine which resistive elements are connected in parallel / series, thus combining a total equivalent resistance Rs. Similarly, REG_C_SEL is another digital code used to combine an equivalent capacitance Cs.

[0152] By writing different digital codes (for example, from 0001 to 1111) to REG_R_SEL and REG_C_SEL, the zero point position and gain peak of the configurable equalization network can be accurately and discretely changed, thus achieving accurate compensation for different channels.

[0153] Specifically, the impedance of the configurable equalization network exhibits different characteristics at different frequencies. At low frequencies, the capacitance in the configurable equalization network presents a high impedance (approximately open circuit), at which time the total impedance of the configurable equalization network is mainly determined by its internal resistance. At high frequencies, the impedance of the capacitance decreases with increasing frequency, and begins to play a dominant role in the total impedance of the configurable equalization network, thus reducing the equivalent impedance of the entire configurable equalization network at high frequencies.

[0154] When this frequency-dependent impedance network is placed at the source of the differential input pair, it changes the gain-frequency relationship of the entire amplifier: at low frequencies where the equivalent impedance is large, the source degeneration effect is strong, and the amplifier gain is low; at high frequencies where the equivalent impedance decreases, the source degeneration effect weakens, and the amplifier gain is correspondingly increased.

[0155] By adjusting the equalization control signals, the embodiment can change the combination of resistive and capacitive elements inside the configurable equalization network, thus changing the value of its equivalent impedance and the turning point of impedance change with frequency. This ultimately reflects on the overall performance of the CTLE circuit, that is, the flexible setting of the zero frequency and high-frequency gain in the frequency response characteristics. For example, in the face of a particularly severe loss channel (such as long-distance PCB wiring), software can configure the equalization control signals to increase the value of the high-frequency gain, providing stronger high-frequency lifting for the signal; at the same time, the position of the zero frequency can also be adjusted to accurately align with the inflection point where the signal spectrum begins to roll off, to achieve the most effective compensation.

[0156] Those skilled in the art can understand that the way to realize the configurable equalization network is not limited to the source degeneration structure. In other embodiments, the configurable equalization network can also be placed at the load end, in parallel with the differential load circuit, to achieve high-frequency enhancement by introducing a frequency-dependent shunt path. Alternatively, a multi-stage amplifier cascade structure can also be used, and adjustable RC elements can be introduced in the inter-stage coupling network. Although the specific circuits are different, these different topologies can all use adjustable frequency-dependent impedance to shape the gain curve of the amplifier.

[0157] By integrating this configurable equalization network, the CTLE circuit provided in this embodiment not only has the ability to calibrate a wide range of inputs and precise offsets, but also has strong channel adaptive capability. The single CTLE IP core can not only span different voltage domains, but also span different physical channels. Whether it is a short-distance, low-loss inter-chip interconnection or a long-distance, high-loss backplane application, it can find its best working equalization parameters through software configuration, greatly improving the versatility of the design and the robustness of the system.

[0158] As an optional embodiment, a digital configurable equalization network internal implementation structure is further provided. In order to realize flexible and accurate adjustment of the equivalent impedance, this embodiment discards complex analog designs such as analog voltage-controlled variable resistors, and instead uses a full-digital control array structure.

[0159] Specifically, the configurable equalization network includes a resistance array and / or a capacitance array:

[0160] The resistance array includes a plurality of resistance elements controlled by a first switch to access;

[0161] The capacitance array includes a plurality of capacitance elements controlled by a second switch to access;

[0162] The equalization control signal adjusts the equivalent impedance by controlling the on-off state of the first switch and / or the second switch.

[0163] In this embodiment, the decoupling control of the low-frequency gain and the high-frequency gain can be realized by a separate resistance array or a separate capacitance array, but also by the coexistence and cooperation of the resistance array and the capacitance array to realize the decoupling control of the low-frequency gain and the high-frequency gain:

[0164] Specifically, the resistance array is composed of a plurality of parallel resistance branches, for example, M resistance branches composed of RS1 to RSM. Each resistance branch internally includes a fixed resistance element and a pass controlled by a first switch (such as a MOS tube switch).

[0165] Similarly, the capacitor array also adopts a similar structure, which is composed of multiple parallel capacitor branches, such as K capacitor branches CS1 to CSK, each of which includes a fixed capacitor element and a second switch.

[0166] Through the above array design, the complex analog parameter adjustment problem is converted into a simple digital logic control problem. The equalization control signals REG_R_SEL and REG_C_SEL are physically two groups of multi-bit digital buses. Each bit of REG_R_SEL is connected to the control end of the corresponding first switch in the resistance array, and each bit of REG_C_SEL is connected to the control end of the corresponding second switch in the capacitor array.

[0167] When the software needs to adjust the equalization characteristics, different digital codes are written to the two registers. The equalization control signals adjust the equivalent impedance by controlling the on-off state of the first switch and / or the second switch. For example, when a bit in REG_R_SEL is high, the corresponding first switch is closed, and the resistance branch is connected in parallel to the circuit; otherwise, the branch is disconnected. By changing the digital value of REG_R_SEL, different resistance branches can be flexibly combined to achieve step-by-step adjustment of the total equivalent resistance The working principle of the capacitor array is exactly the same, and the value of REG_C_SEL controls the size of the total equivalent capacitance .

[0168] The zero frequency of the CTLE is mainly determined by the product of the total equivalent resistance and the total equivalent capacitance , and the high-frequency gain peak value is related to the ratio of the total equivalent resistance and the load resistance. By separating the resistance array and the capacitor array and controlling them with two independent digital codes, this embodiment realizes approximate orthogonal adjustment of the low-frequency frequency and the high-frequency gain, greatly simplifying the design of the system-level adaptive equalization algorithm. The algorithm can first fix one parameter (such as the total equivalent resistance ) and scan the other parameter (such as the total equivalent capacitance ) to find a local optimal solution, and then reverse it for fine tuning, thereby efficiently converging to the globally optimal equalization point.

[0169] Based on the above principle, this embodiment provides a very flexible, accurate and easy-to-integrate digital control resistance / capacitance array structure for the frequency response adjustment of the CTLE circuit. It converts the complex analog tuning task into a simple register read-write operation, greatly improving the robustness of the design and the efficiency of the automatic calibration.​

[0170] The impedance of the configurable equalization network is a function of frequency, as analyzed in the previous embodiments, which presents a higher impedance at low frequencies, mainly due to the total equivalent resistance of the resistance array determination; while at high frequencies, it presents a lower impedance due to the bypass effect of the capacitance array. According to the gain theory of a negative feedback amplifier, the gain of the entire differential amplification stage is approximately proportional to the load impedance and inversely proportional to the source degeneration impedance.

[0171] Therefore, this frequency-dependent source degeneration impedance directly leads to the frequency dependence of the amplifier gain, i.e., the CTLE circuit provided in this embodiment has a first gain at a frequency band lower than the use frequency, and a second gain higher than the first gain at a frequency band higher than the use frequency.

[0172] Specifically, when the signal frequency is low, the equivalent impedance of the configurable equalization network is high and approximately constant, at which time the circuit exhibits a low first gain, i.e., a direct current gain. As the signal frequency increases, the equivalent impedance of the configurable equalization network begins to drop significantly, and the source degeneration effect weakens, thereby gradually increasing the gain of the amplifier. Eventually, the gain reaches a peak, i.e., a second gain higher than the first gain, also known as a high-frequency peak gain.

[0173] The zero frequency is exactly the turning point frequency at which the gain curve starts to rise from the first gain to the second gain. The physical significance of this frequency point is that it marks the starting point of the CTLE for "high-frequency compensation" of the signal. By adjusting the value of the total equivalent resistance and / or the total equivalent capacitance of the configurable equalization network, the position of this zero frequency can be precisely moved.

[0174] This frequency response characteristic capable of generating two different gain flat regions and a controllable gain rise is crucial for the recovery of high-speed serial signals. A typical high-speed signal will suffer more severe attenuation of high-frequency components than low-frequency components after passing through physical channels such as PCB traces and connectors, resulting in inter-symbol interference and eye closure. The CTLE circuit provided in this embodiment can effectively pull the attenuated high-frequency components back to their proper amplitudes by generating a gain curve opposite to the channel loss characteristic, i.e., maintaining a moderate gain at low frequencies and providing a reverse-compensated gain peak at high frequencies, thereby reopening the eye diagram of the signal and providing a clear and reliable waveform for subsequent data decision.

[0175] In summary, by introducing the configurable equalization network, the CTLE circuit provided in this embodiment has the ability of frequency-selective amplification, and can accurately improve the intelligent equalization of damaged high-frequency components.

[0176] As an optional embodiment, the CTLE circuit provided by the application can further comprise a transmission gate structure; the transmission gate structure is coupled between a signal input pad of the CTLE and the differential input stage module; the transmission gate structure is configured to provide a signal path when the CTLE is in an operating state, and provide a high-impedance isolation or electrostatic discharge protection path when the CTLE is in a non-operating state.

[0177] Reference Figure 2 and Figure 3 As shown in FIGS. 1 and 2, the transmission gate structure Tgate is coupled between the signal input pad (i.e. the input+ and input- physical pins of the chip) of the CTLE and the differential input stage module. The coupling mode adopted can be a series insertion relationship, meaning that all differential input signals entering or exiting the CTLE circuit must first pass through this transmission gate structure.

[0178] The transmission gate structure is essentially a high-performance differential analog switch, whose on and off states are strictly controlled by an independent digital control signal (such as the EN signal). Its introduction provides two distinct but crucial functional modes for the CTLE circuit:

[0179] When the entire CTLE is enabled, the transmission gate structure is configured to be in a fully on state, in which it exhibits as low and linear on-resistance as possible to ensure that the external input signal can be transmitted to the internal differential input stage module with minimal distortion and attenuation.

[0180] When the CTLE is in a non-operating state, the transmission gate structure is configured to be in an off state, which provides a high-impedance isolation or electrostatic discharge (ESD) protection path. For example, when the entire chip enters a low-power sleep mode or the function of the CTLE is not used, the transmission gate structure is configured to be in an off state. In this state, it first provides high-impedance isolation. The off transmission gate structure exhibits extremely high impedance, which effectively isolates the internal sensitive core circuit from the external input pad that may have noise or uncertain level, preventing unnecessary signal crosstalk and static power leakage.

[0181] Secondly and more critically, the transmission gate structure is usually designed in coordination with the electrostatic discharge (ESD) protection circuit of the chip, or it itself is part of the ESD protection strategy. When a high-energy electrostatic pulse strikes the input pad, the transmission gate structure in the off state can withstand high voltage and direct the huge instantaneous current to a specially designed ESD discharge path (such as using its parasitic diode or parallel dedicated ESD devices), thereby protecting the more advanced and fragile core amplifier circuit behind it from permanent physical damage.

[0182] Those skilled in the art can understand that the way to realize the signal path control is not only the transmission gate structure. For example, the switching of the module can also be realized by controlling the bias current of the differential input stage module itself, but this way may not provide effective protection for external ESD events. Therefore, adding an independent transmission gate structure at the input end is the best engineering practice considering the functional switching and physical protection.

[0183] In summary, the embodiment greatly improves the practicability and reliability of the CTLE circuit by adding a controllable transmission gate structure on the input path. Not only does it realize power saving through high impedance isolation and give the module level power management ability, but more importantly, it builds a solid physical defense line, significantly enhancing the robustness of the entire chip against electrostatic impact, which is crucial for ensuring product yield and long-term reliability in complex environments.

[0184] Based on the above embodiment, as an optional embodiment, the transmission gate structure includes an NMOS transmission tube and a PMOS transmission tube connected in parallel.

[0185] The input selection circuit controls the on-off of the signal path by controlling the gate voltage of the NMOS transmission tube and the PMOS transmission tube.

[0186] Reference Figure 2 Referring to the details of the transmission gate structure Tgate shown in FIG. 6, it can be seen that each differential signal path (e.g., the IN_P path) is composed of an NMOS transistor and a PMOS transistor connected in parallel. The source and drain of the two transistors are connected to each other, and together form the input and output of the signal. This parallel design cleverly takes advantage of the complementary nature of the device conduction characteristics of NMOS transistors and PMOS transistors to overcome the inherent defects of a single type of transistor as a switch:

[0187] When an NMOS transistor is used as a switch, it can transmit low-level signals close to GND well, but when the input signal level rises, the gate-source voltage difference decreases, and the on-resistance increases sharply, resulting in poor transmission of high-level signals and signal amplitude attenuation.

[0188] On the contrary, when a PMOS transistor is used as a switch, it can transmit high-level signals close to VDD well, but its transmission ability for low-level signals will decrease.

[0189] By connecting the NMOS transistor and the PMOS transistor in parallel, when the input signal is at a low level, the NMOS transistor is in a low-resistance on state; when the input signal is at a high level, the PMOS transistor is in a low-resistance on state; and in the intermediate voltage range, both transistors are in a certain on state. The on-resistance curves of the two are superimposed together, which can maintain a relatively low and flat total on-resistance in the entire voltage range from low level GND to high level VDD. This ensures that the transmission gate structure can realize low-loss transmission for signals of different levels, greatly reducing signal distortion.

[0190] In order to control the switching state of the transmission gate structure, an input selection circuit or an independent enable control logic is used to control the on-off of the signal path by controlling the gate voltages of the NMOS transmission tube and the PMOS transmission tube. The two gate voltages are usually a pair of complementary control signals, such as EN and the inverse signal EN_B of EN.

[0191] When the transmission gate structure needs to be turned on, a high level VDD is applied to the gate of the NMOS transistor, and a low level GND is applied to the gate of the PMOS transistor, so that both transistors enter a strong on state.

[0192] When the transmission gate structure needs to be turned off, the reverse operation is performed, a low level GND is applied to the gate of the NMOS transistor, and a high level VDD is applied to the gate of the PMOS transistor, so that both transistors enter a reliable off state.

[0193] The embodiment provides a high-performance signal switch by using the CMOS transmission gate structure of the parallel connection of the PMOS transistor and the NMOS transistor. Not only does it overcome the limitation of single transistor switch in signal swing, ensuring the fidelity of high-speed signals, but also provides a clear and reliable switching interface controlled by complementary digital signals, perfectly fitting the design concept of digitalization and modularization of the entire CTLE circuit.

[0194] Based on the content of the above embodiment, as an optional embodiment, all key control signals for regulating the behavior of the CTLE, that is, the input mode selection signal, the load configuration information, and the equalization control signal mentioned in the foregoing implementation, and the like, are ultimately in the form of digital signals that can be programmed and configured. That is, in the physical implementation of the circuit, the values of these control signals are not fixedly written by hardware logic, nor are they directly set by analog voltage, but are stored in a series of programmable configuration registers inside the CTLE module.

[0195] For example, the value of the input mode selection signal corresponds to a register named REG_IN_SEL. The value of the load configuration information corresponds to the aforementioned Group A Code and Group B Code register groups. The value of the equalization control signal corresponds to the REG_R_SEL and REG_C_SEL registers.

[0196] Optionally, these registers are connected to the chip's central processing unit (CPU) or dedicated microcontroller through a standard on-chip bus interface, such as the Advanced Peripheral Bus (APB) or similar low-speed configuration bus.

[0197] This fully digital, software programmable architecture brings multiple profound technical advantages:

[0198] First, software can dynamically change any key parameter of the CTLE at runtime through a simple bus write operation. This allows the same CTLE hardware design to be easily configured to support multiple different communication protocols. For example, by changing the equalization parameters to adapt to Universal Serial Bus (USB), or USB and Peripheral Component Interconnect Express (PCIe), or adjusting the equalization code through adaptive algorithms to adapt to different channel environments, or by switching input modes and calibration codes to be compatible with different vendor interface chips.

[0199] Second, it simplifies the implementation of automatic calibration and adaptive algorithms, whether it is the offset calibration at power-on or the adaptive equalization at runtime. The core of both is a "read-compute-write" closed-loop iteration process. Since all control signals are digital registers, this allows the upper-layer firmware or software algorithm to accurately quantize the control of the CTLE and read back the state, greatly simplifying the development and integration of complex control algorithms.

[0200] In addition, it also enhances testability and debuggability, i.e. during the production testing and system debugging of the chip, test engineers or software engineers can directly access these configuration registers, forcing the CTLE to enter a certain specific working mode, or scanning the settings of a parameter one by one, thereby quickly locating design defects or performance bottlenecks. This white-box observability and controllability is crucial for ensuring product quality and accelerating problem solving.

[0201] In summary, this embodiment unifies all core control nodes of CTLE into a software-programmable digital interface, encapsulating a originally complex analog circuit module into a highly software-friendly and predictable digital peripheral, greatly improving reusability, adaptability, and maintainability, and fully aligning with the design trends of modern large-scale integrated circuits.

[0202] To enable those skilled in the art to gain a deeper understanding of the specific circuit implementation of the proposed solution, this embodiment will combine... Figure 2 To elaborate in detail, such as Figure 2 As shown, it illustrates in detail the complete circuit principle of the CTLE circuit in a specific embodiment of the present invention, which integrates all functions such as dual-mode input selection, configurable equalization, and offset calibration with mode linkage.

[0203] First, the differential signal of the CTLE circuit is input from the external pad PAD, and first passes through a CMOS transmission gate structure Tgate controlled by the input mode selection signal REG_IN_SEL and its inverted signal REG_SELB. Tgate is responsible for turning the external signal path on or off and providing electrostatic discharge protection.

[0204] After passing through the Tgate, the signal path is split into two parallel differential amplification paths:

[0205] lie in Figure 2 The PMOS path above consists of a pair of PMOS transistors forming the main differential input pair, used to process input signals with high common-mode voltage.

[0206] lie in Figure 2 The NMOS path below consists of a pair of NMOS transistors forming the main differential input pair, used to process low common-mode voltage input signals. The REG_IN_SEL signal not only controls the front-end Tgate but also controls the switching of the bias current sources for both paths, ensuring that only one path is enabled at any given time, thereby saving power consumption.

[0207] A configurable equalizer network is connected between the source terminals of these two differential paths. This configurable equalizer network consists of a variable resistor and a variable capacitor connected in series, whose resistance and capacitance values ​​are digitally controlled by external equalizer control signals REG_R_SEL and REG_C_SEL, respectively. By adjusting these two equalizer control signals, the low-frequency and high-frequency gains of the CTLE circuit can be precisely set to compensate for different channel losses.

[0208] In the load part of the equalization control signal circuit, the upper and lower paths correspond to the respective differential active loads. The active load is composed of a pair of cross-coupled PMOS transistors, which is used to provide negative resistance characteristics to improve the gain. The key is that an adjustable resistance element is integrated into each side of the differential active load for offset calibration. The control signals of these adjustable resistances, i.e. the final load configuration information TRIM_CODEP for the positive terminal output and the load configuration information TRIM_CODEN for the negative terminal output, are not fixed but dynamically generated by the calibration code selection logic.

[0209] It should be noted that the calibration code selection logic is the key hardware for realizing the core idea of the present application: two independent sets of calibration code registers REG_TRIM_CODEP_A and REG_TRIM_CODEN_A are preset in the circuit, which together constitute the A group of calibration codes, for example, corresponding to the NMOS mode; the calibration code registers REG_TRIM_CODEP_B and REG_TRIM_CODEN_B together constitute the B group of calibration codes, for example, corresponding to the PMOS mode.

[0210] The core function of the two multiplexers MUX is to perform "two-way" switching, and the selection control ends of the two MUXs are connected to the input mode selection signal REG_IN_SEL.

[0211] When REG_IN_SEL selects the NMOS mode, the MUX will send the outputs of the A group of calibration codes REG_TRIM_CODEP_A and REG_TRIM_CODEN_A as TRIM_CODEP and TRIM_CODEN to the load end.

[0212] When REG_IN_SEL switches to the PMOS mode, the MUX will synchronously switch the outputs of the B group of calibration codes REG_TRIM_CODEP_B and REG_TRIM_CODEN_B as TRIM_CODEP and TRIM_CODEN.

[0213] Finally, the outputs OUTP and OUTN of the two differential paths are selected by another set of switches controlled by REG_IN_SEL, ensuring that only the output signal of the path currently enabled is transmitted to the final output end of the CTLE circuit.

[0214] In addition, Figure 2 A reference voltage VREF for stabilizing the output common mode level is also shown in the middle, which is usually connected to the input end of a common mode feedback (CMFB) circuit to ensure that the DC level of the output signal is stabilized at a preset value.

[0215] This embodiment fully demonstrates how to utilize a unified control signal REG_IN_SEL to simultaneously realize triple linkage control of the input physical channel, load imbalance calibration code, and final output channel, thereby constructing a high-performance, high-flexibility, and robust adaptive CTLE circuit.

[0216] Figure 5 is a structural schematic diagram of a high-speed serial communication receiver provided by the application, as Figure 5 The aforementioned CTLE in any of the embodiments is integrated as a core functional module in the receiving link of the high-speed serial communication receiver (hereinafter referred to as a communication receiver), thereby significantly improving the performance and adaptability of the entire communication receiver.

[0217] Optionally, a complete high-speed signal receiving and recovery process performed by the communication receiver provided by the embodiment mainly includes the following key stages:

[0218] The communication signal enters the chip from the receiving pad. As a physical interface for connecting the chip to the external physical channel (such as PCB wiring, cable, or backplane), the received differential signal usually has serious intersymbol interference due to the high-frequency loss of the channel, and the signal eye diagram may have been completely closed.

[0219] The communication signal is first sent to the CTLE circuit provided by any of the embodiments, which is the first level core circuit of the analog front-end (AFE). The CTLE circuit undertakes the preliminary but crucial equalization task of the communication signal, including compensatory enhancement of the high-frequency component of the communication signal through its configurable frequency response characteristics, aiming to reopen the signal eye diagram.

[0220] Since the CTLE circuit provided by the application has a wide input common-mode voltage range, the entire receiver can be directly connected to the transmitter from different voltage domains without additional complex level conversion circuit, greatly enhancing the compatibility and interoperability of the system.

[0221] More importantly, since the adopted CTLE circuit has high-precision imbalance calibration capability linked with the input mode, it can ensure that a DC operating point extremely clean and imbalance-free analog signal is output to the subsequent circuit under any working mode. This is crucial for the performance of the entire receiving link, because any residual DC imbalance may cause the saturation of the subsequent amplifier or the deviation of the decision threshold of the decision maker, thereby causing a large amount of errors.

[0222] The signal which has been preliminarily equalized by the CTLE circuit is then sent to a variable gain amplifier (VGA). The function of the VGA is to amplify the input signal with different attenuation to a basically constant swing which is suitable for the processing of the subsequent circuit through an automatic gain control loop. The CTLE circuit of the present application can make the AGC loop of the VGA more stable and faster to lock, and the dynamic range of the VGA will not be occupied by the DC offset, so that the amplitude variation of the signal can be more effectively processed.

[0223] The communication signal with the standardized amplitude is further sent to a decision feedback equalizer (DFE). The DFE is a kind of nonlinear equalizer which uses the data bits which have been previously judged to eliminate the post-cursor interference caused by them. The CTLE circuit has processed most of the high-frequency loss to provide a better quality input signal for the DFE, which reduces the work burden of the DFE so that it can achieve the same performance with less order, thereby saving power consumption and area, or achieving lower bit error rate under the same complexity.

[0224] Finally, the completely equalized communication signal is sent to a clock and data recovery (CDR) unit. The CDR circuit extracts the clock signal from the serial data stream without independent clock and uses the clock signal to sample the data at the best judgment time to recover the original parallel data and clock. A high-quality eye diagram with a large opening degree is a prerequisite for the CDR to lock and extract a low-jitter clock. The CTLE circuit provided by the present application provides such an ideal input signal for the CDR through its excellent equalization and calibration capability, which directly ensures the reliability of the final data recovery.

[0225] In summary, by integrating the CTLE circuit provided by the present application which has the wide-range input adaptation capability and the mode linkage precise calibration function into the communication receiver, the communication receiver obtains great performance improvement at the system level, which can not only flexibly adapt to more diverse interface standards and physical channels, but more importantly, can ensure the quality of the signal from the front end of the signal processing link, laying a solid foundation for the stable and efficient work of all subsequent modules, and finally embodying the lower bit error rate and stronger environmental robustness of the entire communication system.

[0226] Those skilled in the art can clearly understand the technical solutions of the various embodiments from the above description of the embodiments, and the various embodiments can be implemented by means of software with the necessary general hardware platforms, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that makes a contribution, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0227] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A continuous-time linear equalizer, characterized in that, include: The differential input stage module includes multiple differential input pairs with different input common-mode voltage ranges; An input selection circuit is configured to, in response to an input mode selection signal, select one of all said differential input pairs as the target differential input pair for current operation. A differential load circuit is coupled to the output of the differential input stage module, and the differential load circuit has an adjustable equivalent impedance. A load control circuit is configured to, in response to the input mode selection signal, determine load configuration information corresponding to the target differential input pair, and adjust the equivalent impedance of the differential load circuit according to the load configuration information; The load control circuit includes a storage unit; The storage unit is used to store calibration codes corresponding to each of the differential input pairs; The load control circuit is configured to read the storage unit and use the calibration code corresponding to the target differential input pair as the load configuration information to adjust the equivalent impedance of the differential load circuit according to the load configuration information. The continuous-time linear equalizer further includes: A configurable equalization network, coupled to the signal amplification path of the continuous-time linear equalizer, is configured to adjust its equivalent impedance in response to an equalization control signal to set the low-frequency gain and high-frequency gain in the frequency response characteristics of the continuous-time linear equalizer. The configurable equalization network includes a resistor array and / or a capacitor array: The resistor array includes multiple resistor elements that are controlled and connected by a first switch; The capacitor array includes multiple capacitor elements connected under the control of a second switch; The equalization control signal adjusts the equivalent impedance by controlling the opening and closing states of the first switch and / or the second switch.

2. The continuous-time linear equalizer according to claim 1, characterized in that, The differential input pair consists of two pairs: a first differential input pair and a second differential input pair.

3. The continuous-time linear equalizer according to claim 2, characterized in that, The first differential input pair is composed of PMOS transistors, and the second differential input pair is composed of NMOS transistors; The input common-mode voltage range of the first differential input pair is higher than that of the second differential input pair.

4. The continuous-time linear equalizer according to claim 2, characterized in that, The storage unit includes a first register group and a second register group, and the load control circuit further includes a multiplexer. The first register group stores a first calibration code corresponding to the first differential input pair, and the second register group stores a second calibration code corresponding to the second differential input pair; The multiplexer is controlled by the input mode selection signal to switch the output between the first register group and the second register group.

5. The continuous-time linear equalizer according to claim 1, characterized in that, The differential load circuit includes a variable resistor array; The load configuration information is used to adjust the resistance value of the variable resistor array so that when the differential signal input to the continuous-time linear equalizer is zero, the differential output voltage of the continuous-time linear equalizer is substantially zero.

6. The continuous-time linear equalizer according to claim 1, characterized in that, In frequency bands below the operating frequency, the continuous-time linear equalizer has a first gain; in frequency bands above the operating frequency, the continuous-time linear equalizer has a second gain higher than the first gain.

7. The continuous-time linear equalizer according to claim 1, characterized in that, It also includes transmission gate structures; The transmission gate structure is coupled between the signal input pad of the continuous-time linear equalizer and the differential input stage module. The transmission gate structure is configured to provide a signal path when the continuous-time linear equalizer is in operation, and to provide a high-impedance isolation or electrostatic discharge protection path when the continuous-time linear equalizer is not in operation.

8. The continuous-time linear equalizer according to claim 7, characterized in that, The transmission gate structure includes parallel NMOS transmission transistors and PMOS transmission transistors; The input selection circuit controls the on / off state of the signal path by controlling the gate voltages of the NMOS and PMOS transmission transistors.

9. The continuous-time linear equalizer according to claim 1, characterized in that, The input mode selection signal, the load configuration information, and the equalization control signal are all digital signals that can be configured through software programming.

10. A high-speed serial communication receiver, characterized in that, Includes the continuous-time linear equalizer as described in any one of claims 1 to 9.

Images