Manufacturing method of semiconductor device
By introducing wet etching or vapor etching steps and controlling the deposition of the substrate layer in the manufacturing of 3D NAND memory, the problem of aspect ratio control during the etching process is solved, the stability and reliability of the memory are improved, and the complexity of the etching process is reduced.
Patent Information
- Application Number
- CN202410816860.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-24
- Publication Date
- 2025-12-26
AI Technical Summary
In the manufacturing of 3D NAND memory arrays, it is difficult to control the aspect ratio of word line contacts during the etching process, which can easily lead to over-etching or under-etching, resulting in unwanted short circuits and reduced product stability.
By introducing wet etching or steam etching steps to treat the etching termination layer, and by controlling the deposition conditions of the pad layer, the thickness of the pad layer on the surface of the target dielectric layer at different depths is ensured to be uniform, reducing the difficulty of subsequent etching processes and maintaining effective isolation between the contact electrode and the word line conductive layer.
This improves the stability and reliability of 3D NAND memory, reduces the difficulty of the etching process, and maintains effective isolation between the contact electrodes and the word line conductive layer, thereby enhancing the overall performance of the product.
Smart Images
Figure CN121218596A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates generally to the field of integrated circuits (ICs), and more particularly, to a method of manufacturing a 3D memory device. BACKGROUND
[0002] Memory is commonly used in integrated circuits to store data. Memory typically includes volatile memory and non-volatile memory. One example of non-volatile memory is flash memory, such as 3D NAND memory.
[0003] A typical flash memory device can include a memory array that includes a large number of non-volatile memory cells arranged in rows and columns. In recent years, vertical memory such as 3D memory has been developed. A 3D flash (e.g., 3D NAND memory array) device can include multiple strings of charge storage devices (memory cells) stacked on top of each other. Each group of multiple strings can share multiple access lines, referred to as word lines (WLs). Each of the multiple access lines can be coupled (e.g., electrically connected via a provided contact) to charge storage devices (memory cells) corresponding to a respective layer of each string.
[0004] As 3D NAND memory arrays evolve, they tend to use a larger number of word lines and exhibit greater depth. Thus, in 3D NAND processes, the memory array is often created in a staircase structure of word lines. That is, a 3D NAND memory array typically includes multiple word lines arranged in an interleaved or "staircase" fashion, with vertical contact electrodes connecting a top connection layer to the word lines, each at a particular distance from the top of the memory array. Word lines located at a lower or deeper portion of the staircase are at a relatively greater distance from the top of the memory array than word lines located at a higher or shallower portion of the staircase. As more and more levels of memory cells are packed within the memory array (i.e., as the number of word lines increases), the word line contacts extend deeper into the array to reach the word lines at the relatively bottom of the staircase.
[0005] In the fabrication of 3D NAND memory arrays, it can be challenging to ensure that the formed word line contacts stop on the intended word line without leaking to another word line (e.g., by penetrating the intended word line or leaking to an underlying word line) and thus creating an undesirable short during etching. Currently, the controllability of etching is often improved by adding an etch stop layer. However, during etching of the etch stop layer, the problem of over-etching or under-etching can arise due to the different depths of the word line contacts. SUMMARY
[0006] A method of fabricating a semiconductor device is provided. The method includes providing a stack, wherein the stack includes a plurality of pairs of dielectric layers and conductive layers stacked on each other, a dielectric layer in each pair of dielectric layers and conductive layers is disposed above a conductive layer in the pair, one end of each pair of dielectric layers and conductive layers in a first direction extends beyond a corresponding end of an upper pair of dielectric layers and conductive layers adjacent thereto in the first direction, thereby forming a plurality of stepped portions, and the stack further includes a termination layer disposed on the plurality of pairs of dielectric layers and conductive layers and a step gap fill layer disposed on the termination layer; etching the step gap fill layer to expose the termination layer, thereby forming a first recess corresponding to the plurality of stepped portions; etching the first recess to expose a lower dielectric layer adjacent to the termination layer, thereby forming a second recess having a lateral recess portion; depositing a liner layer such that the liner layer is formed on an entire surface of the second recess, thereby forming a third recess having a width in the first direction that is narrower than the first recess; and etching the third recess to expose a conductive layer corresponding to the lower dielectric layer, thereby forming a contact hole.
[0007] In some preferred embodiments, a conductive material is deposited into the contact hole to form a contact electrode.
[0008] In some preferred embodiments, the conductive material can include copper, tungsten, aluminum, tungsten nitride, tantalum nitride, titanium nitride, and combinations thereof.
[0009] In some preferred embodiments, the gap fill layer can be etched using dry etching.
[0010] In some preferred embodiments, the first recess can be etched using wet etching or vapor etching.
[0011] In some preferred embodiments, the liner layer can be deposited using atomic layer deposition or chemical vapor deposition.
[0012] In some preferred embodiments, the material of the liner layer can be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, metal oxide, metal oxynitride, metal silicate, high-k material, or combinations thereof.
[0013] In some preferred embodiments, the third recess can be etched using dry etching.
[0014] In some preferred embodiments, the semiconductor device can be a 3D NAND memory or a 3D DRAM memory.
[0015] In some preferred embodiments, the conductive layer can be a word line conductive layer.
[0016] In some preferred embodiments, the word line conductive layer can be polysilicon or nitride.
[0017] In some preferred embodiments, the material of the termination layer can be nitride, metal oxide.
[0018] In some preferred embodiments, the depth of the lateral recess can be 30-200 nm.
[0019] Using the memory manufacturing method of the present application, by introducing an additional wet etching or vapor etching step, the etching termination layer is processed so that the etching termination layer on the surface of the target dielectric layer is removed, exposing the target dielectric layer. Then by controlling the deposition conditions to control the formation of the liner layer, the total thickness of the liner layer and the target dielectric layer on the surface of the target word line conductive layer of different depths is relatively uniform, which can better control the synchronization of the subsequent etching process; the material of the liner layer and the target dielectric layer is relatively similar, which significantly reduces the difficulty of the subsequent etching process, and still ensures that the contact electrode and the word line conductive layer maintain effective isolation, improves the stability and reliability of the 3D NAND memory product. BRIEF DESCRIPTION OF DRAWINGS
[0020] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. The drawings are only exemplary and are not a limitation on the present application. In the drawings, the same reference signs represent the same parts in various figures and embodiments of the present application, wherein:
[0021] Figure 1A An example cross-sectional side view schematically illustrates a word line staircase structure of a 3D NAND memory array.
[0022] Figure 1A An example cross-sectional side view schematically illustrates a word line staircase structure of a 3D NAND memory array having an etching termination layer.
[0023] Figures 2A-2D A process method for forming a memory cell according to the commonly used method is shown.
[0024] Figures 3A-3F A process method for forming a memory cell according to the method of an embodiment of the present application is shown.
[0025] Figure 4 An example cross-sectional side view of an integrated word line contact structure obtained according to some embodiments of the present application is shown.
[0026] Figure 5 A TEM image of a cross-section of a semiconductor device obtained according to the commonly used method.
[0027] Figure 6 A TEM image of a cross-section of a semiconductor device obtained according to the method of an embodiment of the present application.
[0028] Reference Signs List
[0029] 100 staircase structure; 101 and 101' dielectric layer; 102 and 102' word line conductive layer; 201 and 201' gap fill layer; 202 and 202' etch stop layer; 301 and 301' support substrate; 302 connection layer; 401 and 401' first recess; 402 second recess; 403 third recess; 404 and 404' contact hole; 402a lateral recess; 501 liner layer; 601 and 601' contact electrode. Wherein a, b, c, d and e represent different dielectric layers and word line conductive layers respectively.
[0030] Like reference numerals and names of elements in the various figures indicate like elements.
[0031] It should be understood that, for clarity's sake and / or for simplicity of illustration, the elements shown in the drawings are not necessarily to scale. For example, the dimensions of some of the elements can be exaggerated relative to other elements for clarity of presentation. Also, for ease of understanding, in the drawings, elements known in the art have been omitted. The dimensions of the drawings are not intended to represent the precise dimensions of and / or the scale relative to the various elements depicted herein. DETAILED DESCRIPTION
[0032] In the following description, numerous specific details are set forth. However, embodiments described herein can be practiced without the specific details. In some instances, well-known structures and techniques have not been shown in detail in order not to obscure the understanding of this description.
[0033] In presenting specific examples in a figure or description having two or more layers in a multi-layer structure, the relative positioning relationship of these layers or the order of arranging the layers as shown reflects the specific implementation of the described or shown example, and different relative positioning relationship or order of arranging the layers is possible.
[0034] As 3D NAND technology develops, memory arrays continue to expand in the stacking direction, and the etching process of the staircase structure becomes more challenging. The 3D memory array described herein includes a plurality of word lines (WLs) and corresponding plurality of word line contacts in the stacking direction. Figure 1A An example cross-sectional side view of a word line staircase structure of a 3D NAND memory array is schematically illustrated. Referring to Figure 1Adepicts a staircase structure 100 formed by alternately layering a plurality of conductive layers (e.g., 102a, 102b, 102c, 102d, and 102e) and a plurality of dielectric layers (e.g., 101a, 101b, 101c, 101d, and 101e) on a support substrate 301 in a 3D NAND memory array. In this context, the conductive layers are generally word line conductors. Although not explicitly shown in the figure, as understood by those skilled in the art, a plurality of memory cells and associated circuit elements, such as silicon-based word line segments, floating gates, control gates, non-silicon metal word line segments, etc., can be formed in the word line conductors 102a, 102b, 102c, 102d, 102e. However, it should be understood that while 5 layers of dielectric layers and 5 layers of word line conductors are shown in Figure 1A , this is illustrative only and that in actual memory there can be more or less layers of dielectric and word line conductors. As shown in Figure 1A , the staircase structure can include two or more word line conductors (e.g., 102a, 102b, 102c, 102d, and 102e) disposed adjacent to each other. In the staircase structure 100, the dielectric layers 101a, 101b, 101c, 101d, and 101e and the word line conductor layers 102a, 102b, 102c, 102d, and 102e are alternately layered. One end of a word line conductor (e.g., 102b) and its corresponding dielectric layer 101b extends beyond the corresponding end of an adjacent word line conductor (e.g., 102a) and its corresponding dielectric layer 101a disposed above the word line conductor 102b and its corresponding dielectric layer 101b, forming a staircase.
[0035] As 3D NAND memory arrays evolve, they tend to use a larger number of word lines and exhibit greater depths. Due to the large difference in word line depths, ranging from a few hundred nanometers to a few microns, the aspect ratio of the etch is large, making it difficult to control the etch precision, and it is easy to cause physical or electrical contact of the word line contact structure with the adjacent word line, thereby reducing the stability of the product. Currently, in the manufacturing process of both FG NAND and RG NAND memory arrays, an etch stop layer is added to prevent physical or electrical contact of the word line contact structure with the adjacent word line of the staircase structure, to avoid unwanted short circuits, improve product performance, and improve the reliability of the etching process. The process of adding an etch stop layer is also used in the manufacturing process of 3D NAND memory arrays. Figure 1B An example cross-sectional side view of a word line staircase structure of a 3D NAND memory array with an etch stop layer is schematically illustrated. As shown in Figure 1B , in Figure 1AAn etching stop layer 202 can be formed on the steps, and a gap fill layer 201 is formed on the surface of the etching stop layer 202.
[0036] It is known that the thickness of the gap fill layer can be several hundred nanometers to several microns with the change of the depth of the word line conductive layer. Although the selectivity of etching can be improved by controlling the etching conditions, part of the etching stop layer will still be etched during the etching process. Since the etching conditions and etching time during the dry etching of the gap fill layer are basically the same, more etching stop layer is etched at the shallowest part of the steps, and less etching stop layer is etched at the deepest part of the steps.
[0037] The method of forming a contact hole in the stepped structure of a 3D NAND memory array to form a word line contact structure typically includes an etching process involving the following steps: etching through the gap fill layer to reach the etching stop layer corresponding to each step, and then etching through the etching stop layer and the dielectric layer of each step (hereinafter referred to as "target dielectric layer") to reach the word line conductive layer of each step (hereinafter referred to as "target word line conductive layer") / end at the target word line conductive layer. During the etching of the etching stop layer and the target dielectric layer, since the thickness of the remaining etching stop layer at different depths of the memory array is different after etching the gap fill layer, over-etching or under-etching is likely to occur in the target word line conductive layer region.
[0038] Figures 2A-2D The typical etching process of the above-mentioned method of forming a contact hole in the stepped structure of a 3D NAND memory array to form a word line contact structure is described. For the purpose of simplification, only a corresponding pair of word line conductive layer and dielectric layer, i.e. the target word line conductive layer and the target dielectric layer of the memory cell, in the plurality of word line conductive layers and the plurality of dielectric layers alternately stacked on the support substrate 301' of the memory cell are depicted in Figures 2A-2D
[0039] As shown in Figure 2A , an etching stop layer 202' is provided on the target dielectric layer 101' and the target word line conductive layer 102' of the stepped structure, and a gap fill layer 201' is provided on the etching stop layer 202'. The etching stop layer 202' and the gap fill layer 201' are continuous on the stepped structure. As shown in Figure 2B , by the first etching, the gap fill layer 201' is removed, a first recess 401' is formed on the stepped structure 100', and the etching is stopped at the etching stop layer 202'. The etching method is a common dry etching process. In some embodiments, after etching, the thickness t' of the etching stop layer 202' is less than the thickness t of the etching stop layer 202. N is 20-120 nm. Next, a second etching is performed along the first groove 401' to remove the etching stop layer 202' and the target dielectric layer 101', exposing the target word line conductive layer 102', forming a contact hole 404', as shown in Figure 2C . The etching method is a common dry etching process. Finally, metal is deposited into the contact hole 404', forming a contact electrode 601', and coupled with the exposed target word line conductive layer 102', forming a structure as shown in Figure 2D .
[0040] As described above, due to the large difference in depth of the different target word line conductive layers 102' in the stepped structure, the thickness of the gap filling layer 201 at different depths is also large. After the first etching process, the thickness (t' N ) of the remaining etching stop layer 202' at different depths is different, and the deeper the depth, the greater the thickness of the remaining etching stop layer 202'. In the second etching process, it is more difficult to control the aspect ratio of the contact hole formed under the same etching conditions, and over-etching in the shallower region and under-etching in the deeper region are prone to occur, as shown in Figure 5 .
[0041] The present application provides a semiconductor device manufacturing method, which can avoid the problems of over-etching and under-etching in the etching stop layer process. It should be understood that, in order not to obscure the technical concept of the present application, many descriptions of known structures and / or process steps are omitted. The examples described below are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application. If a specific technology or condition is not specified in the examples, it is performed according to the technology or condition described in the literature in the art or according to the product instructions.
[0042] Figures 3A-3F A process method for forming a memory cell according to the method of the embodiment of the present application is shown. Each figure shows different stages of the process of forming a memory cell in sequence. For the purpose of simplification, only a corresponding pair of word line conductive layer and dielectric layer, i.e. the target word line conductive layer and the target dielectric layer of the memory cell, is depicted in Figures 3A-3F . Various features of the 3D memory device that can be formed in the process of manufacturing the 3D memory device, such as electrical wiring features, interconnection structures, etc., are not shown in the figures. According to the embodiment of the present application, as shown in Figure 3A , an etching stop layer 202 is provided above the target dielectric layer 101 and the target word line conductive layer 102 of the stepped structure in the stacking direction, and a gap filling layer 201 is provided above the etching stop layer 202, forming a structure as shown in Figure 3AThe etch stop layer 202 and the gap fill layer 201 are continuous on the staircase structure 100. Since the depths of the target dielectric layers 101 and the target word line conductive layers 102 are different on the staircase structure 100, the thickness of the gap fill layer 201 on the target dielectric layers 101 at different depths is not uniform.
[0043] In some embodiments, the thickness of the dielectric layer 101 can be 10-50 nm, and the thickness of each dielectric layer 101 can be the same or different from each other. The thickness of the dielectric layer 101 in a suitable range can ensure effective isolation between the word line conductors and prevent current breakdown. However, when the dielectric layer is thicker, the final memory structure formed is too thick, and the etching process is also more difficult. In some embodiments, the thickness of the word line conductive layer 102 can be 20-60 nm, and the thickness of each word line conductive layer 102 can be the same or different from each other. When the thickness of the word line conductive layer 102 is too small, the height and volume of the corresponding storage unit are too small, resulting in insufficient performance of the single storage unit. In some embodiments, the thickness of the gap fill layer 201 can be 5-30 μm. The gap fill layer 201 is used to achieve effective electrical isolation between different storage units, and when the thickness is too small, the isolation effect between different storage units cannot be guaranteed. In some embodiments, the thickness H n of the etch stop layer 202 can be 30-150 nm. The etch stop layer 202 can effectively buffer the over-etching generated during the etching of the gap fill layer 201, and when the thickness is too small, it cannot play a sufficient buffering role, and when the thickness is too large, it will increase the difficulty of subsequent etching.
[0044] In some embodiments, the material of the dielectric layer 101 can include silicon oxide, silicon nitride, high-k material, or a combination thereof. The high-k material can have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) can have a dielectric constant of about 3.9, and the dielectric layer 101 can include a high-k material having a dielectric constant of about 4 or more. The high-k material can have a dielectric constant of about 20 or more. The high-k material can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In some embodiments, the dielectric layer 101 can be formed of a composite layer including two or more layers of the above high-k materials. In some preferred embodiments, the material of the dielectric layer 101 can be silicon dioxide.
[0045] In some embodiments, the material of the word line conductive layer 102 can include a semiconductor material. The word line conductive layer 102 can include titanium nitride, tungsten, single crystal silicon, polysilicon, or a combination thereof. The word line conductive layer 102 can include an N-type work function material or a P-type work function material. The N-type work function material can have a low work function of about 4.5 eV or less, while the P-type work function material can have a high work function of about 4.5 eV or more. In some preferred embodiments, the material of the word line conductive layer 102 can be polysilicon.
[0046] In some embodiments, the gap filling layer 201 serves as an insulating layer to isolate different memory cells from each other. Therefore, the material of the gap filling layer 201 can include an insulating material, typically an oxide with a high dielectric constant, and can include a silicide, specifically at least one of silicon oxide, silicon nitride, silicon carbide, silicon carbon nitride, silicon carbon oxide, silicon oxynitride, silicon oxycarbonitride, etc. The gap filling layer 201 can be a single layer or a composite layer including one or more than two layers of high dielectric constant materials.
[0047] In some embodiments, the material of the etching stop layer 202 is different from that of the gap filling layer 201 in etching resistance to provide selectivity with respect to the gap filling layer 201 and to achieve the purpose of stopping etching. The material can include a metal oxide or nitride, specifically one or a combination of silicon nitride, tungsten oxide, hafnium oxide, tantalum oxide, zirconium oxide, aluminum oxide, nickel oxide, titanium oxide, etc. In some embodiments, the etching stop layer 202 can be a single layer or a composite layer, and the materials of the layers can be the same or different.
[0048] Figure 3B The initial stage of etching is shown, in which an etching process with a high selectivity ratio with respect to the gap filling layer 201 is selected to remove only the gap filling layer 201 while stopping at the etching stop layer 202 and forming a first recess 401. The etching method can typically be a dry etching method commonly used by those skilled in the art, and since this method has a high selectivity ratio and high anisotropy, the desired first recess 401 can be formed by controlling the etching conditions. However, part of the etching stop layer 202 is removed in the initial stage of etching. In some embodiments, after the initial stage of etching, the thickness t of the etching stop layer 202 is about 20-120 nm. N about 20-120 nm.
[0049] Then, as shown in FIG. 4B, the etching stop layer 202 is removed by etching, and a second recess 402 is formed in the gap filling layer 201. The etching method can be a wet etching method commonly used by those skilled in the art. The etching stop layer 202 is removed by wet etching, and the second recess 402 is formed in the gap filling layer 201. The second recess 402 can be formed by controlling the etching conditions. Figure 3CAs shown, etching continues on the etch stop layer 202 located below the first groove 401, forming a second groove 402 with a lateral recess 402a. The etching method typically chosen is wet etching or vapor etching, a type of "isotropic etching" technique. This technique has high selectivity and isotropy for the etch stop layer 202, meaning it removes the etch stop layer 202 without directional selectivity, allowing for lateral penetration and etching of the etch stop layer 202. Furthermore, the etching process can be controlled by adjusting etching conditions and etching time, ensuring complete etching of the etch stop layer 202 along the stacking direction. In some embodiments, the thickness (t) of the remaining etch stop layer 202 after the initial etching stage is... N When the wavelength is 20–120 nm, the depth (W) of the lateral recess 402a after wet etching or vapor etching is inward relative to the sidewall of the first groove 401. n The etching solution can be 30–200 nm. In some embodiments, the etching solution can be, for example, a hot phosphoric acid solution with a concentration of 85%, and the etching time can be, for example, 10 min.
[0050] After wet etching or vapor etching, a backing layer is needed to fill the space created by the etching process to maintain sufficient electrical isolation between the subsequently formed metal contacts and adjacent word lines. For example... Figure 3D As shown, a liner layer 501 of a certain thickness is formed by deposition onto the inner wall of the second groove 402, which structurally has a third groove 403. The width of the formed third groove 403 is smaller than that of the first groove 401. The deposition method can be atomic layer deposition or chemical vapor deposition. Compared to other methods, the above methods are more likely to obtain a liner layer 501 material with relatively uniform quality, and the film thickness can be controlled by the deposition conditions and deposition time. A liner layer 501 of uniform thickness is formed on the surface of the target dielectric layer 101. The thickness of the liner layer 501 on the surface of the target dielectric layer 101 is h. n Given that the depth of the transverse concave portion 402a is W n In order to completely fill the concave portion of the transverse recess 402a, therefore h n ≥W n And h n ≥1 / 2H n This ensures that both the lateral and longitudinal spaces of the transverse recess 402a are filled. By controlling the deposition conditions, the thickness h of the surface pad layer 501 of different target dielectric layers 101 is varied. n They are identical. This ensures that subsequent etching processes are carried out in essentially the same environment, solving the problem of inconsistent aspect ratios in subsequent etching processes. It also allows for better control of etching synchronization performance, resulting in a more stable memory structure.
[0051] In some embodiments, the material of the liner layer 501 can be a semiconductor commonly used dielectric material, such as silicon oxide, silicon nitride, aluminum oxide, metal oxide, metal oxynitride, metal silicate, high-k material, or a combination thereof.
[0052] In some embodiments, the material of the liner layer 501 can be the same as or different from the material of the target dielectric layer 101. However, both are dielectric materials or insulating materials. The difficulty of subsequent etching process can be reduced, the etching efficiency can be improved, and the etching stability can be improved.
[0053] After the liner layer 501 is formed, the bottom of the liner layer 501 and the dielectric layer 101 deposited along the stacking direction of the staircase structure 100 are etched to form a contact hole 404, so that the word line conductive layer 102 is exposed, as shown in Figure 3E The etching method is selected from the etching methods commonly used by those skilled in the art, for example, a dry etching process with high selectivity can be used. In some embodiments, a dry etching process in a fluorocarbon environment can be selected, which has good selectivity with respect to the liner layer 501, the dielectric layer 101, and the word line conductive layer 102. And since the liner layer 501 and the dielectric layer 101 both use materials with similar structures, there is no need to change the etching conditions in the middle, forming a uniform etching.
[0054] Finally, metal is deposited into the contact hole 404 to form a contact electrode 601 coupled with the word line conductive layer 102, forming a structure as shown in Figure 3F In some embodiments, the material of the contact electrode 601 can be a conductive material, which can include copper material, tungsten material, aluminum material, tungsten nitride, tantalum nitride, titanium nitride, and a combination thereof. Copper material has the advantages of high conductivity, high reliability, low resistance, etc. The introduction of copper material can improve the speed and power of the semiconductor device, while also helping to reduce the size of the chip and power consumption. Aluminum material has poor conductivity, but has good corrosion resistance and stability, and the melting point of the material is low, easy to process and weld. Tungsten material has good high-temperature resistance, corrosion resistance and stability, and can withstand high-power and high-frequency current and electromagnetic wave radiation. Each contact electrode in the contact structure can have a cylindrical shape. In some embodiments, each contact electrode 601 can have an inclined side surface that becomes narrower as the contact structure approaches the support substrate 301, as shown in Figure 4 The contact electrode 601 can provide electrical contact for the corresponding word line conductive layer 102 and the connection layer 302, and route wiring in subsequent levels of the die, and then to the word line driver and other circuits in the support substrate 301 below or around the word line staircase structure 100. The TEM image of the physical structure of the semiconductor device obtained by the method according to the present application is shown in Figure 6As is well known to those skilled in the art, metal deposition is carried out inside the contact hole 404, and metal deposition also occurs on the upper surface of the gap filling layer 201 on the stepped structure 100, so the method also includes removing the deposited metal layer on the upper surface of the gap filling layer 201, which can be achieved by conventional methods such as CMP.
[0055] Compared with the commonly used process method for forming a memory cell (such as Figures 2A-2D As shown in the figure, according to the provided implementation method of the application, a step of wet etching or vapor etching is added in the dry etching process, the etching stop layer is processed, so that the etching stop layer on the surface of the target dielectric layer is removed, and the target dielectric layer is exposed. Then, the deposition conditions are controlled to control the formation of the liner layer, so that the total thickness of the liner layer and the target dielectric layer on the surface of the target word line conductive layer at different depths is relatively uniform, and the synchronization of the subsequent etching process can be well controlled; the material of the liner layer is similar to that of the target dielectric layer, which significantly reduces the difficulty of the subsequent etching process, and still ensures that the contact electrode and the word line conductor maintain effective isolation, thereby improving the stability and reliability of the 3D NAND memory product.
[0056] Meanwhile, the method for forming a memory cell of a 3D NAND memory according to the application has little change to the whole process flow, so it is easy to implement, and the cost increase is very small.
[0057] In addition, it should be understood that although the above embodiments are described in the context of a 3D NAND memory, they can also be used in the manufacturing process of other 3D memories if appropriate.
[0058] In addition, ordinal adjectives such as "first", "second", "third", etc. may be used in this text to refer to elements whose order is not necessarily implied unless explicitly stated otherwise. This is merely to distinguish different elements, and does not imply that the elements referred to must be given in the order mentioned in time, space, or other aspects.
[0059] In addition, it should be understood that although the application is described with respect to specific embodiments, those skilled in the art can modify one or more features thereof without departing from the spirit and scope of the application after reading the specification. Therefore, the present specification is not intended to limit the application. On the contrary, the scope of the application is defined only by the appended claims and their equivalents.
Claims
1. A method of fabricating a semiconductor device, the method comprising: providing a stack, wherein the stack comprises a plurality of pairs of dielectric and conductive layers stacked on each other, a dielectric layer in each pair of dielectric and conductive layers disposed above a conductive layer in the pair, one end of each pair of dielectric and conductive layers in a first direction extending beyond a corresponding end of an immediately upper pair of dielectric and conductive layers in the first direction, thereby forming a plurality of steps, and wherein the stack further comprises a termination layer disposed on the plurality of pairs of dielectric and conductive layers and a step gap fill layer disposed on the termination layer; etching the step gap fill layer to expose the termination layer, thereby forming a first recess corresponding to the plurality of steps; etching the first recess to expose a lower dielectric layer adjacent to the termination layer, thereby forming a second recess having a lateral recess portion; depositing a liner layer such that the liner layer forms an entire surface of the second recess, thereby forming a third recess having a width in the first direction narrower than the first recess; etching the third recess to expose a conductive layer corresponding to the lower dielectric layer, thereby forming a contact hole.
2. The method of claim 1, further comprising: depositing a conductive material into the contact hole, thereby forming a contact electrode.
3. The method of claim 2, wherein, The conductive material comprises copper, tungsten, aluminum, tungsten nitride, tantalum nitride, titanium nitride, and combinations thereof.
4. The method of claim 1, wherein, Etching the step gap fill layer comprises: etching the step gap fill layer using dry etching.
5. The method of claim 1, wherein, Etching the first recess comprises: etching the first recess using wet etching or vapor etching.
6. The method of claim 1, wherein, Depositing the liner layer comprises: depositing the liner layer using atomic layer deposition or chemical vapor deposition.
7. The method of claim 1, wherein, The liner layer is a dielectric or electrically insulating material comprising silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, metal oxide, metal oxynitride, metal silicate, high-k material, or combinations thereof.
8. The method of claim 1, wherein, Etching the third recess comprises: etching the third recess using dry etching.
9. The method of claim 1, wherein, The semiconductor device is a 3D NAND memory or a 3D DRAM memory.
10. The method of claim 1, wherein, The conductive layer is a word line conductive layer.
11. The method of claim 10, wherein, The word line conductive layer is polysilicon or nitride.
12. The method of claim 1, wherein, The termination layer is a nitride or a metal oxide.
13. The method of claim 1, wherein, The lateral recess portion has a depth of 30-200 nm.