Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, and the semiconductor device comprises a semiconductor body provided with a first surface and a second surface, an isolation layer, a gate insulation layer, a gate structure, a source electrode and a drain electrode. The semiconductor body further includes a JFET region and a first region, and a well region. And an isolation layer extending from the first surface into the semiconductor body. On the first surface, the isolation layer is arranged between the first region and the well region. And the gate insulating layer is arranged on the first surface, and the gate insulating layer at least covers the JFET region and the well region. And the gate structure is arranged on one side, far away from the semiconductor body, of the gate insulating layer. The source electrode is arranged on the first surface. The drain electrode is arranged on the second surface. The isolation layer is arranged between the first region and the well region, so that the uniformity of the thickness of the gate insulation layer covering the transition region of the first region and the well region is improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. BACKGROUND

[0002] As one of the key structures in a metal-oxide-semiconductor field-effect transistor (MOSFET), the quality of a gate insulating layer directly affects the performance of the device. The uniformity of the thickness of the gate insulating layer is crucial for ensuring the consistency of the threshold voltage of the transistor, reducing the variation caused by random doping, and improving the reliability of the circuit.

[0003] However, in the planar structure of the SIC MOSFET, there is a difference in doping concentration and doping type between the transition region between the NN region and the well region, resulting in inconsistent thickness of the covered gate insulating layer. SUMMARY

[0004] The present application provides a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, aiming to improve the thickness uniformity of the gate insulating layer.

[0005] To achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions:

[0006] In one aspect, a semiconductor device, which can be a SiC MOSFET, is provided. The semiconductor device includes a semiconductor body, an isolation layer, a gate insulating layer, a gate structure, a source and a drain. The semiconductor body is configured as a first conductivity type, and includes a first surface and a second surface arranged oppositely. The semiconductor body further includes a JFET region configured as the first conductivity type, a first region configured as the first conductivity type, and a well region configured as a second conductivity type. The JFET region, the first region and the well region are arranged on the first surface in a first direction parallel to the first surface.

[0007] The isolation layer extends from the first surface into the semiconductor body. On the first surface, the isolation layer is arranged between the first region and the well region. The gate insulating layer is arranged on the first surface and covers at least the JFET region and the well region. The gate structure is arranged on a side of the gate insulating layer away from the semiconductor body. The source is arranged on the first surface. The drain is arranged on the second surface.

[0008] In the embodiments of the present application, since the first region is a heavily doped N-type semiconductor, on the one hand, the doping atoms of the N-type semiconductor are usually donor impurities, which can increase the number of free electrons, so that a stronger electric field is formed near the first surface, which can accelerate the decomposition of oxygen molecules and promote the oxidation process of the semiconductor bulk material. On the other hand, due to the high carrier concentration, the electric field strength is also enhanced, which helps to improve the mobility of oxygen atoms, and the doping concentration also affects the interface state density and fixed charge amount, thereby accelerating the oxidation rate of the semiconductor bulk material.

[0009] Based on this, the isolation layer is arranged in the transition region between the first region and the well region, which is equivalent to replacing the heavily doped N-type semiconductor material in the transition region with the isolation layer. Therefore, the transition region does not have a heavily doped N-type semiconductor material, and thus the transition region will not be oxidized to form an insulating layer. This can avoid the situation that the thickness of the insulating layer in the transition region is relatively large after the gate insulating layer is formed, which is beneficial to improving the thickness uniformity of the gate insulating layer.

[0010] In some embodiments, part of the first region is arranged on the side of the isolation layer away from the first surface.

[0011] In the first direction, the first region includes a first boundary near the side of the JFET region, and the isolation layer includes a second boundary near the side of the JFET region, and the first boundary is flush with the second boundary.

[0012] In some embodiments, part of the first region is arranged on the side of the isolation layer away from the first surface.

[0013] In the first direction, the first region includes a first boundary near the side of the JFET region, and the isolation layer includes a second boundary near the side of the JFET region, and the second boundary exceeds the first boundary.

[0014] In some embodiments, the material of the isolation layer includes at least one of tungsten, aluminum, titanium, or nickel.

[0015] On the other hand, the embodiments of the present application also provide a preparation method of a semiconductor device, which includes: forming a semiconductor bulk, which is arranged to be of a first conductivity type and includes oppositely arranged first and second surfaces. The semiconductor bulk further includes a first region arranged to be of the first conductivity type and a well region arranged to be of a second conductivity type, and the first region and the well region are arranged on the first surface and arranged along a first direction parallel to the first surface. An isolation layer is formed, which extends from the first surface into the semiconductor bulk. On the first surface, the isolation layer is located between the first region and the well region. A gate insulating layer is formed on the first surface, which covers at least the well region. A gate structure is formed on the side of the gate insulating layer away from the semiconductor bulk. A source electrode is formed on the second surface. A drain electrode is formed on the second surface.

[0016] In the embodiments of the present application, the isolation layer is formed between the first region and the well region, so that the transition region between the first region and the well region does not have heavily doped N-type semiconductor material, and thus the transition region cannot be oxidized to form an insulating layer. Therefore, after the gate insulating layer is formed, the insulating layer in the transition region has a small thickness, which is beneficial to improve the thickness uniformity of the gate insulating layer.

[0017] In some embodiments, the isolation layer is formed by:

[0018] The recess is formed on the first surface, and part of the first region is located at the bottom of the recess. In the first direction, the first region includes a first boundary close to the side of the well region, and the recess includes a rim close to the side of the well region. The first boundary is flush with the rim of the recess, or the rim of the recess exceeds the first boundary.

[0019] The isolation layer is formed by filling the isolation material in the recess.

[0020] In some embodiments, the gate insulating layer is formed by a thermal oxidation process.

[0021] The orthogonal projection of the gate insulating layer on the first surface does not overlap with the region where the isolation layer is located.

[0022] In another aspect, the embodiments of the present application also provide a power module, which includes a substrate and the semiconductor device according to any one of the above embodiments. The substrate is used to carry the semiconductor device.

[0023] In another aspect, the embodiments of the present application also provide a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the semiconductor device according to any one of the above embodiments. The semiconductor device is electrically connected to the circuit board.

[0024] In another aspect, the embodiments of the present application also provide a vehicle, which includes a load and the power conversion circuit according to the above embodiments. The power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and then input to the load.

[0025] The power module, the power conversion circuit, and the vehicle have the same structure and beneficial technical effects as the semiconductor device provided in some of the above embodiments, and thus will not be described here. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and / or additional aspects and advantages of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 FIG. 1 is a structural schematic diagram of a semiconductor device provided in the embodiments of the present application.

[0028] Figure 2 Another semiconductor device structure schematic diagram provided for an embodiment of the present application;

[0029] Figure 3 A method flowchart for manufacturing a semiconductor device provided for an embodiment of the present application;

[0030] Figures 4 to 14 A diagram of each step for manufacturing a semiconductor device provided for an embodiment of the present application;

[0031] Figure 15 A structure schematic diagram of a power module provided for an embodiment of the present application;

[0032] Figure 16 A structure schematic diagram of a power conversion circuit provided for an embodiment of the present application;

[0033] Figure 17 A structure schematic diagram of a vehicle provided for an embodiment of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in some embodiments of the present application will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0035] Unless otherwise required by context, the term “comprises” in the specification and claims is to be construed as an open, inclusive meaning, i.e. “comprises, but is not limited to”.

[0036] Hereinafter, the terms “first” and “second” are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of “a plurality of” is two or more.

[0037] In describing some embodiments, the term “connected” and its conjugations can be used. The term “connected” should be interpreted broadly, for example, “connected” can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. For example, in describing some embodiments, the term “connected” can be used to indicate that two or more components have direct physical or electrical contact with each other.

[0038] In addition, the use of "based on" means open and inclusive, as a process, step, calculation, or other action "based on" one or more recited conditions or values can in practice be based on additional conditions or values beyond those recited.

[0039] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0040] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are idealized examples. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0041] Gate insulating layer as one of the key structures in metal oxide semiconductor field effect transistor (MOSFET), its quality directly affects the performance of the device. The uniformity of the gate insulating layer thickness is essential to ensure the consistency of the threshold voltage of the transistor, reduce the variation caused by random doping and improve the reliability of the circuit. However, in the SIC MOSFET planar structure, the transition region between the first region and the well region, due to the difference of the doping concentration and the doping type, leads to the inconsistent thickness of the covered gate insulating layer.

[0042] To solve the above problems, the embodiment of the present application provides a semiconductor device, such as Figure 1 as shown in the figure, Figure 1 A semiconductor device 10 structure schematic diagram is provided for the embodiment of the present application.

[0043] As shown in the figure, Figure 1As shown, the semiconductor device 10 includes a semiconductor body 101, an isolation layer 105, a gate insulating layer 106, and a gate structure 107, a source 108, and a drain 109. The semiconductor body 101 includes a silicon carbide substrate 1012 and an epitaxial layer 1011. The semiconductor body 101 is of a first conductivity type, and includes a first surface P1 and a second surface P2 oppositely arranged. The semiconductor body 101 further includes a JFET region 104 of the first conductivity type, a first region 102 of the first conductivity type, and a well region 103 of a second conductivity type. The JFET region 104, the first region 102, and the well region 103 are arranged on the first surface P1, and are arranged in a first direction X parallel to the first surface P1, in sequence. In an embodiment, the semiconductor body 101 and the first region 102 are of the first conductivity type, and the well region 103 is of the second conductivity type. For example, the first conductivity type is N-type, and the second conductivity type is P-type. Thus, the first region 102, the well region 103, and the semiconductor body 101 form an NPN junction.

[0044] The isolation layer 105 extends from the first surface P1 into the semiconductor body 101. On the first surface P1, the isolation layer 105 is arranged between the first region 102 and the well region 103. The material of the isolation layer 105 cannot be thermally oxidized to form silicon oxide. The gate insulating layer 106 is arranged on the first surface P1, and covers at least the JFET region 104 and the well region 103. The gate structure 107 is arranged on a side of the gate insulating layer 106 away from the semiconductor body 101. The source 108 is arranged on the first surface P1. The drain 109 is arranged on the second surface P2. The gate structure 107, the source 108, and the drain 109 form three electrodes of the semiconductor device 10.

[0045] The semiconductor body 101 further includes a second region 110 of the second conductivity type.

[0046] When the semiconductor device 10 is forwardly turned on, and the working current is small, the working current flows from the source 108 to the drain 109 through the first region 102, the well region 103, the JFET region 104, the epitaxial layer 1011, and the silicon carbide substrate 1012, by transmitting an opening voltage to the gate structure 107.

[0047] Since the P-type ion concentration of the second region 110 is higher than that of the well region 103, the second region 110 forms more PN junctions with the epitaxial layer 1011. When the working current is large, the working current flows from the source 108 to the drain 109 through the second region 110, the epitaxial layer 1011, and the silicon carbide substrate 1012, so as to avoid the large working current flowing through the well region 103, thereby protecting the channel in the well region 103.

[0048] In the embodiments of the present application, since the first region 102 is a heavily doped N-type semiconductor, on the one hand, the doping atoms of the N-type semiconductor are usually donor impurities, which increase the number of free electrons, so that a stronger electric field is formed near the first surface P1, which can accelerate the decomposition of oxygen molecules and promote the oxidation process of the semiconductor bulk material. On the other hand, due to the high carrier concentration, the electric field strength is also enhanced, which helps to improve the mobility of oxygen atoms, and the doping concentration also affects the interface state density and fixed charge amount, accelerating the oxidation rate of the semiconductor bulk material.

[0049] Therefore, the isolation layer 105 is arranged in the transition region between the first region 102 and the well region 103, that is, the heavily doped N-type semiconductor material in the transition region is replaced by the isolation layer 105. Therefore, the transition region does not exist heavily doped N-type semiconductor material, so the transition region will not be oxidized to form an insulating layer, which can avoid the thickness of the insulating layer in the transition region being larger after the gate insulating layer 106 is formed, and is beneficial to improve the thickness uniformity of the gate insulating layer 106.

[0050] In some embodiments, as shown in Figure 1 In the first direction X, the first region 102 includes a first boundary D1 near the side of the JFET region 104, and the isolation layer 105 includes a second boundary D2 near the side of the JFET region 104, and the first boundary D1 is flush with the second boundary D2.

[0051] It can be understood that, in the first direction X, the well region 103 between the first region 102 and the JFET region 104 serves as a channel layer.

[0052] In the above embodiments of the present application, the isolation layer 105 is located between the first region 102 and the well region 103, and part of the first region 102 is also located below the isolation layer 105, the first boundary D1 of the first region 102 is flush with the second boundary D2 of the isolation layer 105, and it can be seen that the entire isolation layer 105 is embedded in the first region 102, that is, the isolation layer 105 only replaces the heavily doped N-type semiconductor material in the first region 102. The isolation layer 105 does not replace the material of the well region 103, that is, the isolation layer 105 does not replace the material of the channel layer, so as to avoid the influence of the arrangement of the isolation layer 105 on the conductivity of the channel layer.

[0053] In some embodiments, as shown in Figure 2As shown, part of the first region 102 is disposed on the side of the isolation layer 105 away from the first surface P1. In the first direction X, the first region 102 includes a first boundary D1 on the side close to the JFET region 104, and the isolation layer 105 includes a second boundary D2 on the side close to the JFET region 104, the second boundary D2 being beyond the first boundary D1.

[0054] It can be understood that the first region 102 includes heavily doped N-type ions, which not only promotes the oxidation of the surface of the first region 102, but also easily promotes the oxidation of the surface of the well region 103 adjacent to the first region 102.

[0055] In the above embodiments of the present application, the isolation layer 105 is located between the first region 102 and the well region 103, and part of the first region 102 is also located below the isolation layer 105, and the second boundary D2 of the isolation layer 105 is beyond the first boundary D1 of the first region 102. It can be seen that part of the isolation layer 105 is embedded in the first region 102, and another part is embedded in the well region 103. That is, the isolation layer 105 not only replaces the surface of the first region 102 in the transition region, but also replaces the surface of the well region 103 in the transition region. This can avoid the formation of an insulating layer on the surface of the well region 103 close to the first region 102, and further improve the thickness uniformity of the gate insulating layer 106.

[0056] In some embodiments, the material of the isolation layer 105 includes a metal material, which is not easy to be oxidized to form an insulating layer. For example, the material of the isolation layer 105 includes tungsten, aluminum, titanium or nickel, which is not easy to be oxidized to form an oxide layer.

[0057] On the other hand, the embodiments of the present application also provide a preparation method of a semiconductor device, as shown in Figure 3 Figure 3 A flow chart of a preparation method of a semiconductor device provided by the embodiments of the present application is shown in Figures 4 to 14 A diagram of each step of a preparation method of a semiconductor device provided by the embodiments of the present application is shown in

[0058] As shown in Figure 3 The preparation method includes the following steps S10-S60:

[0059] Step S10: as shown in Figures 4 to 6 The semiconductor body 101 is formed, and the semiconductor body 101 is set to the first conductive type and includes oppositely arranged first and second surfaces P1 and P2. The semiconductor body 101 further includes a first region 102 set to the first conductive type and a well region 103 set to the second conductive type, and the first region 102 and the well region 103 are both disposed on the first surface P1 and arranged along a first direction X parallel to the first surface P1. ​

[0060] For example, such as Figures 4 to 6 As shown, a silicon carbide substrate 1012 is provided, and a silicon carbide epitaxial layer 1011 is epitaxially grown on the silicon carbide substrate 1012. The silicon carbide substrate 1012 and the silicon carbide epitaxial layer 1011 constitute a semiconductor body 101. The conductivity type of the semiconductor body 101 is N-type. On the first surface P1 of the semiconductor body 101, a mask is formed, an ion implantation region is defined, and P-type ion implantation is performed using a photolithography process. + Ion implantation forms the first region 102.

[0061] like Figure 5 As shown, after removing the mask, a new mask is formed using photolithography, the ion implantation region is defined, and N2O is performed. + Ion implantation was performed to form well region 103.

[0062] In some embodiments, such as Figure 4 As shown, the semiconductor body 101 also includes a second region 110 configured with a second conductivity type, the second region 110 being disposed on the first surface P1. P-type ions are implanted into the second region 110, and the second region 110 may also be referred to as "P..." + Contact area". Step S20: Form an isolation layer 105, which extends from the first surface P1 into the semiconductor body 101; on the first surface P1, the isolation layer 105 is located between the first region 102 and the well region 103.

[0063] The above-mentioned step S20 includes the following steps S201 to S202.

[0064] Specifically, step S201: as follows Figure 7 As shown, a groove T1 is formed on the first surface P1 by etching, and a portion of the first region 102 is located at the bottom of the groove T1. In the first direction X, the first region 102 includes a first boundary D1 near the well region 103, and the groove T1 includes an edge D3 near the well region 103. The first boundary D1 is flush with the edge D3 of the groove T1, or as shown... Figure 8 As shown, the edge D3 of the groove T1 extends beyond the first boundary D1.

[0065] Step S202: As Figure 9 As shown, the groove T1 is filled with insulating material to form an insulating layer 105.

[0066] For example, such as Figure 9 As shown, the groove T1 can be filled with an isolation material by a deposition process, such as chemical vapor deposition, physical vapor deposition or electroplating. The material of the isolation layer 105 cannot be thermally oxidized to form silicon oxide. The material of the isolation layer 105 can be tungsten, aluminum, titanium or nickel.

[0067] For example, such asFigure 10 As shown, after forming the isolation layer 105 and before forming the gate insulating layer 106, the fabrication process further includes the following step S21:

[0068] Step S21: As Figure 10 As shown, on the first surface P1 of the semiconductor body 101, a mask is formed by photolithography, an ion implantation region is defined, and N2O is performed. + Ion implantation was performed to form JFET region 104.

[0069] Step S30: As Figure 11 As shown, a gate insulating layer 106 is formed on the first surface P1, and the gate insulating layer 106 at least covers the well region 103.

[0070] For example, such as Figure 11 As shown, a gate insulating layer 106 is formed using a thermal oxidation process. The orthogonal projection of the gate insulating layer 106 onto the first surface P1 does not overlap with the region containing the isolation layer 105. During the thermal oxidation process, silicon atoms on the silicon carbide surface combine with oxygen atoms to form a dense silicon oxide layer on the first surface P1. This oxide layer has good insulation properties and interface quality. In this process, the isolation layer 105 cannot be oxidized, so the oxide layer only covers the well region 103 and the second region 110. The oxide layer covering the second region 110 is then etched to form the gate insulating layer 106. The formation of a precisely aligned gate insulating layer 106 through etching and self-alignment techniques improves the reliability of the semiconductor device 10.

[0071] For example, such as Figure 12 As shown, chemical vapor deposition (CVD) can also be used to form an insulating layer. In this case, the insulating layer covers the first surface P1 of the semiconductor body 101, and then the gate insulating layer 106 is formed by etching. The gate insulating layer 106 can cover the well region 103 and part of the isolation layer 105.

[0072] Step S40: As Figure 11 As shown, a gate structure 107 is formed, which is located on the side of the gate insulating layer 106 away from the semiconductor body 101.

[0073] For example, such as Figure 11 As shown, a conductive material is deposited on the side of the gate insulating layer 106 away from the semiconductor body 101. Then, the conductive material is processed into the desired gate shape by photolithography and etching processes to form the gate structure 107.

[0074] Step S50: As Figure 13 As shown, a source electrode 108 is formed on the first surface P1.

[0075] For example, such as Figure 13As shown, a conductive material layer is formed on the first surface P1 by sputtering, evaporation, or other methods, and then patterned to form the source electrode 108. The source electrode 108 material can be aluminum, copper, or tungsten. At the same time, a gate metal layer 111 can be formed on the side of the gate structure 107 away from the semiconductor body 101.

[0076] Step S60: As Figure 14 As shown, a drain electrode 109 is formed on the second surface P2.

[0077] For example, such as Figure 14 As shown, a layer of conductive material is formed on the second surface P2 by sputtering, evaporation and other methods to form a drain electrode 109. The material of the drain electrode 109 can be aluminum, copper or tungsten.

[0078] In this embodiment, an isolation layer 105 is formed between the first region 102 and the well region 103, so that there is no heavily doped N-type semiconductor material in the transition region between the first region 102 and the well region 103. Therefore, the transition region will not be oxidized to form an insulating layer, which can avoid the large thickness of the insulating layer in the transition region after the gate insulating layer 106 is formed, which is beneficial to improving the thickness uniformity of the gate insulating layer 106.

[0079] On the other hand, embodiments of this application also provide a power module. Figure 15 This is a schematic diagram of the power module provided in an embodiment of this application.

[0080] like Figure 15 As shown, the power module 200 includes a substrate 201 and a semiconductor device 10 in any of the above embodiments, with the substrate 201 used to support the semiconductor device 10.

[0081] For example, power module 200 can be used as one of a power amplifier, power converter, power controller, power management module, or power regulator. A power amplifier amplifies the power of an electrical signal. A power converter converts electrical energy from one form to another; for example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is a device for controlling the flow of power. A power management module manages the power supply, ensuring that power is stably and efficiently distributed to different parts of the electronic device. A power regulator adjusts the power output to meet the needs of a specific application.

[0082] On the other hand, embodiments of this application also provide a power conversion circuit. Figure 16 This is a schematic diagram of the power conversion circuit provided in an embodiment of this application.

[0083] like Figure 16As shown, the power conversion circuit 300 includes a circuit board 301 and the semiconductor device 10 in any of the above embodiments, and the semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0084] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used for converting alternating current into direct current, the AC / AC converter is used for converting alternating current into alternating current, the DC / DC converter is used for converting direct current into direct current, the DC / AC inverter is used for converting direct current into alternating current, and the power factor correction circuit is used for improving the power factor of the power supply and reducing the harmonic pollution of the power grid.

[0085] In another aspect, the embodiments of the present application also provide a vehicle, Figure 17 A structural schematic diagram of the vehicle provided by the embodiments of the present application is shown.

[0086] As shown in the figure, Figure 17 The vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiments, and the power conversion circuit 300 is used for converting alternating current into direct current, converting alternating current into alternating current, converting direct current into direct current or converting direct current into alternating current, and then inputting to the load 401, so as to supply power to the load 401.

[0087] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other; the semiconductor body also includes a JFET region configured with the first conductivity type, a first region configured with the first conductivity type, and a well region configured with the second conductivity type, wherein the JFET region, the first region, and the well region are all disposed on the first surface and arranged sequentially along a first direction parallel to the first surface; An isolation layer extends from the first surface into the semiconductor body; on the first surface, the isolation layer is disposed between the first region and the well region; A gate insulating layer is disposed on the first surface, the gate insulating layer at least covering the JFET region and the well region; A gate structure is disposed on the side of the gate insulating layer away from the semiconductor body; The source electrode is disposed on the first surface; The drain electrode is disposed on the second surface.

2. The semiconductor device according to claim 1, characterized in that, A portion of the first region is located on the side of the isolation layer away from the first surface; In the first direction, the first region includes a first boundary near the side of the JFET region, and the isolation layer includes a second boundary near the side of the JFET region, with the first boundary and the second boundary being flush.

3. The semiconductor device according to claim 1, characterized in that, A portion of the first region is located on the side of the isolation layer away from the first surface; In the first direction, the first region includes a first boundary near the side of the JFET region, and the isolation layer includes a second boundary near the side of the JFET region, the second boundary extending beyond the first boundary.

4. The semiconductor device according to claim 1, characterized in that, The material of the insulating layer includes at least one of tungsten, aluminum, titanium, or nickel.

5. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body is formed, the semiconductor body being configured with a first conductivity type, including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a first region configured with the first conductivity type and a well region configured with a second conductivity type, the first region and the well region being disposed on the first surface, and the first region and the well region being arranged along a first direction parallel to the first surface; An isolation layer is formed, the isolation layer extending from the first surface into the semiconductor body; on the first surface, the isolation layer is located between the first region and the well region; A gate insulating layer is formed on the first surface, the gate insulating layer at least covering the well region; A gate structure is formed, wherein the gate structure is located on the side of the gate insulating layer away from the semiconductor body; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

6. The preparation method according to claim 5, characterized in that, Forming the isolation layer includes: A groove is formed on the first surface, a portion of the first region is located at the bottom of the groove; in the first direction, the first region includes a first boundary near the side of the well region, and the groove includes an edge near the side of the well region; the first boundary is flush with the edge of the groove, or the edge of the groove extends beyond the first boundary; The groove is filled with insulating material to form the insulating layer.

7. The preparation method according to claim 5, characterized in that, The gate insulating layer is formed using a thermal oxidation process; The orthographic projection of the gate insulating layer onto the first surface does not overlap with the region where the isolation layer is located.

8. A power module, characterized in that, include: At least one semiconductor device as described in any one of claims 1 to 4; A substrate for supporting the semiconductor device.

9. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that, include: The load and the power conversion circuit as described in claim 9, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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