Gate injection type ferroelectric field effect transistor

Abstract

The invention provides a gate injection type ferroelectric field effect transistor and a preparation method thereof, and belongs to the technical field of micro-nano electronics. The ferroelectric field effect transistor structurally comprises a semiconductor substrate, a highly-doped source region, a highly-doped drain region, a metal gate electrode and a gate stack, the structure of the gate stack sequentially comprises a channel insulating layer, a ferroelectric layer, a charge trapping layer and a gate insulating layer from bottom to top, the charge trapping layer comprises three layers of materials, and the structure of the charge trapping layer sequentially comprises a layer of charge trapping material, a layer of barrier layer insertion layer and a layer of charge trapping material from bottom to top; the metal gate electrode is located on the gate stack, and the highly-doped source region and the highly-doped drain region are located on the two sides of a channel region below the gate stack respectively. By introducing the charge trapping layer and inserting the barrier layer in the charge trapping layer, the storage characteristic of the device is improved, the preparation method is simple, and a material system is compatible with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process; the storage window and the retention characteristic of the gate injection type ferroelectric field effect transistor are improved, and the gate injection type ferroelectric field effect transistor has high practical value.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a novel gate-injection ferroelectric field-effect transistor and its fabrication method. Background Technology

[0002] Currently, Vertical NAND flash memory (VNAND) is the mainstream technology in the high-density storage field. This technology increases storage capacity and density by stacking storage cells vertically, while reducing the cost per bit. Since its commercialization, the number of VNAND stacking layers has increased from 24 to over 200. With the rapid development of technologies such as the Internet of Things, big data, artificial intelligence, and autonomous driving, the amount of data generated is growing exponentially, thus increasing the demand for storage density in data storage media. Samsung predicts that the number of VNAND stacking layers will increase exponentially with each technological iteration. However, limited by the high operating voltage of traditional charge-trap flash memory (CTF-VNAND), the miniaturization of its adjacent layer spacing has reached its physical limit. Simply increasing the number of stacking layers would result in excessively high VNAND stack height, introducing challenges in process integration and high manufacturing costs, hindering the realization of higher integration densities.

[0003] To address the aforementioned issues, gate-injected ferroelectric field-effect transistors (FFETs) are considered one of the most promising candidates for next-generation VNAND technology. This technology combines ferroelectric switching and gate charge trapping to achieve a larger storage window, meeting the multi-value storage requirements of VNAND technology. The ferroelectric material used is a hafnium oxide-based thin film material, offering good CMOS compatibility. The core advantage of this technology lies in leveraging the "non-linear" relationship between charge and voltage during ferroelectric switching to enhance charge injection efficiency. Therefore, it has a lower operating voltage compared to traditional CTF-VNAND, allowing for further miniaturization of interlayer spacing. This enables an increase in the number of stacked layers within the same VNAND stack height, thereby further improving integration density.

[0004] Currently, gate-injected ferroelectric field-effect transistors (FeFETs) widely employ a metal-gate insulating-ferroelectric layer-channel insulating-semiconductor (MIFIS) structure. While this significantly improves the memory window (MW) compared to using ferroelectric polarization charge alone, and the operating voltage is lower than that of traditional CTF flash memory, the aforementioned MIFIS gate stack structure has certain limitations. Firstly, electrons injected from the gate have high energy and range, resulting in lower storage efficiency at the interface between the gate metal and gate insulating layer, which weakens the MW improvement effect of the gate injection mechanism. Secondly, gate-injected FeFETs suffer from severe retention problems at high threshold states because some stored electrons are unstable and emit towards the gate and channel. How to balance improving the memory window with resolving the long-standing retention challenge has become a critical technical hurdle for gate-injected FeFETs. Summary of the Invention

[0005] The purpose of this invention is to improve the gate stack structure of traditional MIFIS by proposing a gate-injected FeFET with high storage window and high retention characteristics, and its fabrication method. By inserting a charge trapping layer between the gate insulating layer and the ferroelectric layer, an additional body trap is provided for the trapping of gate-injected electrons, thereby increasing the trapping efficiency of gate-injected electrons during programming. Furthermore, a thin barrier layer is inserted into the charge trapping layer. On the one hand, during programming, high-energy gate-injected electrons are "intercepted" by the barrier layer and remain within the charge trapping layer, thereby further improving the trapping efficiency and storage window. On the other hand, during retention, the barrier layer and the gate insulating layer, which also has a high bandgap, together form an energy potential well for electrons, which can effectively alleviate the emission effect of electrons trapped in the trap in both directions toward the gate and the channel, thereby improving the retention characteristics.

[0006] Specifically, the technical solution of the present invention is as follows:

[0007] A gate-injection ferroelectric field-effect transistor includes a semiconductor substrate, a highly doped source region, a highly doped drain region, a metal gate electrode, and a gate stack. The gate stack, from bottom to top, comprises a channel insulating layer, a ferroelectric layer, a charge trapping layer, and a gate insulating layer. The charge trapping layer comprises three layers of material, with the structure from bottom to top consisting of a charge trapping material layer, a barrier intercalation layer, and another charge trapping material layer. The metal gate electrode is located on the gate stack, and the highly doped source region and the highly doped drain region are located on either side of the channel region below the gate stack.

[0008] The thickness of the ferroelectric layer is 7–15 nm, depending on the highest ferroelectricity. The ferroelectric layer is made of hafnium oxide-based ferroelectric material, and can be doped with materials such as hafnium zirconium oxide (HZO), hafnium aluminum oxide (HAO), hafnium silicon oxide (HSO), hafnium lanthanum oxide (HLO), or undoped hafnium oxide ferroelectric material and related combined doping materials.

[0009] In the multilayer structure of the charge trapping layer, the thickness of the upper charge trapping material is 2-3 nm, and the thickness of the lower charge trapping material is 1-2 nm. The thickness of the upper charge trapping material should be greater than that of the lower charge trapping material to maximize the charge trapping efficiency. The barrier layer intercalation is grown using atomic layer deposition and has a relatively thin thickness of 0.5-1.5 nm. The charge trapping material can be selected from hafnium oxide (HfO2) or silicon nitride (SiN). x Materials such as aluminum oxide (Al2O3) and boron nitride (BN) can be used for the barrier layer. The band gap of the intercalation material of the barrier layer should be greater than the band gap of the charge trapping material.

[0010] The gate insulating layer is a single silicon oxide (SiO2) layer with a thickness of 2–4 nm; or the gate insulating layer is a silicon oxide / silicon nitride / silicon oxide (SiO2 / SiN) layer. x The structure is a three-layer structure of (SiO2), with each layer having a thickness of 1.5–2.5 nm.

[0011] In the gate-injection type ferroelectric field-effect transistor, the metal gate electrode is made of a material with a suitable coefficient of thermal expansion so as to apply stress to the ferroelectric layer during rapid thermal annealing to activate ferroelectricity. Metal gate electrode materials such as titanium nitride (TiN), tantalum nitride (TaN), and tungsten (W) can be selected.

[0012] The present invention also provides a method for fabricating the above-mentioned gate-injected ferroelectric field-effect transistor, comprising the following steps:

[0013] (1) Define the active region on the semiconductor substrate using an isolation method;

[0014] (2) Use diluted hydrofluoric acid solution to remove the native oxide layer on the active silicon surface;

[0015] (3) Growing a channel insulating layer on the substrate surface;

[0016] (4) Ferroelectric materials with hafnium oxide-based deposition on the entire substrate;

[0017] (5) In the whole sheet, a charge trapping layer is deposited first, then a barrier layer is intercalated, and finally another layer of charge trapping material is deposited.

[0018] (6) Deposit a gate insulating layer over the entire wafer;

[0019] (7) Deposit metal gate electrode material over the entire wafer;

[0020] (8) Define the gate region by photolithography, and then form the gate electrode pattern by photolithography and etching;

[0021] (9) Photolithography is performed on the doped source and drain regions, and ion implantation is performed using photoresist and metal gate electrodes as masks to form highly doped source and drain regions;

[0022] (10) Perform rapid thermal annealing on the entire sheet to activate the ferroelectricity of the ferroelectric layer and source / drain injection impurities;

[0023] (11) Finally, CMOS back-end processes are performed, including depositing interlayer dielectric, etching vias and metallization, to ultimately form the gate-injected ferroelectric field-effect transistor.

[0024] In the above preparation method, the semiconductor substrate in step (1) is selected from Si, Ge, SiGe, GaAs or other binary or ternary compound semiconductors of group II-VI, III-V and IV-IV, silicon on insulator (SOI) or germanium on insulator (GOI).

[0025] In the above preparation method, the channel insulation layer in step (3) is selected from common channel insulation layer materials such as silicon dioxide, aluminum oxide, and silicon oxynitride.

[0026] In the above preparation method, the method for growing the channel insulation layer in step (3) is selected from one of the following methods: wet chemical method, conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition, atomic layer deposition or physical vapor deposition.

[0027] In the above preparation method, the ferroelectric layer and charge trapping layer in steps (4) and (5) are prepared by atomic layer deposition.

[0028] In the above preparation method, the deposition method of the gate insulating layer in step (6) is atomic layer deposition or chemical vapor deposition.

[0029] In the above preparation method, the metal gate electrode material in step (7) is selected from TiN, W, TaN and other metals that can be annealed to apply stress to the ferroelectric layer to form ferroelectricity, and the growth method is physical vapor deposition or chemical vapor deposition.

[0030] Advantages and positive effects of the present invention:

[0031] First, the additional charge trapping layer provides a bulk trap for electrons injected into the gate during programming, increasing the electron trapping efficiency. Furthermore, the barrier layer intercalation has a large bandgap, which plays an additional "interception" role for high-energy electrons, further increasing the trapping efficiency of gate-injected electrons and thus improving the memory window.

[0032] Second, the intercalation of the barrier layer in the charge trapping layer and the gate insulating layer together form an energy potential well for storing electrons, which makes the electrons stored in the charge trapping material more stable, reduces the emission mechanism to the channel and gate, and improves the retention characteristics.

[0033] Third, the preparation method and material system of the gate stack structure proposed in this invention are compatible with the traditional NAND technology process, which can simplify the overall preparation process.

[0034] In short, the gate-injected ferroelectric field-effect transistor with this structure improves device performance and simplifies fabrication by introducing a charge-trapping layer with a barrier intercalation layer on top of the traditional MIFIS structure gate stack. Compared to existing gate-injected ferroelectric field-effect transistors, it offers a larger storage window and better characteristic retention, making it a promising candidate for advanced high-density memory applications and possessing significant practical value. Attached Figure Description

[0035] Figure 1 This is a cross-sectional schematic diagram of a gate-injected ferroelectric field-effect transistor according to an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the process steps of a gate-injection type ferroelectric field-effect transistor according to an embodiment of the present invention, wherein:

[0037] (a) is a cross-sectional view of hafnium oxide-based ferroelectric material grown on a semiconductor substrate after growing a channel insulating layer and then growing it by atomic layer deposition (ALD).

[0038] (b) is a cross-sectional view of the whole sheet after growing a charge trapping layer by ALD, based on (a);

[0039] (c) is a cross-sectional view of the metal gate electrode after the gate insulating layer is grown by ALD or chemical vapor deposition (CVD) based on (b).

[0040] (d) is a cross-sectional view of (c) after the gate region pattern is defined by photolithography and the metal gate electrode and gate stack material in the non-patterned region are removed by dry etching.

[0041] (e) is a cross-sectional view of (d) after the source and drain doped regions are defined by photolithography, ion implantation is performed, and thermal annealing is carried out to form highly doped regions.

[0042] In the picture:

[0043] 1 — Semiconductor substrate 2 — Highly doped source region

[0044] 3—Highly doped drain region; 4—Channel insulation layer

[0045] 5—Hafnium oxide-based ferroelectric materials; 6—Lower-layer charge trapping materials

[0046] 7—Barrier layer intercalation; 8—Upper layer charge trapping material

[0047] 9 — Gate insulating layer 10 — Metal gate electrode Detailed Implementation

[0048] The present invention will be further described below with reference to the accompanying drawings.

[0049] like Figure 1 As shown, the gate-injection ferroelectric field-effect transistor of this embodiment includes a semiconductor substrate 1, a highly doped source region 2, a highly doped drain region 3, a channel insulating layer 4, a hafnium oxide-based ferroelectric material 5, a lower charge trapping material 6, a barrier layer intercalation layer 7, an upper charge trapping material 8, a gate insulating layer 9, and a metal gate electrode 10. The channel insulating layer 4 is located on the semiconductor substrate 1, the hafnium oxide-based ferroelectric material 5 is located on the channel insulating layer 4, the barrier layer intercalation layer 7 is located between the lower charge trapping material 6 and the upper charge trapping material 8, the gate insulating layer 9 is located on the upper charge trapping material 8, and the metal gate electrode 10 is located on the gate insulating layer 9.

[0050] The specific implementation steps for fabricating the gate-injection type ferroelectric field-effect transistor of the present invention are as follows: Figure 2 As shown:

[0051] (1) Active region isolation is performed on a bulk silicon wafer substrate 1 with a crystal orientation of (100) using shallow trench isolation technology; the substrate is cleaned, and the native oxide layer on the surface of the active region silicon is removed using a diluted hydrofluoric acid solution. Then, a channel insulating layer 4 is grown by thermal oxidation. The material is SiO2, and the thickness is 0.5 nm to 3 nm. Hafnium zirconium oxide (HZO) ferroelectric material 5 is deposited using atomic layer deposition (ALD) method, with a thickness of 7 to 15 nm. Figure 2 As shown in (a).

[0052] (2) Using the ALD method, a lower charge trapping material 6, a barrier layer intercalation layer 7, and an upper charge trapping material 8 are sequentially grown on the hafnium zirconium oxide (HZO) grown in step (1). Specifically, the materials are 1 nm hafnium oxide (HfO2), 1 nm aluminum oxide (Al2O3), and 2 nm hafnium oxide (HfO2), respectively. Figure 2 As shown in (b).

[0053] (3) A gate insulating layer 9 with a thickness of 3 nm is grown on the surface of the charge trapping layer prepared in step (2) by ALD, and the material is silicon oxide (SiO2); a metal gate electrode 10 with a thickness of 50 nm is deposited by physical vapor deposition (PVD), and the material is titanium nitride (TiN). Figure 2 As shown in (c).

[0054] (4) Define the gate electrode pattern using photolithography, then use photoresist as a mask to remove the metal gate electrodes and gate stack in the non-gate region using dry etching, such as... Figure 2 As shown in (d).

[0055] (5) The doped regions are defined by photolithography, and ion implantation is performed using photoresist and metal gate electrodes as masks to form highly doped regions 2 and 3. The entire wafer is then subjected to rapid thermal annealing to activate the impurities in the highly doped regions and the hafnium zirconium oxide (HZO) ferroelectric material 5, such as... Figure 2 As shown in (e).

[0056] Finally, the conventional CMOS back-end processes, including depositing interlayer dielectrics, etching vias, and metallization, are used to fabricate the gate-injected ferroelectric field-effect transistor.

[0057] This invention proposes a gate-injected FeFET with high storage window and high retention characteristics, and its fabrication method. First, a charge trapping layer is inserted between the gate insulating layer and the ferroelectric layer to provide additional bulk traps for gate-injected electrons, thereby increasing the gate-injected electron trapping efficiency during programming. To reduce the voltage division of the charge trapping layer in the gate stack and to meet the gate stack thickness limitations in VNAND process integration, the charge trapping layer is selected from materials with high dielectric constant and high bulk trap density, and its thickness is controlled to within 5 nm. Further, a thin barrier layer is inserted into the charge trapping layer, with a bandgap larger than that of the charge trapping material, and it should be an amorphous material. During programming, high-energy gate-injected electrons are "intercepted" by the barrier layer and remain within the charge trapping layer, further improving the gate-injected electron trapping efficiency and storage window. On the other hand, during the retention process, the barrier layer and the gate insulating layer, which also has a high bandgap, together form an energy potential well for electrons, which can effectively alleviate the emission effect of electrons trapped in the trap in both directions of the gate and the channel, thereby improving the retention characteristics.

[0058] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A gate-injection ferroelectric field-effect transistor, comprising a semiconductor substrate, a highly doped source region, a highly doped drain region, a metal gate electrode, and a gate stack, characterized in that, The gate stack consists of, from bottom to top, a channel insulating layer, a ferroelectric layer, a charge trapping layer, and a gate insulating layer. The charge trapping layer comprises three layers of material, which, from bottom to top, consist of a charge trapping material layer, a barrier intercalation layer, and a charge trapping material layer. The metal gate electrode is located on the gate stack, and the highly doped source region and highly doped drain region are located on both sides of the channel region below the gate stack.

2. The gate-injection ferroelectric field-effect transistor as described in claim 1, characterized in that, The thickness of the channel insulating layer is 0.5–3 nm, and the material is silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), or silicon oxynitride (SiO2). x N y ).

3. The gate-injection ferroelectric field-effect transistor as described in claim 1, characterized in that, The ferroelectric layer material is an undoped hafnium oxide ferroelectric material, or a hafnium oxide-doped ferroelectric material: hafnium zirconium oxide (HZO), hafnium aluminum oxide (HAO), hafnium silicon oxide (HSO), or hafnium lanthanum oxide (HLO), with a thickness of 7–15 nm.

4. The gate-injection ferroelectric field-effect transistor as described in claim 1, characterized in that, The intercalation thickness of the barrier layer in the charge trapping layer is 0.5–1.5 nm, and the material is alumina (Al2O3) or boron nitride (BN).

5. The gate-injection ferroelectric field-effect transistor as described in claim 1, characterized in that, The band gap of the charge trapping material in the charge trapping layer is smaller than the band gap of the intercalation material in the barrier layer. The charge trapping material is hafnium oxide (HfO2) or silicon nitride (SiN). x The thickness of the upper charge-trapping material is 2-3 nm, and the thickness of the lower charge-trapping material is 1-2 nm. The thickness of the upper charge-trapping material is greater than that of the lower charge-trapping material.

6. The gate-injection ferroelectric field-effect transistor as described in claim 1, characterized in that, The gate insulating layer is a single silicon oxide (SiO2) layer with a thickness of 2–4 nm; or the gate insulating layer is a silicon oxide / silicon nitride / silicon oxide (SiO2 / SiN) layer. x The structure is a three-layer structure of (SiO2), with each layer having a thickness of 1.5–2.5 nm.

7. A method for fabricating a gate-injection type ferroelectric field-effect transistor as described in claim 1, characterized in that, Includes the following steps: (1) Define the active region on the semiconductor substrate using an isolation method; (2) Use diluted hydrofluoric acid solution to remove the native oxide layer on the active silicon surface; (3) Growing a channel insulating layer on the substrate surface; (4) Ferroelectric materials with hafnium oxide-based deposition on the entire substrate; (5) In the whole sheet, a charge trapping layer is deposited first, then a barrier layer is intercalated, and finally another layer of charge trapping material is deposited. (6) Deposit a gate insulating layer over the entire wafer; (7) Deposit metal gate electrode material over the entire wafer; (8) Define the gate region by photolithography, and then form the gate electrode pattern by photolithography and etching; (9) Photolithography is performed on the doped source and drain regions, and ion implantation is performed using photoresist and metal gate electrodes as masks to form highly doped source and drain regions; (10) Perform rapid thermal annealing on the entire sheet to activate the ferroelectricity of the ferroelectric layer and source / drain injection impurities; (11) Finally, CMOS back-end processes are performed, including depositing interlayer dielectric, etching vias and metallization, to ultimately form the gate-injected ferroelectric field-effect transistor.

8. The method as described in claim 7, characterized in that, The semiconductor material in step (1) is silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), group II-VI binary or ternary compounds, group III-V binary or ternary compounds, group IV-IV binary or ternary compounds, silicon on an insulator, or germanium on an insulator.

9. The method as described in claim 7, characterized in that, The method for growing the channel insulating layer in step (3) is selected from one of the following methods: wet chemical method, conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition, atomic layer deposition or physical vapor deposition; the method for growing the ferroelectric layer and charge trapping layer in steps (4) and (5) is atomic layer deposition; the method for growing the gate insulating layer in step (6) is atomic layer deposition or chemical vapor deposition.

10. The method as described in claim 7, characterized in that, In step (7), the metal gate electrode material is titanium nitride (TiN), tungsten (W), or tantalum nitride (TaN), and its growth method is physical vapor deposition or chemical vapor deposition.

Images