Silicon carbide power device and method of making the same

Abstract

The application relates to a silicon carbide power device and a preparation method thereof, which comprises a substrate, a source metal and a shielding area. The substrate comprises, in sequence along a first direction, a base, a buffer layer and an epitaxial layer. The epitaxial layer comprises a well region extending into the epitaxial layer through a first surface of the epitaxial layer, and a strip-shaped MPS structure and a strip-shaped gate alternately arranged in a second direction and penetrating the well region in a direction opposite to the first direction. The source metal extends into the well region in a direction opposite to the first direction and is in contact with the strip-shaped MPS structure. The top surface of the shielding area is located within the bottom surface of the strip-shaped gate. The strip-shaped MPS structure comprises doped columns arranged in a third direction. The doped columns and the epitaxial layer and the buffer layer directly below the doped columns are used to form a PiN structure. The epitaxial layer between adjacent doped columns is in contact with the source metal directly above the epitaxial layer and forms a Schottky structure. The silicon carbide power device has low Ron and Vf, high surge resistance and low manufacturing cost.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a silicon carbide power device and its fabrication method. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used and high-performance power devices. Among them, SiC material, due to its excellent properties, is highly attractive for high-power applications and has become one of the ideal materials for high-performance power MOSFETs. SiC MOSFET devices mainly include lateral double-diffused DMOSFETs and vertical trench gate structures. Trench-gate silicon carbide (SiC) MOSFET devices are highly sought after due to their advantages such as high trench gate mobility, small cell size, high channel density, and absence of JFET region resistance.

[0003] With the development of semiconductor technology, small size, high power, and high performance have become the main development trends. The continuous miniaturization of the physical size of devices has driven the continuous reduction of the design pitch of their cells. However, due to limitations in process technology and structural design, the miniaturization of trench gate MOSFET devices has limited room for performance optimization. Summary of the Invention

[0004] Therefore, it is necessary to provide a silicon carbide power device and its fabrication method to address the technical problems in the existing technology, which can at least achieve device miniaturization and performance upgrade while effectively reducing manufacturing costs.

[0005] In a first aspect, this application provides a silicon carbide power device, comprising: a substrate, a source metal, and a shielding region;

[0006] The substrate includes a base, a buffer layer, and an epitaxial layer arranged sequentially along a first direction;

[0007] The epitaxial layer includes a well region extending into the epitaxial layer via a first surface of the epitaxial layer, and strip-shaped MPS structures and strip-shaped gates that are alternately arranged along a second direction and away from the first direction through the well region.

[0008] The source metal extends into the well region in a direction away from the first direction and contacts the strip-shaped MPS structure; the top surface of the shielding region is located inside the bottom surface of the strip-shaped gate.

[0009] The strip-shaped MPS structure includes doped pillars spaced apart along a third direction; the doped pillars, together with the epitaxial layer, buffer layer, and substrate directly below, form a PiN structure; the epitaxial layer between adjacent doped pillars contacts the source metal directly above, forming a Schottky structure.

[0010] The first direction, the second direction, and the third direction are all perpendicular to each other.

[0011] In some embodiments, the doped pillar and the shielding region are prepared simultaneously in the same process steps;

[0012] The source metal and the Schottky structure are prepared simultaneously in the same process steps.

[0013] In some embodiments, the well region includes strip-shaped source regions and strip-shaped base regions arranged sequentially away from the first direction;

[0014] The source metal penetrates the strip-shaped source region along a direction away from the first direction and extends into the strip-shaped base region to connect with the top surface of the doped pillar and part of the epitaxial layer.

[0015] The bottom surface of the strip gate is lower than the bottom surface of the strip base region.

[0016] In some embodiments, the cross-section of the source metal is T-shaped, including a first part and a second part arranged along a first direction;

[0017] The width of the first part is smaller than the width of the second part;

[0018] The bottom surface of the first part is flush with the first surface.

[0019] The second part comes into contact with the doped pillar, forming an ohmic contact;

[0020] The second part contacts the epitaxial layer, forming a Schottky junction;

[0021] Width is used to characterize the dimension along the second direction.

[0022] In some embodiments, the width of the PiN structure is the same as the width of the Schottky structure, but smaller than the width of the strip source region;

[0023] The bottom surface of the doped column is flush with the bottom surface of the shielding area.

[0024] Secondly, this application provides a method for fabricating a silicon carbide power device, comprising: providing a substrate; the substrate includes a base, a buffer layer, and an epitaxial layer arranged sequentially along a first direction;

[0025] A well region extending into the epitaxial layer through a first surface of the epitaxial layer is formed therein, and a strip-shaped MPS structure and a strip-shaped gate are arranged alternately in the well region along a second direction and away from a first direction; a shielding area is provided on the bottom surface of the strip-shaped gate.

[0026] A source metal is formed that extends into the well region in a direction away from the first direction and contacts the strip-shaped MPS structure.

[0027] The strip-shaped MPS structure includes doped pillars spaced apart along a third direction; the doped pillars, together with the epitaxial layer, buffer layer, and substrate directly below, form a PiN structure; the epitaxial layer between adjacent doped pillars contacts the source metal directly above, forming a Schottky structure.

[0028] The first direction, the second direction, and the third direction are all perpendicular to each other.

[0029] In some embodiments, forming a well region includes:

[0030] Strip-shaped base regions are formed in the substrate, spaced apart along the second direction and extending along the third direction;

[0031] A strip-shaped source region is formed extending from the first surface into the strip-shaped base region; the strip-shaped base region and the strip-shaped source region are used to constitute the well region.

[0032] In some embodiments, forming a strip-shaped MPS structure includes:

[0033] An ion implantation process is performed on the substrate to form doped pillars spaced apart along the third direction between adjacent strip-shaped base regions and strip-shaped source regions;

[0034] After forming the strip gate, a dielectric layer is formed covering the first surface;

[0035] Remove a portion of the dielectric layer and a portion of the substrate located between adjacent strip gates to form a multi-level contact hole extending away from the first direction;

[0036] Source metal is formed within multi-level contact holes.

[0037] In some embodiments, the cross-section of the source metal is T-shaped, including a first part and a second part arranged along a first direction;

[0038] The width of the first part is smaller than the width of the second part;

[0039] The bottom surface of the first part is flush with the first surface.

[0040] The second part comes into contact with the doped pillar, forming an ohmic contact;

[0041] The second part contacts the epitaxial layer, forming a Schottky junction;

[0042] Width is used to characterize the dimension along the second direction.

[0043] In some embodiments, forming a shielding zone includes:

[0044] Based on the same ion implantation process using doped pillars, a shielding region extending in a third direction is formed within the strip-shaped base region and the strip-shaped source region.

[0045] In the above embodiments, the Schottky structure and the PiN structure are integrated below the source contact hole and arranged alternately along the longitudinal direction (i.e., the third direction) to form a strip-shaped MPS structure. Since the strip-shaped MPS structure and the strip-shaped gate are alternately arranged along the second direction and are not tightly attached to the sidewall of the gate trench, the effective channel length on both sides of the gate is avoided from being squeezed out, thereby increasing the overall channel density and reducing the specific on-resistance.

[0046] In addition, by over-etching multi-level contact holes, the source metal extends along the direction away from the first direction into the epitaxial layer between adjacent doped pillars in the well region. This introduces a height difference and a potential barrier of Schottky contacts between the epitaxial layer and the source region, blocking the path of carrier diffusion in the lateral (second direction). This avoids direct lateral (i.e., second direction) penetration between the epitaxial layer and the strip-shaped source region, effectively solving the penetration risk problem that is prone to occur in traditional compact layouts, and improving the breakdown voltage stability and operational reliability of the device. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 Power devices with trench gate structures provided in related technologies;

[0049] Figure 2 This is a schematic diagram of the silicon carbide power device provided in the embodiments of this application;

[0050] Figure 3 This is a flowchart of a method for fabricating a silicon carbide power device provided in one embodiment;

[0051] Figure 4 This is a schematic cross-sectional view of the substrate in step S20 of the preparation method provided in one embodiment;

[0052] Figure 5 This is a schematic cross-sectional view of the structure obtained after forming the well region in step S402 of the preparation method provided in one embodiment;

[0053] Figure 6 This is a cross-sectional schematic diagram of the structure obtained after forming the doped pillar and the shielding region in step S404 of the preparation method provided in one embodiment;

[0054] Figure 7 for Figure 6 The photomask used;

[0055] Figure 8This is the photomask used in step S404 in another embodiment;

[0056] Figure 9 This is a schematic cross-sectional view of the structure obtained after forming the gate trench in step S406 of the preparation method provided in one embodiment;

[0057] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming the gate in step S408 of the preparation method provided in one embodiment;

[0058] Figure 11 This is a schematic cross-sectional view of the structure obtained after forming the dielectric layer in step S602 of the preparation method provided in one embodiment;

[0059] Figure 12 This is a cross-sectional schematic diagram of the structure obtained after forming multi-level contact holes in step S604 of the preparation method provided in one embodiment;

[0060] Figure 13 This is a cross-sectional schematic diagram of the structure obtained after forming multi-level contact holes in step S606 of the preparation method provided in one embodiment;

[0061] Figure 14 for Figure 13 A cross-sectional schematic diagram of the structure obtained after performing the back-side metallization process.

[0062] Explanation of reference numerals in the attached figures:

[0063] 1. Substrate; 2. Buffer layer; 3. Epitaxial layer; 10. Substrate; 20. Well region; 21. Strip base region; 22. Strip source region; 23. Shielding region; 24. Doped pillar; 30. Strip MPS structure; 31. Schottky structure; 32. PiN structure; 40. Strip gate; 401. Gate trench; 41. Gate oxide layer; 42. Gate conductive layer; 11. Dielectric layer; 501. Multilevel contact hole; 51. Source metal; 511. First part; 512. Second part. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0066] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0067] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It should be understood that, in addition to the orientations shown in the drawings, spatial relation terms also include different orientations of the device in use and operation. For example, if the device is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0068] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0069] Embodiments of the invention are described herein with reference to cross-sectional drawings illustrating preferred embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the drawings are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.

[0070] Traditional power MOSFETs all contain parasitic PiN body diodes. When these diodes switch from on to reverse breakdown state, they generate large reverse recovery currents and voltage spikes. Furthermore, the charge accumulated during reverse recovery leads to significant switching losses. In addition, the on-state voltage of silicon carbide body diodes is theoretically greater than 3.5V, resulting in high power dissipation. These issues cause high switching losses and severe electromagnetic interference (EMI) in SiC MOSFETs, and can even lead to circuit oscillations and device damage. Trench-type SiC power MOSFETs are not immune to these problems either.

[0071] In related technologies, an optimized SiC trench MOSFET structure integrating a Schottky junction has been proposed based on this typical structure. The specific structure is as follows: Figure 1 . Figure 1 (a) in the figure is a three-dimensional diagram of the structure. Figure 1 (b) in the figure is a top view of the structure, as shown below. Figure 1 As shown, the improved structure mainly adopts the design idea of ​​alternating Schottky and source-level ohmic contacts, integrating the Schottky structure into the sidewall of the gate trench. The design intercept is reduced, which occupies part of the channel length, resulting in an increase in the forward specific on-resistance of the MOS device, which is not conducive to the overall performance improvement.

[0072] Furthermore, to prevent the N+ source layer from directly contacting and punching through to the N- type epitaxial layer, P-type doping is required to separate them. This necessitates four layers of patterned photolithography and corresponding ion implantation (source N+, P-well, P-type protective layer, source P+). Since ion implantation in silicon carbide (SiC) device fabrication requires high-temperature implantation and a hard mask, the repeated ion implantation significantly increases manufacturing costs and results in low failure efficiency.

[0073] For ease of understanding, in this embodiment mentioned in the application, the epitaxial layer may include a first surface located on the front side and a back surface, i.e., a second surface, opposite to the front side. Ignoring the flatness of the first and second surfaces, a direction away from the substrate is defined as the first direction, and directions parallel to the first surface include the second direction and a third direction. The first direction, the second direction, and the third direction are perpendicular to each other. The first direction is defined as the Z-axis direction, the second direction as the Y-axis direction, and the third direction as the X-axis direction.

[0074] Please refer to this. Figure 2 , Figure 2 Image (a) shows a partial planar top view of the silicon carbide power device provided in this application. Figure 2 (b) and Figure 2 (c) in the figure corresponds to exemplary cross-sections taken along lines A-A' and B-B', respectively. This application provides a silicon carbide power device, comprising: a substrate 10, a shielding region 23, a strip-shaped MPS structure 30, a strip-shaped gate 40, and a source metal 51. In the embodiments mentioned in this application, N+ or P+ represents heavy doping, and N- or P- represents light doping.

[0075] Specifically, the substrate 10 is composed of an N+ type substrate 1, an N+ type buffer layer 2, and an N- type epitaxial layer 3 arranged sequentially along the OZ direction. The epitaxial layer 3 has a well region 20 extending into the epitaxial layer 3 via a first surface. The well region 20 includes a P-type strip base region 21 and an N+ type strip source region 22 arranged along the OZ direction.

[0076] Furthermore, the epitaxial layer 3 also includes a P+ type shielding region 23 and a doped pillar 24, wherein, for example... Figure 2 As shown in Figure (b), the shielding region 23 is located at the bottom of the strip gate 40. The doped pillars 24 and the shielding region 23 are arranged at intervals along the OX direction, forming the PiN structure 32 in the strip MPS structure 30 together with the N-type epitaxial layer 3, the N+ type buffer layer 2, and the N+ type substrate 1 below.

[0077] The top surface of the epitaxial layer is provided with a source metal 51 with a "T" shaped cross-section, such as... Figure 2 (b) includes a first part 511 and a second part 512 arranged along the OZ direction. The second part 512 and the dielectric layer 11 are arranged alternately along the OY direction, and the width of the second part 512 is greater than the width of the second part 512. The first part 511 penetrates the strip-shaped source region 22 along the ZO direction and extends into the strip-shaped base region 21. While forming an ohmic contact with the P+ type doped pillar 24, it forms a Schottky structure 31 with the N- type epitaxial layer 3 between the adjacent doped pillars 24 along the OX direction. The specific structure is as follows: Figure 2 As shown in (c) in the figure.

[0078] Figure 2As shown in (a), the strip MPS structure 30 and the strip gate 40 are arranged alternately along the OY direction, and the Schottky structure 31 and the PiN structure 32 are arranged alternately along the OX direction. The specific structure of PiN is as follows. Figure 2 (b) Schottky structure 31 Figure 2 As shown in (c) in the figure.

[0079] In the above embodiments, the PiN structure and Schottky structure are alternately arranged and parallel to the gate trench, which does not increase the cell pitch and, since they are not tightly attached to the trench sidewalls, does not encroach on the length of the MOS channel. Compared to related technologies, such as Figure 1 The power device shown in this application has a larger channel density and a lower on-resistance Rsp.

[0080] In some embodiments, the doped pillar 24 and the shielding region 23 are fabricated simultaneously in the same process steps, and the source metal 51 and the Schottky structure 31 are fabricated simultaneously in the same process steps. This significantly reduces manufacturing costs compared to the original approach.

[0081] The following describes an embodiment of the silicon carbide power device described above. Please refer to [link to example]. Figure 3 The preparation method provided in this application includes: steps S20-S60.

[0082] Step S20: Provide a substrate; the substrate includes a base, a buffer layer, and an epitaxial layer arranged sequentially along a first direction.

[0083] Step S40: A well region extending into the epitaxial layer through the first surface of the epitaxial layer is formed in the epitaxial layer, and a strip MPS structure and a strip gate are alternately arranged in the well region along a second direction and away from the first direction; a shielding area is provided on the bottom surface of the strip gate.

[0084] Step S60: Form a source metal extending into the well region in a direction away from the first direction and in contact with the strip MPS structure; the strip MPS structure includes doped pillars spaced apart along the third direction; the doped pillars, the epitaxial layer directly below, and the buffer layer are used to form a PiN structure; the epitaxial layer between adjacent doped pillars is in contact with the source metal directly above to form a Schottky structure.

[0085] It should be understood that, although Figure 3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 3At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0086] Below, in conjunction with Figures 4 to 13 An exemplary method of the power device according to this application is described. Figures 4 to 13 A step-by-step cross-sectional view illustrating an exemplary method of fabricating a power device according to this application.

[0087] Please see Figure 4 , Figure 4 This is the original state of the SiC substrate with an epitaxial layer provided in this application. Along the OZ direction, it consists of substrate 1, buffer layer 2, and epitaxial layer 3, all doped with nitrogen. Specifically, in this embodiment, the typical concentration of substrate 1 is 1e20cm⁻¹. -3 The typical concentration of buffer layer 2 is 1e18cm. -3 Epitaxial layer 3 is lightly doped, denoted by N-, with a typical concentration of 1e16cm⁻¹ in this example. -3 .

[0088] Please see Figures 5-10 The extension step of step S40 includes:

[0089] Step S402: Perform first-layer patterned ion implantation on epitaxial layer 3 to form strip-shaped base regions 21 arranged sequentially along the OZ direction and spaced apart along the OY direction, resulting in the structure shown below. Figure 5 As shown. In this embodiment, the strip-shaped base region 21 and the strip-shaped source region 22 are collectively referred to as the well region 20.

[0090] Specifically, the element implanted in the strip-shaped base region 21 is aluminum, with a doping concentration ranging from 5e16cm. -3 -5e18cm -3 For example, 5e16cm -3 5e17cm -3 Or 5e18cm -3 The implantation depth is approximately 0.3 μm–1.0 μm, for example, 0.3 μm, 0.5 μm, 0.7 μm, or 1 μm. The implanted element in the strip-shaped source region 22 is nitrogen, with a doping concentration of 1e19 cm⁻¹. -3 -5e20cm -3 For example, 1e19cm -3 1e20cm -3 Or 5e20cm -3The injection depth is approximately 0.02μm-0.3μm, for example, 0.02μm, 0.04μm, 0.06μm, 0.08μm, 0.1μm.

[0091] In this embodiment, the doping concentration of the strip-shaped base region 21 is 8e17cm. -3 The implantation depth is 0.5 μm, and the strip-shaped source region 22 is N+ doped with a doping concentration of 1e20cm. -3 The injection depth is 0.1 μm. The spacing between adjacent injection regions is approximately 0.2 μm to 2 μm, for example, 0.2 μm, 1 μm, 1.2 μm or 2 μm, etc. In this embodiment, the spacing is 0.6 μm.

[0092] Step S404: Combining photolithography and ion implantation processes, a second layer of patterned ion implantation is performed on the epitaxial layer 3 to form doped pillars 24 spaced apart along the OX direction between adjacent well regions 20; simultaneously, shielding regions 23 are formed within the well regions 20, alternating with the doped pillars 24 along the OY direction, resulting in the structure shown below. Figure 6 As shown.

[0093] Specifically, ion implantation can be performed at a certain angle, between 0° and 7°. The implanted element in doped column 24 is aluminum, with a doping concentration of 1e19cm⁻¹. -3 -5e20cm -3 For example, 1e19cm -3 1e20cm -3 Or 5e20cm -3 The implantation depth is 0.8 μm-1.5 μm, for example, 0.8 μm, 1 μm, 1.2 μm, or 1.5 μm. In this embodiment, the doped column 24 is P+ doped with a doping concentration of 2e20cm. -3 The injection depth was 1.2 μm.

[0094] Furthermore, Figure 7 The photomask used in step S404 is shown. In its design, the photomask has different injection features along the longitudinal direction of the device, with the black areas representing the injection regions. The narrow injection region is the diode region, with a typical width of 0.6 μm; the wide injection region is the protective layer at the bottom of the trench, with a typical width of 0.9 μm. The position of the A-A' tangent line corresponds to... Figure 6 The section shown in (b) represents P+ implantation into the implantation region gap, where doped pillar 24 (i.e., the anode of the PiN diode) will be formed; the position of the B-B' tangent corresponds to... Figure 6 The section shown in (c) represents the area where P+ was not injected into the inter-region, where the Schottky structure described later will be formed.

[0095] Of course, in some embodiments, the x:y ratio on the photomask can be freely adjusted to obtain a more reasonable PiN:Schottky ratio. A typical value for this technical solution is 1.5μm:1.5μm. Alternatively, [the following can be used]... Figure 8 The staggered photolithography plate shown enables the simultaneous fabrication of the shielding region 23 and the doped pillar 24. After these two steps of patterned implantation, the entire device ion implantation process is complete. This significantly reduces the number of layers compared to conventional methods, effectively lowering the device's manufacturing complexity and cost.

[0096] Step S406: After completing the above two steps of pattern implantation, the device is subjected to high-temperature annealing to activate the implanted ions. A typical annealing temperature range is 1600℃~1750℃. Gate trench 401 is then etched into epitaxial layer 3, resulting in the structure shown below. Figure 9 As shown.

[0097] Specifically, the width of the gate trench 401 needs to be slightly wider than the shielding area 23, and the depth needs to be approximately shallower than the shielding area 23. In this embodiment, the width of the gate trench 401 is 1.0 μm and the depth is 0.8 μm, so that the shielding area 23 surrounds the bottom surface of the gate trench 401.

[0098] Step S408: Using a gate oxide process, after forming a gate oxide layer 41 in the gate trench, polysilicon is filled and etched back to form a gate conductive layer 42, resulting in a strip-shaped gate structure as shown below. Figure 10 As shown, they are arranged at intervals along the OY direction and extend along the OX direction.

[0099] In the above embodiments, the bottom shielding area serves as an electric field shielding layer during reverse bias. This ensures that the channel density is not significantly damaged while protecting the bottom of the trench and shielding against high electric fields. This significantly enhances the gate oxide reliability of the device and reduces the requirements for the gate oxide process.

[0100] Please see 11- Figure 13 The extension step of step S60 includes:

[0101] Step S602: A dielectric layer 11 is formed on the first surface using a deposition process, and the top surface is flattened using a reflow process or a chemical mechanical planarization process, resulting in the structure shown below. Figure 11 As shown.

[0102] For example, the material of dielectric layer 11 includes, but is not limited to, materials with a high k dielectric constant. Examples include aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), hafnium oxynitride (HfON), zirconium oxide (ZrO₂), tantalum oxide (Ta₂O₅), titanium oxide (TiO₂), or strontium titanium oxide (SrTiO₃). In this embodiment, the thickness of dielectric layer 11 is 1 μm.

[0103] Step S604: Etch dielectric layer 11 to form multi-level contact holes 501 extending along the ZO and X directions, resulting in the structure shown below. Figure 12 As shown.

[0104] Specifically, the multi-level contact hole 501 is etched in two steps. The first step is to use a narrow etching mask opening to etch the dielectric layer 11 and over-etch it into the epitaxial layer 3, ensuring that the bottom surface is lower than the bottom surface of the strip source region 22. The typical etching depth is 0.3 μm. The second step is to use a wide etching mask opening to continue etching the dielectric layer 11 and cut off at the first surface. This increases the contact area between the source metal and the strip source region 22, while introducing a height difference and a Schottky contact barrier between the epitaxial layer 3 and the strip source region 22. This blocks the path of carrier diffusion in the lateral (second direction) direction and prevents the N-type epitaxial layer 3 and the N+ type strip source region 22 from directly penetrating in the lateral (i.e., second direction).

[0105] Step S606: Form a metal layer that fills the multi-level contact holes 501 and covers the top surface of the dielectric layer 11. The metal layer within the multi-level contact holes 501 constitutes the source metal 51, and the resulting structure is as follows. Figure 13 As shown in (a) of the diagram.

[0106] Along the OX direction, such as Figure 13 As shown in (b), the first part 511 of the source metal 51 is in contact with the top surface of the doped pillar 24, forming an ohmic contact; as Figure 13 As described in (b), the first part 511 is connected to the epitaxial layer 3 between adjacent doped pillars 24 along the OX direction to form a Schottky junction.

[0107] In the above embodiments, the embedded Schottky junction together with the original PiN structure constitutes the MPS structure. The low barrier characteristic of the Schottky structure can reduce the reverse conduction voltage drop Vf. The Schottky junction has no conductivity modulation effect, which can significantly reduce the reverse recovery loss Erec. The reverse recovery loss Erec, the PiN structure mainly undertakes the surge current withstand function, and comprehensively improves the performance of the device's diode region.

[0108] In some embodiments, step S604 further includes front-side metallization processes such as NiSilicide formation, Ti / TiN deposition, W deposition, and Al / Cμ deposition. After step S604, back-side substrate 1 needs to be thinned and metallized. Since this is not the focus of this technical solution, it will not be described in detail here. The final structure is as follows: Figure 14 As shown.

[0109] In the above embodiments, the unexpected technical effect of this application is:

[0110] The silicon carbide power device provided in this application avoids an increase in cell pitch by alternating PiN and Schottky structures parallel to the trench. Simultaneously, the MPS structure is not tightly attached to the trench sidewalls, ensuring high MOS channel density. The ratio of Schottky to PiN structures within the device can be flexibly adjusted, and the simple ion implantation distribution design effectively reduces manufacturing costs. In terms of electrical performance, it combines the advantages of low specific on-resistance (Ron) and low forward voltage (Vf), and exhibits outstanding surge protection.

[0111] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A silicon carbide power device, characterized in that, include: Substrate, source metal, shielding area; The substrate includes a substrate, a buffer layer, and an epitaxial layer arranged sequentially in a first direction; The epitaxial layer includes a well region extending into the epitaxial layer via a first surface of the epitaxial layer, and strip-shaped MPS structures and strip-shaped gates that penetrate the well region in a direction opposite to the first direction and are alternately arranged in a second direction. The strip-shaped gate is a trench gate; The source metal extends into the well region in a direction opposite to the first direction and contacts the strip-shaped MPS structure; the top surface of the shielding region is located inside the bottom surface of the strip-shaped gate. The strip-shaped MPS structure includes doped pillars spaced apart along a third direction; the doped pillars, together with the epitaxial layer, buffer layer, and substrate directly below, form a PiN structure; the epitaxial layer between adjacent doped pillars is in contact with the source metal directly above, forming a Schottky structure. The doped pillar is formed by epitaxial layer ion implantation between adjacent well regions along the second direction; In the strip-shaped MPS structure, the ratio of PIN structure to Schottky structure can be freely adjusted by forming a photomask for doped pillars; the shielding region is prepared simultaneously with the doped pillars, and the shielding region is either aligned or staggered on both sides of the doped pillars. The first direction, the second direction, and the third direction are all perpendicular to each other.

2. The silicon carbide power device according to claim 1, characterized in that, The source metal and the Schottky structure are prepared simultaneously in the same process steps.

3. The silicon carbide power device according to claim 2, characterized in that, The well region includes strip-shaped source regions and strip-shaped base regions arranged sequentially in a direction away from the first direction; The source metal penetrates the strip-shaped source region along a direction opposite to the first direction and extends into the strip-shaped base region to connect with the doped pillar and part of the top surface of the epitaxial layer; The bottom surface of the strip gate is lower than the bottom surface of the strip base region.

4. The silicon carbide power device according to claim 3, characterized in that, The cross-section of the source metal is "T" shaped, including a first part and a second part arranged along the first direction; The width of the first part is smaller than the width of the second part; The bottom surface of the first part is flush with the first surface; The second part comes into contact with the doped pillar to form an ohmic contact; The second part contacts the epitaxial layer to form a Schottky junction; The width is used to characterize the dimension along the second direction.

5. The silicon carbide power device according to claim 3, characterized in that, The width of the PiN structure is the same as the width of the Schottky structure, but smaller than the width of the strip source region; The bottom surface of the doped column is flush with the bottom surface of the shielding area.

6. A method for fabricating a silicon carbide power device, characterized in that, include: A substrate is provided; the substrate includes a base, a buffer layer, and an epitaxial layer arranged sequentially in a first direction; A well region extending into the epitaxial layer through a first surface of the epitaxial layer is formed therein, and strip-shaped MPS structures and strip-shaped gates are arranged alternately along a second direction and passing through the well region in a direction opposite to the first direction; a shielding area is provided on the bottom surface of the strip-shaped gates; the strip-shaped gates are trench gates. A source metal is formed that extends into the well region in a direction opposite to the first direction and contacts the strip-shaped MPS structure; The strip-shaped MPS structure includes doped pillars spaced apart along a third direction; the doped pillars, together with the epitaxial layer, buffer layer, and substrate directly below, form a PiN structure; the epitaxial layer between adjacent doped pillars is in contact with the source metal directly above, forming a Schottky structure. The doped pillar is formed by epitaxial layer ion implantation between adjacent well regions along the second direction; In the strip-shaped MPS structure, the ratio of PIN structure to Schottky structure can be freely adjusted by forming a photomask for doped pillars; the shielding region is prepared simultaneously with the doped pillars, and the shielding region is either aligned or staggered on both sides of the doped pillars. The first direction, the second direction, and the third direction are all perpendicular to each other.

7. The preparation method according to claim 6, characterized in that, Forming the well region includes: Strip-shaped base regions are formed within the substrate, spaced apart along the second direction and extending along the third direction; A strip-shaped source region is formed extending into the strip-shaped base region via the first surface; the strip-shaped base region and the strip-shaped source region are used to constitute the well region.

8. The preparation method according to claim 7, characterized in that, Forming the strip-shaped MPS structure includes: An ion implantation process is performed on the substrate to form doped pillars spaced apart along the third direction between adjacent strip-shaped base regions and strip-shaped source regions; After the strip gate is formed, a dielectric layer is formed covering the first surface; Remove a portion of the dielectric layer and a portion of the substrate located between adjacent strip gates to form a multi-level contact hole extending away from the first direction; The source metal is formed within the multi-level contact holes.

9. The preparation method according to claim 8, characterized in that, The cross-section of the source metal is "T" shaped, including a first part and a second part arranged along the first direction; The width of the first part is smaller than the width of the second part; The bottom surface of the first part is flush with the first surface; The second part comes into contact with the doped pillar to form an ohmic contact; The second part contacts the epitaxial layer to form a Schottky junction; The width is used to characterize the dimension along the second direction.

10. The preparation method according to claim 7, characterized in that, The shielding zone is formed by: Based on the same ion implantation process of the doped column, a shielding region extending in the third direction is formed in the strip-shaped base region and the strip-shaped source region.

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