Display panel, preparation method and display device

Abstract

A display panel comprises a substrate (10), a display structure layer and a first organic insulating layer, wherein the display structure layer and the first organic insulating layer are located on one side of the substrate (10). The display structure layer comprises a plurality of display metal layers, and one of the plurality of display metal layers farthest from the substrate (10) comprises a plurality of adapter pads (611, 612). The first organic insulating layer is located on one side of the plurality of adapter pads (611, 612) away from the substrate (10), and is provided with a plurality of adapter holes (V1, V2) corresponding to the plurality of adapter pads (611, 612). The first organic insulating layer comprises a first edge part and a second edge part which at least partially surround the transfer holes (V1 and V2), the second edge part is located on the side, away from the transfer holes (V1 and V2), of the first edge part, and the maximum thickness of the first edge part is smaller than or equal to the minimum thickness of the second edge part; the first edge portion covers at least part of the edge of the corresponding adapter pad (611, 612) exposed by the adapter hole (V1, V2).

Description

Display panel and its preparation method, display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display panel and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] This disclosure provides a display panel, a method for manufacturing the panel, and a display device.

[0006] On one hand, this embodiment provides a display panel, including: a substrate, a display structure layer located on one side of the substrate, and a first organic insulating layer. The display structure layer includes a plurality of display metal layers, and the display metal layer furthest from the substrate among the plurality of display metal layers includes a plurality of transition pads. The first organic insulating layer is located on the side of the plurality of transition pads furthest from the substrate, and is provided with a plurality of transition holes corresponding to the plurality of transition pads, the plurality of transition holes being configured to expose a portion of the corresponding transition pad surface facing away from the substrate. The first organic insulating layer includes a first edge portion and a second edge portion at least partially surrounding the transition hole, the second edge portion being located on the side of the first edge portion furthest from the transition hole, the maximum thickness of the first edge portion being less than or equal to the minimum thickness of the second edge portion, and the first edge portion covering at least a portion of the edge of the corresponding transition pad exposed by the transition hole.

[0007] In some exemplary embodiments, the overlap length between the first organic insulating layer and one side edge of the transition pad is greater than or equal to 3.5 micrometers.

[0008] In some exemplary embodiments, the overlap length between the first edge of the first organic insulating layer and one side edge of the adapter pad is greater than or equal to 2.5 micrometers, and the overlap length between the second edge and one side edge of the adapter pad is greater than or equal to 1 micrometer.

[0009] In some exemplary embodiments, the substrate includes: a display area and a first border area located on one side of the display area along a second direction, the first border area including: a first trace area, a bending area and a second trace area sequentially disposed along a direction away from the display area; the plurality of transition pads include: a plurality of first transition pads located in the first trace area and a plurality of second transition pads located in the second trace area.

[0010] In some exemplary embodiments, the display panel further includes: a touch structure layer located on the side of the display structure layer away from the substrate, the touch structure layer including at least one touch conductive layer; the at least one touch conductive layer including: a touch lead located in the first wiring area and a touch adapter line located in the second wiring area; the touch lead is connected to the first adapter pad, and the touch adapter line is connected to the second adapter pad.

[0011] In some exemplary embodiments, the first adapter pad includes: a first end near the bending region and a second end away from the bending region along the second direction, and a third end and a fourth end opposite each other along the first direction; the first direction intersects the second direction. The orthographic projection of the first edge of the first organic insulating layer on the substrate does not overlap with the orthographic projection of the first end of the first adapter pad on the substrate; however, the orthographic projection of the first edge of the first organic insulating layer on the substrate overlaps with the orthographic projections of the second end, third end, and fourth end of the first adapter pad on the substrate.

[0012] In some exemplary embodiments, the second adapter pad includes: a fifth end near the bending region along the second direction and a sixth end away from the bending region, and a seventh end and an eighth end opposite each other along a first direction, the first direction intersecting the second direction. The orthographic projection of the first edge portion of the first organic insulating layer on the substrate does not overlap with the orthographic projection of the fifth end of the second adapter pad on the substrate, but overlaps with the orthographic projections of the sixth, seventh, and eighth ends of the second adapter pad on the substrate.

[0013] In some exemplary embodiments, the display structure layer includes at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, and a second planarization layer disposed on the substrate; the plurality of transition pads are located on the second source / drain metal layer, and the first organic insulating layer includes the second planarization layer.

[0014] In some exemplary embodiments, the display structure layer includes at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a third source / drain metal layer, and a third planarization layer disposed on the substrate; the plurality of transition pads are located on the third source / drain metal layer, and the first organic insulating layer includes the third planarization layer.

[0015] In some exemplary embodiments, the display structure layer includes at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a third source / drain metal layer, a third planarization layer, a fourth source / drain metal layer, and a fourth planarization layer disposed on the substrate; the plurality of transition pads are located on the fourth source / drain metal layer, and the first organic insulating layer includes the fourth planarization layer.

[0016] In some exemplary embodiments, the display structure layer includes at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a third source / drain metal layer, a third planarization layer, and a fourth planarization layer disposed on the substrate; the plurality of transition pads are located on the third source / drain metal layer, and the first organic insulating layer includes the fourth planarization layer.

[0017] In some exemplary embodiments, the display structure layer further includes a pixel definition layer located on the side of the plurality of display metal layers away from the substrate; the orthographic projection of the pixel definition layer on the substrate does not overlap with the orthographic projection of the plurality of transition pads on the substrate.

[0018] In some exemplary embodiments, the first trace area is provided with a first isolation dam and a second isolation dam extending along a first direction, the first isolation dam being located on the side of the second isolation dam closer to the display area. The first trace area includes: a first pixel definition cutout area and a second pixel definition cutout area, the pixel definition layer does not overlap with the orthographic projection of the first pixel definition cutout area and the second pixel definition cutout area on the substrate, the first pixel definition cutout area and the second pixel definition cutout area are connected, the length of the first pixel definition cutout area along the first direction is greater than the length of the second pixel definition cutout area along the first direction, the orthographic projection of the second pixel definition cutout area on the substrate covers the orthographic projection of the plurality of first transition pads on the substrate, the first pixel definition cutout area is located on the side of the second isolation dam away from the display area, wherein the first direction intersects the second direction.

[0019] On the other hand, this embodiment provides a display device, including the display panel as described above.

[0020] On the other hand, this embodiment provides a method for fabricating a display panel, comprising: fabricating a display structure layer on one side of a substrate, the display structure layer comprising a plurality of display metal layers, wherein the display metal layer furthest from the substrate comprises a plurality of transition pads; fabricating a first organic insulating layer on the side of the plurality of transition pads furthest from the substrate, the first organic insulating layer having a plurality of transition holes corresponding to the plurality of transition pads, the plurality of transition holes being configured to expose a portion of the corresponding transition pad surface facing away from the substrate; the first organic insulating layer comprising at least a first edge portion and a second edge portion surrounding the transition holes, the second edge portion being located on the side of the first edge portion furthest from the transition holes, the maximum thickness of the first edge portion being less than or equal to the minimum thickness of the second edge portion, and the first edge portion covering at least a portion of the edge of the corresponding transition pad exposed by the transition hole.

[0021] In some exemplary embodiments, the preparation of the first organic insulating layer includes: forming the plurality of transition holes, a first edge portion and a second edge portion of the first organic insulating layer using a semi-mask process.

[0022] On the other hand, this embodiment provides a display panel, including: a substrate and a display structure layer located on one side of the substrate. The display structure layer includes a plurality of display metal layers and a pixel definition layer located on the side of the plurality of display metal layers away from the substrate. The display structure layer farthest from the substrate among the plurality of display metal layers includes a plurality of transition pads; the orthographic projection of the pixel definition layer on the substrate and the orthographic projection of the plurality of transition pads on the substrate do not overlap.

[0023] In some exemplary embodiments, the substrate includes: a display area and a first border area located on one side of the display area along a second direction. The first border area includes: a first trace area, a bending area, and a second trace area sequentially disposed along a direction away from the display area. The plurality of transition pads include: a plurality of first transition pads located in the first trace area and a plurality of second transition pads located in the second trace area. The first trace area is provided with a first isolation dam and a second isolation dam extending along a first direction. The first isolation dam is located on the side of the second isolation dam closer to the display area; the first direction intersects the second direction. The first trace area includes: a first pixel definition cutout area and a second pixel definition cutout area. The pixel definition layer does not overlap with the orthographic projection of the first pixel definition cutout area and the second pixel definition cutout area on the substrate. The first pixel definition cutout area and the second pixel definition cutout area are connected. The length of the first pixel definition cutout area along the first direction is greater than the length of the second pixel definition cutout area along the first direction. The orthographic projection of the second pixel definition cutout area on the substrate covers the orthographic projection of the plurality of first transition pads on the substrate. The first pixel definition cutout area is located on the side of the second isolation dam away from the display area.

[0024] In some exemplary embodiments, the display panel further includes: a touch structure layer located on the side of the display structure layer away from the substrate, the touch structure layer including at least one touch conductive layer; the at least one touch conductive layer including: a touch lead located in the first wiring area and a touch adapter line located in the second wiring area. The touch lead is connected to the first adapter pad, and the touch adapter line is connected to the second adapter pad.

[0025] In some exemplary embodiments, the touch structure layer includes: a first touch conductive layer and a second touch conductive layer disposed along a direction away from the substrate, wherein the touch lead and the touch adapter line are located in the second touch conductive layer.

[0026] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0027] Overview of the attached figures

[0028] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0029] Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure;

[0030] Figure 2A is a partial cross-sectional schematic diagram of the display area of ​​a display panel according to at least one embodiment of the present disclosure;

[0031] Figure 2B is another partial cross-sectional view of the display area of ​​a display panel according to at least one embodiment of the present disclosure;

[0032] Figure 2C is another partial cross-sectional view of the display area of ​​a display panel according to at least one embodiment of the present disclosure;

[0033] Figure 3 is a partial structural schematic diagram of the first border region according to at least one embodiment of the present disclosure;

[0034] Figure 4 is a schematic diagram of the local structure of region S1 in Figure 3;

[0035] Figure 5 is a magnified view of a portion of region S2 in Figure 4;

[0036] Figure 6A is a partial cross-sectional view along the Q1a-Q1a' direction in Figure 5;

[0037] Figure 6B is a partial cross-sectional view along the Q1b-Q1b' direction in Figure 5;

[0038] Figure 7 is a magnified view of a portion of region S3 in Figure 4;

[0039] Figure 8A is a partial cross-sectional view along the Q2a-Q2a' direction in Figure 7;

[0040] Figure 8B is a partial cross-sectional view along the Q2b-Q2b' direction in Figure 7;

[0041] Figure 9 is another enlarged schematic diagram of region S3 in Figure 4;

[0042] Figure 10 is a schematic diagram of a partial cross-section along the Q3-Q3' direction in Figure 9;

[0043] Figure 11 is another enlarged view of region S3 in Figure 4;

[0044] Figure 12 is a partial cross-sectional view along the Q4-Q4' direction in Figure 11;

[0045] Figure 13 is another enlarged schematic diagram of region S3 in Figure 4;

[0046] Figure 14 is a partial cross-sectional view along the Q5-Q5' direction in Figure 13;

[0047] Figure 15 is a partial structural schematic diagram of the first wiring area according to at least one embodiment of the present disclosure;

[0048] Figure 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0049] Detailed Explanation

[0050] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0051] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0052] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0053] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0054] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Joining" can include "electrical connection," which can include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on "components having some electrical function," as long as they enable the transmission of electrical signals between the connected constituent elements. Examples of "components having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components.

[0055] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0056] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0057] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0058] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0059] In this specification, "approximately" and "about" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" includes values ​​differing by less than 10%, such as values ​​differing by less than 5%.

[0060] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0061] The phrase "A and B are of the same layer" in this specification means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection area of ​​A, or the orthographic projection of A covers the orthographic projection of B.

[0062] With the development of display technology, narrow-bezel display products are receiving increasing attention. Taking OLED display panels as an example, narrow-bezel OLED display panels face challenges such as a higher risk of growing dark spots (GDS), reduced yield, and increased costs. GDS refers to the phenomenon where moisture continuously penetrates the light-emitting devices along the gaps in the display panel, causing the organic materials in the devices to oxidize and fail, resulting in a gradually expanding area of ​​non-luminous areas and ultimately, display defects. For instance, the transition holes located in the multi-layer metal overlap areas of the display panel can have significant height differences, making them prone to film peeling and GDS issues.

[0063] This embodiment provides a display panel, a method for manufacturing the panel, and a display device, which can improve the problems of film peeling and GDS in the display panel.

[0064] This embodiment provides a display panel, including: a substrate, a display structure layer located on one side of the substrate, and a first organic insulating layer. The display structure layer includes multiple display metal layers, and the display metal layer furthest from the substrate includes multiple transition pads. The first organic insulating layer is located on the side of the multiple transition pads furthest from the substrate and has multiple transition holes corresponding to the multiple transition pads. The multiple transition holes are configured to expose a portion of the corresponding transition pad surface facing away from the substrate. The first organic insulating layer includes a first edge portion and a second edge portion at least partially surrounding the transition holes. The second edge portion is located on the side of the first edge portion furthest from the transition holes. The maximum thickness of the first edge portion is less than or equal to the minimum thickness of the second edge portion, and the first edge portion covers at least a portion of the edge of the corresponding transition pad exposed by the transition hole.

[0065] The display panel provided in this embodiment utilizes a first organic insulating layer to effectively cover the edge of the adapter pad, which can reduce the slope angle of the first organic insulating layer at the adapter hole, thereby reducing the height difference at the adapter hole and mitigating the risk of peeling and wire breakage of the film layer above the adapter pad.

[0066] In some exemplary embodiments, the overlap length between the first organic insulating layer and one side edge of the adapter pad can be greater than or equal to 3.5 micrometers. In some examples, the overlap length between the first edge of the first organic insulating layer and one side edge of the adapter pad is greater than the overlap length between the second edge and one side edge of the adapter pad. For example, the overlap length between the first edge of the first organic insulating layer and one side edge of the adapter pad is greater than or equal to 2.5 micrometers, and the overlap length between the second edge of the first organic insulating layer and one side edge of the adapter pad can be greater than or equal to 1 micrometer. This example, by effectively covering the edges of the adapter pad located on the top layer of the display metal layer, can help reduce the height difference at the adapter hole and mitigate the risk of peeling and wiring breakage of the film layer above the adapter pad.

[0067] In some exemplary embodiments, the substrate may include: a display area and a first border area located on one side of the display area along a second direction. The first border area may include: a first trace area, a bending area, and a second trace area sequentially arranged along a direction away from the display area. Multiple adapter pads may include: multiple first adapter pads located in the first trace area and multiple second adapter pads located in the second trace area. In some examples, the display panel may further include: a touch structure layer located on the side of the display structure layer away from the substrate. The touch structure layer may include at least one touch conductive layer; the at least one touch conductive layer includes: touch leads located in the first trace area and touch adapter lines located in the second trace area. The touch leads are connected to the first adapter pads, and the touch adapter lines are connected to the second adapter pads. This example utilizes the first and second adapter pads to connect the touch leads and touch adapter lines, which can ensure the transmission of touch signals and mitigate the risk of trace breakage at the adapter hole location. This embodiment is not limited in this respect. In other examples, the adapter hole in this embodiment may be located in the second border area, the third border area, the fourth border area, or the display area.

[0068] In some exemplary embodiments, the display structure layer may further include a pixel definition layer located on the side of the plurality of display metal layers away from the substrate; the orthographic projection of the pixel definition layer onto the substrate does not overlap with the orthographic projection of the plurality of transition pads onto the substrate. This example, by removing the pixel definition layer above the transition pads, can reduce the film height difference caused by the transition holes and improve problems such as film peeling and trace breakage at the transition hole location.

[0069] In some exemplary embodiments, the first trace area may be provided with a first isolation dam and a second isolation dam extending along a first direction, with the first isolation dam located on the side of the second isolation dam closer to the display area. The first trace area includes: a first pixel definition cutout area and a second pixel definition cutout area. The orthographic projections of the pixel definition layer, the first pixel definition cutout area, and the second pixel definition cutout area onto the substrate do not overlap. The first pixel definition cutout area and the second pixel definition cutout area are connected. The length of the first pixel definition cutout area along the first direction may be greater than the length of the second pixel definition cutout area along the first direction. The orthographic projection of the second pixel definition cutout area onto the substrate may cover the orthographic projections of multiple first transition pads onto the substrate. The first pixel definition cutout area may be located on the side of the second isolation dam away from the display area. In some examples, the edge of the second isolation dam away from the display area may coincide with the boundary of the first pixel definition cutout area closer to the display area. This example, by extending the cutout boundary of the pixel definition layer in the first trace area to the second isolation dam, can help avoid film peeling and trace breakage caused by an excessively small cutout area of ​​the pixel definition layer.

[0070] The following examples illustrate the solution of this embodiment.

[0071] Figure 1 is a schematic diagram of a display panel according to at least one embodiment of the present disclosure. Figure 1 shows a plan view of the display panel before the bending process. In some examples, as shown in Figure 1, the display panel may include: a display area AA, and a peripheral area BB surrounding the display area AA. For example, the peripheral area BB may include: a first border area B1 located on one side of the display area AA, and border areas located on other sides of the display area AA (e.g., may include a second border area B2, a third border area B3, and a fourth border area B4). Wherein, the first border area B1 may be the bottom border of the display panel, the second border area B2 may be the top border of the display panel, the third border area B3 may be the left border of the display panel, and the fourth border area B4 may be the right border of the display panel.

[0072] In some examples, as shown in Figure 1, the display area AA can be a flat area comprising multiple sub-pixels PX that make up a pixel array. These sub-pixels PX can be configured to display moving or still images. The display area AA can be referred to as the active area. In some examples, the display area AA can be rectangular. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as circular or elliptical. In some examples, the display panel can be a flexible panel, and therefore the display panel can be deformable, such as rolled, bent, folded, or rolled up.

[0073] In some examples, as shown in Figure 1, the display area AA may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a first direction X, and the multiple data lines DL may extend along a second direction Y. The orthogonal projections of the multiple gate lines GL and the multiple data lines DL onto the substrate may intersect to form multiple sub-pixel regions, each of which may contain one sub-pixel PX. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals, or may include scan signals, or may include scan signals, reset control signals, and light emission control signals.

[0074] In some examples, as shown in Figure 1, the first direction X can be the extension direction of the grid line GL in the display area AA (e.g., the row direction), and the second direction Y can be the extension direction of the data line DL in the display area AA (e.g., the column direction). The first direction X and the second direction Y can intersect each other, for example, they can be perpendicular to each other.

[0075] In some examples, a pixel unit of the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0076] In some examples, the shape of the subpixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three subpixels, the three subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four subpixels, the four subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0077] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the manufacturing process, reduce the manufacturing difficulty of the display panel, and improve product yield. In other examples, the multiple transistors in the pixel circuit may include both P-type and N-type transistors.

[0078] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display panel—an LTPS+Oxide (LTPO) display panel—leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0079] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0080] Figure 2A is a partial cross-sectional schematic diagram of the display area of ​​a display panel according to at least one embodiment of the present disclosure. Figure 2A illustrates the structure of a sub-pixel of the display area as an example. In this example, it is described that the multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OPS). In other examples, the multiple transistors in the pixel circuit can be both LPS and OPS. Furthermore, this example illustrates a display panel integrating a mutual capacitance touch structure to form an FMLOC structure.

[0081] In some examples, as shown in Figure 2A, the display area of ​​the display panel may include a substrate 10, and a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, and a touch structure layer 50 sequentially disposed on the substrate 10. The display structure layer may include at least the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 30 may include at least light-emitting elements for multiple sub-pixels.

[0082] In some examples, Figure 2A illustrates a sub-pixel comprising a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 20 of the display area may include a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer disposed on the substrate 10. In this example, the multiple display metal layers of the display structure layer may include a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer. A first gate insulating layer 101 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 102 may be disposed between the first and second gate metal layers; an interlayer insulating layer 103 may be disposed between the second gate metal layer and the first source / drain metal layer; a passivation layer 104 and a first planarization layer 105 may be disposed between the first and second source / drain metal layers; and a second planarization layer 106 may be disposed on the side of the second source / drain metal layer away from the substrate 10. In this embodiment, the first gate insulating layer 101, the second insulating layer 102, the interlayer insulating layer 103, and the passivation layer 104 can be inorganic insulating layers, while the first planarization layer 105 and the second planarization layer 106 can be organic insulating layers. However, this embodiment is not limited to these. In other examples, a buffer layer can be provided on the side of the semiconductor layer near the substrate. The buffer layer can prevent harmful substances in the substrate from penetrating the interior of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can be provided on the side of the buffer layer near the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the thin-film transistor of the pixel circuit to avoid external light affecting the performance of the thin-film transistor. In other examples, the passivation layer can be omitted between the first source / drain metal layer and the second source / drain metal layer, and only the first planarization layer can be provided between the first source / drain metal layer and the second source / drain metal layer.

[0083] In some examples, as shown in FIG2A, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 10 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 10. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 10 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 103 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 103, the second gate insulating layer 102, and the first gate insulating layer 101 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 104 and the first planarization layer 105. In this example, the first transition electrode 231 can be used to achieve the electrical connection between the pixel circuit and the light-emitting element.

[0084] In some examples, the gate lines of the display area may be located in the first gate metal layer, the data lines of the display area may be located in the second source-drain metal layer, and the high-potential power lines of the display area may be located in the second source-drain metal layer. This embodiment is not limited in this respect.

[0085] In some examples, as shown in Figure 2A, the light-emitting structure layer 30 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on the second planarization layer 106 and electrically connected to the first transition electrode 231 through a third pixel via formed in the second planarization layer 106. The pixel definition layer 304 is disposed on the first electrode 301 and the second planarization layer 106, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer may also be provided on the side of the pixel definition layer 304 away from the substrate 10, and the isolation pillar layer may include multiple isolation pillars (PS).

[0086] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0087] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0088] In some examples, as shown in Figure 2A, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external moisture from entering the light-emitting element. However, this embodiment is not limited to this. For example, the encapsulation structure layer may employ a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0089] In some examples, as shown in Figure 2A, the touch structure layer 50 of the display area may include, in the direction perpendicular to the display panel, a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, a second touch conductive layer 512, and a protective layer 503, arranged sequentially. For example, the touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, and the protective layer 503 may be an inorganic insulating layer or an organic insulating layer.

[0090] In some examples, the touch structure layer of the display area may include a plurality of first touch units and a plurality of second touch units. The first touch units may have a linear shape extending along a first direction X, and the plurality of first touch units may be arranged sequentially along a second direction Y. The second touch units may also have a linear shape extending along the second direction Y, and the plurality of second touch units may be arranged sequentially along the first direction X. Each first touch unit may include a plurality of first touch electrodes and a first connecting portion arranged sequentially along the first direction X, and the first touch electrodes and the first connecting portions may be alternately arranged and sequentially connected. Each second touch unit may include a plurality of second touch electrodes arranged sequentially along the second direction Y, and the plurality of second touch electrodes may be spaced apart. Adjacent second touch electrodes may be connected to each other through second connecting portions. In some examples, the film layer containing the second connecting portion may be different from the film layers containing the first touch electrodes and the second touch electrodes.

[0091] In some examples, as shown in Figure 2A, multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions can be disposed on the same layer of the first touch conductive layer 511 and formed through the same patterning process. The first touch electrodes and the first connecting portions can be an integral structure interconnected with each other. Second connecting portions can be disposed on the second touch conductive layer 512 and can be interconnected with adjacent second touch electrodes through vias formed in the interlayer insulating layer 502. In other examples, multiple first touch electrodes, multiple second touch electrodes, and multiple second connecting portions can be disposed on the same layer of the first touch conductive layer 511. The second touch electrodes and second connecting portions can be an integral structure interconnected with each other. First connecting portions can be disposed on the second touch conductive layer 512 and can be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer 502. In some examples, the first touch electrode can be a driving (Tx) electrode, and the second touch electrode can be a sensing (Rx) electrode. Alternatively, the first touch electrode can be a sensing (Rx) electrode, and the second touch electrode can be a driving (Tx) electrode. This embodiment does not limit this.

[0092] Figure 2B is another partial cross-sectional view of the display area of ​​a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2B, the circuit structure layer 20 of the display area may include, in the direction perpendicular to the display panel, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer disposed on the substrate 10. A second planarization layer 106 is disposed between the second and third source / drain metal layers, and a third planarization layer 107 is disposed on the side of the third source / drain metal layer away from the substrate 10. The third source / drain metal layer may include at least a second transition electrode 232. The second transition electrode 232 can be electrically connected to a first transition electrode 231 located on the second source / drain metal layer through a pixel via formed in the second planarization layer 106. The second transition electrode 232 can be electrically connected to a first electrode 301 (e.g., anode) of the light-emitting element through a pixel via formed in the third planarization layer 107. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 231 and the second transition electrode 232. The circuit structure layer in this example may include three source / drain metal layers, which avoids arranging too many traces within a single source / drain metal layer, thus facilitating the implementation of a narrow bezel structure. The remaining structure of the display panel in this example can be referred to the description in the foregoing embodiments, and will not be repeated here.

[0093] Figure 2C is another partial cross-sectional view of the display area of ​​a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2C, the circuit structure layer 20 of the display area may include, in the direction perpendicular to the display panel, a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, a third source / drain metal layer, and a fourth source / drain metal layer disposed on the substrate 10. A second planarization layer 106 is disposed between the second and third source / drain metal layers, a third planarization layer 107 is disposed between the third and fourth source / drain metal layers, and a fourth planarization layer 108 is disposed on the side of the fourth source / drain metal layer away from the substrate 10. The fourth source / drain metal layer may include at least a third transition electrode 233. The third transition electrode 233 may be electrically connected to the second transition electrode 232 located on the third source / drain metal layer through a pixel via formed in the third planarization layer 107. The third transition electrode 233 may be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through a pixel via formed in the fourth planarization layer 108. This example utilizes a first transition electrode 231, a second transition electrode 232, and a third transition electrode 233 to achieve electrical connection between the pixel circuit and the light-emitting element. The circuit structure layer of this example may include four source / drain metal layers, which avoids arranging numerous traces within a single source / drain metal layer, thus facilitating a narrow bezel structure. The remaining structure of the display panel in this example can be referred to the description in the foregoing embodiments, and will not be repeated here.

[0094] In some examples, as shown in Figure 1, the touch structure layers of the third bezel area B3 and the fourth bezel area B4 of the display panel may each include multiple touch leads 252. The multiple touch leads 252 can be electrically connected to the first touch unit and the second touch unit, respectively. The multiple touch leads 252 may all be located in the first touch conductive layer, or all in the second touch conductive layer; or the multiple touch leads 252 may be alternately arranged in the first touch conductive layer and the second touch conductive layer. However, this embodiment is not limited to this.

[0095] In some examples, as shown in Figure 1, the first bezel area B1 of the display panel may include: a first wiring area B11, a bending area B12, and a second wiring area B13 arranged sequentially along a direction away from the display area AA. The first wiring area B11 can be connected to the display area AA, and the first wiring area B11 may be provided with at least a first power line, a second power line, multiple display leads, and multiple touch leads 252. The first power line may be configured as a high-potential power line connected to the display area AA, and the second power line may be configured as a low-potential power line connected to the third bezel area B13 and the fourth bezel area B14. The multiple display leads may include at least: multiple data leads and multiple drive leads (not shown). The multiple data leads may be electrically connected to multiple data lines DL of the display area AA; for example, the multiple data leads and multiple data lines DL may be electrically connected one-to-one. The multiple data leads may extend from the first wiring area B11 to the bending area B12 in a fan-out wiring manner. Multiple drive leads can extend from the third border region B3 and the fourth border region B4 to the first wiring region B11. These drive leads can be electrically connected to the gate drive circuitry within the third border region B3 and the fourth border region B4. The drive leads can be configured to provide control signals to the gate drive circuitry; for example, the control signals may include start signals, clock signals, etc. Multiple touch leads 252 can extend from the third border region B3 and the fourth border region B4 to the first wiring region B11, and can be located on the side of the multiple display leads away from the substrate.

[0096] In some examples, as shown in Figure 1, the bending area B12 connects between the first wiring area B11 and the second wiring area B13, and can be configured such that the second wiring area B13 bends to the back of the display area AA. The bending area B12 can have multiple bent connection lines, such as multiple data bent connection lines 261, multiple drive bent connection lines (not shown), multiple touch bent connection lines 262, a first power bent connection line (not shown), and a second power bent connection line (not shown). The first power bent connection line can be electrically connected to a first power line, and the second power bent connection line can be electrically connected to a second power line. The multiple data bent connection lines 261 can be electrically connected to multiple data leads, the multiple drive bent connection lines can be electrically connected to multiple drive leads, and the multiple touch bent connection lines 262 can be electrically connected to multiple touch leads 252. For example, in the edge area of ​​the first wiring area B11 near the bending area B12, the touch bending connection line 262 can be electrically connected to the touch lead line 252 through the first adapter hole V1.

[0097] In some examples, as shown in Figure 1, multiple bent connecting lines may all extend along the second direction Y. In some examples, the multiple bent connecting lines may be in the same layer. In some examples, the multiple touch bent connecting lines 262 may be located on opposite sides of the multiple data bent connecting lines 261 and the multiple drive bent connecting lines in the first direction X. This embodiment is not limited in this respect.

[0098] In some examples, as shown in Figure 1, the second wiring area B13 can be provided with multiple adapter cables, such as multiple data adapter cables and multiple touch adapter cables 272. The multiple data adapter cables can be electrically connected to multiple data bend connection cables 261, for example, in a one-to-one correspondence. The multiple touch adapter cables 272 can be electrically connected to multiple touch bend connection cables 262, for example, in a one-to-one correspondence. For example, in the edge region of the second wiring area B13 near the bend area B12, the touch adapter cable 272 can be electrically connected to the touch bend connection cable 262 through the second adapter hole V2.

[0099] In some examples, as shown in Figure 1, the second trace area B13 may include at least one first signal access area B131 and at least one second signal access area B132. This example illustrates one first signal access area B131 and one second signal access area B132. In other examples, the display panel may be a large-size panel, which may include multiple first signal access areas B131 and multiple second signal access areas B132. The multiple first signal access areas B131 may be arranged sequentially along the first direction X, and the multiple second signal access areas B132 may be arranged sequentially along the first direction X. The first signal access area B131 may be located on the side of the second signal access area B132 closer to the display area AA. In other words, the second signal access area B132 may be located on the side of the first signal access area B131 away from the bending area B12 in the second direction Y. In some examples, the second trace area B13 may also include a first circuit area located on the side of the first signal access area B131 closer to the bending area B12, and the first circuit area may be provided with multiple test circuits (not shown). The test circuit can be configured to be electrically connected to multiple data leads via data adapter cables and data bend connectors 261, providing test data signals to multiple data lines DL in the display area AA during the testing phase. The first circuit area may also include multiple electrostatic discharge circuits to provide electrostatic discharge paths. In this example, the data bend connector 261 can be electrically connected to the test circuit after being connected via data adapter cables. The data adapter cables are located on the side of the data bend connector 261 closest to the substrate, which facilitates the routing of the connection to the test circuit.

[0100] Figure 3 is a partial structural schematic diagram of the first border region according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the multiple bent connecting lines of the bending area B12 may include: four sets of data bent connecting lines (e.g., including a first set of data bent connecting lines 261a, a second set of data bent connecting lines 261b, a third set of data bent connecting lines 261c, and a fourth set of data bent connecting lines 261d) and three sets of first power bent connecting lines (e.g., including a first set of first power bent connecting lines 263a, a second set of first power bent connecting lines 263b, and a third set of first power bent connecting lines 263c). Four sets of second power supply bending connection lines (e.g., including the first set of second power supply bending connection lines 264a, the second set of second power supply bending connection lines 264b, the third set of second power supply bending connection lines 264c and the fourth set of second power supply bending connection lines 264d), two sets of drive bending connection lines (e.g., including the first set of drive bending connection lines 265a and the second set of drive bending connection lines 265b), and two sets of touch bending connection lines (e.g., including the first set of touch bending connection lines 262a and the second set of touch bending connection lines 262b).

[0101] In some examples, the first group of drive bending connection lines 265a, the first group of second power bending connection lines 264a, the first group of touch bending connection lines 262a, the second group of second power bending connection lines 264b, the third group of data bending connection lines 261c, the second group of first power bending connection lines 263b, the first group of data bending connection lines 261a, the first group of first power bending connection lines 263a, the second group of data bending connection lines 261b, the third group of first power bending connection lines 263c, the fourth group of data bending connection lines 261d, the third group of second power bending connection lines 264c, the second group of touch bending connection lines 262b, the fourth group of second power bending connection lines 264d, and the second group of drive bending connection lines 265b can be arranged sequentially along the first direction X.

[0102] In some examples, the second wiring area B13 may be provided with a first power lead 42, and second power leads 431 and 432. The first power lead 42 may include: a power body portion 420 extending along a first direction X; a first power extension portion 421 and a second power extension portion 422 extending along a second direction Y and located on the side of the power body portion 420 away from the bending area B12; and a plurality of power connection portions (e.g., including three power connection portions 423a, 423b, and 423c) extending along the second direction Y and located on the side of the power body portion 420 near the bending area B12. The power body portion 420, the first power extension portion 421, the second power extension portion 422, and the plurality of power connection portions may be an integral structure interconnected with each other. The first power extension portion 421 is connected to one end of the power body portion 420 in the first direction X, and the second power extension portion 422 is connected to the other end of the power body portion 420 in the first direction X. The first power extension 421 can bypass the first signal access area B131 from the side opposite to the first direction X (e.g., the left side) and extend to the second signal access area B132, connecting with the contact pad within the second signal access area B132. The second power extension 422 can bypass the first signal access area B131 from the other side of the first direction X (e.g., the right side) and extend to the second signal access area B132, connecting with the contact pad within the second signal access area B132. The three power connection portions 423a, 423b, and 423c can be electrically connected one-to-one with the first set of first power bent connection lines 263a, the second set of first power bent connection lines 263b, and the third set of first power bent connection lines 263c, so as to achieve electrical connection with the first power line within the first wiring area B11 through the three sets of first power bent connection lines. In some examples, the first power lead 42 can be a single-layer trace located in the first source-drain metal layer, or it can be a single-layer trace located in the second source-drain metal layer, or it can be a double-layer trace located in the first source-drain metal layer and the second source-drain metal layer.

[0103] In some examples, the second power lead 431 can be located on the opposite side of the first power lead 42 in the first direction X, and the second power lead 432 can be located on the same side as the first power lead 42 in the first direction X. The second power lead 431 can be connected to the first set of second power bend connection lines 264a and the second set of second power bend connection lines 264b to achieve electrical connection with the second power line within the first routing area B11; the second power lead 432 can be connected to the third set of second power bend connection lines 264c and the fourth set of second power bend connection lines 264d to achieve electrical connection with the second power line within the first routing area B11. In some examples, the second power leads 431 and 432 can be single-layer traces located in the first source / drain metal layer, or single-layer traces located in the second source / drain metal layer, or double-layer traces located in both the first and second source / drain metal layers.

[0104] In some examples, the first power lead 42 can be configured to transmit a first voltage signal, and the second power leads 431 and 432 can be configured to transmit a second voltage signal. The first voltage signal is different from the second voltage signal. For example, the first voltage signal can be greater than the second voltage signal. The first voltage signal can be configured to be provided to the pixel circuit of a sub-pixel of the display area, and the second voltage signal can be configured to be provided to the cathode of the light-emitting element of the sub-pixel of the display area. This embodiment is not limited in this respect.

[0105] Figure 4 is a partial structural diagram of region S1 in Figure 3. In some examples, as shown in Figure 4, the first trace area B11 can be provided with multiple first transition pads 611, which can be arranged in a row along the first direction X. The multiple first transition pads 611 can be located between the two connection ends of the second power line 433. The second power line 433 can be located, for example, in the first source / drain metal layer, or it can be a double-layer trace structure of the first source / drain metal layer and the second source / drain metal layer. For example, the multiple first transition pads 611 can realize the electrical connection between multiple touch lead-out lines 252 and multiple touch bent connection lines 262. In some examples, the first transition pads 611 and the touch bent connection lines 262 can be in the same layer, or the first transition pads 611 can be located on the side of the touch bent connection lines 262 away from the substrate; the touch lead-out lines 252 can be located on the side of the first transition pads 611 away from the substrate.

[0106] In some examples, as shown in Figure 4, the second wiring area B13 can be provided with multiple second transition pads 612. Multiple second transition pads 612 arranged along the first direction X can be referred to as a row of second transition pads 612, and multiple rows of second transition pads 612 can be arranged along the second direction Y. Multiple second transition pads 612 can be located between the two connection ends of the second power lead 431. Multiple second transition pads 612 can realize electrical connections between multiple touch-sensitive bent connection lines 262 and multiple touch-sensitive adapter lines 272. In some examples, the second transition pads 612 and the touch-sensitive bent connection lines 262 can be in the same layer, or the second transition pads 612 can be located on the side of the touch-sensitive bent connection lines 262 away from the substrate; the touch-sensitive adapter lines 272 can be located on the side of the second transition pads 612 away from the substrate. For example, the touch-sensitive adapter lines 272 and the touch lead 252 can be in the same layer, such as both located in the second touch conductive layer.

[0107] The following explanation uses the first and second adapter pads connected by the first set of touch bending connection lines as an example. The structure of the first and second adapter pads connected by the second set of touch bending connection lines is similar, so it will not be described again here.

[0108] Figure 5 is a partially enlarged schematic diagram of region S2 in Figure 4. Figure 6A is a partial cross-sectional schematic diagram along the Q1a-Q1a' direction in Figure 5. Figure 6B is a partial cross-sectional schematic diagram along the Q1b-Q1b' direction in Figure 5. This example uses the film layer structure of the display panel as shown in Figure 2B as an example for illustration. In this example, the first organic insulating layer can be the third planarization layer 107.

[0109] In some examples, as shown in Figures 5, 6A, and 6B, the first adapter pad 611 may be located in the third source / drain metal layer. The first adapter pad 611 may be electrically connected to the touch bend connection line 262 located in the second source / drain metal layer via the third adapter hole V3 formed in the second planarization layer 106. The orthographic projection of the first adapter pad 611 onto the substrate may cover the orthographic projection of the third adapter hole V3 onto the substrate. The orthographic projection of the third planarization layer 107 onto the substrate and the orthographic projection of the third adapter hole V3 onto the substrate may not overlap.

[0110] In some examples, the orthographic projection of the first adapter pad 611 onto the substrate can be rectangular, such as a square or a rounded rectangle. The first adapter pad 611 may include: a first end (e.g., the lower end) and a second end (e.g., the upper end) along the second direction Y near the bending region B12, and a third end (e.g., the left end) and a fourth end (e.g., the right end) opposite each other along the first direction X.

[0111] In some examples, the third planarization layer 107 may have a plurality of first transition holes V1, each corresponding to a plurality of first transition pads 611. The first transition holes V1 may expose a portion of the surface of the first transition pads 611 away from the substrate. For example, the orthographic projection of the first transition hole V1 onto the substrate may be rectangular. However, this embodiment is not limited to this. In other examples, the orthographic projection of the first transition hole onto the substrate may be circular or elliptical.

[0112] In some examples, the third planarization layer 107 may include at least a portion of a first edge 1071 and a second edge 1072 surrounding the first transition hole V1. The second edge 1072 may be located on the side of the first edge 1071 away from the first transition hole V1. The maximum thickness of the first edge 1071 may be less than or equal to the minimum thickness of the second edge 1072. The maximum thickness of the first edge 1071 may be the thickness at the junction of the first edge 1071 and the second edge 1072, and the minimum thickness of the first edge 1071 may be the thickness at the edge closest to the first transition hole V1. The average thickness of the first edge 1071 is less than the average thickness of the second edge 1072. In some examples, the thickness of the second edge 1072 may range from 1.0 micrometer to 2.0 micrometers, for example, from 1.2 micrometers to 1.8 micrometers, and further from 1.5 micrometers to 1.55 micrometers. In this example, the film thickness refers to the distance between the surface of the film away from the substrate and the surface near the substrate in a plane perpendicular to the substrate.

[0113] In some examples, the first edge portion 1071 may surround three sides of the first adapter hole V1, and the second edge portion 1072 may surround the periphery of the first adapter hole V1. The second edge portion 1072 may be located outside the first edge portion 1071. For example, the side of the first adapter hole V1 near the bending area B12 (corresponding to the first end of the first adapter pad 611) may be surrounded by the second edge portion 1072, and the side of the first adapter hole V1 away from the bending area B12 (corresponding to the second end of the first adapter pad 611) and both sides along the first direction X (corresponding to the third and fourth ends of the first adapter end 611) may be surrounded by the first edge portion 1071.

[0114] In some examples, the slope angle α of the first edge portion 1071 surrounding the first transition hole V1 of the third planarization layer 107 can be less than or equal to 70 degrees, for example, it can be greater than or equal to 10 degrees and less than or equal to 50 degrees. Further, the slope angle α can be greater than or equal to 20 degrees and less than or equal to 40 degrees, for example, it can be approximately 30 degrees, 31 degrees, 32 degrees, 33 degrees, 34 degrees, or 35 degrees. The slope angle of the first edge portion 1071 refers to the angle between the surface of the first edge portion 1071 away from the substrate and the plane containing the substrate. The surface of the first edge portion 1071 away from the substrate can be an arc-shaped slope or a flat slope. This embodiment is not limited in this respect.

[0115] In some examples, the orthographic projection of the first edge portion 1071 of the third planarization layer 107 onto the substrate may overlap with the orthographic projections of the second, third, and fourth ends of the first adapter pad 611 onto the substrate, but may not overlap with the orthographic projection of the first end of the first adapter pad 611 onto the substrate. The orthographic projection of the second edge portion 1072 of the third planarization layer 107 onto the substrate may overlap with the orthographic projections of the third and fourth ends of the first adapter pad 611 onto the substrate, but may not overlap with the orthographic projections of the first and second ends of the first adapter pad 611 onto the substrate.

[0116] In some examples, along the first direction X, the overlap length between the second edge 1072 of the third planarization layer 107 and one side edge of the first transition pad 611 can be a first distance L1, and the overlap length between the first edge 1071 of the third planarization layer 107 and one side edge of the first transition pad 611 can be a second distance L2; along the first direction X, the overlap length between the third planarization layer 107 and one side edge of the first transition pad 611 can be the sum of the first distance L1 and the second distance L2. Along the second direction Y, the overlap length between the first edge 1071 of the third planarization layer 107 and one side edge of the first contact pad 611 can be a third distance L3. The third distance L3 can be greater than the second distance L2, and the second distance L2 can be greater than the first distance L1. For example, the sum of the first distance L1 and the second distance L2 can be greater than or equal to 3.5 micrometers. For example, the second distance L2 can be greater than or equal to 2.5 micrometers, and the first distance L1 can be greater than or equal to 1 micrometer. For example, the second distance L2 can be approximately 2.5 micrometers, and the first distance L1 can be approximately 1 micrometer.

[0117] In some examples, as shown in Figure 6A, the touch lead 252 can be located in the second touch conductive layer. The touch interlayer insulating layer 502 can be provided with a fifth transition hole V5, through which the touch lead 252 can connect to the first transition pad 611 located in the third source / drain metal layer via the fifth transition hole V5 in the touch interlayer insulating layer 502 and the first transition hole V1 provided in the third planarization layer 107. The orthographic projection of the fifth transition hole V5 onto the substrate can be within the orthographic projection range of the first transition hole V1 onto the substrate. The touch interlayer insulating layer 502 can contact the first edge portion 1071 and the second edge portion 1072 of the third planarization layer 107 surrounding the first transition hole V1.

[0118] In this example, the first edge portion 1071 and the second edge portion 1072 of the third flat layer 107 are used to cover the edge of the first transition pad 611 located in the third source-drain metal layer. This can prevent cracks from forming at the edge of the third source-drain metal layer when the touch interlayer insulating layer 502 is directly deposited on the surface of the third source-drain metal layer, which is beneficial to achieving an effective connection between the first transition pad 611 and the touch lead 252.

[0119] In some examples, the first edge portion 1071 and the second edge portion 1072 of the third planarization layer 107 can be fabricated using a halftone mask process. The halftone mask used in the halftone mask process can include a non-transparent region, a semi-transparent region, and a transmissive region. The transmissive region can correspond at least to the location of the first transition hole, the semi-transparent region can correspond at least to the location of the first edge portion, and the non-transparent region can correspond to the location of the second edge portion. For example, when fabricating the third planarization layer, photoresist can be coated on the planar thin film used to form the third planarization layer. After exposing and developing the photoresist using a halftone mask, a photoresist fully retained region, a photoresist semi-retained region, and a photoresist completely removed region can be formed. The photoresist fully retained region corresponds to the non-transparent region of the halftone mask, the photoresist semi-retained region corresponds to the semi-transparent region of the halftone mask, and the photoresist completely removed region corresponds to the transmissive region of the halftone mask. Subsequently, etching processes can be performed sequentially in the photoresist-completely removed area and the photoresist-partially retained area to form the first transition hole and the first edge portion of the third planarization layer. The photoresist-completely retained area can form the second edge portion of the third planarization layer. The halftone mask process used in the display panel of this example can reduce the slope of the edge side profile of the first transition hole, which is beneficial for the edge planarization of the first transition pad located in the third source / drain metal layer, and can avoid cracks and poor overlap caused by height differences during subsequent film layer stacking.

[0120] Figure 7 is a partially enlarged schematic diagram of region S3 in Figure 4. Figure 8A is a partial cross-sectional schematic diagram along the Q2a-Q2a' direction in Figure 7. Figure 8B is a partial cross-sectional schematic diagram along the Q2b-Q2b' direction in Figure 7. This example uses the film layer structure of the display panel as shown in Figure 2B as an example for illustration. In this example, the first organic insulating layer can be the third planarization layer 107.

[0121] In some examples, as shown in Figures 7, 8A, and 8B, the second adapter pad 612 may be located in the third source / drain metal layer. The second adapter pad 612 can be electrically connected to the touch-sensitive bent connection line 262 located in the second source / drain metal layer via a fourth adapter hole V4 formed in the second planarization layer 106. The orthographic projection of the second adapter pad 612 onto the substrate may overlap with the orthographic projection of the fourth adapter hole V4 onto the substrate. The orthographic projection of the third planarization layer 107 onto the substrate and the orthographic projection of the fourth adapter hole V4 onto the substrate may not overlap.

[0122] In some examples, the orthographic projection of the second adapter pad 612 onto the substrate can be rectangular, such as a square or a rounded rectangle. The second adapter pad 612 may include: a fifth end (e.g., the upper end) close to the bending region B12 along the second direction Y and a sixth end (e.g., the lower end) away from the bending region B12, and a seventh end (e.g., the left end) and an eighth end (e.g., the right end) opposite each other along the first direction X.

[0123] In some examples, the third planarization layer 107 may have a plurality of second transition holes V2, each corresponding to a plurality of second transition pads 612. The second transition holes V2 may expose a portion of the surface of the second transition pads 612 away from the substrate. For example, the orthographic projection of the second transition hole V2 onto the substrate may be rectangular. However, this embodiment is not limited to this. In other examples, the orthographic projection of the second transition hole onto the substrate may be circular or elliptical.

[0124] In some examples, the third planarization layer 107 may include at least partially surrounding a first edge portion 1071 and a second edge portion 1072 surrounding the second transition hole V2. The second edge portion 1072 may be located on the side of the first edge portion 1071 away from the second transition hole V2. The maximum thickness of the first edge portion 1071 may be less than or equal to the minimum thickness of the second edge portion 1072. The maximum thickness of the first edge portion 1071 may be the thickness at the junction of the first edge portion 1071 and the second edge portion 1072, and the minimum thickness of the first edge portion 1071 may be the thickness at the edge closest to the second transition hole V2. The average thickness of the first edge portion 1071 is less than the average thickness of the second edge portion 1072. In some examples, the thickness of the second edge portion 1072 may range from 1.0 micrometer to 2.0 micrometers, for example, from 1.2 micrometers to 1.8 micrometers, and further from 1.5 micrometers to 1.55 micrometers.

[0125] In some examples, the first edge portion 1071 may surround three sides of the second adapter hole V2, and the second edge portion 1072 may surround the periphery of the second adapter hole V2. The second edge portion 1072 may be located outside the first edge portion 1071. For example, the side of the second adapter hole V2 near the bending area B12 (corresponding to the fifth end of the second adapter pad 612) may be surrounded by the second edge portion 1072, and the side of the second adapter hole V2 away from the bending area B12 (corresponding to the sixth end of the second adapter pad 612) and both sides along the first direction X (corresponding to the seventh and eighth ends of the second adapter end 612) may be surrounded by the first edge portion 1071.

[0126] In some examples, the slope angle of the first edge portion 1071 surrounding the second transition hole V2 of the third planarization layer 107 can be less than or equal to 70 degrees, for example, it can be greater than or equal to 10 degrees and less than or equal to 50 degrees. Further, the slope angle can be greater than or equal to 20 degrees and less than or equal to 40 degrees, for example, it can be approximately 30 degrees, 31 degrees, 32 degrees, 33 degrees, 34 degrees, or 35 degrees. The surface of the first edge portion 1071 away from the substrate can be an arc-shaped slope or a flat slope.

[0127] In some examples, the orthographic projection of the first edge portion 1071 of the third planarization layer 107 onto the substrate may overlap with the orthographic projections of the sixth, seventh, and eighth ends of the second transition pad 612 onto the substrate, but may not overlap with the orthographic projection of the fifth end of the second transition pad 612 onto the substrate. Similarly, the orthographic projection of the second edge portion 1072 of the third planarization layer 107 onto the substrate may overlap with the orthographic projections of the seventh and eighth ends of the second transition pad 612 onto the substrate, but may not overlap with the orthographic projections of the fifth and sixth ends of the second transition pad 612 onto the substrate.

[0128] In some examples, along the first direction X, the overlap length between the second edge 1072 of the third planarization layer 107 and one side edge of the second transition pad 612 can be a fourth distance L4, and the overlap length between the first edge 1071 of the third planarization layer 107 and one side edge of the second transition pad 612 can be a fifth distance L5; along the first direction X, the overlap length between the third planarization layer 107 and one side edge of the second transition pad 612 can be the sum of the fourth distance L4 and the fifth distance L5. Along the second direction Y, the overlap length between the first edge 1071 of the third planarization layer 107 and one side edge of the second contact pad 612 can be a sixth distance L6. The sixth distance L6 can be greater than the fifth distance L5, and the fifth distance L5 can be greater than the fourth distance L4. For example, the sum of the fourth distance L4 and the fifth distance L5 can be greater than or equal to 3.5 micrometers. For example, the fifth distance L5 can be greater than or equal to 2.5 micrometers, and the fourth distance L4 can be greater than or equal to 1 micrometer. For example, the fifth distance L5 can be approximately 2.5 micrometers, and the fourth distance L4 can be approximately 1 micrometer.

[0129] In some examples, as shown in Figure 8A, the touch adapter cable 272 can be located in the second touch conductive layer. The touch interlayer insulating layer 502 can be provided with a sixth adapter hole V6, through which the touch adapter cable 272 can connect to the second adapter pad 612 located in the third source / drain metal layer via the sixth adapter hole V6 in the touch interlayer insulating layer 502 and the second adapter hole V2 provided in the third planarization layer 107. The orthographic projection of the sixth adapter hole V6 onto the substrate can be within the orthographic projection range of the second adapter hole V2 onto the substrate. The touch interlayer insulating layer 502 can contact the first edge portion 1071 and the second edge portion 1072 of the third planarization layer 107 surrounding the second adapter hole V2.

[0130] In this example, the first edge portion 1071 and the second edge portion 1072 of the third flat layer 107 are used to cover the edge of the second transition pad 612 located in the third source-drain metal layer. This can prevent cracks from forming at the edge of the third source-drain metal layer when the interlayer insulation layer 502 is directly deposited on the surface of the third source-drain metal layer, which is beneficial to achieving an effective connection between the second transition pad 612 and the touch transition cable 272.

[0131] Figure 9 is another enlarged view of region S3 in Figure 4. Figure 10 is a partial cross-sectional view along the Q3-Q3' direction in Figure 9. This example uses the film layer structure of the display panel as shown in Figure 2A as an example for illustration. In this example, the first organic insulating layer can be the second planarization layer 106.

[0132] In some examples, as shown in Figures 9 and 10, the second adapter pad 612 may be located in the second source / drain metal layer. The second adapter pad 612 and the touch bend connection line 262 located in the second source / drain metal layer may be an integral structure interconnected. The orthographic projection of the second adapter pad 612 onto the substrate may be rectangular, such as a square or a rounded rectangle. The second adapter pad 612 may include: a fifth end (e.g., the upper end) and a sixth end (e.g., the lower end) along the second direction Y near the bend region B12, and a seventh end (e.g., the left end) and an eighth end (e.g., the right end) opposite along the first direction X.

[0133] In some examples, the second planarization layer 106 may have a plurality of second transition holes V2, each corresponding to a plurality of second transition pads 612. The second transition holes V2 may expose a portion of the surface of the second transition pads 612 away from the substrate. For example, the orthographic projection of the second transition hole V2 onto the substrate may be rectangular. However, this embodiment is not limited to this. In other examples, the orthographic projection of the second transition hole onto the substrate may be circular or elliptical.

[0134] In some examples, the second planarization layer 106 may include at least partially surrounding a first edge portion 1061 and a second edge portion 1062 surrounding the second transition hole V2. The second edge portion 1062 may be located on the side of the first edge portion 1061 away from the second transition hole V2. The maximum thickness of the first edge portion 1061 may be less than or equal to the minimum thickness of the second edge portion 1062. The maximum thickness of the first edge portion 1061 may be the thickness at the junction of the first edge portion 1061 and the second edge portion 1062, and the minimum thickness of the first edge portion 1061 may be the thickness at the edge closest to the second transition hole V2. The average thickness of the first edge portion 1061 is less than the average thickness of the second edge portion 1062. In some examples, the thickness of the second edge portion 1062 may range from 1.0 micrometer to 2.0 micrometers, for example, from 1.2 micrometers to 1.8 micrometers, and further from 1.5 micrometers to 1.55 micrometers.

[0135] In some examples, the orthographic projection of the first edge portion 1061 of the second planarization layer 106 onto the substrate may overlap with the orthographic projections of the sixth, seventh, and eighth ends of the second transition pad 612 onto the substrate, but may not overlap with the orthographic projection of the fifth end of the second transition pad 612 onto the substrate. Similarly, the orthographic projection of the second edge portion 1062 of the second planarization layer 106 onto the substrate may overlap with the orthographic projections of the seventh and eighth ends of the second transition pad 612 onto the substrate, but may not overlap with the orthographic projections of the fifth and sixth ends of the second transition pad 612 onto the substrate.

[0136] In some examples, along the first direction X, the overlap length between the second edge 1062 of the second planarization layer 106 and one side edge of the second transition pad 612 can be a fourth distance L4, and the overlap length between the first edge 1061 of the second planarization layer 106 and one side edge of the second transition pad 612 can be a fifth distance L5; along the first direction X, the overlap length between the second planarization layer 106 and one side edge of the second transition pad 612 can be the sum of the fourth distance L4 and the fifth distance L5. Along the second direction Y, the overlap length between the first edge 1061 of the second planarization layer 106 and one side edge of the second contact pad 612 can be a sixth distance L6. The sixth distance L6 can be greater than the fifth distance L5, and the fifth distance L5 can be greater than the fourth distance L4. For example, the sum of the fourth distance L4 and the fifth distance L5 can be greater than or equal to 3.5 micrometers. For example, the fifth distance L5 can be greater than or equal to 2.5 micrometers, and the fourth distance L4 can be greater than or equal to 1 micrometer. For example, the fifth distance L5 can be approximately 2.5 micrometers, and the fourth distance L4 can be approximately 1 micrometer.

[0137] In some examples, the touch adapter cable 272 may be located in the second touch conductive layer. The touch adapter cable 272 can be connected to the second adapter pad 612 located in the second source / drain metal layer through the sixth adapter hole V6 formed in the touch interlayer insulating layer 502 and the second adapter hole V2 formed in the second planarization layer 106. The touch interlayer insulating layer 502 may contact the first edge portion 1061 and the second edge portion 1062 of the second planarization layer 106 surrounding the second adapter hole V2.

[0138] This example uses the first edge portion 1061 and the second edge portion 1062 of the second planarization layer 106 to cover the edge of the second transition pad 612 located in the second source / drain metal layer. This avoids cracking at the edge of the second source / drain metal layer when the interlayer insulating layer 502 is directly deposited on the surface of the second source / drain metal layer, thus facilitating an effective connection between the second transition pad 612 and the touch transition cable 272. Further descriptions of the second planarization layer in this example can be found in the description of the third planarization layer in the foregoing embodiment, and will not be repeated here. The structure of the first transition pad in this example can be found in the structure of the second transition pad, and will not be repeated here.

[0139] Figure 11 is another enlarged view of region S3 in Figure 4. Figure 12 is a partial cross-sectional view along the Q4-Q4' direction in Figure 11. This example uses the film layer structure of the display panel as shown in Figure 2C as an example for illustration. In this example, the first organic insulating layer can be the fourth planarization layer 108.

[0140] In some examples, as shown in Figures 11 and 12, the second adapter pad 612 may be located in the fourth source / drain metal layer. The second adapter pad 612 can be electrically connected to the touch-sensitive bent connection line 262 located in the second source / drain metal layer via a fourth adapter hole V4 formed in the third planarization layer 107 and the second planarization layer 106. The orthographic projection of the second adapter pad 612 onto the substrate may overlap with the orthographic projection of the fourth adapter hole V4 onto the substrate. The orthographic projection of the fourth planarization layer 108 onto the substrate and the orthographic projection of the fourth adapter hole V4 onto the substrate may not overlap.

[0141] In some examples, the orthographic projection of the second adapter pad 612 onto the substrate can be rectangular, such as a square or a rounded rectangle. The second adapter pad 612 may include: a fifth end (e.g., the upper end) close to the bending region B12 along the second direction Y and a sixth end (e.g., the lower end) away from the bending region B12, and a seventh end (e.g., the left end) and an eighth end (e.g., the right end) opposite each other along the first direction X.

[0142] In some examples, the fourth planarization layer 108 may have a plurality of second transition holes V2, each corresponding to a plurality of second transition pads 612. The second transition holes V2 may expose a portion of the surface of the second transition pads 612 away from the substrate. For example, the orthographic projection of the second transition hole V2 onto the substrate may be rectangular. However, this embodiment is not limited to this. In other examples, the orthographic projection of the second transition hole onto the substrate may be circular or elliptical.

[0143] In some examples, the fourth planarization layer 108 may include at least partially surrounding a first edge portion 1081 and a second edge portion 1082 around the second transition hole V2. The second edge portion 1082 may be located on the side of the first edge portion 1081 away from the second transition hole V2. The maximum thickness of the first edge portion 1081 may be less than or equal to the minimum thickness of the second edge portion 1082. The maximum thickness of the first edge portion 1081 may be the thickness at the junction of the first edge portion 1081 and the second edge portion 1082, and the minimum thickness of the first edge portion 1081 may be the thickness at the edge closest to the second transition hole V2. The average thickness of the first edge portion 1081 is less than the average thickness of the second edge portion 1082. In some examples, the thickness of the second edge portion 1082 may range from 1.0 micrometer to 2.0 micrometers, for example, from 1.2 micrometers to 1.8 micrometers, and further from 1.5 micrometers to 1.55 micrometers.

[0144] In some examples, the orthographic projection of the first edge portion 1081 of the fourth planarization layer 108 onto the substrate may overlap with the orthographic projections of the sixth, seventh, and eighth ends of the second transition pad 612 onto the substrate, but may not overlap with the orthographic projection of the fifth end of the second transition pad 612 onto the substrate. Similarly, the orthographic projection of the second edge portion 1082 of the fourth planarization layer 108 onto the substrate may overlap with the orthographic projections of the seventh and eighth ends of the second transition pad 612 onto the substrate, but may not overlap with the orthographic projections of the fifth and sixth ends of the second transition pad 612 onto the substrate.

[0145] In some examples, along the first direction X, the overlap length between the second edge 1082 of the fourth planarization layer 108 and one side edge of the second transition pad 612 can be a fourth distance L4, and the overlap length between the first edge 1081 of the fourth planarization layer 108 and one side edge of the second transition pad 612 can be a fifth distance L5; along the first direction X, the overlap length between the fourth planarization layer 108 and one side edge of the second transition pad 612 can be the sum of the fourth distance L4 and the fifth distance L5. Along the second direction Y, the overlap length between the first edge 1081 of the fourth planarization layer 108 and one side edge of the second contact pad 612 can be a sixth distance L6. The sixth distance L6 can be greater than the fifth distance L5, and the fifth distance L5 can be greater than the fourth distance L4. For example, the sum of the fourth distance L4 and the fifth distance L5 can be greater than or equal to 3.5 micrometers. For example, the fifth distance L5 can be greater than or equal to 2.5 micrometers, and the fourth distance L4 can be greater than or equal to 1 micrometer. For example, the fifth distance L5 can be approximately 2.5 micrometers, and the fourth distance L4 can be approximately 1 micrometer.

[0146] In some examples, the touch adapter cable 272 may be located in the second touch conductive layer. The touch adapter cable 272 can be connected to the second adapter pad 612 located in the fourth source / drain metal layer through the sixth adapter hole V6 opened in the touch interlayer insulating layer 502 and the second adapter hole V2 opened in the fourth planarization layer 108. The touch interlayer insulating layer 502 may contact the first edge portion 1081 and the second edge portion 1082 of the fourth planarization layer 108 surrounding the second adapter hole V2.

[0147] This example uses the first edge portion 1081 and the second edge portion 1082 of the fourth planarization layer 108 to cover the edge of the second transition pad 612 located in the fourth source-drain metal layer. This avoids cracks at the edge of the fourth source-drain metal layer when the interlayer insulating layer 502 is directly deposited on the surface of the fourth source-drain metal layer, which is beneficial for achieving an effective connection between the second transition pad 612 and the touch transition cable 272. Further descriptions of the fourth planarization layer in this example can be found in the description of the third planarization layer in the aforementioned embodiment, and will not be repeated here. The structure of the first transition pad in this example can be found in the structure of the second transition pad, and will not be repeated here.

[0148] Figure 13 is another partially enlarged schematic diagram of region S3 in Figure 4. Figure 14 is a partial cross-sectional schematic diagram along the Q5-Q5' direction in Figure 13. In this example, the display structure layer of the display panel may include at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer 106, a third source / drain metal layer, a third planarization layer 107, and a fourth planarization layer 108 sequentially disposed on the substrate. The first organic insulating layer in this example may include the fourth planarization layer 108.

[0149] In some examples, as shown in Figures 13 and 14, the second adapter pad 612 may be located in the third source / drain metal layer. The second adapter pad 612 can be electrically connected to the touch-sensitive bent connection line 262 located in the second source / drain metal layer via a fourth adapter hole V4 formed in the second planarization layer 106. The third planarization layer 107 may have a seventh adapter hole V7 exposing a portion of the surface of the second adapter pad 612 away from the substrate. The fourth planarization layer 108 may have a second adapter hole V2 exposing a portion of the surface of the second adapter pad 612 away from the substrate. The second adapter hole V2 communicates with the seventh adapter hole V7. For example, the orthographic projection of the second adapter hole V2 onto the substrate may overlap the orthographic projection of the seventh adapter hole V7 onto the substrate.

[0150] In some examples, the fourth planarization layer 108 may include at least partially surrounding a first edge portion 1081 and a second edge portion 1082 around the second transition hole V2. The second edge portion 1082 may be located on the side of the first edge portion 1081 away from the second transition hole V2. The maximum thickness of the first edge portion 1081 may be less than or equal to the minimum thickness of the second edge portion 1082. The maximum thickness of the first edge portion 1081 may be the thickness at the junction of the first edge portion 1081 and the second edge portion 1082, and the minimum thickness of the first edge portion 1081 may be the thickness at the edge closest to the second transition hole V2. The average thickness of the first edge portion 1081 is less than the average thickness of the second edge portion 1082.

[0151] In some examples, along the first direction X, the overlap length between the second edge 1082 of the fourth planarization layer 108 and one side edge of the second transition pad 612 can be a fourth distance L4, and the overlap length between the first edge 1081 of the fourth planarization layer 108 and one side edge of the second transition pad 612 can be a fifth distance L5; along the first direction X, the overlap length between the fourth planarization layer 108 and one side edge of the second transition pad 612 can be the sum of the fourth distance L4 and the fifth distance L5. Along the second direction Y, the overlap length between the first edge 1081 of the fourth planarization layer 108 and one side edge of the second contact pad 612 can be a sixth distance L6. The sixth distance L6 can be greater than the fifth distance L5, and the fifth distance L5 can be greater than the fourth distance L4. For example, the sum of the fourth distance L4 and the fifth distance L5 can be greater than or equal to 3.5 micrometers. For example, the fifth distance L5 can be greater than or equal to 2.5 micrometers, and the fourth distance L4 can be greater than or equal to 1 micrometer. For example, the fifth distance L5 can be approximately 2.5 micrometers, and the fourth distance L4 can be approximately 1 micrometer.

[0152] In some examples, the touch adapter cable 272 may be located in the second touch conductive layer. The touch adapter cable 272 may be connected to the second adapter pad 612 located in the third source / drain metal layer through the sixth adapter hole V6 formed in the touch interlayer insulating layer 502, the second adapter hole V2 provided in the fourth planarization layer 108, and the seventh adapter hole V7 provided in the third planarization layer 107. The touch interlayer insulating layer 502 may contact the first edge portion 1081 and the second edge portion 1082 of the fourth planarization layer 108 surrounding the second adapter hole V2.

[0153] This example uses the first edge portion 1081 and the second edge portion 1082 of the fourth planarization layer 108 to cover the edge of the second transition pad 612 located in the third source-drain metal layer. This avoids cracks at the edge of the third source-drain metal layer when the interlayer insulating layer 502 is directly deposited on the surface of the third source-drain metal layer, which is beneficial for achieving an effective connection between the second transition pad 612 and the touch transition cable 272. Further descriptions of the fourth planarization layer in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here. The structure of the first transition pad in this example can be found in the structure of the second transition pad, and will not be repeated here.

[0154] The display panel provided in this embodiment can improve the situation of cracks caused by height differences, metal layer deformation, or poor overlap caused by wire breaks during multi-layer transitions, while ensuring the overlap effect of the film layers, without increasing costs. Furthermore, it can reduce the differences between multiple transition holes, reducing regional variations and improving the reliability at the transition holes. In some examples, for high-resolution (PPI) display products and display panels that use jumpers to lead out data signals in the display area, sufficient edge wrapping of the transition pads can facilitate the rational distribution of signal lines in the bending area.

[0155] Figure 15 is a partial structural schematic diagram of the first wiring area according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 15, the first wiring area B11 may be provided with a first isolation dam DAM1 and a second isolation dam DAM2 extending along the first direction X. The first isolation dam DAM1 may be located on the side of the second isolation dam DAM2 closer to the display area AA. In the first wiring area B11, the orthographic projection of the pixel definition layer on the substrate and the orthographic projection of the plurality of first transition pads 611 on the substrate may not overlap. In the second wiring area, the orthographic projection of the pixel definition layer on the substrate and the orthographic projection of the plurality of second transition pads on the substrate may not overlap. In this example, by removing the pixel definition layer disposed on the side of the transition pads away from the substrate, it is possible to avoid wiring breakage when the touch conductive layer is deposited on the surface of the pixel definition layer at the transition hole location, and to avoid film peeling when the interlayer insulating layer is deposited on the surface of the pixel definition layer at the transition hole location.

[0156] In some examples, the first isolation dam DAM1 and the second isolation dam DAM2 can be formed by stacking multiple dam bases. For example, taking the display film layer shown in Figure 2B as an example, the first isolation dam DAM1 may include: a dam base in the same layer as the second planarization layer, a dam base in the same layer as the third planarization layer, and a dam base in the same layer as the pixel definition layer; the second isolation dam DAM2 may include: a dam base in the same layer as the first planarization layer, a dam base in the same layer as the second planarization layer, a dam base in the same layer as the third planarization layer, and a dam base in the same layer as the pixel definition layer. This embodiment is not limited in this respect.

[0157] In some examples, as shown in Figure 15, the first trace area B11 may include a first pixel definition cutout area 701 and a second pixel definition cutout area 702. The pixel definition layer does not overlap with the orthographic projection of the first pixel definition cutout area 701 and the second pixel definition cutout area 702 onto the substrate; in other words, the pixel definition layer within the first pixel definition cutout area 701 and the second pixel definition cutout area 702 is cut out. The first pixel definition cutout area 701 and the second pixel definition cutout area 702 are connected. The length of the first pixel definition cutout area 701 along the first direction X may be greater than the length of the second pixel definition cutout area 702 along the first direction X. The second pixel definition cutout area 702 may be located on the side of the first pixel definition cutout area 701 near the bending area B12. The orthographic projection of the second pixel definition cutout area 702 onto the substrate may cover the orthographic projection of multiple first adapter pads 611 onto the substrate. The boundary of the first pixel definition cutout area 701 near the display area AA may coincide with the edge of the second isolation dam DAM2 away from the display area AA.

[0158] This example reduces the risk of peeling and wire breakage of the film layer above the first adapter pad and in the area near the second isolation dam by removing the pixel definition layer above the first adapter pad.

[0159] This embodiment also provides a method for fabricating a display panel, comprising: fabricating a display structure layer on one side of a substrate, the display structure layer including a plurality of display metal layers, wherein the display metal layer furthest from the substrate includes a plurality of transition pads; fabricating a first organic insulating layer on the side of the plurality of transition pads furthest from the substrate, the first organic insulating layer having a plurality of transition holes corresponding to the plurality of transition pads, the plurality of transition holes being configured to expose a portion of the corresponding transition pad surface facing away from the substrate; the first organic insulating layer including a first edge portion and a second edge portion at least partially surrounding the transition holes, the second edge portion being located on the side of the first edge portion furthest from the transition holes, the maximum thickness of the first edge portion being less than or equal to the minimum thickness of the second edge portion, and the first edge portion covering at least a portion of the edge of the corresponding transition pad exposed by the transition hole.

[0160] In some exemplary embodiments, the fabrication of the first organic insulating layer includes forming the plurality of transition holes, a first edge portion, and a second edge portion of the first organic insulating layer using a semi-mask process. In this example, the first organic insulating layer fabricated using the semi-mask process can effectively cover the edges of the transition pad, thereby reducing the slope angle of the first organic insulating layer at the transition holes. This helps to reduce the height difference at the transition holes and mitigates the risk of peeling and wiring breakage of the film layer above the transition pad.

[0161] The method for manufacturing the display panel in this example can be referred to the description of the foregoing embodiments, and therefore will not be repeated here.

[0162] This embodiment also provides a display panel, including: a substrate and a display structure layer located on one side of the substrate. The display structure layer includes a plurality of display metal layers and a pixel definition layer located on the side of the plurality of display metal layers away from the substrate. The display structure layer farthest from the substrate among the plurality of display metal layers includes a plurality of transition pads; the orthographic projection of the pixel definition layer on the substrate and the orthographic projection of the plurality of transition pads on the substrate do not overlap.

[0163] This embodiment removes the pixel definition layer located on the side of the adapter pad away from the substrate, which can prevent the touch conductive layer from being deposited on the surface of the pixel definition layer at the adapter hole location, thus avoiding the situation of trace breakage, and also avoids the situation of film peeling caused by the interlayer insulating layer being deposited on the surface of the pixel definition layer at the adapter hole location.

[0164] In some exemplary embodiments, the substrate includes: a display area and a first border area located on one side of the display area along a second direction. The first border area includes: a first trace area, a bending area, and a second trace area sequentially disposed along a direction away from the display area. The plurality of transition pads include: a plurality of first transition pads located in the first trace area and a plurality of second transition pads located in the second trace area. The first trace area is provided with a first isolation dam and a second isolation dam extending along a first direction. The first isolation dam is located on the side of the second isolation dam closer to the display area; the first direction intersects the second direction. The first trace area includes: a first pixel definition cutout area and a second pixel definition cutout area. The pixel definition layer does not overlap with the orthographic projection of the first pixel definition cutout area and the second pixel definition cutout area on the substrate. The first pixel definition cutout area and the second pixel definition cutout area are connected. The length of the first pixel definition cutout area along the first direction is greater than the length of the second pixel definition cutout area along the first direction. The orthographic projection of the second pixel definition cutout area on the substrate covers the orthographic projection of the plurality of first transition pads on the substrate. The first pixel definition cutout area is located on the side of the second isolation dam away from the display area.

[0165] In some exemplary embodiments, the display panel further includes: a touch structure layer located on the side of the display structure layer away from the substrate, the touch structure layer including at least one touch conductive layer; the at least one touch conductive layer including: a touch lead located in the first wiring area and a touch adapter line located in the second wiring area. The touch lead is connected to the first adapter pad, and the touch adapter line is connected to the second adapter pad. In some examples, the touch structure layer includes: a first touch conductive layer and a second touch conductive layer disposed along a direction away from the substrate, the touch lead and the touch adapter line being located in the second touch conductive layer.

[0166] Further descriptions of the display panel in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0167] Figure 16 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 16, the display panel 910 can be an OLED display panel. The display device 91 can be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited thereto.

[0168] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0169] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, comprising: Substrate; The display structure layer, located on one side of the substrate, includes multiple display metal layers, wherein the display metal layer furthest from the substrate includes multiple transition pads; A first organic insulating layer is located on the side of the plurality of transition pads away from the substrate, and is provided with a plurality of transition holes corresponding to the plurality of transition pads, the plurality of transition holes being configured to expose the portion of the corresponding transition pad surface facing away from the substrate; The first organic insulating layer includes at least a first edge portion and a second edge portion surrounding the adapter hole, the second edge portion being located on the side of the first edge portion away from the adapter hole, the maximum thickness of the first edge portion being less than or equal to the minimum thickness of the second edge portion, and the first edge portion covering at least a portion of the edge of the corresponding adapter pad exposed by the adapter hole.

2. The display panel according to claim 1, wherein, The overlap length between the first organic insulating layer and one side edge of the transition pad is greater than or equal to 3.5 micrometers.

3. The display panel according to claim 1, wherein, The overlap length between the first edge of the first organic insulating layer and one side edge of the adapter pad is greater than or equal to 2.5 micrometers, and the overlap length between the second edge of the first organic insulating layer and one side edge of the adapter pad is greater than or equal to 1 micrometer.

4. The display panel according to any one of claims 1 to 3, wherein, The substrate includes: a display area and a first border area located on one side of the display area along a second direction, the first border area including: a first trace area, a bending area and a second trace area arranged sequentially along a direction away from the display area; the plurality of transition pads include: a plurality of first transition pads located in the first trace area and a plurality of second transition pads located in the second trace area.

5. The display panel according to claim 4, further comprising: A touch structure layer located on the side of the display structure layer away from the substrate, the touch structure layer including at least one touch conductive layer; The at least one touch conductive layer includes: a touch lead located in the first wiring area and a touch adapter located in the second wiring area; The touch lead is connected to the first adapter pad, and the touch adapter cable is connected to the second adapter pad.

6. The display panel according to claim 4, wherein, The first adapter pad includes: a first end near the bending area and a second end away from the bending area along the second direction, and a third end and a fourth end opposite each other along the first direction; the first direction intersects the second direction; The first edge of the first organic insulating layer does not overlap with the orthographic projection of the first end of the first adapter pad onto the substrate. The first edge of the first organic insulating layer overlaps with the orthographic projections of the second, third, and fourth ends of the first adapter pad on the substrate.

7. The display panel according to claim 4, wherein, The second adapter pad includes: a fifth end near the bending area along the second direction and a sixth end away from the bending area, and a seventh end and an eighth end opposite each other along the first direction, the first direction intersecting the second direction; The first edge of the first organic insulating layer does not overlap with the orthographic projection of the fifth end of the second adapter pad on the substrate, but overlaps with the orthographic projections of the sixth, seventh, and eighth ends of the second adapter pad on the substrate.

8. The display panel according to claim 4, wherein, The display structure layer further includes a pixel definition layer located on the side of the plurality of display metal layers away from the substrate; the orthographic projection of the pixel definition layer on the substrate does not overlap with the orthographic projection of the plurality of transition pads on the substrate.

9. The display panel according to claim 8, wherein, The first wiring area is provided with a first isolation barrier and a second isolation barrier extending along a first direction, with the first isolation barrier located on the side of the second isolation barrier closer to the display area; The first trace area includes: a first pixel definition cutout area and a second pixel definition cutout area. The pixel definition layer does not overlap with the orthographic projection of the first pixel definition cutout area and the second pixel definition cutout area on the substrate. The first pixel definition cutout area and the second pixel definition cutout area are connected. The length of the first pixel definition cutout area along the first direction is greater than the length of the second pixel definition cutout area along the first direction. The orthographic projection of the second pixel definition cutout area on the substrate covers the orthographic projection of the plurality of first transition pads on the substrate. The first pixel definition cutout area is located on the side of the second isolation dam away from the display area. The first direction intersects the second direction.

10. The display panel according to any one of claims 1 to 9, wherein, The display structure layer includes at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, and a second planarization layer disposed on the substrate; the plurality of transition pads are located on the second source / drain metal layer, and the first organic insulating layer includes the second planarization layer.

11. The display panel according to any one of claims 1 to 9, wherein, The display structure layer includes at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a third source / drain metal layer, and a third planarization layer disposed on the substrate; the plurality of transition pads are located on the third source / drain metal layer, and the first organic insulating layer includes the third planarization layer.

12. The display panel according to any one of claims 1 to 9, wherein, The display structure layer includes at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a third source / drain metal layer, a third planarization layer, a fourth source / drain metal layer, and a fourth planarization layer disposed on the substrate; the plurality of transition pads are located on the fourth source / drain metal layer, and the first organic insulating layer includes the fourth planarization layer.

13. The display panel according to any one of claims 1 to 9, wherein, The display structure layer includes at least: a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, a second planarization layer, a third source / drain metal layer, a third planarization layer, and a fourth planarization layer disposed on the substrate; the plurality of transition pads are located on the third source / drain metal layer, and the first organic insulating layer includes the fourth planarization layer.

14. A display device comprising a display panel as claimed in any one of claims 1 to 13.

15. A method for manufacturing a display panel, comprising: A display structure layer is fabricated on one side of a substrate. The display structure layer includes multiple display metal layers, and the display metal layer furthest from the substrate includes multiple transition pads. A first organic insulating layer is prepared on the side of the plurality of transition pads away from the substrate. The first organic insulating layer is provided with a plurality of transition holes corresponding to the plurality of transition pads. The plurality of transition holes are configured to expose the portion of the corresponding transition pad surface away from the substrate. The first organic insulating layer includes at least a first edge portion and a second edge portion surrounding the adapter hole, the second edge portion being located on the side of the first edge portion away from the adapter hole, the maximum thickness of the first edge portion being less than or equal to the minimum thickness of the second edge portion, and the first edge portion covering at least a portion of the edge of the corresponding adapter pad exposed by the adapter hole.

16. The preparation method according to claim 15, wherein, The preparation of the first organic insulating layer includes: forming the plurality of transition holes, the first edge portion and the second edge portion of the first organic insulating layer using a semi-mask process.

17. A display panel, comprising: Substrate; The display structure layer, located on one side of the substrate, includes multiple display metal layers and layers located on the multiple display metal layers. The pixel definition layer on the side of the display metal layer away from the substrate, and the display structure layer that is furthest from the substrate among the plurality of display metal layers includes a plurality of transition pads; The orthographic projection of the pixel definition layer onto the substrate does not overlap with the orthographic projection of the plurality of transition pads onto the substrate.

18. The display panel according to claim 17, wherein, The substrate includes: a display area and a first border area located on one side of the display area along a second direction, wherein the first border area includes: a first trace area, a bending area and a second trace area sequentially arranged along a direction away from the display area; The plurality of transition pads include: a plurality of first transition pads located in the first wiring area and a plurality of second transition pads located in the second wiring area; The first wiring area is provided with a first isolation barrier and a second isolation barrier extending along a first direction, the first isolation barrier being located on the side of the second isolation barrier closer to the display area; the first direction intersects the second direction; The first trace area includes: a first pixel definition cutout area and a second pixel definition cutout area. The pixel definition layer does not overlap with the orthographic projection of the first pixel definition cutout area and the second pixel definition cutout area on the substrate. The first pixel definition cutout area and the second pixel definition cutout area are connected. The length of the first pixel definition cutout area along the first direction is greater than the length of the second pixel definition cutout area along the first direction. The orthographic projection of the second pixel definition cutout area on the substrate covers the orthographic projection of the plurality of first transition pads on the substrate. The first pixel definition cutout area is located on the side of the second isolation dam away from the display area.

19. The display panel according to claim 18, further comprising: A touch structure layer located on the side of the display structure layer away from the substrate, the touch structure layer including at least one touch conductive layer; The at least one touch conductive layer includes: a touch lead located in the first wiring area and a touch adapter located in the second wiring area; The touch lead is connected to the first adapter pad, and the touch adapter cable is connected to the second adapter pad.

20. The display panel according to claim 19, wherein, The touch structure layer includes: a first touch conductive layer and a second touch conductive layer disposed along a direction away from the substrate, wherein the touch lead and the touch adapter are located in the second touch conductive layer.

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