Chip testing method and system, computer equipment and storage medium

Abstract

The invention is suitable for the field of chip testing, and provides a chip testing method and system, computer equipment and a storage medium, and the method comprises the steps: executing testing processing under the condition that a probe in a probe card is not in contact with a chip on a wafer according to a chip testing item, and obtaining a first testing result of each station in the probe card, and the probe card is used for detecting the electrical contact of the chip on the wafer, recording the electrical contact of the chip on the wafer in the memory, executing test processing under the condition that the probe in the probe card is in contact with the chip on the wafer to obtain a second test result of each station, and correcting the second test result of the corresponding station based on the first test result to obtain an electrical contact test result of the chip on the wafer. According to the scheme, error correction can be carried out on chip testing.

Description

Technical Field

[0001] This application belongs to the field of chip testing, and in particular relates to a chip testing method, system, computer equipment and storage medium. Background Technology

[0002] Probe cards are key consumables and interface components in semiconductor wafer testing. Their core function is to perform electrical performance testing and functional verification on individual chips (dies) that have not yet been cut and packaged (i.e., are still in the wafer stage) during the chip manufacturing process.

[0003] Probe cards typically have multiple testing stations. During chip production testing, differences in test items at multiple stations may occasionally occur. If these differences in hardware testing stations are not detected and corrected, they will lead to false positives, affecting the testing results and increasing the chip defect rate, thus failing to meet chip testing requirements. Summary of the Invention

[0004] This application provides a chip testing method, system, computer equipment, and storage medium to address the problem that failure to detect and correct differences in hardware testing stations during chip production testing can lead to false positives.

[0005] A first aspect of this application provides a chip testing method applied to a chip testing system, the chip testing system comprising: Probe cards are used to perform electrical contact tests with chips on a wafer; Memory, used to store the test results of chip test items; The method includes: According to the chip test items, the test process is performed without the probes in the probe card contacting the chip on the wafer, and the first test result of each station in the probe card is obtained and recorded in the memory; According to the chip test items, the test process is performed when the probes in the probe card are in contact with the chip on the wafer to obtain the second test results of each of the workstations; Based on the first test result, the second test result of the corresponding workstation is corrected to obtain the electrical contact test result of the chip on the wafer.

[0006] The step of correcting the second test result at the corresponding workstation based on the first test result to obtain the electrical contact test result of the chip on the wafer includes: The electrical contact test results of the chips on the wafer are obtained by calculating the average value of the chip test item value of each station in the second test result and the chip test item value of the corresponding station in the first test result.

[0007] Optionally, the step of performing test processing according to the chip test items without the probes in the probe card contacting the chip on the wafer, to obtain the first test result for each station in the probe card, includes: Without the probes in the probe card contacting the chips on the wafer, a set number of cyclic tests are performed on the chip test items to obtain the first test result for each of the workstations in each test.

[0008] Optionally, the chip test items include dark current test items.

[0009] Optionally, the chip testing system further includes: A light source, located in the middle of the probe card, is used to emit light of different wavelengths onto the wafer; A light source sub-board is arranged on the probe card; An adapter board is connected to the light source sub-board, and the light source is electrically connected to the light source sub-board through the adapter board; According to the chip test items, the test process is performed when the probes in the probe card are not in contact with the chip on the wafer, and during the test process when the probes in the probe card are in contact with the chip on the wafer, the light source is controlled to emit light of the target wavelength toward the wafer.

[0010] Optionally, the light source sub-plate includes: A first light source sub-plate and a second light source sub-plate are arranged at relative positions on the probe card; The adapter plate is connected to the first light source sub-plate, and the light source is electrically connected to the first light source sub-plate through the adapter plate.

[0011] A second aspect of this application provides a chip testing system, including: Probe cards are used to perform electrical contact tests with chips on a wafer; Memory, used to store the test results of chip test items; The system also includes: The first test module is used to perform test processing according to the chip test items, without the probes in the probe card contacting the chip on the wafer, to obtain the first test result of each station in the probe card, and record it in the memory; The second test module is used to perform test processing according to the chip test items, when the probe in the probe card contacts the chip on the wafer, and to obtain the second test results of each of the workstations. The test correction module is used to correct the second test result of the corresponding workstation based on the first test result to obtain the electrical contact test result of the chip on the wafer.

[0012] Optionally, the test calibration module is specifically used for: The electrical contact test results of the chips on the wafer are obtained by calculating the average value of the chip test item value of each station in the second test result and the chip test item value of the corresponding station in the first test result.

[0013] A third aspect of this application provides a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method described in the first aspect.

[0014] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0015] A fifth aspect of this application provides a computer program product that, when run on a control device of a self-moving device, causes the control device of the self-moving device to perform the steps of the method described in the first aspect.

[0016] As can be seen from the above, in this embodiment of the application, the probe hardware test items are detected before chip testing. Based on this, error correction is performed on chip testing, which can promptly detect and correct defective products caused by differences in hardware testing stations and reduce the chip defect rate. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the chip testing system provided in an embodiment of this application; Figure 2 This is a flowchart of a chip testing method provided in an embodiment of this application; Figure 3 This is a schematic diagram of a chip testing system provided in an embodiment of this application; Figure 4 This is a structural diagram of the computer device provided in the embodiments of this application. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0021] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrases "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0024] In specific implementations, the devices / equipment described in the embodiments of this application include, but are not limited to, floor scrubbers, mops, etc., which have touch-sensitive surfaces (e.g., touch screen displays and / or touch panels).

[0025] Various applications that can run on a device / app can use at least one common physical user interface device, such as a touch-sensitive surface. One or more functions of the touch-sensitive surface and the corresponding information displayed on the device / app can be adjusted and / or changed between and / or within applications. In this way, the common physical architecture of the device / app (e.g., the touch-sensitive surface) can support various applications with user interfaces that are intuitive and transparent to the user.

[0026] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0027] In semiconductor wafer testing, probe cards act as a precision interface between the wafer and the chips on it. A single probe card typically contains multiple test sites, allowing for the simultaneous testing of multiple chips to improve efficiency. However, in actual testing, it has been found that even a perfectly good wafer can exhibit systematic deviations in test results across different sites.

[0028] For example, the dark current value measured at station 1 is always a few pA higher than that at station 2. This difference does not originate from the chip itself, but is caused by a slight multi-site variation inherent in the probe card hardware system, for example: Minor differences in cable length and shielding effectiveness across channels; The parasitic parameters of the probe pins at different workstations are not completely consistent; Performance tolerances of electronic components in each channel within the system components.

[0029] These hardware differences can be superimposed on the actual chip signals, leading to distorted test results.

[0030] In some cases, these discrepancies may misclassify a perfectly good chip as a defective one (because the measured value is out of tolerance) or mask the true chip defect, thus seriously affecting the accuracy of testing and yield statistics.

[0031] To address the aforementioned problems, embodiments of this application provide a chip testing method. This method is applied to a chip testing system.

[0032] Combination Figure 1 As shown, the chip testing system includes: Probe cards are used to perform electrical contact tests with chips on a wafer; Memory, used to store the test results of chip test items.

[0033] The memory, for example, is an EEPROM (Electrically Erasable Programmable Read-Only Memory). The memory can record the test result data of the target test items obtained by each test station of the probe card during cyclic testing.

[0034] Optionally, combined Figure 1 As shown, the chip testing system may include: a tester connected to a probe card.

[0035] In this embodiment of the application, the chip testing method can be executed in a tester, or the tester or a specific processing module can be integrated into a probe card, and the chip testing method is executed in the probe card.

[0036] Optionally, the target test item is the test item that produces hardware differences during chip testing. This target test item can be preset by the user, or it can be obtained by manually recording test items that produce hardware differences during chip testing.

[0037] In some cases, combined Figure 1 As shown, the chip testing system may also include: The light source, located in the middle of the probe card, is used to emit light of different wavelengths onto the wafer; The light source sub-board is mounted on the probe card; The adapter board connects to the light source sub-board, and the light source is electrically connected to the light source sub-board through the adapter board.

[0038] Since the light source needs to be integrated on the probe card, a special sub-board is required to fix and connect the light source. Through the light source sub-board and the adapter board, the light source is precisely integrated onto the probe card to ensure effective optical testing.

[0039] In order to achieve the test calibration given in the embodiments of this application, the probe card itself has undergone design changes, such as reserving a position and interface for installing the light source sub-board.

[0040] Optionally, the light source can adjust the type and intensity of emitted light according to the test requirements to adapt to the test scenarios of wafers of different specifications, thereby realizing the calibration process of introducing optical stimulation into the electrical performance test of the chip.

[0041] In this embodiment, the memory is changed from a conventional memory that only stores management information such as the ID, model, and number of times the probe card is used, to a memory that can be used to store deviation test data measured in real time at each station of the probe card, giving it a new purpose.

[0042] The memory can be integrated on the adapter board, allowing for the local, fast, and reliable storage and retrieval of large amounts of calibration data at each workstation.

[0043] In this embodiment, the adapter board changes the conventional adapter board's function of simply routing and converting signals. By integrating a light source and a memory for storing test data required for calibration, the adapter board is given a new chip test error correction function.

[0044] In some cases, the light source sub-board may include a first light source sub-board and a second light source sub-board arranged at opposite positions on the probe card. Figure 1The diagram shows a first light source sub-board, designated A, and a second light source sub-board, designated B. Each light source sub-board also includes an adapter board connected to the first light source sub-board, through which the light source is electrically connected.

[0045] The aforementioned hardware system platform effectively supports and executes both non-contact cyclic testing and contact formal testing. By comparing the test results of the two modes, contact and non-contact, a calibration effect is achieved, realizing hardware correction in the chip testing system.

[0046] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0047] See Figure 2 , Figure 2 This is a flowchart of a chip testing method provided in an embodiment of this application. Figure 2 As shown, a chip testing method includes the following steps: Step 201: According to the chip test items, perform the test process without the probes in the probe card contacting the chips on the wafer, obtain the first test result of each station in the probe card, and record it in the memory.

[0048] This test step does not test the performance of the chip itself, but rather the deviation test of the chip testing system's own "basic noise" or "hardware deviation." These "hardware deviations" may include: Line noise: Electrical noise introduced by wires and connectors in the test path; Temperature drift: Minor signal changes caused by system preheating or uneven heating; Power supply noise: Minor fluctuations inherent in the power supply system; Light source fluctuations: Minor inconsistencies in the brightness of LEDs or other light sources; Inherent differences between channels in the probe card: Minor performance inconsistencies inherent in amplifiers, switches, and other components in different channels, etc.

[0049] In some implementations, step 201, according to the chip test items, performs test processing without the probes in the probe card contacting the chip on the wafer, obtaining the first test result for each station in the probe card, including: Without the probes in the probe card contacting the chips on the wafer, a set number of cyclic tests are performed on the chip test items to obtain the first test result of each station in each test.

[0050] This step allows for multiple cyclic tests to be performed without the probes contacting the wafer DIE, recording the test results of each station into the EEPROM memory.

[0051] For example, the number of loop tests is 100.

[0052] Optionally, the number of cyclic tests can be adjusted according to the actual test accuracy requirements, and the adjustment range shall not be less than 10 times. Cyclic testing can effectively eliminate random noise (such as cosmic rays and sporadic electronic interference) and capture stable, repeatable inherent deviations of the system. For example, by averaging multiple measurements (or using other algorithms), an accurate test result that represents the inherent deviation of each workstation can be obtained.

[0053] In an optional implementation, the wafer platform is raised, but the height is controlled to maintain a small distance (e.g., 10 μm) between the probe tip and the wafer surface, ensuring no electrical contact. In this state, the test system simulates a real test process, performing multiple (e.g., 100) cyclic tests. The signals measured at this time are purely system noise and bias. For example, a "dark current floor" value is measured at each station. This data is recorded in real-time in the EEPROM memory.

[0054] Step 202: According to the chip test items, perform test processing when the probes in the probe card are in contact with the chips on the wafer to obtain the second test results of each station.

[0055] Optionally, during the test execution of steps 201 and 202, the test parameters used in the chip test items are the same.

[0056] In an optional implementation, the wafer platform continues to rise, allowing the probes to make normal contact with the chip pads for standard electrical performance tests (such as dark current testing). At this point, the tester obtains a mixed signal, specifically a superposition of the chip's actual signal and the system hardware deviation signal.

[0057] Step 203: Based on the first test result, the second test result of the corresponding workstation is corrected to obtain the electrical contact test result of the chip on the wafer.

[0058] The calibration algorithm can be customized and optimized according to the characteristics of different chip test items to ensure the accuracy of the correction of the differences in the workstations of each chip test item.

[0059] The processor inside the system calls the test results stored in step 201 and uses an algorithm (such as (contact test value + non-contact test value) / 2; or the variance of each contact test value and non-contact test value) to remove the inherent hardware deviations of the system from the mixed signal, so as to obtain more realistic and accurate chip performance data, thereby greatly reducing misjudgments caused by hardware differences.

[0060] In an optional implementation, step 203, based on the first test result, corrects the second test result of the corresponding workstation to obtain the electrical contact test result of the chip on the wafer, including: The electrical contact test results of the chips on the wafer are obtained by calculating the average value of the chip test item values ​​at each station in the second test results and the corresponding chip test item values ​​in the first test results.

[0061] Optionally, the chip test items include dark current test items.

[0062] When the test item is dark current, step 201 specifically involves performing a set number of cyclic tests while the probes of the probe card are not in contact with the chips in the wafer, and recording the values ​​of each station in each dark current test item to the memory; step 202 specifically includes retrieving the dark current test item value of each station recorded in the memory, adding it to the dark current test value of the corresponding station obtained from the current probe contact test of the chip in the wafer, calculating the dark current reference value of each station, and dividing the dark current reference value of each station by 2 to obtain the corrected dark current test value of each station.

[0063] In an optional embodiment, when the chip testing system further includes a light source, a light source sub-board, and an adapter board, the light source is connected to the probe card and the probe card is connected to the tester during the execution process.

[0064] Optionally, depending on the chip test item, during the test process performed when the probes in the probe card are not in contact with the chip on the wafer, and during the test process performed when the probes in the probe card are in contact with the chip on the wafer, it is necessary to control the light source to emit light of the target wavelength onto the wafer.

[0065] The light source can adjust the type and intensity of emitted light according to testing requirements to adapt to testing scenarios for wafers of different specifications.

[0066] In one embodiment, by controlling the light source to emit light of the target wavelength onto the wafer, a dark field environment completely consistent with real chip testing (e.g., dark current testing) can be provided for the testing process when the probes in the probe card do not contact the chips on the wafer. This ensures that the system deviation is effectively excited during the non-contact detection stage, which serves as the actual deviation in the formal chip testing when the probes in the probe card contact the chips on the wafer, so as to effectively correct the deviation and ensure the test simulation and deviation correction effect in the system.

[0067] The embodiments provided in this application completely solve this problem by introducing a "dry test" (i.e., testing without touching the chip) process into the system self-test phase before formal testing of the chip.

[0068] Before chip testing, the probe hardware test items are checked. Based on this, error correction is performed on the formal chip testing. This can promptly detect and correct defective products caused by differences in hardware testing stations, thereby reducing the chip defect rate.

[0069] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0070] Furthermore, in the above embodiments of this application, the various embodiments and implementation methods can be combined with each other, and there is no obstacle to their combination due to the separate description of the embodiments and implementation methods. The implementation processes of the various embodiments and implementation methods can be mutually referred to, and features can be integrated to form an overall solution that includes the technical features of each embodiment or implementation method.

[0071] Based on the same inventive concept, this application also provides some embodiments of chip testing systems. The chip testing systems provided in this application can implement the various processes of the above-described chip testing method embodiments and achieve the same technical effects. Therefore, the specific limitations of one or more chip testing system embodiments provided below can be found in the limitations of the chip testing method above, and will not be repeated here to avoid repetition.

[0072] This embodiment can divide the device into functional modules according to the above method. For example, each function can be divided into its own functional module, or two or more functions can be integrated into one processing module.

[0073] See Figure 3 , Figure 3 This is a schematic diagram of a chip testing system provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0074] The chip testing system 300 includes: Probe cards are used to perform electrical contact tests with chips on a wafer; Memory, used to store the test results of chip test items; The chip testing system 300 also includes: The test module 301 is used to perform test processing according to the chip test items when the probes in the probe card are not in contact with the chip on the wafer, to obtain the first test result of each station in the probe card and record it in the memory; and to perform test processing according to the chip test items when the probes in the probe card are in contact with the chip on the wafer, to obtain the second test result of each station. The calibration module 302 is used to calibrate the second test result of the corresponding workstation based on the first test result to obtain the electrical contact test result of the chip on the wafer.

[0075] Optionally, the correction module 302 is specifically used for: The electrical contact test results of the chips on the wafer are obtained by calculating the average value of the chip test item value of each station in the second test result and the chip test item value of the corresponding station in the first test result.

[0076] Optionally, test module 301 is specifically used for: Without the probes in the probe card contacting the chips on the wafer, a set number of cyclic tests are performed on the chip test items to obtain the first test result for each of the workstations in each test.

[0077] Optionally, the chip test items include dark current test items.

[0078] Optionally, the chip testing system further includes: A light source, located in the middle of the probe card, is used to emit light of different wavelengths onto the wafer; A light source sub-board is arranged on the probe card; An adapter board is connected to the light source sub-board, and the light source is electrically connected to the light source sub-board through the adapter board; According to the chip test items, the test process is performed when the probes in the probe card are not in contact with the chip on the wafer, and during the test process when the probes in the probe card are in contact with the chip on the wafer, the light source is controlled to emit light of the target wavelength toward the wafer.

[0079] Optionally, the light source sub-plate includes: A first light source sub-plate and a second light source sub-plate are arranged at relative positions on the probe card; The adapter plate is connected to the first light source sub-plate, and the light source is electrically connected to the first light source sub-plate through the adapter plate.

[0080] The integrated modules described above can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used.

[0081] It should be noted that the chip testing system provided in this application can implement all the processes of the above-described chip testing method embodiments and achieve the same technical effect. The relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module; to avoid repetition, it will not be repeated here.

[0082] Figure 4 This is a structural diagram of a computer device provided in an embodiment of this application. As shown in the figure, the computer device 4 of this embodiment includes: at least one processor 40 ( Figure 4 (Only one is shown in the diagram), memory 41, and computer program 42 stored in said memory 41 and executable on said at least one processor 40, wherein said processor 40 executes said computer program 42 to implement the steps in any of the above method embodiments.

[0083] The computer device 4 may include, but is not limited to, a processor 40 and a memory 41. Those skilled in the art will understand that... Figure 4 This is merely an example of computer device 4 and does not constitute a limitation on computer device 4. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device may also include input / output devices, network access devices, buses, etc.

[0084] The processor 40 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0085] The memory 41 can be an internal storage unit of the computer device 4, such as a hard disk or memory of the computer device 4. The memory 41 can also be an external storage device of the computer device 4, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device 4. Furthermore, the memory 41 can include both internal and external storage units of the computer device 4. The memory 41 is used to store the computer program and other programs and data required by the computer device. The memory 41 can also be used to temporarily store data that has been output or will be output.

[0086] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0088] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0089] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus / computer device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0090] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0091] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0092] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0093] The methods described in this application can be implemented in whole or in part by a computer program product. When the computer program product is run on a computer device, the computer device executes the steps in the various method embodiments described above.

[0094] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method of testing a chip, characterized by, The application is applied to a chip testing system, which comprises: a probe card for electrically contacting a chip on a wafer; a memory for storing a testing result of a chip testing item; the method comprises: performing a testing process according to the chip testing item without the probe in the probe card contacting the chip on the wafer, obtaining a first testing result of each station in the probe card, and recording in the memory; performing a testing process according to the chip testing item with the probe in the probe card contacting the chip on the wafer, obtaining a second testing result of each station; correcting the second testing result of the corresponding station based on the first testing result, and obtaining an electrically contacting testing result of the chip on the wafer.

2. The method of claim 1, wherein, The correction of the second testing result of the corresponding station based on the first testing result, and the obtaining of the electrically contacting testing result of the chip on the wafer, comprise: calculating a value of the chip testing item of each station in the second testing result and an average value of the value of the chip testing item of the corresponding station in the first testing result, and obtaining the electrically contacting testing result of the chip on the wafer.

3. The method of claim 1, wherein, The performance of the testing process according to the chip testing item without the probe in the probe card contacting the chip on the wafer, and the obtaining of the first testing result of each station in the probe card, comprise: performing a loop test of a set number of times on the chip testing item without the probe in the probe card contacting the chip on the wafer, and obtaining the first testing result of each station in each test.

4. The method of claim 1, wherein, The chip testing item comprises a dark current testing item.

5. The method of claim 1, wherein, The chip testing system further comprises: a light source located at a middle position of the probe card for emitting light of different wavelengths to the wafer; a light source sub-board arranged on the probe card; an adapter board connected with the light source sub-board, and the light source is electrically connected with the light source sub-board through the adapter board; controlling the light source to emit light of a target wavelength to the wafer during the performance of the testing process according to the chip testing item without the probe in the probe card contacting the chip on the wafer, and the performance of the testing process according to the chip testing item with the probe in the probe card contacting the chip on the wafer.

6. The method of claim 5, wherein, The light source sub-board comprises: a first light source sub-board and a second light source sub-board arranged at opposite positions on the probe card; the adapter board is connected with the first light source sub-board, and the light source is electrically connected with the first light source sub-board through the adapter board.

7. A chip testing system, characterized by comprising: The system further comprises: a probe card for electrically contacting a chip on a wafer; a memory for storing a testing result of a chip testing item; the system further comprises: a testing module for performing a testing process according to the chip testing item without the probe in the probe card contacting the chip on the wafer, obtaining a first testing result of each station in the probe card, and recording in the memory; and performing a testing process according to the chip testing item with the probe in the probe card contacting the chip on the wafer, obtaining a second testing result of each station; A correction module is configured to correct the second test result of each station based on the first test result to obtain the electrical contact test result of the chip on the wafer.

8. The system of claim 7, wherein, The test correction module is specifically configured to: calculate the average value of the numerical value of the chip test item of each station in the second test result and the numerical value of the chip test item of the corresponding station in the first test result to obtain the electrical contact test result of the chip on the wafer.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 6.

10. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 9. The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

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