Physical unclonable function generation method and system based on static memory

Abstract

The application provides a physical unclonable sequence generation method and system based on static memory, relates to the technical field of information security, and comprises the following steps: applying a pulse voltage stress to a storage unit and collecting a transient response signal as a physical fingerprint feature; performing multi-scale decomposition on a feature parameter matrix and dividing the feature parameter matrix into a bimodal distribution to generate a bit sequence; constructing a cyclic trigger chain to generate a disturbance sequence to enhance randomness; and constructing a physical unclonable sequence by using a fractal dimension segmentation algorithm and local entropy value adaptive crossover recombination. The application can effectively improve the randomness, uniqueness and attack resistance of the sequence and enhance the information security protection capability.

Description

Technical Field

[0001] This invention relates to the field of information security technology, and in particular to a method and system for generating physically unclonable sequences based on static memory. Background Technology

[0002] Physically unclonable functions (PUFs) are security primitives that generate unique identifiers based on the physical characteristics of a chip, and can be used in fields such as chip authentication and key generation. Static random access memory (SRAM) is an ideal carrier for implementing PUFs due to the inherent manufacturing process variability of its internal transistors. SRAM PUFs typically use the random initial state of the SRAM cell at power-on as a physical fingerprint, but traditional methods suffer from insufficient reliability and security.

[0003] Traditional PUF sequence generation methods based on static memory primarily rely on power-on initialization, failing to fully utilize the dynamic transient response characteristics of memory cells under voltage stress. This results in insufficient uniqueness and randomness of the generated sequences, making them vulnerable to side-channel attacks. Existing technologies for processing acquired physical fingerprint features are relatively simple, lacking systematic multi-dimensional feature extraction and optimization algorithms. This makes it difficult to effectively distinguish between noise and genuine fingerprint features, reducing the stability and reliability of the generated sequences. Furthermore, existing methods for generating physically unclonable sequences lack effective randomness enhancement mechanisms, resulting in insufficient resistance to environmental changes and aging effects, making it difficult to guarantee long-term stability under harsh conditions. Additionally, post-processing algorithms generally neglect internal sequence structure optimization, failing to meet the requirements of high-security applications. Summary of the Invention

[0004] The present invention provides a method and system for generating physically unclonable sequences based on static memory, which can solve the problems in the prior art.

[0005] A first aspect of the present invention provides a method for generating physically unclonable sequences based on static memory, comprising:

[0006] In the storage cell array of static memory, each storage cell is sequentially selected by a row and column address decoder, and a pulse voltage stress is applied to the selected storage cell; the transient response signal of the storage cell under the pulse voltage stress is acquired by an analog front-end circuit, and the time-domain characteristic parameters of the transient response signal are used as the physical fingerprint characteristics of the storage cell;

[0007] Based on the physical fingerprint features, a feature parameter matrix is ​​constructed and multi-scale decomposition is performed. Based on the information entropy criterion, the feature components of the optimal decomposition level are selected and divided into a bimodal distribution using a dynamic clustering method. The bit sequence is generated based on the distance between the two peaks as the decision threshold.

[0008] An odd number of signal inversion modules are connected in a ring to form a cyclic trigger chain. An independent operating environment is built for the cyclic trigger chain and deployed in the static memory. The oscillation period of the cyclic trigger signal of the cyclic trigger chain is used as a random seed to generate a perturbation sequence. The randomness of the bit sequence is enhanced by performing an XOR operation between the perturbation sequence and the bit sequence to obtain a random enhanced bit sequence.

[0009] The randomized enhanced bit sequence is divided into multiple sequence segments using a fractal dimension segmentation algorithm. A local entropy value is calculated for each sequence segment, and adaptive crossover and recombination are performed based on the local entropy value to construct a physically unclonable sequence.

[0010] In the static memory's cell array, each memory cell is sequentially selected via a row and column address decoder. Applying pulse voltage stress to the selected memory cells includes:

[0011] A gating sequence is generated based on the row and column structure of the storage cell array, and the gating sequence ensures that the storage cell in each gating operation is in the same row or column as the storage cell in the previous gating operation in terms of physical location.

[0012] In the storage cell array, the target storage cell to be selected and the buffer storage cells around the target storage cell are constructed as a storage cell gating window. The storage cell gating window is slid in the storage cell array according to the gating sequence, and the target storage cell is sequentially assigned to each storage cell in the gating sequence.

[0013] Based on the row address and column address of the target memory cell, a row strobe signal and a column strobe signal are generated in the row and column address decoder, respectively. The row strobe signal and the column strobe signal are applied to the row line and column line of the target memory cell to complete the selection of the target memory cell.

[0014] A time interval longer than the memory cell recovery time is set between adjacent gating operations; in the gating state, a pulse voltage stress greater than the standard operating voltage is applied to the target memory cell, and the charge accumulation effect between the target memory cell and the buffer memory cell is eliminated within the time interval.

[0015] The transient response signal of the storage cell under the pulse voltage stress is acquired using an analog front-end circuit, and the time-domain characteristic parameters of the transient response signal are used as the physical fingerprint characteristics of the storage cell, including:

[0016] A transimpedance amplifier for current-to-voltage conversion is designed, and the analog front-end circuit is constructed using the transimpedance amplifier, a feedback resistor, and a compensation capacitor. After the pulse voltage stress is applied to the memory cell, the analog front-end circuit amplifies the signal and compensates the bandwidth through the feedback resistor and the compensation capacitor, and acquires the generated transient current signal. The transient current signal is converted into a voltage signal using the transimpedance amplifier to obtain the transient response signal.

[0017] The transient response signal is input to a bandpass filter circuit for filtering. The bandpass filter circuit filters out noise and interference components outside the operating frequency band in the transient response signal to obtain the filtered transient response signal.

[0018] The rise time parameter, peak amplitude parameter, and peak time parameter of the filtered transient response signal from the initial value to the peak value are extracted. The decay time constant parameter of the filtered transient response signal is extracted based on exponential fitting. The rise time parameter, the peak amplitude parameter, the peak time parameter, and the decay time constant parameter are combined to form a time-domain feature vector, and the time-domain feature vector is used as the physical fingerprint feature of the storage unit.

[0019] Based on the physical fingerprint features, a feature parameter matrix is ​​constructed and multi-scale decomposition is performed. The feature components of the optimal decomposition level are selected based on the information entropy criterion and divided into a bimodal distribution using a dynamic clustering method. A bit sequence is generated based on the distance between the two peaks as a decision threshold, including:

[0020] The physical fingerprint features of all storage units are used to construct the feature parameter matrix according to the physical location of the storage units, and each row of the feature parameter matrix corresponds to one physical fingerprint feature.

[0021] A two-dimensional discrete wavelet transform is performed on the feature parameter matrix to obtain multiple decomposition levels. The discreteness of each decomposition level is calculated, and the decomposition level with the largest discreteness is selected as the optimal decomposition level. The coefficient matrix of the optimal decomposition level is extracted as the feature component.

[0022] The feature components are clustered using a binary K-means clustering algorithm to obtain two cluster centers. The elements in the feature components are assigned to the nearest cluster center to form a cluster subset. New cluster centers are calculated based on the cluster subsets. The clustering is iterated until the cluster centers converge to obtain a bimodal distribution of the feature components. The distance between the peaks in the bimodal distribution is calculated as the decision threshold.

[0023] Elements in the feature components that are greater than the decision threshold are quantized to 1, and elements in the feature components that are less than or equal to the decision threshold are quantized to 0, thereby generating the binarized bit sequence.

[0024] A cyclic trigger chain is formed by connecting an odd number of signal inversion modules in a ring. Constructing an independent operating environment for the cyclic trigger chain and deploying it to the static memory includes:

[0025] The signal inversion module is configured as a program component with bidirectional triggering function. In an odd number of program components, the output terminal of each program component is logically connected to the input terminal of the next program component in sequence. The bidirectional triggering function is used to randomly flip signals between adjacent program components to form the cyclic triggering chain.

[0026] A resource isolation component is configured in the static memory, and a buffer is used to establish a connection between the resource isolation component and the loop trigger chain and isolate external influences on the loop trigger chain. The resource isolation component provides an independent operating environment for the loop trigger chain.

[0027] The system clock signal is input to the cyclic trigger chain to obtain the cyclic trigger signal. The cyclic trigger chain is logically connected to the scheduling module of the static memory through the signal distribution module. The cyclic trigger signal is distributed to each of the scheduling modules through the signal distribution module to obtain the static memory where the cyclic trigger chain is deployed.

[0028] Using the oscillation period of the cyclic trigger signal of the cyclic trigger chain as a random seed to generate a perturbation sequence, and enhancing the randomness of the bit sequence by performing an XOR operation between the perturbation sequence and the bit sequence, a random enhanced bit sequence is obtained, comprising:

[0029] The oscillation period is obtained by calculating the time interval between two adjacent rising edges of the cyclic trigger signal;

[0030] The difference between two adjacent oscillation periods is calculated to obtain a period difference value. The period difference value is then binary quantized to obtain a binary sequence containing multiple binary bits. Each preset number of binary bits is grouped into a group, and a random seed value is obtained by performing a shift and accumulation operation on each group of binary bits.

[0031] The random seed values ​​are combined in the order of generation to form a random seed sequence. The random seed sequence is input into a linear feedback shift register. The first and second bits of the random seed sequence are used to select the tap position of the linear feedback shift register. The last bit of the random seed sequence is used to set the feedback coefficient of the linear feedback shift register. The perturbation sequence is output through the linear feedback shift register.

[0032] The randomized enhanced bit sequence is obtained by performing an XOR operation between each bit in the perturbation sequence and the corresponding bit in the bit sequence.

[0033] The randomized enhanced bit sequence is divided into multiple sequence segments using a fractal dimension segmentation algorithm. A local entropy value is calculated for each sequence segment. Based on the local entropy value, adaptive crossover and recombination are performed to construct a physically unclonable sequence, including:

[0034] The scaling exponent of the range standard deviation and sequence length is calculated for the random enhanced bit sequence. The fractal dimension of the sequence is obtained by differentiating the scaling exponent. The sequence fluctuation curve is calculated based on the sequence fractal dimension. The inflection point of the sequence fluctuation curve is determined as the segmentation point. The random enhanced bit sequence is divided into multiple sequence segments based on the segmentation point.

[0035] The information entropy, conditional entropy, and approximate entropy are calculated for each sequence segment and combined to form a quality score for the sequence segment. The sequence segments are then sorted in descending order based on the quality scores.

[0036] The mutual information between the sequence segments is calculated, and the sequence segments are cross-recombined at the position where the mutual information is minimum to obtain a cross-recombined sequence. An adaptive mutation probability negatively correlated with the quality score is used to locally perturb the cross-recombined sequence. When the quality score of the cross-recombined sequence reaches a preset quality threshold, the physically unclonable sequence is obtained.

[0037] A second aspect of the present invention provides a system for generating physically unclonable sequences based on static memory, comprising:

[0038] The first unit is used to sequentially select each memory cell in the memory cell array of the static memory through a row and column address decoder, apply pulse voltage stress to the selected memory cell, and use an analog front-end circuit to collect the transient response signal of the memory cell under the pulse voltage stress, and use the time-domain characteristic parameters of the transient response signal as the physical fingerprint feature of the memory cell.

[0039] The second unit is used to construct a feature parameter matrix based on the physical fingerprint features and perform multi-scale decomposition. Based on the information entropy criterion, the feature components of the optimal decomposition level are selected and divided into a bimodal distribution through a dynamic clustering method. The bit sequence is generated based on the distance between the two peaks as the decision threshold.

[0040] The third unit is used to form a cyclic trigger chain by connecting an odd number of signal inversion modules in a ring. It constructs an independent operating environment for the cyclic trigger chain and deploys it in the static memory. It uses the oscillation period of the cyclic trigger signal of the cyclic trigger chain as a random seed to generate a perturbation sequence. By performing an XOR operation between the perturbation sequence and the bit sequence, the randomness of the bit sequence is enhanced to obtain a random enhanced bit sequence.

[0041] The fourth unit is used to divide the randomized enhanced bit sequence into multiple sequence segments using a fractal dimension segmentation algorithm, calculate the local entropy value for each sequence segment, and perform adaptive crossover and recombination based on the local entropy value to construct a physically unclonable sequence.

[0042] A third aspect of the present invention,

[0043] An electronic device is provided, comprising:

[0044] processor;

[0045] Memory used to store processor-executable instructions;

[0046] The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0047] Fourth aspect of the embodiments of the present invention,

[0048] A computer-readable storage medium is provided, having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0049] The beneficial effects of this application are as follows:

[0050] By applying pulsed voltage stress to the storage cells of static memory and collecting transient response signals as physical fingerprint features, and combining multi-scale decomposition and dynamic clustering methods to generate bit sequences, the uniqueness and stability of physically unclonable sequences are ensured, effectively utilizing the inherent physical characteristics differences of semiconductor devices.

[0051] A cyclic trigger chain consisting of an odd number of signal inversion modules is introduced as a random seed. The randomness of the bit sequence is enhanced by XOR operation, which effectively increases the entropy of the generated sequence, enhances the unpredictability of the sequence, and improves security.

[0052] By employing a fractal dimension segmentation algorithm and adaptive cross-recombination technology, the sequence is optimized based on the local entropy value, further enhancing the complexity and randomness of physically unclonable sequences while maintaining their physical unclonability, thus providing more reliable technical support for information security and identity authentication. Attached Figure Description

[0053] Figure 1 This is a flowchart illustrating the method for generating physically unclonable sequences based on static memory according to an embodiment of the present invention.

[0054] Figure 2 A schematic diagram of the process for gating storage cells and applying pulse voltage stress. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0057] Figure 1 This is a flowchart illustrating the method for generating physically unclonable sequences based on static memory according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0058] In the storage cell array of static memory, each storage cell is sequentially selected by a row and column address decoder, and a pulse voltage stress is applied to the selected storage cell; the transient response signal of the storage cell under the pulse voltage stress is acquired by an analog front-end circuit, and the time-domain characteristic parameters of the transient response signal are used as the physical fingerprint characteristics of the storage cell;

[0059] Based on the physical fingerprint features, a feature parameter matrix is ​​constructed and multi-scale decomposition is performed. Based on the information entropy criterion, the feature components of the optimal decomposition level are selected and divided into a bimodal distribution using a dynamic clustering method. The bit sequence is generated based on the distance between the two peaks as the decision threshold.

[0060] An odd number of signal inversion modules are connected in a ring to form a cyclic trigger chain. An independent operating environment is built for the cyclic trigger chain and deployed in the static memory. The oscillation period of the cyclic trigger signal of the cyclic trigger chain is used as a random seed to generate a perturbation sequence. The randomness of the bit sequence is enhanced by performing an XOR operation between the perturbation sequence and the bit sequence to obtain a random enhanced bit sequence.

[0061] The randomized enhanced bit sequence is divided into multiple sequence segments using a fractal dimension segmentation algorithm. A local entropy value is calculated for each sequence segment, and adaptive crossover and recombination are performed based on the local entropy value to construct a physically unclonable sequence.

[0062] In one optional implementation, in the static memory's cell array, each memory cell is sequentially selected via a row and column address decoder, and applying pulse voltage stress to the selected memory cells includes:

[0063] A gating sequence is generated based on the row and column structure of the storage cell array, and the gating sequence ensures that the storage cell in each gating operation is in the same row or column as the storage cell in the previous gating operation in terms of physical location.

[0064] In the storage cell array, the target storage cell to be selected and the buffer storage cells around the target storage cell are constructed as a storage cell gating window. The storage cell gating window is slid in the storage cell array according to the gating sequence, and the target storage cell is sequentially assigned to each storage cell in the gating sequence.

[0065] Based on the row address and column address of the target memory cell, a row strobe signal and a column strobe signal are generated in the row and column address decoder, respectively. The row strobe signal and the column strobe signal are applied to the row line and column line of the target memory cell to complete the selection of the target memory cell.

[0066] A time interval longer than the memory cell recovery time is set between adjacent gating operations; in the gating state, a pulse voltage stress greater than the standard operating voltage is applied to the target memory cell, and the charge accumulation effect between the target memory cell and the buffer memory cell is eliminated within the time interval.

[0067] like Figure 2 As shown, the method includes:

[0068] Analyzing the static memory array structure, assuming the array is an 8×8 matrix containing 64 memory cells, each identified by a unique row and column address, a serpentine scanning method can be used to generate a gating sequence to ensure the continuity of gating operations and reduce latency caused by cross-array gating. This ensures that memory cells for adjacent gating operations share the same row or column physically. For example, starting from memory cell (0,0), gating cells (0,0), (0,1), (0,2)... up to (0,7) are selected from left to right along row 0. Then, moving to the next row, row 1, gating cells (1,7), (1,6)... up to (1,0) from right to left, then moving to row 2 and selecting cells from left to right, and so on. This pattern ensures that each gating operation shares a row or column with the memory cell of the previous operation, thereby improving gating efficiency and reducing charge accumulation effects.

[0069] To reduce interference to adjacent cells during the gating process, this invention introduces the concept of a storage cell gating window. The gating window includes the target storage cell to be gated and its surrounding buffer storage cells. Taking a 3×3 gating window as an example, when the target storage cell is (2,3), the cells covered by the gating window include (1,2), (1,3), (1,4), (2,2), (2,3), (2,4), (3,2), (3,3), and (3,4), where (2,3) is the target cell and the rest are buffer cells.

[0070] Based on the generated gating sequence, the gating window slides across the memory cell array, with the target memory cell corresponding to each cell in the gating sequence in turn. For example, when the gating sequence moves to cell (2,3), the row address decoder decodes row address 2 into a row gating signal, and the column address decoder decodes column address 3 into a column gating signal. These signals are applied to the second row line and the third column line, respectively, thereby gating the target memory cell (2,3).

[0071] A standard decoder is used to generate the strobe signals. For example, for an 8×8 array, each row and column address requires 3 bits of binary data. When the target cell is (2,3), the row address is "010" and the column address is "011". The row address decoder converts "010" into the strobe signal for the second row, and the column address decoder converts "011" into the strobe signal for the third column.

[0072] To ensure that each memory cell has sufficient recovery time, a time interval is set between two adjacent gating operations. Based on the characteristics of static memory, the typical memory cell recovery time is 100 nanoseconds. In this embodiment, the time interval is set to 200 nanoseconds, which is longer than the memory cell recovery time, to ensure that the memory cell can be fully recovered.

[0073] When applying pulsed voltage stress to the target memory cell, the stress voltage value is set to 1.5 times the standard operating voltage. Assuming the standard operating voltage is 1.2V, the applied pulsed voltage stress is 1.8V. The pulse width is set to 50 nanoseconds, sufficient to trigger electromigration within the memory cell without causing permanent damage. The pulsed voltage stress is generated by a voltage regulation circuit that provides an additional 0.6V voltage increment on top of the standard operating voltage.

[0074] To eliminate the charge accumulation effect between the target memory cell and the buffer memory cell, after the pulse voltage stress is removed, the row and column lines of the target memory cell are connected to ground potential for 100 nanoseconds to ensure that the charge inside the memory cell is completely released. At the same time, the buffer memory cell is precharged to 0.6V (half of the standard operating voltage) for 50 nanoseconds to neutralize the charge accumulation.

[0075] Testing showed that applying pulsed voltage stress to the memory cell array using the above method effectively assesses the durability and reliability of the memory cells. After 10,000 cycles of testing, the failure rate of the memory cells was less than 0.01%, far lower than the 0.1% failure rate under the traditional random gating method. Furthermore, the total testing time was reduced by approximately 30%, demonstrating the significant advantages of the method of this invention in improving testing efficiency and reducing the risk of memory cell damage.

[0076] The method provided by this invention can not only efficiently perform reliability testing on each memory cell of a static memory, but also significantly reduce misjudgments and memory cell damage caused by charge accumulation during the testing process, providing memory manufacturers with a more accurate and efficient quality assurance means.

[0077] In one optional implementation, an analog front-end circuit is used to acquire the transient response signal of the storage cell under the pulse voltage stress, and the time-domain characteristic parameters of the transient response signal are used as the physical fingerprint characteristics of the storage cell, including:

[0078] A transimpedance amplifier for current-to-voltage conversion is designed, and the analog front-end circuit is constructed using the transimpedance amplifier, a feedback resistor, and a compensation capacitor. After the pulse voltage stress is applied to the memory cell, the analog front-end circuit amplifies the signal and compensates the bandwidth through the feedback resistor and the compensation capacitor, and acquires the generated transient current signal. The transient current signal is converted into a voltage signal using the transimpedance amplifier to obtain the transient response signal.

[0079] The transient response signal is input to a bandpass filter circuit for filtering. The bandpass filter circuit filters out noise and interference components outside the operating frequency band in the transient response signal to obtain the filtered transient response signal.

[0080] The rise time parameter, peak amplitude parameter, and peak time parameter of the filtered transient response signal from the initial value to the peak value are extracted. The decay time constant parameter of the filtered transient response signal is extracted based on exponential fitting. The rise time parameter, the peak amplitude parameter, the peak time parameter, and the decay time constant parameter are combined to form a time-domain feature vector, and the time-domain feature vector is used as the physical fingerprint feature of the storage unit.

[0081] The analog front-end circuit uses the high-performance transimpedance amplifier AD8066, which has high bandwidth and low noise characteristics, meeting the requirements of transient signal acquisition. The transimpedance amplifier, together with the feedback resistor Rf (10kΩ) and the compensation capacitor Cf (1.5pF), constitutes a complete front-end acquisition circuit. The addition of the compensation capacitor Cf effectively improves the stability of the circuit and prevents the generation of high-frequency oscillations.

[0082] When a pulsed voltage stress is applied to a memory cell, the differences in the internal physical characteristics of the cell result in a unique transient current response. This transient current signal is acquired through the aforementioned analog front-end circuit. Specifically, the transient current of the memory cell flows through the feedback resistor Rf, generating a voltage drop across Rf. The transimpedance amplifier converts this current signal into a voltage signal for output. According to the characteristics of the transimpedance amplifier, the relationship between the output voltage V_out and the input current I_in is V_out = -Rf × I_in. For a typical memory cell, when a 1.5V pulse voltage is applied, the peak transient current generated is approximately 120μA. After conversion by the transimpedance amplifier, the peak output voltage is approximately -1.2V.

[0083] To improve signal quality, the acquired transient response signal needs to be processed by a bandpass filter circuit. A second-order active bandpass filter is used, consisting of an operational amplifier LM358 and a precision resistor-capacitor network. The filter's low cutoff frequency is set to 10kHz, and its high cutoff frequency is 5MHz. This frequency band effectively removes power frequency interference (50Hz / 60Hz) and high-frequency noise while preserving the key characteristics of the transient response signal. The signal-to-noise ratio of the filtered signal is improved by approximately 12dB, making subsequent feature extraction more accurate.

[0084] The filtered transient response signal is digitized by a high-speed data acquisition system with a sampling rate of 50 MSa / s and a resolution of 12 bits. This ensures complete capture of the details of the transient signal. The digitized signal data is then transmitted to the processing unit for extraction of time-domain feature parameters.

[0085] The time-domain feature parameter extraction process includes the following steps: determining the initial value of the signal, i.e., the steady-state voltage value before the pulse is applied, which is usually close to 0V; secondly, identifying the peak point of the signal, recording the peak amplitude and the time point when the peak occurs; calculating the time required for the signal to rise from the initial value to the peak, which is defined as the rise time parameter; and finally, performing exponential fitting on the attenuation part after the peak of the signal to extract the attenuation time constant.

[0086] In actual testing, measurements were taken on 128 identical memory cells, revealing significant differences in their characteristic parameters. The rise time parameter ranged from 18ns to 35ns, with a standard deviation of 3.2ns; the peak amplitude parameter ranged from 0.8V to 1.6V, with a standard deviation of 0.15V; the peak time parameter ranged from 45ns to 70ns, with a standard deviation of 4.8ns; and the decay time constant parameter ranged from 80ns to 150ns, with a standard deviation of 12.5ns. These parameters form a four-dimensional feature vector, creating a unique physical fingerprint for each memory cell.

[0087] To verify the reliability of the physical fingerprint feature, 100 repeated measurements were performed on the same group of memory cells. The results show that the feature parameters of the same memory cell have high consistency across different measurements, the coefficient of variation of the Euclidean distance of the feature vector is less than 3%, and the average Euclidean distance of the feature vectors between different memory cells is more than 8 times that of a single memory cell, indicating that the physical fingerprint feature has good distinguishability.

[0088] The technical solution of this embodiment provides an efficient and reliable means for the secure authentication of storage units by accurately acquiring the transient response signal of the storage unit under pulse voltage stress and extracting its time-domain feature parameters as physical fingerprint features. This technology can be applied to security-critical scenarios such as IoT device identity authentication, electronic product anti-counterfeiting, and key protection.

[0089] In one optional implementation, a feature parameter matrix is ​​constructed based on the physical fingerprint features and multi-scale decomposition is performed. Feature components at the optimal decomposition level are selected based on the information entropy criterion and divided into a bimodal distribution using a dynamic clustering method. A bit sequence is generated based on the distance between the two peaks as a decision threshold, including:

[0090] The physical fingerprint features of all storage units are used to construct the feature parameter matrix according to the physical location of the storage units, and each row of the feature parameter matrix corresponds to one physical fingerprint feature.

[0091] A two-dimensional discrete wavelet transform is performed on the feature parameter matrix to obtain multiple decomposition levels. The discreteness of each decomposition level is calculated, and the decomposition level with the largest discreteness is selected as the optimal decomposition level. The coefficient matrix of the optimal decomposition level is extracted as the feature component.

[0092] The feature components are clustered using a binary K-means clustering algorithm to obtain two cluster centers. The elements in the feature components are assigned to the nearest cluster center to form a cluster subset. New cluster centers are calculated based on the cluster subsets. The clustering is iterated until the cluster centers converge to obtain a bimodal distribution of the feature components. The distance between the peaks in the bimodal distribution is calculated as the decision threshold.

[0093] Elements in the feature components that are greater than the decision threshold are quantized to 1, and elements in the feature components that are less than or equal to the decision threshold are quantized to 0, thereby generating the binarized bit sequence.

[0094] The physical fingerprint features are arranged according to the physical location of the storage cells to construct a feature parameter matrix. Assuming the storage device contains an array of n rows and m columns of storage cells, the resulting feature parameter matrix X has a dimension of n×m, where each row of X corresponds to the physical fingerprint feature of one storage cell. For example, for an array containing 64×64 storage cells, the collected physical fingerprint features (such as the initial value of SRAM after power-on, DRAM access latency, etc.) will constitute a 64×64 feature parameter matrix.

[0095] After constructing the feature parameter matrix, a Haar wavelet basis function transformation is performed on the matrix to decompose it into multiple levels. Each level contains four sub-bands: low-frequency sub-band (LL), horizontal high-frequency sub-band (LH), vertical high-frequency sub-band (HL), and diagonal high-frequency sub-band (HH). For a 64×64 feature parameter matrix, the first level of decomposition yields four 32×32 sub-bands, the second level yields four 16×16 sub-bands, and so on.

[0096] To determine the optimal decomposition level, information entropy is used to measure the dispersion of each decomposition level. Higher dispersion indicates richer information content at that level. For decomposition level k, the sum of the information entropies of its four sub-bands LL_k, LH_k, HL_k, and HH_k is calculated as the dispersion of that level. During the information entropy calculation, the sub-band data is normalized to a probability distribution, and the entropy value is calculated. In practical applications, a 64×64 feature parameter matrix is ​​decomposed into 5 levels, and the dispersion of each level is calculated. Assuming the calculation results show that the third level decomposition has the largest dispersion value of 2.73, then the third level is selected as the optimal decomposition level, and the coefficient matrices of its four sub-bands are extracted as feature components.

[0097] After obtaining the feature components, a binary K-means clustering algorithm is used to cluster them. Two initial cluster centers are randomly selected; for example, for the LL subband (size 8×8) of the third-level decomposition, values ​​of 0.2 and 0.7 are chosen as initial cluster centers. Each element in the feature component is assigned to the nearest cluster center, forming two cluster subsets C1 and C2. The cluster centers are recalculated based on the current cluster subsets, i.e., the average value of all elements in each subset is used as the new cluster center. This process is repeated until the cluster centers no longer change significantly. In the example, after 10 iterations, the two cluster centers converge to 0.35 and 0.82.

[0098] After clustering, the elements of the feature components will exhibit a bimodal distribution. The distance between the two peaks is calculated as the decision threshold. In the example above, the decision threshold is 0.82 - 0.35 = 0.47. Alternatively, the midpoint between the two cluster centers can be chosen as the decision threshold, i.e., (0.35 + 0.82) / 2 = 0.585.

[0099] Binarization is performed on the feature components based on the decision threshold to generate a bit sequence. Elements in the feature components greater than the decision threshold are quantized to 1, and elements less than or equal to the decision threshold are quantized to 0. For the aforementioned 8×8 LL subband, assuming an element value of 0.76 is less than the decision threshold of 0.585, the bit value at that position is 0; if the element value is 0.92, greater than the decision threshold of 0.585, the bit value at that position is 1. In this way, an 8×8 feature component matrix will generate a 64-bit sequence.

[0100] The above method can extract stable bit sequences from the physical fingerprint features of memory. These sequences can be used in applications such as device authentication and key generation. Actual testing shows that the bit sequences generated by this method have good randomness and stability, with repeatability exceeding 96% under different environmental conditions, meeting practical application requirements.

[0101] In one optional implementation, a cyclic trigger chain is formed by connecting an odd number of signal inversion modules in a ring. Constructing an independent operating environment for the cyclic trigger chain and deploying it to the static memory includes:

[0102] The signal inversion module is configured as a program component with bidirectional triggering function. In an odd number of program components, the output terminal of each program component is logically connected to the input terminal of the next program component in sequence. The bidirectional triggering function is used to randomly flip signals between adjacent program components to form the cyclic triggering chain.

[0103] A resource isolation component is configured in the static memory, and a buffer is used to establish a connection between the resource isolation component and the loop trigger chain and isolate external influences on the loop trigger chain. The resource isolation component provides an independent operating environment for the loop trigger chain.

[0104] The system clock signal is input to the cyclic trigger chain to obtain the cyclic trigger signal. The cyclic trigger chain is logically connected to the scheduling module of the static memory through the signal distribution module. The cyclic trigger signal is distributed to each of the scheduling modules through the signal distribution module to obtain the static memory where the cyclic trigger chain is deployed.

[0105] The signal inversion module is designed as the basic unit of the cyclic trigger chain. Each signal inversion module is configured as a programmable component with bidirectional triggering functionality. This component can receive the input signal and generate the inverted output signal. The bidirectional triggering function means that when the input terminal receives a high-level signal, the output terminal generates a low-level signal; when the input terminal receives a low-level signal, the output terminal generates a high-level signal. For example, in practical implementation, this function can be accomplished using a NOT gate circuit or a logic NOT operation implemented through software programming. Specifically, using an inverter circuit in CMOS technology, its input threshold voltage is set to 1.5V. When the input voltage is lower than 1.5V, the output is a high level of 3.3V; when the input voltage is higher than 1.5V, the output is a low level of 0V.

[0106] Choose an odd number of signal inversion modules, such as 5, 7, or 9. Taking 7 signal inversion modules as an example, number these modules sequentially as Module-1, Module-2, Module-3, Module-4, Module-5, Module-6, and Module-7. In the ring connection process, the output of Module-1 is connected to the input of Module-2, the output of Module-2 is connected to the input of Module-3, and so on. Finally, the output of Module-7 is connected to the input of Module-1, forming a complete ring structure.

[0107] Because an odd number of inverters connected in series form a ring structure, a stable state cannot be achieved. The signal will continuously flip in the loop. For example, if the output of Module-1 is high in the initial state, it will become low after passing through Module-2. After being passed in sequence, when the signal returns to Module-1, the signal state is opposite to the initial state due to the odd number of flips, causing continuous oscillation. This instability is the basis for the random signal flipping. Actual measurements show that in a loop composed of 7 modules, the signal flipping frequency is approximately the reciprocal of the total loop delay. For example, if the delay of each module is 1ns, the total delay is 7ns, and the flipping frequency is approximately 143MHz.

[0108] To protect the loop trigger chain from external interference, a resource isolation component needs to be configured in the static memory. The resource isolation component can be implemented as a dedicated memory region or logical unit. Hardware firewalls or software access control mechanisms can be used to prevent other system components from directly accessing or modifying the loop trigger chain. For example, a memory protection mechanism can be set up using a memory management unit (MMU) to mark the memory region where the loop trigger chain is located as a privileged access region, allowing only specific system components to access it.

[0109] The buffer can be implemented as a FIFO (First-In-First-Out) queue or a double-buffered mechanism to smooth signal transmission and filter interference. The size of the buffer can be set according to actual needs. For example, for time-sensitive applications, it can be set to a 64-byte buffer to ensure that the data transmission delay does not exceed 10μs. The buffer can also be configured with signal filtering mechanisms, such as a sliding window averaging algorithm with a window size of 8, averaging eight consecutive received signal values ​​to filter out high-frequency noise interference.

[0110] The system clock can be a stable clock signal generated by an external crystal oscillator, such as a 50MHz square wave signal. The clock signal is input to a node of the cyclic trigger chain through a dedicated clock distribution network, such as the input of Module-1. The rising edge of the clock signal triggers the cyclic trigger chain to start running, and then the cyclic trigger chain will autonomously maintain the oscillation state to generate a cyclic trigger signal.

[0111] The signal distribution module can be implemented as a multiplexer, which distributes the cyclic trigger signal to different target components according to preset rules. The distribution rules can be based on a time-slice round-robin algorithm, for example, using a time interval of 5μs as a distribution unit, and distributing the signal to different scheduling modules in turn.

[0112] In practical deployments, the scheduling module can be configured as a trigger condition detector. When a specific pattern of a cyclic trigger signal (such as three consecutive high levels) is received, the corresponding operation is triggered. For example, memory refresh operations in static memory can be initiated by such a trigger signal to achieve random interval memory refreshes, reducing the security risks associated with predictability.

[0113] The cyclic trigger chain deployed by the above method can operate stably in static memory, generating unpredictable trigger signals, effectively improving the system's operational safety and anti-interference capability. Experimental results show that the cyclic trigger chain constructed using this method can still maintain stable operation within a temperature range of -20℃ to 85℃ and under power supply voltage fluctuations of ±10%. The randomness of the trigger signal is verified by the NIST random number test suite, with an entropy value of over 0.95.

[0114] In one optional implementation, the oscillation period of the cyclic trigger signal of the cyclic trigger chain is used as a random seed to generate a perturbation sequence. The randomness of the bit sequence is enhanced by performing an XOR operation between the perturbation sequence and the bit sequence to obtain a randomly enhanced bit sequence, including:

[0115] The oscillation period is obtained by calculating the time interval between two adjacent rising edges of the cyclic trigger signal;

[0116] The difference between two adjacent oscillation periods is calculated to obtain a period difference value. The period difference value is then binary quantized to obtain a binary sequence containing multiple binary bits. Each preset number of binary bits is grouped into a group, and a random seed value is obtained by performing a shift and accumulation operation on each group of binary bits.

[0117] The random seed values ​​are combined in the order of generation to form a random seed sequence. The random seed sequence is input into a linear feedback shift register. The first and second bits of the random seed sequence are used to select the tap position of the linear feedback shift register. The last bit of the random seed sequence is used to set the feedback coefficient of the linear feedback shift register. The perturbation sequence is output through the linear feedback shift register.

[0118] The randomized enhanced bit sequence is obtained by performing an XOR operation between each bit in the perturbation sequence and the corresponding bit in the bit sequence.

[0119] For each cyclic trigger signal, the time interval between two adjacent rising edges, i.e., the oscillation period, needs to be accurately measured. In practical implementation, a high-precision counter can be used to record the number of clock cycles between two consecutive rising edges. For example, assuming the system clock frequency is 1GHz, if the counter records 1025 clock cycles between two adjacent rising edges, then the oscillation period is 1.025 microseconds.

[0120] After measuring the oscillation period, the continuously acquired oscillation periods are differentially processed, that is, the difference between two adjacent oscillation periods is calculated to obtain the period difference value. These difference values ​​can capture the jitter characteristics of the oscillator and contain a high entropy value. For example, assuming that three consecutive oscillation periods are measured as 1025, 1028 and 1022 clock cycles, the difference values ​​between two adjacent periods are 3 and -6, respectively.

[0121] To convert the periodic difference values ​​into binary form, binary quantization is used. For positive difference values, the highest bit is set to 1, and for negative difference values, the highest bit is set to 0. Then, the absolute value of the difference is converted into a binary representation. For example, the difference value 3 is quantized as "100000011", and the difference value -6 is quantized as "000000110". For ease of processing, all quantization results can be standardized to a fixed length, such as 16 bits.

[0122] The quantized binary sequence is grouped into preset groups, each group containing 8, 16, or 32 bits. A shift-accumulation operation is performed on each group to generate a random seed value. Specifically, the shift-accumulation operation involves: shifting the current group's binary sequence one bit to the right, XORing it with the original sequence to obtain an intermediate result; shifting this intermediate result two bits to the right again, XORing it with the previous result; and so on, completing multiple shift and XOR operations to obtain a random seed value. For example, for the binary group "10110101", first shifting it one bit to the right yields "01011010", XORing the two yields "11101111"; then shifting "11101111" two bits to the right yields "00111011", XORing the two yields "11010100", which can be used as a random seed value.

[0123] As the cyclic trigger chain continues to work, the continuously generated random seed values ​​are combined in the order of generation to form a random seed sequence. For example, the three consecutively generated random seed values ​​"11010100", "01101001" and "10011110" are combined to form the random seed sequence "1101010001101001100111110".

[0124] The random seed sequence is then input into a linear feedback shift register (LFSR), a structure that generates pseudo-random sequences and contains multiple flip-flops and feedback paths. In this implementation, the first bit of the random seed sequence is used to select the tap position of the LFSR, and the last bit of the random seed sequence is used to set the feedback coefficient of the LFSR, thereby enhancing the unpredictability of the LFSR output sequence. For example, assuming the LFSR is 16 bits, if the first bit of the random seed sequence is 1, then the 15th bit can be selected as the tap; if it is 0, then the 13th bit is selected as the tap. Similarly, the last bit of the random seed sequence determines whether the feedback path uses an XOR or XNOR operation.

[0125] LFSR generates a perturbation sequence based on the input random seed sequence and configured tap positions and feedback coefficients. This perturbation sequence exhibits good statistical properties and a period length of up to 2^n. n-1 (n is the number of bits in the LFSR). For example, a 16-bit LFSR can generate a non-repeating sequence of up to 65535.

[0126] For each bit in the perturbation sequence, an XOR operation is performed with the corresponding bit in the bit sequence. For example, if the perturbation sequence is "10110010" and the original bit sequence is "11001101", the XOR result is "01111111". This operation effectively disrupts the pattern of the original bit sequence, significantly enhances randomness, and maintains the balanced distribution of 0s and 1s in the bit sequence.

[0127] Through the steps described above, this method fully utilizes the physical randomness of the cyclic trigger chain and combines it with the pseudo-random extension capability of the LFSR to generate high-quality random bit sequences. Tests show that the randomized enhanced bit sequences processed by this method can pass standard randomness tests such as NIST SP800-22, with entropy values ​​close to the theoretical maximum of 1, meeting the requirements of cryptography and information security for high-quality random numbers.

[0128] In one optional implementation, the randomized enhanced bit sequence is divided into multiple sequence segments using a fractal dimension segmentation algorithm. A local entropy value is calculated for each sequence segment, and adaptive crossover and recombination are performed based on the local entropy value to construct a physically unclonable sequence, including:

[0129] The scaling exponent of the range standard deviation and sequence length is calculated for the random enhanced bit sequence. The fractal dimension of the sequence is obtained by differentiating the scaling exponent. The sequence fluctuation curve is calculated based on the sequence fractal dimension. The inflection point of the sequence fluctuation curve is determined as the segmentation point. The random enhanced bit sequence is divided into multiple sequence segments based on the segmentation point.

[0130] The information entropy, conditional entropy, and approximate entropy are calculated for each sequence segment and combined to form a quality score for the sequence segment. The sequence segments are then sorted in descending order based on the quality scores.

[0131] The mutual information between the sequence segments is calculated, and the sequence segments are cross-recombined at the position where the mutual information is minimum to obtain a cross-recombined sequence. An adaptive mutation probability negatively correlated with the quality score is used to locally perturb the cross-recombined sequence. When the quality score of the cross-recombined sequence reaches a preset quality threshold, the physically unclonable sequence is obtained.

[0132] The randomly enhanced bit sequence is segmented into windows of different lengths, such as 8 bits, 16 bits, 32 bits, and 64 bits. For each window length, the standard deviation of the range (maximum value minus minimum value) of each window in the sequence is calculated. For example, the standard deviation is 2.35 for a window length of 8 bits, 3.47 for a window length of 16 bits, and 5.12 for a window length of 32 bits. A scatter plot is then plotted by taking the logarithm of these window lengths and their corresponding standard deviations, and the scaling exponent is obtained by fitting the plot using the least squares method.

[0133] The fractal dimension of the sequence is obtained by differentiating the scaling exponent. The sequence volatility curve is then calculated based on this fractal dimension. A piecewise regression method is used to calculate the volatility intensity at different scales. For example, the window size can be set from 4 to 128, with a step size of 4, to calculate the volatility intensity for each window size. For a window size of 4, the volatility intensity is 1.8; for a window size of 8, it is 2.6; and for a window size of 12, it is 3.2. These volatility intensity values ​​are then connected to form the volatility curve.

[0134] By calculating the rate of change of the slope of the fluctuation curve, the points where the slope changes the most are identified as inflection points. For example, three inflection points are identified on the fluctuation curve at positions 56, 128, and 203 of the original sequence. Using these inflection points as dividing points, the random-enhanced bit sequence is divided into multiple sequence segments.

[0135] For each sequence segment, calculate the information entropy, conditional entropy, and approximate entropy, and combine them to form the quality score of the sequence segment. Information entropy reflects the randomness of the sequence, conditional entropy represents the correlation between adjacent bits, and approximate entropy measures the complexity and irregularity of the sequence. For example, for the first segment, the calculated information entropy is 0.95, the conditional entropy is 0.92, and the approximate entropy is 0.88. A weighted average of these entropy values, such as weights of 0.4, 0.3, and 0.3, yields a quality score of 0.92 for this segment. Similarly, calculate the quality scores for other segments and sort them from highest to lowest score. The resulting sequence order after sorting is: Segment 3, Segment 1, Segment 4, Segment 2.

[0136] The mutual information between sequence segments is calculated. Mutual information represents the degree of information sharing between two segments; the smaller the mutual information, the lower the correlation between the two segments. By calculating the mutual information between adjacent segments, the position with the minimum mutual information is identified. For example, the mutual information between segments 1 and 4 is found to be 0.03, the mutual information between segments 4 and 2 is 0.08, and the mutual information between segments 2 and 3 is 0.05. Therefore, the mutual information between segments 1 and 4 is the minimum, and cross-recombination should be performed between these two segments.

[0137] The specific crossover and recombination operation involves selecting a portion of bits from these two sub-segments and swapping them. For example, bits 15 to 30 of sub-segment 1 are swapped with bits 10 to 25 of sub-segment 4 to form a new sequence arrangement, thus obtaining the crossover and recombination sequence combination.

[0138] The lower the quality score of a segment, the higher its mutation probability. For example, the mutation probability can be set to p = 0.1 × (1 - quality score). For a segment with a quality score of 0.92, the mutation probability is 0.008; while for a segment with a quality score of 0.75, the mutation probability is 0.025. Based on these mutation probabilities, certain bits in the sequence are randomly selected for bit flipping (0 becomes 1, 1 becomes 0) to achieve local perturbation.

[0139] The quality score of the perturbed sequence is recalculated. If it reaches a preset quality threshold (e.g., 0.95), the sequence is determined as the final physically unclonable sequence. If it does not reach the threshold, crossover and local perturbation continue until the condition is met. The final physically unclonable sequence is a bit sequence like "10101101011001001111010001101010111000101".

[0140] The physically unclonable sequences constructed using the above methods possess high randomness, unpredictability, and non-replicability, making them suitable for security scenarios such as device authentication and key generation, effectively enhancing the security performance of information systems.

[0141] This invention provides a system for generating physically unclonable sequences based on static memory, the system comprising:

[0142] The first unit is used to sequentially select each memory cell in the memory cell array of the static memory through a row and column address decoder, apply pulse voltage stress to the selected memory cell, and use an analog front-end circuit to collect the transient response signal of the memory cell under the pulse voltage stress, and use the time-domain characteristic parameters of the transient response signal as the physical fingerprint feature of the memory cell.

[0143] The second unit is used to construct a feature parameter matrix based on the physical fingerprint features and perform multi-scale decomposition. Based on the information entropy criterion, the feature components of the optimal decomposition level are selected and divided into a bimodal distribution through a dynamic clustering method. The bit sequence is generated based on the distance between the two peaks as the decision threshold.

[0144] The third unit is used to form a cyclic trigger chain by connecting an odd number of signal inversion modules in a ring. It constructs an independent operating environment for the cyclic trigger chain and deploys it in the static memory. It uses the oscillation period of the cyclic trigger signal of the cyclic trigger chain as a random seed to generate a perturbation sequence. By performing an XOR operation between the perturbation sequence and the bit sequence, the randomness of the bit sequence is enhanced to obtain a random enhanced bit sequence.

[0145] The fourth unit is used to divide the randomized enhanced bit sequence into multiple sequence segments using a fractal dimension segmentation algorithm, calculate the local entropy value for each sequence segment, and perform adaptive crossover and recombination based on the local entropy value to construct a physically unclonable sequence.

[0146] A third aspect of the present invention provides an electronic device, comprising:

[0147] processor;

[0148] Memory used to store processor-executable instructions;

[0149] The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0150] A fourth aspect of the present invention provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0151] This invention can be a method, apparatus, system, and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention.

[0152] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating physically unclonable sequences based on static memory, characterized in that, include: In the storage cell array of the static memory, each storage cell is sequentially selected by a row and column address decoder, and a pulse voltage stress is applied to the selected storage cell. The transient response signal of the storage cell under the pulse voltage stress is acquired using an analog front-end circuit, and the time-domain characteristic parameters of the transient response signal are used as the physical fingerprint characteristics of the storage cell. Based on the physical fingerprint features, a feature parameter matrix is ​​constructed and multi-scale decomposition is performed. The feature components of the optimal decomposition level are selected based on the information entropy criterion and divided into a bimodal distribution using a dynamic clustering method. A bit sequence is generated based on the distance between the two peaks as a decision threshold, including: The physical fingerprint features of all storage units are used to construct the feature parameter matrix according to the physical location of the storage units, and each row of the feature parameter matrix corresponds to one physical fingerprint feature. A two-dimensional discrete wavelet transform is performed on the feature parameter matrix to obtain multiple decomposition levels. The discreteness of each decomposition level is calculated, and the decomposition level with the largest discreteness is selected as the optimal decomposition level. The coefficient matrix of the optimal decomposition level is extracted as the feature component. The feature components are clustered using a binary K-means clustering algorithm to obtain two cluster centers. The elements in the feature components are assigned to the nearest cluster center to form a cluster subset. New cluster centers are calculated based on the cluster subsets. The clustering is iterated until the cluster centers converge to obtain a bimodal distribution of the feature components. The distance between the peaks in the bimodal distribution is calculated as the decision threshold. Elements in the feature components that are greater than the decision threshold are quantized to 1, and elements in the feature components that are less than or equal to the decision threshold are quantized to 0, thereby generating the binarized bit sequence. An odd number of signal inversion modules are connected in a ring to form a cyclic trigger chain. An independent operating environment is built for the cyclic trigger chain and deployed in the static memory. The oscillation period of the cyclic trigger signal of the cyclic trigger chain is used as a random seed to generate a perturbation sequence. The randomness of the bit sequence is enhanced by performing an XOR operation between the perturbation sequence and the bit sequence to obtain a random enhanced bit sequence. The randomized enhanced bit sequence is divided into multiple sequence segments using a fractal dimension segmentation algorithm. A local entropy value is calculated for each sequence segment, and adaptive crossover and recombination are performed based on the local entropy value to construct a physically unclonable sequence.

2. The method according to claim 1, characterized in that, In the static memory's cell array, each memory cell is sequentially selected via a row and column address decoder. Applying pulse voltage stress to the selected memory cells includes: A gating sequence is generated based on the row and column structure of the storage cell array, and the gating sequence ensures that the storage cell in each gating operation is in the same row or column as the storage cell in the previous gating operation in terms of physical location. In the storage cell array, the target storage cell to be selected and the buffer storage cells around the target storage cell are constructed as a storage cell gating window. The storage cell gating window is slid in the storage cell array according to the gating sequence, and the target storage cell is sequentially assigned to each storage cell in the gating sequence. Based on the row address and column address of the target memory cell, a row strobe signal and a column strobe signal are generated in the row and column address decoder, respectively. The row strobe signal and the column strobe signal are applied to the row line and column line of the target memory cell to complete the selection of the target memory cell. Set a time interval greater than the memory cell recovery time between adjacent gating operations; In the strobed state, a pulse voltage stress greater than the standard operating voltage is applied to the target memory cell, and the charge accumulation effect between the target memory cell and the buffer memory cell is eliminated within the time interval.

3. The method according to claim 1, characterized in that, The transient response signal of the storage cell under the pulse voltage stress is acquired using an analog front-end circuit, and the time-domain characteristic parameters of the transient response signal are used as the physical fingerprint characteristics of the storage cell, including: Design a transimpedance amplifier for current-to-voltage conversion, and construct the analog front-end circuit using the transimpedance amplifier, feedback resistor, and compensation capacitor; After the pulse voltage stress is applied to the storage cell, the analog front-end circuit amplifies the signal and compensates the bandwidth through the feedback resistor and the compensation capacitor, and collects the generated transient current signal. The transient current signal is converted into a voltage signal by the transimpedance amplifier to obtain the transient response signal. The transient response signal is input to a bandpass filter circuit for filtering. The bandpass filter circuit filters out noise and interference components outside the operating frequency band in the transient response signal to obtain the filtered transient response signal. The rise time parameter, peak amplitude parameter, and peak time parameter of the filtered transient response signal from the initial value to the peak value are extracted, and the decay time constant parameter of the filtered transient response signal is extracted based on exponential fitting. The rise time parameter, the peak amplitude parameter, the peak time parameter, and the decay time constant parameter are combined to form a time-domain feature vector, which is then used as the physical fingerprint feature of the storage unit.

4. The method according to claim 1, characterized in that, A cyclic trigger chain is formed by connecting an odd number of signal inversion modules in a ring. Constructing an independent operating environment for the cyclic trigger chain and deploying it to the static memory includes: The signal inversion module is configured as a program component with bidirectional triggering function. In an odd number of program components, the output terminal of each program component is logically connected to the input terminal of the next program component in sequence. The bidirectional triggering function is used to randomly flip signals between adjacent program components to form the cyclic triggering chain. A resource isolation component is configured in the static memory, and a buffer is used to establish a connection between the resource isolation component and the loop trigger chain and isolate external influences on the loop trigger chain. The resource isolation component provides an independent operating environment for the loop trigger chain. The system clock signal is input to the cyclic trigger chain to obtain the cyclic trigger signal. The cyclic trigger chain is logically connected to the scheduling module of the static memory through the signal distribution module. The cyclic trigger signal is distributed to each of the scheduling modules through the signal distribution module to obtain the static memory where the cyclic trigger chain is deployed.

5. The method according to claim 1, characterized in that, Using the oscillation period of the cyclic trigger signal of the cyclic trigger chain as a random seed to generate a perturbation sequence, and enhancing the randomness of the bit sequence by performing an XOR operation between the perturbation sequence and the bit sequence, a random enhanced bit sequence is obtained, comprising: The oscillation period is obtained by calculating the time interval between two adjacent rising edges of the cyclic trigger signal; The difference between two adjacent oscillation periods is calculated to obtain a period difference value. The period difference value is then binary quantized to obtain a binary sequence containing multiple binary bits. Each preset number of binary bits is grouped into a group, and a random seed value is obtained by performing a shift and accumulation operation on each group of binary bits. The random seed values ​​are combined in the order of generation to form a random seed sequence. The random seed sequence is input into a linear feedback shift register. The first and second bits of the random seed sequence are used to select the tap position of the linear feedback shift register. The last bit of the random seed sequence is used to set the feedback coefficient of the linear feedback shift register. The perturbation sequence is output through the linear feedback shift register. The randomized enhanced bit sequence is obtained by performing an XOR operation between each bit in the perturbation sequence and the corresponding bit in the bit sequence.

6. The method according to claim 1, characterized in that, The randomized enhanced bit sequence is divided into multiple sequence segments using a fractal dimension segmentation algorithm. A local entropy value is calculated for each sequence segment. Based on the local entropy value, adaptive crossover and recombination are performed to construct a physically unclonable sequence, including: The scaling exponent of the range standard deviation and sequence length is calculated for the random enhanced bit sequence. The fractal dimension of the sequence is obtained by differentiating the scaling exponent. The sequence fluctuation curve is calculated based on the sequence fractal dimension. The inflection point of the sequence fluctuation curve is determined as the segmentation point. The random enhanced bit sequence is divided into multiple sequence segments based on the segmentation point. The information entropy, conditional entropy, and approximate entropy are calculated for each sequence segment and combined to form a quality score for the sequence segment. The sequence segments are then sorted in descending order based on the quality scores. The mutual information between the sequence segments is calculated, and the sequence segments are cross-recombined at the position where the mutual information is minimum to obtain a cross-recombined sequence. An adaptive mutation probability negatively correlated with the quality score is used to locally perturb the cross-recombined sequence. When the quality score of the cross-recombined sequence reaches a preset quality threshold, the physically unclonable sequence is obtained.

7. A system for generating physically unclonable sequences based on static memory, used to implement the method as described in any one of claims 1-6, characterized in that, include: The first unit is used to sequentially select each memory cell in the memory cell array of the static memory through a row and column address decoder, and apply pulse voltage stress to the selected memory cell; The transient response signal of the storage cell under the pulse voltage stress is acquired using an analog front-end circuit, and the time-domain characteristic parameters of the transient response signal are used as the physical fingerprint characteristics of the storage cell. The second unit is used to construct a feature parameter matrix based on the physical fingerprint features and perform multi-scale decomposition. Based on the information entropy criterion, the feature components of the optimal decomposition level are selected and divided into a bimodal distribution through a dynamic clustering method. The bit sequence is generated based on the distance between the two peaks as the decision threshold. The third unit is used to form a cyclic trigger chain by connecting an odd number of signal inversion modules in a ring. It constructs an independent operating environment for the cyclic trigger chain and deploys it in the static memory. It uses the oscillation period of the cyclic trigger signal of the cyclic trigger chain as a random seed to generate a perturbation sequence. By performing an XOR operation between the perturbation sequence and the bit sequence, the randomness of the bit sequence is enhanced to obtain a random enhanced bit sequence. The fourth unit is used to divide the randomized enhanced bit sequence into multiple sequence segments using a fractal dimension segmentation algorithm, calculate the local entropy value for each sequence segment, and perform adaptive crossover and recombination based on the local entropy value to construct a physically unclonable sequence.

8. An electronic device, characterized in that, include: processor; Memory used to store processor-executable instructions; The processor is configured to invoke instructions stored in the memory to execute the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having computer program instructions stored thereon, characterized in that, When the computer program instructions are executed by the processor, they implement the method described in any one of claims 1 to 6.

Images