Method and device for counting number of transistors in chip
By analyzing the circuit description language file and the functional module hierarchy, and combining it with consistency checks, the number of transistors in the target chip can be accurately counted, solving the problem of statistical error in the prior art and achieving high-precision and high-efficiency transistor count.
Patent Information
- Application Number
- CN202511233244.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-29
- Publication Date
- 2025-12-30
AI Technical Summary
Existing methods for counting transistors contain errors and cannot accurately reflect the actual number of transistors in different types of standard cells. Furthermore, the extra area caused by design factors during the placement and routing process is miscalculated, affecting the accuracy of the statistics.
By parsing the circuit description language file, the number of transistors in each type of standard cell is counted. Combined with the functional module hierarchy, the number of transistors in the target chip is determined by traversing level by level. Consistency checks are used to ensure the consistency between the layout and the circuit description language file, thus avoiding design errors.
It improves the accuracy and universality of transistor count statistics, reduces redundant calculations, enhances statistical efficiency and accuracy, and adapts to the design requirements of different types of standard cells.
Smart Images
Figure CN121234903A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a method and apparatus for counting the number of transistors in a chip. Background Technology
[0002] In the field of integrated circuit technology, the number of transistors is a core indicator for measuring chip performance, process technology advancements, and design complexity, and its accurate statistics are of paramount importance. Existing technologies use the area of the least-input NAND gate in a standard cell as the unit of measurement to count the number of transistors. The specific steps are as follows: determine the area of the least-input NAND gate (which consists of 2 PMOS (P-type metal-oxide-semiconductor field-effect transistors) and 2 NMOS (N-type metal-oxide-semiconductor field-effect transistors); calculate the total area of all standard cells; determine the number of gates by dividing the total area of the standard cells by the area of the least-input NAND gate; and the number of transistors is then calculated by multiplying the number of gates by 4.
[0003] However, the transistor count calculated using the aforementioned statistical methods has significant errors. Firstly, the area ratio between different types of standard cells and least-input NAND gates is not fixed. Complex standard cells, such as flip-flops and multiplexers, have areas much larger than least-input NAND gates. Simply converting based on area ratios leads to errors in gate count estimation, thus affecting the accuracy of transistor counts. Secondly, during placement and routing, additional area is generated due to design factors such as routing channels and isolation regions. This area does not actually contain effective transistors but is included in the total area of standard cells in the calculation, further amplifying the error.
[0004] Therefore, the related technologies suffer from the problem of low accuracy in counting the number of transistors in the target chip. Summary of the Invention
[0005] To address the aforementioned technical problems, this application proposes a method and apparatus for counting the number of transistors in a chip.
[0006] To address the aforementioned technical problems, this application proposes a method for counting the number of transistors in a chip, the method comprising:
[0007] Determine the number of transistors in each type of standard cell in the target chip;
[0008] Obtain the functional module hierarchy structure in the target chip, wherein there is a parent-child relationship between adjacent upper and lower layers of the functional module hierarchy structure, and each functional module in the last layer consists of a standard unit;
[0009] The number of transistors in the last layer functional module is determined based on the number of transistors corresponding to the type of standard unit in the last layer functional module.
[0010] Based on the hierarchical parent-child relationship of the functional module hierarchy and the number of transistors in the last layer of functional modules, the number of transistors in each layer of functional modules is traversed upwards until the number of transistors in the target chip is determined.
[0011] This includes determining the number of transistors in various types of standard cells within the target chip, including:
[0012] Obtain a circuit description language file, wherein the circuit description language file is used to describe the circuit structure of all types of standard cells in the target chip;
[0013] Based on preset characters, the description language of each type of standard unit is searched in the circuit description language file;
[0014] The number of transistors corresponding to each type of standard cell is determined based on the description language.
[0015] By directly parsing the description language of standard cells in the circuit description language file, the actual number of transistors in each standard cell can be accurately counted. This method is applicable to the differences in the number of transistors in different types of standard cells. It is especially effective for standard cells with special designs, such as standard cells with large area and few single transistors or small area but many transistors. The method can still maintain statistical accuracy. By parsing the description language of standard cells, the accuracy and universality of transistor count statistics are improved.
[0016] The determination of the number of transistors corresponding to each type of standard cell based on the description language includes:
[0017] For each type of standard cell in the target chip, count the first number of occurrences of the first description language and the second number of occurrences of the second description language in the description language corresponding to the current type of standard cell;
[0018] The number of transistors corresponding to the standard cell of the current type is determined based on the first quantity and the second quantity.
[0019] By counting the number of occurrences of a specific descriptive element (first descriptive language and second descriptive language) in the statistical descriptive language, the cumulative number of occurrences of the specific descriptive element can be used to determine the number of transistors in the standard cell. This allows for the rapid extraction of the number of transistors in each type of standard cell, improving the statistical efficiency of transistor count.
[0020] By listing logic units with timing definitions separately in the transistor report, the number of transistors in the logic unit is represented more intuitively, which helps in evaluating the performance of the target chip based on the transistor report.
[0021] Determining the number of transistors in various types of units in the target chip further includes:
[0022] Based on the layout of the target chip and the circuit description language file of the target chip, a consistency check is performed on the target chip to obtain a consistency file;
[0023] The number of transistors for each type of cell is determined based on the consistency document.
[0024] Consistency checks ensure the consistency between the layout and the circuit description language file, determine the number of transistors in various standard cells, and avoid statistical deviations in the number of transistors caused by designers misplacing standard cells during the design process, thereby further improving the accuracy of transistor count statistics.
[0025] The process of obtaining the functional module hierarchy structure in the target chip includes:
[0026] Starting from the top-level functional module, iterate through the composition of all functional modules in each layer in turn;
[0027] When traversing to a level where all functional modules consist of a standard unit, it is determined that the last level of the target chip has been traversed, and the traversal result is obtained.
[0028] The hierarchical structure of the functional modules is determined based on the traversal results.
[0029] By traversing the target chip level by level and constructing a complete hierarchical structure between functional modules based on the parent-child relationship between functional modules and the next level functional modules during the traversal, the system can ensure the completeness of the hierarchical structure identification of the chip functional modules. Moreover, the level-by-level traversal has no redundancy and effectively reduces the computational resources consumed.
[0030] After determining the number of transistors in the target chip, the method further includes:
[0031] Obtain the first failure rate of a single transistor;
[0032] For each functional module in each layer, the overall failure rate of each functional module is determined based on the first failure rate and the transistors of the corresponding functional module.
[0033] By obtaining the failure rate parameter of a single transistor, i.e., the first failure rate, and combining it with the number of transistors in a functional module, such as through weighted calculation, the overall failure rate of each functional module can be obtained. Calculating the failure rate of functional modules helps to improve the accuracy of functional safety analysis.
[0034] The method for counting the number of transistors in the chip further includes:
[0035] The number of transistors in the target chip that match the preset type of standard unit is recorded in the transistor report, wherein the standard unit that matches the preset type includes at least one of the following: register, clock gating unit, and logic gate unit.
[0036] To address the aforementioned technical problems, this application also proposes a transistor count device in a chip, the transistor count device comprising: a first determining unit, used to determine the number of transistors in various types of standard units in a target chip;
[0037] The acquisition unit is used to acquire the functional module hierarchy structure in the target chip, wherein there is a parent-child relationship between adjacent upper and lower layers of the functional module hierarchy structure, and each functional module in the last layer is composed of a standard unit.
[0038] The second determining unit is used to determine the number of transistors in the last layer functional module based on the number of transistors corresponding to the type of standard unit of the last layer functional module.
[0039] The traversal unit is used to traverse upwards the number of transistors in each functional module according to the hierarchical parent-child relationship of the functional module hierarchy and the number of transistors in the last functional module, until the number of transistors in the target chip is determined.
[0040] To address the aforementioned technical problems, this application also proposes another transistor count device in a chip, comprising a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the transistor count method in the chip as described above.
[0041] To address the aforementioned technical problems, this application also proposes a computer storage medium / computer program product, wherein the computer storage medium is used to store a computer program, and the computer program product includes a computer program, which, when executed by a computer, is used to implement the method for counting the number of transistors in a chip as described above.
[0042] Compared with the prior art, the beneficial effects of this application are: by counting the number of transistors in each type of standard unit and combining it with the functional module hierarchy, the number of transistors is calculated backward from the last level until the number of transistors in the target chip is determined. This allows for accurate counting of the number of transistors in the target chip and can be adapted to the design of different types of standard units in the target chip, such as standard units with large area and few single transistors or small area but many transistors. Compared with the related technologies that use area conversion to calculate the number of transistors, the embodiments of this application improve the statistical accuracy of the number of transistors, and avoid repeated calculation of the number of transistors by traversing the functional module hierarchy level by level, thus reducing data redundancy. Attached Figure Description
[0043] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0044] in:
[0045] Figure 1 This is a flowchart illustrating the method for counting the number of transistors in a chip provided in this application;
[0046] Figure 2 This is a schematic diagram of the description language for a type of standard unit provided in this application;
[0047] Figure 3 This is a schematic diagram of the hierarchical structure of functional modules in one embodiment provided in this application;
[0048] Figure 4 This is a schematic diagram of the hierarchical structure of the functional modules provided in this application;
[0049] Figure 5 This is a schematic diagram showing the number of transistors provided in this application;
[0050] Figure 6 This is a flowchart illustrating the process of capturing the hierarchical structure of the functional modules provided in this application;
[0051] Figure 7 This is a schematic diagram of an embodiment of the transistor count device in a chip provided in this application;
[0052] Figure 8 This is a schematic diagram of another embodiment of the transistor count device in the chip provided in this application;
[0053] Figure 9This is a schematic diagram of the structure of an embodiment of the computer storage medium / computer program product provided in this application. Detailed Implementation
[0054] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0055] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0056] Please see Figure 1 , Figure 1 This is a flowchart illustrating the method for counting the number of transistors in a chip provided in this application, as shown below. Figure 1 As shown, the specific steps are as follows:
[0057] Step S11: Determine the number of transistors for each type of standard cell in the target chip. In this embodiment, for the standard cells that may be used in the target chip, determine the number of transistors for each type of standard cell. Different types of standard cells are composed of different numbers of transistors. For example, AND gates and OR gates are different types of standard cells. An AND gate is composed of 2 transistors, while an OR gate is composed of 3 transistors.
[0058] In an optional embodiment, determining the number of transistors for various types of standard cells in a target chip includes: acquiring a circuit description language file, wherein the circuit description language file is used to describe the circuit structure of all types of standard cells in the target chip; searching for the description language for each type of standard cell in the circuit description language file based on preset characters; and determining the number of transistors corresponding to each type of standard cell based on the description language.
[0059] In this embodiment, the number of transistors of various types is determined by a circuit description language file, which describes the circuit structure of all types of standard cells in the target chip.
[0060] The default characters include a header character and an end character. The description language for each type of standard cell begins with the header character and ends with the end character. The content between the header and end characters defines in detail the name of the standard cell, the names of the transistors in the standard cell, and their parameters. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of a description language for a type of standard unit provided in this application, such as... Figure 2 As shown, the header character is Subckt and the end character is .end. The descriptive language between the header and end characters is a specific description of the transistors in the standard cell, including the standard cell name, the type and name of each transistor (transistor 1, transistor 2... transistor n) in the standard cell, and the corresponding parameters (such as size parameters). The descriptive language of the standard cell is found using preset characters, and the number of transistors in each type of standard cell can be determined based on the descriptive language.
[0061] By directly parsing the description language of standard cells in the circuit description language file, the actual number of transistors in each standard cell can be accurately counted. This method is applicable to the differences in the number of transistors in different types of standard cells. It is especially effective for standard cells with special designs, such as standard cells with large area and few single transistors or small area but many transistors. The method can still maintain statistical accuracy. By parsing the description language of standard cells, the accuracy and universality of transistor count statistics are improved.
[0062] The method of determining the number of transistors corresponding to each type of standard unit based on the description language includes: for each type of standard unit in the target chip, counting the first number of occurrences of the first description language and the second number of occurrences of the second description language in the description language corresponding to the standard unit of the current type; and determining the number of transistors corresponding to the standard unit of the current type based on the first number and the second number.
[0063] In the embodiments of this application, please refer to Table 1, which shows the types of transistors in the standard cell.
[0064] Table 1
[0065] NMOS nch_mac, nch_hvt_mac, nch_lvt_mac, nch_uhvt_mac PMOS pch_mac, pch_hvt_mac, pch_lvt_mac, pch_uhvt_mac
[0066] The transistors in the standard cell are divided into PMOS and NMOS. PMOS is further divided into PMOS with parasitic parameters, high threshold voltage PMOS, low threshold voltage PMOS, and ultra-high threshold PMOS, which correspond to pch_mac, pch_hvt_mac, pch_lvt_mac, and pch_uhvt_mac in Table 1, respectively. Among them, pch_mac, pch_hvt_mac, pch_lvt_mac, and pch_uhvt_mac are all first description languages. NMOS is further divided into NMOS with parasitic parameters, high threshold voltage NMOS, low threshold voltage NMOS, and ultra-high threshold NMOS, which correspond to nch_mac, nch_hvt_mac, nch_lvt_mac, and nch_uhvt_mac in Table 1, respectively. Among them, nch_mac, nch_hvt_mac, nch_lvt_mac, and nch_uhvt_mac are all second description languages.
[0067] The number of times the first description language appears in the description language (i.e., the first quantity) and the number of times the second description unit appears (i.e., the second quantity) are counted. The sum of the first quantity and the second quantity is the number of transistors in the standard unit.
[0068] By counting the number of occurrences of a specific descriptive element (first descriptive language and second descriptive language) in the statistical descriptive language, the cumulative number of occurrences of the specific descriptive element can be used to determine the number of transistors in the standard cell. This allows for the rapid extraction of the number of transistors in each type of standard cell, improving the statistical efficiency of transistor count.
[0069] In another optional embodiment, determining the number of transistors for each type of unit in the target chip further includes: performing a consistency check on the target chip based on the layout of the target chip and the circuit description language file of the target chip to obtain a consistency file; and determining the number of transistors for each type of unit based on the consistency file.
[0070] In this embodiment of the application, a consistency file is obtained by performing a consistency check on the target chip, and the number of transistors of various types of units is extracted from the consistency file.
[0071] Layout Versus Schematic (LVS) is one of the core steps in physical verification in chip design. Its core objective is to ensure that the chip layout and schematic are completely consistent in terms of circuit connections, device composition, and parameters.
[0072] During the conformance check, the number of transistors in various standard cells is extracted from the layout, as well as the number of transistors in the circuit description language file of the schematic. The extracted transistor counts are placed in the conformance file. The number of transistors in standard cells is extracted using a preset command, which can be the ".hcell" (hierarchical cel) command.
[0073] Please refer to Table 2, which provides an example of the number of transistors in a standard cell in the conformance document.
[0074] Table 2
[0075] territory Circuit description language file Number of PMOS a a NMOS quantity b b
[0076] Table 2 shows one column representing the number of NMOS and PMOS transistors of the standard cell extracted from the layout, and the other column representing the number of NMOS and PMOS transistors of the standard cell extracted from the circuit description language file. If the data in the two columns are consistent, it means that the standard cell has passed the consistency check, and the number of transistors in the standard cell can be directly determined. If the data in the two columns are inconsistent, it is necessary to re-perform the consistency check or adjust the structure of the target chip to redetermine the number of transistors in the standard cell. For example, in Table 2, the number of PMOS transistors extracted from both the layout and the circuit description language file is 'a', and the number of NMOS transistors extracted from both the layout and the circuit description language file is 'b', then the number of transistors in the standard cell is a+b.
[0077] Through the above embodiments, consistency checks ensure the consistency between the layout and the circuit description language file, determine the number of transistors in various standard cells, avoid statistical deviations in the number of transistors due to errors in placing standard cells by designers during the design process, and further improve the accuracy of transistor count statistics.
[0078] Step S12: Obtain the functional module hierarchy structure in the target chip, wherein there is a parent-child relationship between adjacent upper and lower layers of the functional module hierarchy structure, and each functional module in the last layer consists of a standard unit.
[0079] In the embodiments of this application, the logical structure, i.e., the hierarchical structure of the functional modules of the target chip, generally presents a tree structure. Adjacent layers in the tree structure have a parent-child relationship. The top layer is the entire chip, and the bottom layer consists of functional modules directly composed of standard units. Please refer to [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic diagram of the functional module hierarchy in one embodiment provided in this application, such as... Figure 3As shown, the top layer is the overall chip L1, which includes two sub-functional modules, L2-1 and L2-2. L2-1 further includes two sub-functional modules, L3-1 and L3-2. L2-2 consists of a standard unit and has no further subdivisions. L3-1 and L3-2 also consist of a standard unit and have no further subdivisions.
[0080] In an optional embodiment, obtaining the functional module hierarchy structure in the target chip includes: starting from the top-level functional module, sequentially traversing the composition of all functional modules in each layer; when traversing to a layer where all functional modules are composed of a standard unit, determining that the last layer of the target chip has been traversed, and obtaining the traversal result; and determining the functional module hierarchy structure based on the traversal result.
[0081] In this embodiment of the application, the hierarchical structure of the target chip is obtained by hierarchical traversal. First, the traversal starts from the top-level functional module (first-level functional module). When traversing the top-level functional module, the sub-functional modules contained in the top-level functional module are obtained to obtain the second-level functional module. Then, the second-level functional module is traversed again to obtain the sub-functional modules of the second-level functional module to obtain the third-level functional module, and so on, until the last-level functional module is traversed.
[0082] When traversing to a certain functional module, it is determined whether all functional modules in that layer have corresponding sub-functional modules. If none of the functional modules in a certain layer have further sub-functional modules, that is, all functional modules in a certain layer are composed of a standard unit, then the functional module in that layer is the last functional module.
[0083] By traversing the target chip level by level and constructing a complete hierarchical structure between functional modules based on the parent-child relationship between functional modules and the next level functional modules during the traversal, the system can ensure the completeness of the hierarchical structure identification of the chip functional modules. Moreover, the level-by-level traversal has no redundancy and effectively reduces the computational resources consumed.
[0084] Step S13: Determine the number of transistors in the last layer functional module according to the number of transistors corresponding to the type of standard unit of the last layer functional module.
[0085] In this embodiment of the application, after obtaining the functional module hierarchy of the target chip, the number of transistors in each functional module in the last layer is first determined. Each functional module in the last layer is composed of a standard unit. The number of transistors in the functional module is determined according to the type of the standard unit corresponding to any functional module in the last layer.
[0086] Step S14: According to the hierarchical parent-child relationship of the functional module hierarchy and the number of transistors in the last layer of functional modules, traverse upwards to the number of transistors in each layer of functional modules until the number of transistors in the target chip is determined.
[0087] Based on the parent-child relationship in the functional module hierarchy, the number of transistors corresponding to each functional module in each layer is obtained by summarizing from the last layer to the top layer. When the sum is summarized, the number of transistors in the target chip is obtained.
[0088] By statistically analyzing the number of transistors in each type of standard cell and combining this with the functional module hierarchy, the number of transistors is calculated backward from the last level until the number of transistors in the target chip is determined. This method can accurately count the number of transistors in the target chip and is adaptable to the design of different types of standard cells in the target chip, such as standard cells with large area and few single transistors or small area but many transistors. Compared with related technologies that use area conversion to calculate the number of transistors, the embodiments of this application improve the statistical accuracy of the number of transistors, and avoid repeated calculation of the number of transistors by traversing the functional module hierarchy level by level, thus reducing data redundancy.
[0089] Please see Figure 4 , Figure 4 This is a schematic diagram of the hierarchical structure of the functional modules provided in this application, such as... Figure 4 As shown, the first layer (top layer) corresponds to an overall functional module of the target chip; the first set and the second set corresponding to the functional modules of the second layer are extracted from the functional modules of the first layer. The functional modules in the first set all correspond to the next layer sub-modules, and the functional modules in the second set are all composed of a standard unit and do not have a next layer sub-module.
[0090] From the first set of the functional modules in the second layer, further extract the first set and the second set corresponding to the functional modules in the third layer. Extract in sequence until only the second set is extracted and the first set is not extracted. Then the hierarchical structure of the functional modules corresponding to the entire target chip is obtained.
[0091] Please see Figure 5 , Figure 5 This is a schematic diagram showing the number of transistors provided in this application, such as... Figure 5 As shown, after obtaining the following Figure 4 After showing the functional module hierarchy, determine the number of transistors in each standard unit of the second set in the last layer; then feed the statistical data on the number of transistors in the last layer back to the previous layer. Figure 5In the first set of the third layer, the number of transistors of each sub-functional module in the first set of the third layer is obtained; then the number of transistors of each standard unit in the second set of the third layer is determined; the number of transistors of each sub-functional module in the first set of the third layer and the number of transistors of each standard unit in the second set of the third layer are fed back to the second layer to obtain the number of transistors of each sub-functional module in the first set of the second layer; and so on, until fed back to the first layer to obtain the number of transistors of the target chip.
[0092] In an optional embodiment, after determining the number of transistors in the target chip, the method further includes: obtaining a first failure rate of a single transistor; and for each functional module in each layer, determining the overall failure rate of each functional module based on the first failure rate and the number of transistors in the corresponding functional module.
[0093] In this embodiment, the failure rate parameter of a single transistor, i.e., the first failure rate, is obtained and combined with the number of transistors in the functional module for calculation, such as weighted calculation, to obtain the overall failure rate of each functional module. The calculation of the failure rate of the functional modules helps to improve the accuracy of functional safety analysis.
[0094] In the embodiments of this application, please refer to Table 3 for the transistor count of each functional module. Table 3 records the transistor count of functional modules at different levels in the target chip.
[0095] Table 3
[0096] Functional module name Number of transistors Number of doors L1 800 200 L2-1 400 100 L3-1 200 50 L3-2 200 50 L2-2 400 100
[0097] As shown in Table 3, when counting the number of transistors in each functional module, the number of gates in each functional module can also be counted. Specifically, the number of gates in a functional module can be obtained by dividing the number of transistors in that functional module by 4.
[0098] In an optional embodiment, the method for counting the number of transistors in the chip further includes: recording the number of transistors in standard units matching a preset type in the target chip in a transistor report, wherein the standard units matching the preset type include at least one of the following: registers, clock gating units, and logic gate units.
[0099] In the embodiments of this application, after counting the number of transistors in various types of standard units, the standard units contained in the physical design of the target chip need to be classified. There are many types, generally divided into physical units and logic units.
[0100] Physical cells refer to units that do not have logical functions. They are usually used as boundary isolation cells, capacitor cells, physical fill cells, etc. Boundary isolation cells are cells that exist in chip design to avoid design rule violations. Capacitor cells help improve the voltage drop of the chip. Physical fill cells are used to fill specific spaces in the chip.
[0101] After determining the number of transistors in various types of standard cells in the target chip, the number of transistors in various types of standard cells is recorded in the transistor report. Physical cells do not constitute functional modules at each level in the target chip. Therefore, the number of transistors in physical cells is not counted when performing transistor count statistics, and physical cells are filtered out from the captured report.
[0102] Each standard unit is denoted as the target unit. The timing information of the target unit is captured by the tool. If a timing definition exists, it is considered a logical unit; if no timing information exists, it is considered a physical unit.
[0103] The transistor report records logic gates, registers, and clock gating units. Logic gates include non-buffered units and large macrocells. Buffers added during the physical design phase have a single function, serving as signal relays and do not affect the logic design. A pair of inverters is equivalent to one buffer, so non-buffered units that do not contain inverters in the design are recorded in the transistor report. The transistor count information for registers and clock gating units is an indicator for evaluating the performance of the corresponding statistical modules, and therefore needs to be recorded in the transistor report.
[0104] In addition, although the memory in the target chip is large in size, similar to a macrocell, the memory function is the same as a register. In some cases, the memory will be replaced by a register array. Therefore, the memory will be listed separately in the transistor report in the design report, and the corresponding bit width indicating the storage capacity will be marked.
[0105] In this embodiment, logic units with timing definitions are listed separately in the transistor report, making the representation of the number of transistors in the logic unit more intuitive and helping to evaluate the performance of the target chip based on the transistor report.
[0106] Please see Figure 6 , Figure 6 This is a flowchart illustrating the hierarchical structure capture of the functional modules provided in this application, such as... Figure 6 As shown, it includes:
[0107] Step S21: Traverse each functional module in the functional module hierarchy of the target chip;
[0108] Step S22: Does the currently traversed functional module only include standard units? If yes, proceed to step S23; otherwise, proceed to step S24.
[0109] Step S23: Backtrack the number of transistors of the currently traversed functional module to the previous level, and then execute step S21.
[0110] Step S24: Calculate the number of transistors in all standard units in the second set of the current functional module, and then execute step S21.
[0111] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.
[0112] To implement the transistor count method described above, this application also proposes another transistor count device for chips, which can be found in the details below. Figure 7 , Figure 7 This is a schematic diagram of an embodiment of the transistor count device in a chip provided in this application.
[0113] The transistor count device 500 in this embodiment includes:
[0114] The first determining unit 51 is used to determine the number of transistors in various types of standard units in the target chip;
[0115] The acquisition unit 52 is used to acquire the functional module hierarchy structure in the target chip, wherein there is a parent-child relationship between adjacent upper and lower layers of the functional module hierarchy structure, and each functional module in the last layer is composed of a standard unit.
[0116] The second determining unit 53 is used to determine the number of transistors in the last layer functional module according to the number of transistors corresponding to the type of standard unit of the last layer functional module.
[0117] Traversal unit 54 is used to traverse upwards the number of transistors in each functional module according to the hierarchical parent-child relationship of the functional module hierarchy and the number of transistors in the last functional module, until the number of transistors in the target chip is determined.
[0118] The first determining unit 51 is further configured to acquire a circuit description language file, wherein the circuit description language file is used to describe the circuit structure of all types of standard units in the target chip; to search for the description language of each type of standard unit in the circuit description language file using preset characters; and to determine the number of transistors corresponding to each type of standard unit based on the description language.
[0119] The first determining unit 51 is further configured to, for each type of standard unit in the target chip, count the first number of occurrences of the first description language and the second number of occurrences of the second description language in the description language corresponding to the standard unit of the current type; and determine the number of transistors corresponding to the standard unit of the current type based on the first number and the second number.
[0120] The first determining unit 51 is further configured to perform a consistency check on the target chip based on the layout of the target chip and the circuit description language file of the target chip to obtain a consistency file; and determine the number of transistors of the various types of units according to the consistency file.
[0121] The acquisition unit 52 is further configured to start from the top-level functional module and sequentially traverse the composition of all functional modules in each layer; when traversing to a layer where all functional modules are composed of a standard unit, determine that the last layer of the target chip has been traversed and obtain the traversal result; and determine the functional module hierarchical structure based on the traversal result.
[0122] The transistor count device 500 further includes: a third determining unit, used to determine the number of transistors in the target chip, and then obtain the first failure rate of a single transistor; for each functional module in each layer, the unit determines the overall failure rate of each functional module based on the first failure rate and the number of transistors in the corresponding functional module.
[0123] The transistor count device 500 further includes: a recording unit, used to determine the function type of the current function module for each function module in each layer; and to record the current function module in the transistor count report if the function type matches a preset function type, wherein the preset function type includes at least one of the following: timing function, statistical function, and register function.
[0124] To implement the transistor count method described above, this application also proposes another transistor count device for chips, which can be found in the details below. Figure 8 , Figure 8 This is a schematic diagram of an embodiment of the transistor count device in a chip provided in this application.
[0125] The transistor count device 400 in this embodiment includes a processor 41, a memory 42, an input / output device 43, and a bus 44.
[0126] The processor 41, memory 42, and input / output device 43 are respectively connected to the bus 44. The memory 42 stores program data, and the processor 41 is used to execute the program data to implement the method for counting the number of transistors in the chip described in the above embodiment.
[0127] In this embodiment, processor 41 can also be referred to as a CPU (Central Processing Unit). Processor 41 may be an integrated circuit chip with signal processing capabilities. Processor 41 can also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor, or processor 41 can be any conventional processor.
[0128] This application also provides a computer storage medium / computer program product; please refer to the following: Figure 9 , Figure 9 This is a schematic diagram of an embodiment of the computer storage medium / computer program product provided in this application. The computer storage medium 600 is used to store a computer program 61. The computer program product 600 includes the computer program 61. When the computer program 61 is executed by a computer, it is used to implement the method for counting the number of transistors in the chip in the above embodiment.
[0129] When the embodiments of this application are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0130] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A method for counting the number of transistors in a chip, characterized in that, The method for counting the number of transistors in the chip includes: Determine the number of transistors in each type of standard cell in the target chip; Obtain the functional module hierarchy structure in the target chip, wherein there is a parent-child relationship between adjacent upper and lower layers of the functional module hierarchy structure, and each functional module in the last layer consists of a standard unit; The number of transistors in the last layer functional module is determined based on the number of transistors corresponding to the type of standard unit in the last layer functional module. Based on the hierarchical parent-child relationship of the functional module hierarchy and the number of transistors in the last layer of functional modules, the number of transistors in each layer of functional modules is traversed upwards until the number of transistors in the target chip is determined.
2. The method for counting the number of transistors in a chip according to claim 1, characterized in that, Determine the number of transistors in various types of standard cells in the target chip, including: Obtain a circuit description language file, wherein the circuit description language file is used to describe the circuit structure of all types of standard cells in the target chip; Based on preset characters, the description language of each type of standard unit is searched in the circuit description language file; The number of transistors corresponding to each type of standard cell is determined based on the description language.
3. The method for counting the number of transistors in a chip according to claim 2, characterized in that, Determining the number of transistors corresponding to each type of standard cell based on the description language includes: For each type of standard cell in the target chip, count the first number of occurrences of the first description language and the second number of occurrences of the second description language in the description language corresponding to the current type of standard cell; The number of transistors corresponding to the standard cell of the current type is determined based on the first quantity and the second quantity.
4. The method for counting the number of transistors in a chip according to claim 1, characterized in that, Determining the number of transistors in various types of units in the target chip also includes: Based on the layout of the target chip and the circuit description language file of the target chip, a consistency check is performed on the target chip to obtain a consistency file; The number of transistors for each type of cell is determined based on the consistency document.
5. The method for counting the number of transistors in a chip according to claim 1, characterized in that, Obtaining the functional module hierarchy structure in the target chip includes: Starting from the top-level functional module, iterate through the composition of all functional modules in each layer in turn; When traversing to a level where all functional modules consist of a standard unit, it is determined that the last level of the target chip has been traversed, and the traversal result is obtained. The hierarchical structure of the functional modules is determined based on the traversal results.
6. The method for counting the number of transistors in a chip according to claim 1, characterized in that, After determining the number of transistors in the target chip, the method further includes: Obtain the first failure rate of a single transistor; For each functional module in each layer, the overall failure rate of each functional module is determined based on the first failure rate and the transistors of the corresponding functional module.
7. The method for counting the number of transistors in a chip according to claim 1, characterized in that, The method for counting the number of transistors in the chip also includes: The number of transistors in the target chip that match the preset type of standard unit is recorded in the transistor report, wherein the standard unit that matches the preset type includes at least one of the following: register, clock gating unit, and logic gate unit.
8. A transistor count device in a chip, characterized in that, The transistor count device in the chip includes: The first determining unit is used to determine the number of transistors in various types of standard cells in the target chip; The acquisition unit is used to acquire the functional module hierarchy structure in the target chip, wherein there is a parent-child relationship between adjacent upper and lower layers of the functional module hierarchy structure, and each functional module in the last layer is composed of a standard unit. The second determining unit is used to determine the number of transistors in the last layer functional module based on the number of transistors corresponding to the type of standard unit of the last layer functional module. The traversal unit is used to traverse upwards the number of transistors in each functional module according to the hierarchical parent-child relationship of the functional module hierarchy and the number of transistors in the last functional module, until the number of transistors in the target chip is determined.
9. A device for counting the number of transistors in a chip, characterized in that, The transistor count device in the chip includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the method for counting the number of transistors in a chip as described in any one of claims 1 to 7.
10. A computer storage medium / computer program product, characterized in that, The computer storage medium is used to store a computer program, the computer program product including the computer program, which, when executed by a computer, is used to implement the method for counting the number of transistors in a chip as described in any one of claims 1 to 7.