Display panel and display device

Abstract

The invention relates to the technical field of display, and provides a display panel and a display device.The display panel comprises a substrate, a plurality of pixel driving circuits, a first grid line and a fourth grid line, orthographic projections of the pixel driving circuits on the substrate are distributed in an array mode in the first direction and the second direction, and the first direction and the second direction intersect; the pixel driving circuit comprises a driving transistor, a second transistor and a ninth transistor, a first electrode of the ninth transistor is connected with a grid electrode of the driving transistor, a second electrode of the ninth transistor is connected with a first electrode of the second transistor, and a second electrode of the second transistor is connected with a second electrode of the driving transistor; orthographic projections of the first grid lines on the substrate extend along a first direction, and the first grid lines are used for providing grid driving signals for second transistors in a plurality of pixel driving circuits distributed in the first direction; the orthographic projection of the fourth grid line on the substrate extends in the second direction, and the fourth grid line is used for providing grid driving signals for ninth transistors in a plurality of pixel driving circuits distributed in the second direction. According to the display panel, the refreshing frequency of the local display area can be adjusted.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, in order to improve the display effect of the display panel, the display panel has a high refresh rate. However, an excessively high refresh rate of the display panel will lead to excessive power consumption of the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0005] Substrate;

[0006] Multiple pixel driving circuits, wherein the orthographic projections of the multiple pixel driving circuits on the substrate are distributed in an array along a first direction and a second direction, the first direction and the second direction intersecting;

[0007] The pixel driving circuit includes a driving transistor, a second transistor, and a ninth transistor. The first terminal of the ninth transistor is connected to the gate of the driving transistor, the second terminal of the ninth transistor is connected to the first terminal of the second transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor.

[0008] A first gate line, whose orthogonal projection on the substrate extends along the first direction, is used to provide a gate drive signal to a second transistor in a plurality of pixel driving circuits distributed in the first direction.

[0009] A fourth gate line, whose orthogonal projection on the substrate extends along the second direction, is used to provide a gate drive signal to a ninth transistor in a plurality of pixel drive circuits distributed in the second direction.

[0010] In one exemplary embodiment of this disclosure, the display panel further includes:

[0011] A ninth active portion, wherein the ninth active portion is used to form the channel region of the ninth transistor;

[0012] The sixth conductive part is connected to a stable power supply terminal. The conductive layer where the sixth conductive part is located is located between the active layer where the ninth active part is located and the substrate. The orthographic projection of the sixth conductive part on the substrate and the orthographic projection of the ninth active part on the substrate at least partially overlap.

[0013] In one exemplary embodiment of this disclosure, the display panel further includes:

[0014] A shielding layer is located on one side of the substrate, and the shielding layer includes a first shielding portion;

[0015] A first active layer is located on the side of the shielding layer away from the substrate. The first active layer includes a third active portion, which is used to form the channel region of the driving transistor. The orthographic projection of the first shielding portion on the substrate and the orthographic projection of the third active portion on the substrate at least partially overlap.

[0016] The sixth conductive part is located in the shielding layer.

[0017] In one exemplary embodiment of this disclosure, the shielding layer further includes:

[0018] A second connecting portion is connected between two adjacent first blocking portions in the second direction;

[0019] The sixth conductive part is connected to the second connecting part, and the orthographic projection of the sixth conductive part on the substrate is located on the side of the orthographic projection of the second connecting part on the substrate in the first direction.

[0020] In one exemplary embodiment of this disclosure, the display panel further includes:

[0021] The second active portion is used to form the channel region of the second transistor;

[0022] A ninth active portion, wherein the ninth active portion is used to form the channel region of the ninth transistor;

[0023] The second active portion and the ninth active portion are located in the same active layer, and the area of ​​the orthographic projection of the ninth active portion on the substrate is smaller than the area of ​​the orthographic projection of the second active portion on the substrate.

[0024] In one exemplary embodiment of this disclosure, the length of the channel region of the ninth transistor is less than the length of the channel region of the second transistor;

[0025] And / or, the width of the channel region of the ninth transistor is smaller than the width of the channel region of the second transistor.

[0026] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, the first terminal of the first transistor being connected to a first initial signal line, and the second terminal of the first transistor being connected to the second terminal of the driving transistor. The display panel further includes:

[0027] The first active portion is used to form the channel region of the first transistor;

[0028] A ninth active portion, wherein the ninth active portion is used to form the channel region of the ninth transistor;

[0029] The first active portion and the ninth active portion are located in the same active layer, and the area of ​​the orthographic projection of the ninth active portion on the substrate is smaller than the area of ​​the orthographic projection of the first active portion on the substrate.

[0030] In one exemplary embodiment of this disclosure, the driving transistor and the ninth transistor are P-type transistors, and the display panel further includes:

[0031] A first active layer is located on one side of the substrate. The first active layer includes a third active portion and a ninth active portion. The third active portion is used to form the channel region of the driving transistor, and the ninth active portion is used to form the channel region of the ninth transistor.

[0032] In one exemplary embodiment of this disclosure, the driving transistor is a P-type transistor, the ninth transistor is an N-type transistor, and the display panel further includes:

[0033] A first active layer is located on one side of the substrate. The first active layer includes a third active portion, which is used to form the channel region of the driving transistor.

[0034] The second active layer is located on the side of the first active layer away from the substrate. The second active layer includes a ninth active portion, which is used to form the channel region of the ninth transistor.

[0035] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor and a fourth transistor. The first terminal of the first transistor is connected to a first initial signal line, the second terminal of the first transistor is connected to the second terminal of the driving transistor, the first terminal of the fourth transistor is connected to a data line, and the second terminal of the fourth transistor is connected to the first terminal of the driving transistor.

[0036] The display panel also includes:

[0037] A first reset signal line is located on one side of the substrate. The orthographic projection of the first reset signal line on the substrate extends along a first direction, and a portion of the structure of the first reset signal line is used to form the gate of the first transistor.

[0038] The second gate line is located on one side of the substrate, and the orthographic projection of the second gate line on the substrate extends along the first direction, and a portion of the structure of the second gate line is used to form the gate of the fourth transistor.

[0039] In the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first reset signal line on the substrate.

[0040] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fourth transistor, wherein the first terminal of the fourth transistor is connected to a data line, and the second terminal is connected to the first terminal of the driving transistor;

[0041] In the first direction of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor on the substrate is located between the orthographic projection of the channel region of the fourth transistor on the substrate and the orthographic projection of the channel region of the second transistor on the substrate.

[0042] In one exemplary embodiment of this disclosure, the length direction of the channel region of the second transistor is a second direction, and the length direction of the channel region of the ninth transistor is a first direction.

[0043] In one exemplary embodiment of this disclosure, the display panel further includes:

[0044] The first source / drain layer is located on one side of the substrate. The first source / drain layer includes a ninth bridging portion, which is connected to the first electrode of the ninth transistor and the gate of the driving transistor through vias.

[0045] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes a first power line, which is used to provide a high-level power signal to the pixel driving circuit.

[0046] The third source / drain layer is located on the side of the second source / drain layer away from the substrate, and the third source / drain layer includes the fourth gate line.

[0047] In one exemplary embodiment of this disclosure, the display panel further includes:

[0048] A first power line is used to provide a high-level power signal to the pixel driving circuit, and the orthographic projection of the first power line on the substrate extends along the second direction.

[0049] The orthographic projection of the fourth gate line on the substrate and the orthographic projection of the first power line on the substrate at least partially overlap.

[0050] In an exemplary embodiment of this disclosure, the first power line includes: a first extension and a second extension, wherein the size of the orthographic projection of the first extension onto the substrate in the first direction is greater than the size of the orthographic projection of the second extension onto the substrate in the first direction.

[0051] The orthographic projection of the fourth gate line on the substrate and the orthographic projection of the second extension on the substrate at least partially overlap.

[0052] In one exemplary embodiment of this disclosure, the display panel further includes:

[0053] A first power line is located on one side of the substrate. The first power line is used to provide a high-level power signal to the pixel driving circuit. The orthographic projection of the first power line on the substrate and the orthographic projection of the channel region of the ninth transistor on the substrate at least partially overlap.

[0054] In one exemplary embodiment of this disclosure, the display panel further includes:

[0055] A first source / drain layer is located on one side of the substrate. The first source / drain layer includes a second bridging portion and a ninth bridging portion. The second bridging portion is connected to the second terminal of the driving transistor and the second terminal of the second transistor through vias, respectively. The ninth bridging portion is connected to the first terminal of the ninth transistor and the gate of the driving transistor through vias, respectively.

[0056] The second source / drain layer is located on the side of the first source / drain layer away from the substrate. The second source / drain layer includes a first power line, which is used to provide a high-level power signal to the pixel driving circuit.

[0057] Wherein, the orthographic projection of the first power line on the substrate and the orthographic projection of the second bridging portion on the substrate at least partially overlap, and / or, the orthographic projection of the first power line on the substrate and the orthographic projection of the ninth bridging portion on the substrate at least partially overlap.

[0058] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, wherein a first terminal of the first transistor is connected to a first initial signal line, and a second terminal of the first transistor is connected to a second terminal of the driving transistor;

[0059] The display panel also includes:

[0060] The second bridging portion is located on one side of the substrate. The second bridging portion is connected to the second terminal of the driving transistor, the second terminal of the second transistor, and the second terminal of the first transistor through vias.

[0061] The first gate line includes a third extension and a fourth extension. The third extension is used to form the gate of the second transistor. The size of the orthogonal projection of the third extension on the substrate in the second direction is larger than the size of the orthogonal projection of the fourth extension on the substrate in the second direction.

[0062] The second bridging portion and the first gate line are located in different conductive layers. The second bridging portion includes a first sub-bridging portion. The orthographic projection of the first sub-bridging portion on the substrate extends along the second direction. The orthographic projection of the first sub-bridging portion on the substrate and the orthographic projection of the fourth extension portion on the substrate intersect.

[0063] In one exemplary embodiment of this disclosure, the second bridging portion further includes:

[0064] The second sub-bridge portion is connected to the second terminal of the first transistor via a via;

[0065] The third sub-bridge portion is connected to the second terminal of the second transistor and the second terminal of the driving transistor via a via;

[0066] Wherein, the first sub-bridging portion is connected between the second sub-bridging portion and the third sub-bridging portion, the angle between the orthographic projection of the first sub-bridging portion on the substrate and the orthographic projection of the second sub-bridging portion on the substrate is less than 180°, and the angle between the orthographic projection of the first sub-bridging portion on the substrate and the orthographic projection of the third sub-bridging portion on the substrate is less than 180°.

[0067] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is used to drive the light-emitting unit to emit light. The pixel driving circuit further includes:

[0068] A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal is connected to the second terminal of the driving transistor;

[0069] The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor.

[0070] The fifth transistor has its first terminal connected to the first power supply line and its second terminal connected to the first terminal of the driving transistor.

[0071] The sixth transistor has its first terminal connected to the second terminal of the driving transistor, and the second terminal connected to the light-emitting unit;

[0072] The seventh transistor has its first terminal connected to the second initial signal line and its second terminal connected to the light-emitting unit.

[0073] The eighth transistor has its first terminal connected to the third initial signal line and its second terminal connected to the first terminal of the driving transistor.

[0074] The capacitor has a first electrode connected to the gate of the driving transistor and a second electrode connected to the first power supply line.

[0075] Wherein, the first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, the second transistor is an N-type transistor, and the ninth transistor is either an N-type transistor or a P-type transistor.

[0076] In one exemplary embodiment of this disclosure, the pixel driving circuit includes P-type transistors and N-type transistors, and the display panel further includes:

[0077] A first active layer is located on one side of the substrate, and a portion of the structure of the first active layer is used to form the channel region of the P-type transistor in the pixel driving circuit.

[0078] A first gate layer is located on the side of the first active layer away from the substrate, and a portion of the structure of the first gate layer is used to form the gate of the P-type transistor in the pixel driving circuit.

[0079] The second gate layer is located on the side of the first gate layer away from the substrate, and a portion of the structure of the second gate layer is used to form the bottom gate of the N-type transistor in the pixel driving circuit.

[0080] The second active layer is located on the side of the second gate layer away from the substrate, and a portion of the structure of the second active layer is used to form the channel region of the N-type transistor in the pixel driving circuit.

[0081] The third gate layer is located on the side of the second active layer away from the substrate, and a portion of the structure of the third gate layer is used to form the top gate of the N-type transistor in the pixel driving circuit.

[0082] The first source / drain layer is located on the side of the third gate layer opposite to the substrate, and a portion of the structure of the first source / drain layer is used to form a bridging portion connecting different transistors.

[0083] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0084] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0085] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0086] Figure 1 This is a schematic diagram of the structure of a display panel in an exemplary embodiment of the related art;

[0087] Figure 2 A schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0088] Figure 3 for Figure 2 The timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown is as follows;

[0089] Figure 4 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;

[0090] Figure 5 This is a timing diagram of some signal lines in an exemplary embodiment of the display panel of this disclosure;

[0091] Figure 6 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0092] Figure 7 for Figure 6 Structural layout of the middle shielding layer;

[0093] Figure 8 for Figure 6 Structural layout of the first active layer;

[0094] Figure 9 for Figure 6 The structural layout of the first gate layer;

[0095] Figure 10 for Figure 6The structural layout of the second gate layer;

[0096] Figure 11 for Figure 6 Structural layout of the second active layer;

[0097] Figure 12 for Figure 6 The structural layout of the third gate layer;

[0098] Figure 13 for Figure 6 Structural layout of the first source / drain layer;

[0099] Figure 14 for Figure 6 Structural layout of the second source / drain layer;

[0100] Figure 15 for Figure 6 Structural layout of the third source / drain layer;

[0101] Figure 16 for Figure 6 Structural layout of the middle shielding layer and the first active layer;

[0102] Figure 17 for Figure 6 The structural layout of the middle shielding layer, the first active layer, and the first gate layer;

[0103] Figure 18 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer;

[0104] Figure 19 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer;

[0105] Figure 20 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer;

[0106] Figure 21 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer;

[0107] Figure 22 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer;

[0108] Figure 23 for Figure 6The diagram shows a partial sectional view of the display panel cut along the dashed line BB.

[0109] Figure 24 This is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the third gate layer in an exemplary embodiment of the display panel disclosed herein.

[0110] Figure 25 for Figure 24 The diagram shows the structural layout of the shielding layer in the display panel;

[0111] Figure 26 for Figure 24 The diagram shows the structural layout of the second gate layer in the display panel.

[0112] Figure 27 for Figure 24 The diagram shows the structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel.

[0113] Figure 28 This is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0114] Figure 29 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0115] Figure 30 for Figure 29 Structural layout of the middle shielding layer;

[0116] Figure 31 for Figure 29 Structural layout of the first active layer;

[0117] Figure 32 for Figure 29 The structural layout of the first gate layer;

[0118] Figure 33 for Figure 29 The structural layout of the second gate layer;

[0119] Figure 34 for Figure 29 Structural layout of the second active layer;

[0120] Figure 35 for Figure 29 The structural layout of the third gate layer;

[0121] Figure 36 for Figure 29 Structural layout of the first source / drain layer;

[0122] Figure 37 for Figure 29 Structural layout of the second source / drain layer;

[0123] Figure 38 for Figure 29 Structural layout of the third source / drain layer;

[0124] Figure 39 for Figure 29 Structural layout of the middle shielding layer and the first active layer;

[0125] Figure 40 for Figure 29 The structural layout of the middle shielding layer, the first active layer, and the first gate layer;

[0126] Figure 41 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer;

[0127] Figure 42 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer;

[0128] Figure 43 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer;

[0129] Figure 44 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer;

[0130] Figure 45 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer;

[0131] Figure 46 for Figure 29 The shown is a partial cross-sectional view of the display panel cut along the dashed line CC.

[0132] Figure 47 This is a cross-sectional view of another exemplary embodiment of the display panel disclosed herein;

[0133] Figure 48 This is a cross-sectional view of another exemplary embodiment of the display panel disclosed herein;

[0134] Figure 49 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein. Detailed Implementation

[0135] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0136] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0137] like Figure 1The diagram shown illustrates an exemplary embodiment of a display panel in the related art. The display panel may include a timing controller, a source driving circuit, a gate driving circuit, and a pixel array. The timing controller is connected to both the source driving circuit and the gate driving circuit. The source driving circuit is connected to multiple data lines (Da1 to Dan). The gate driving circuit includes a scan driving circuit and a light-emitting driving circuit. The scan driving circuit is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driving circuit is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. Each sub-pixel Pxij may include a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The pixel driving circuit may be connected to the scan signal lines, light-emitting signal lines, and data lines. The data lines can be used to provide the data signal terminals described above, and the light-emitting signal lines can be used to provide the enable signal terminals described above. This exemplary embodiment only shows one scan signal line connected to the pixel driving circuit. Each row of pixel driving circuits can be connected to multiple scan signal lines, which can be used to provide the first gate driving signal terminal, the second gate driving signal terminal, the first reset signal terminal, and the second reset signal terminal described above, respectively. In the exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the source driving circuit to the source driving circuit, provide clock signals, scan start signals, etc. of specifications suitable for the scan driving circuit to the scan driving circuit, and provide clock signals, emission stop signals, etc. of specifications suitable for the light-emitting driving circuit to the light-emitting driving circuit. The source driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data signals to be provided to the data lines Da1, Da2, Da3, ... and Dan. For example, the source driver circuit can sample grayscale values ​​using a clock signal and apply data signals corresponding to the grayscale values ​​to data lines Da1 to Dan in pixel rows, where n can be a natural number. The scan driver circuit can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from a timing controller. For example, the scan driver circuit can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting driver circuit can sequentially provide transmit signals with off-level pulses to light-emitting signal lines E1 to Eo.For example, the light-emitting driving circuit can be constructed as a shift register, and can generate a transmission signal by sequentially transmitting a transmit stop signal provided in the form of a cutoff level pulse to the next stage circuit under the control of a clock signal, where 0 can be a natural number. Thus, the display panel can achieve line-by-line scanning and driving.

[0138] This exemplary embodiment provides a pixel driving circuit, such as Figure 2 , 3 As shown, Figure 2 This is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure. Figure 3 for Figure 2 The timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown is illustrated.

[0139] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a capacitor C. Specifically, the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, the second terminal of the fourth transistor T4 is connected to the first terminal of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2. The first terminal of the fifth transistor T5 is connected to the first power supply terminal VDD, the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM. The gate of the driving transistor T3 is connected to node N. The second terminal of the second transistor T2 is connected to the second terminal of the driving transistor T3, and the gate of the second transistor T2 is connected to the first gate driving signal terminal G1. The first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor T3, the second terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7, and the gate of the sixth transistor T6 is connected to the enable signal terminal EM. The first terminal of the seventh transistor T9 is connected to the second power supply terminal G2. The initial signal terminal Vinit2 is connected to the gate of the seventh transistor T7, which is connected to the second reset signal terminal Re2. The first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3. The gate of the first transistor T1 is connected to the first reset signal terminal Re1. The first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, and the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3. The gate of the eighth transistor T8 is connected to the second reset signal terminal Re2. The first electrode of the ninth transistor T9 is connected to the gate of the driving transistor T3, and the second electrode of the ninth transistor T9 is connected to the first electrode of the second transistor T2. The gate of the ninth transistor T9 is connected to the fourth gate drive signal terminal G4. The first electrode of the capacitor C is connected to node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit L. The first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. Among them, the second transistor T2 and the ninth transistor T9 can be N-type transistors. For example, the second transistor T2 and the ninth transistor T9 can be N-type metal-oxide transistors. N-type transistors have smaller leakage current, which can reduce the leakage current of node N through the ninth transistor T9 and the second transistor T2 during the light-emitting stage.Meanwhile, the first transistor T1, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be P-type transistors. For example, driving transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, and eighth transistor T8 can be P-type low-temperature polysilicon transistors. P-type transistors have higher carrier mobility, which is beneficial for realizing display panels with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal, second initial signal terminal, and third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0140] like Figure 3 As shown, G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM. One driving cycle of this pixel driving circuit may include a first reset phase t1, a data writing phase t2, a second reset phase t3, and a light emission phase t4.

[0141] When the fourth gate drive signal terminal G4 turns on the ninth transistor T9:

[0142] In the first reset phase t1: the first gate drive signal terminal G1 outputs a high level, the first reset signal terminal Re1 outputs a low level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to node N through the first transistor T1 and the second transistor T2. In the data writing phase t2: the second gate drive signal terminal G2 outputs a low level signal, the first gate drive signal terminal G1 outputs a high level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal, and Vth is the threshold voltage of the driving transistor T3. In the second reset phase t3: the second reset signal terminal Re2 outputs a low level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit L, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. During the light-emitting stage t4: the enable signal terminal EM outputs a low-level signal, turning on the sixth transistor T6 and the fifth transistor T5. This drives the light-emitting unit to emit light under the compensation voltage Vdata+Vth stored in capacitor C, caused by the driving transistor T3. The formula for the output current of the driving transistor is as follows:

[0143] I = (μWCox / 2L)(Vgs-Vth)2

[0144] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit described above, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0145] When the fourth gate drive signal terminal G4 turns off the ninth transistor T9: the pixel drive circuit will not write the initial signal and new data signal to the drive transistor T3 during the scanning phase, and the gate of the drive transistor will maintain the voltage of the previous frame.

[0146] like Figure 4 The diagram shown is a structural schematic of an exemplary embodiment of the display panel of this disclosure. The display panel includes: a substrate, multiple pixel driving circuits P1-P9, multiple first gate lines G11-G13, and multiple fourth gate lines G41-G43. The orthographic projections of the multiple pixel driving circuits on the substrate are arrayed along a first direction X and a second direction Y. The first direction X and the second direction Y intersect; for example, the first direction X can be a row direction, and the second direction Y can be a column direction. The orthographic projections of the first gate lines on the substrate extend along the first direction, and the first gate lines are used to provide gate driving signals to second transistors in the multiple pixel driving circuits distributed along the first direction X. The orthographic projections of the fourth gate lines on the substrate extend along the second direction Y, and the fourth gate lines are used to provide gate driving signals to ninth transistors in the multiple pixel driving circuits distributed along the second direction Y.

[0147] It should be noted that, Figure 4 The display panel shown is illustrated using a nine-pixel driving circuit as an example. It should be understood that the display panel may include other numbers of pixel driving circuits, and correspondingly, the display panel may include other numbers of first gate lines and fourth gate lines.

[0148] like Figure 4As shown, the fourth gate line G41 controls the on / off state of the ninth transistor T9 in the pixel driving circuits P1, P4, and P7 distributed along the second direction Y; the fourth gate line G42 controls the on / off state of the ninth transistor T9 in the pixel driving circuits P2, P5, and P8 distributed along the second direction Y; and the fourth gate line G43 controls the on / off state of the ninth transistor T9 in the pixel driving circuits P3, P6, and P9 distributed along the second direction Y. If the fourth gate lines G41 and G43 control the ninth transistor T9 in the pixel driving circuits P1, P4, P7, P3, P6, and P9 to be turned off, the pixel driving circuits P1, P4, P7, P3, P6, and P9 will not write initial signals and new data signals to their driving transistor T3, and the gate of the driving transistor will maintain the voltage of the previous frame. The corresponding pixel driving circuits P1, P4, P7, P3, P6, and P9 can achieve low-frequency display. If the fourth gate line G42 controls the ninth transistor T9 in pixel driving circuits P2, P5, and P8 to turn on, then pixel driving circuits P2, P5, and P8 can normally write compensation voltage to the gate of the driving transistor. At this time, the refresh frequency of pixel driving circuits P2, P5, and P8 can be controlled by controlling the frequency of the gate driving signals output by the first gate lines G11, G12, and G13. For example, if the first gate line G11 outputs a conduction signal every frame, then pixel driving circuit P2 will refresh every frame; if the first gate line G12 outputs a conduction signal every 3 frames, then pixel driving circuit P5 will refresh every 3 frames. This method can control the refresh frequency of different pixel driving circuits by controlling the frequency of the conduction signals output by the fourth and first gate lines.

[0149] The display panel can also control the refresh rate of local areas through other driving methods. For example, the frequency of the output conduction signal of each first gate line can be the same. When the display panel scans each row of pixel driving circuits, different fourth gate lines can control the on / off state of the ninth transistor T9 connected to them, so as to control whether the pixel driving circuits of different areas write data signals. For example, during the scanning of pixel driving circuits P1, P2, and P3, the fourth gate line G41 can control the ninth transistor in pixel driving circuit P1 to turn on, the fourth gate line G42 can control the ninth transistor in pixel driving circuit P2 to turn on, and the fourth gate line G43 can control the ninth transistor in pixel driving circuit P3 to turn off. This allows pixel driving circuits P1 and P2 to be refreshed, while pixel driving circuit P3 is not refreshed. During the scanning of pixel driving circuits P4, P5, and P6, the fourth gate line G41 can control the ninth transistor in pixel driving circuit P4 to turn off, the fourth gate line G42 can control the ninth transistor in pixel driving circuit P5 to turn on, and the fourth gate line G43 can control the ninth transistor in pixel driving circuit P6 to turn off. This allows pixel driving circuit P5 to be refreshed, while pixel driving circuits P4 and P6 are not refreshed.

[0150] It should be understood that in other exemplary embodiments, the pixel driving circuit can also have other structures, as long as the pixel driving circuit includes a driving transistor T3, a second transistor T2, and a ninth transistor T9, with the first terminal of the ninth transistor connected to the gate of the driving transistor T3, the second terminal of the ninth transistor T9 connected to the first terminal of the second transistor T2, and the second terminal of the second transistor T2 connected to the second terminal of the driving transistor T3. In this exemplary embodiment, the refresh frequency of different areas of the display panel can be controlled by turning the ninth transistor T9 on and off. The second transistor T2 and the ninth transistor T9 can be either P-type transistors or N-type transistors.

[0151] Furthermore, in other exemplary embodiments, one or more of the first transistor T1, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may also be N-type transistors.

[0152] like Figure 5 The diagram shown is a timing diagram of some signal lines in an exemplary embodiment of the display panel of this disclosure. G4x is the timing diagram of the fourth gate line in the low refresh rate region, and G4y is the timing diagram of the fourth gate line in the high refresh rate region. In the low refresh rate region, the fourth gate line outputs an off signal in some frames and an on signal in others; in the high refresh rate region, the fourth gate line continuously outputs an on signal. When the ninth transistor T9 changes from the on state to the off state, the signal on the fourth gate line changes from a high level to a low level. Under the gate-source coupling of the ninth transistor T9, the gate of the driving transistor is pulled low, resulting in a screen splitting phenomenon where the brightness is high in the low refresh rate region and low in the high refresh rate region.

[0153] Of course, when the ninth transistor T9 is a P-type transistor, when the ninth transistor T9 changes from the on state to the off state, the signal on the fourth gate line will change from low level to high level. Under the gate-source coupling effect of the ninth transistor T9, the gate of the driving transistor will be pulled high, thus the same screen splitting phenomenon of low brightness in the low refresh area and high brightness in the high refresh area will occur.

[0154] It should be noted that the turn-off signal is the signal that turns off the target circuit. For example, the turn-off signal for a P-type transistor is a high-level signal, and the turn-off signal for an N-type transistor is a low-level signal. The turn-on signal is the signal that turns on the target circuit. For example, the turn-on signal for a P-type transistor is a low-level signal, and the turn-on signal for an N-type transistor is a high-level signal.

[0155] Based on this, this exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and a third source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. Figure 6-22As shown, Figure 6 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 7 for Figure 6 Structural layout of the middle shading layer, Figure 8 for Figure 6 The structural layout of the first active layer in the middle, Figure 9 for Figure 6 The structural layout of the first gate layer in the middle, Figure 10 for Figure 6 The structural layout of the second gate layer in the middle. Figure 11 for Figure 6 The structural layout of the second active layer in the middle. Figure 12 for Figure 6 The structural layout of the third gate layer in the middle, Figure 13 for Figure 6 The structural layout of the first source / drain layer in the middle. Figure 14 for Figure 6 Structural layout of the second source / drain layer. Figure 15 for Figure 6 Structural layout of the third source / drain layer in the middle. Figure 16 for Figure 6 The structural layout of the middle shielding layer and the first active layer. Figure 17 for Figure 6 The structural layout of the middle shielding layer, the first active layer, and the first gate layer. Figure 18 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer. Figure 19 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer. Figure 20 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer. Figure 21 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer. Figure 22 for Figure 6 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer. This display panel may include multiple... Figure 2 The pixel driving circuit shown has multiple pixel driving circuits arrayed in the first direction X and the second direction Y.

[0156] like Figure 6As shown, the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X. At least a portion of the structures of the first pixel driving circuit P1 and the second pixel driving circuit P2 may be mirror-symmetrically arranged with a mirror symmetry plane AA. The mirror symmetry plane AA may be perpendicular to the substrate. Furthermore, at least a portion of the orthographic projections of the first pixel driving circuit P1 and the second pixel driving circuit P2 on the substrate may be symmetrically arranged with the intersection of the mirror symmetry plane AA and the substrate as the axis of symmetry. The first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units arrayed in the first direction X and the second direction Y. The second direction Y and the first direction X may intersect; for example, the first direction X may be a row direction, and the second direction Y may be a column direction. In addition, in this exemplary embodiment, the display panel may have design errors and process errors, and the first pixel driving circuit P1 and the second pixel driving circuit P2 may be approximately mirror-symmetrical with respect to the mirror symmetry plane AA.

[0157] like Figure 6 , 7 As shown in Figure 16, the shielding layer includes a plurality of first shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the first shielding portions 81 are interconnected by a second connecting portion 82.

[0158] like Figure 6 , 8As shown in 16 and 17, the first active layer may include: a first active section 71, a third active section 73, a fourth active section 74, a fifth active section 75, a sixth active section 76, a seventh active section 77, an eighth active section 78, a twenty-first active section 721, a tenth active section 710, an eleventh active section 711, a twelfth active section 712, a thirteenth active section 713, a fourteenth active section 714, a fifteenth active section 715, a sixteenth active section 716, a seventeenth active section 717, and an eighteenth active section 718. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the twenty-first active portion 721 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 The 12th active section 712 is connected to both ends of the 8th active section 78; the 11th active section 711 is connected between the 4th active section 74 and the 3rd active section 73; the 13th active section 713 is connected to the side of the 4th active section 74 away from the 3rd active section 73; the 14th active section 714 is connected to the side of the 7th active section 77 away from the 6th active section 76; the 15th active section 715 is connected to the side of the 5th active section 75 away from the 3rd active section 73; the 16th active section 716 is connected between the 7th active section 77 and the 6th active section 76; and the 17th and 18th active sections 717 are connected to both ends of the 1st active section 71. The first active layer can be formed of polycrystalline silicon material, and correspondingly, the first transistor T1, the driving transistor T3, the 4th transistor T4, the 5th transistor T5, the 6th transistor T6, the 7th transistor T7, and the 8th transistor T8 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0159] The orthographic projection of the first shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The first shielding portion 81 can shield the third active portion 73 from light to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source. The shielding layer can also act as a signal shield for the pixel driving circuit.

[0160] like Figure 6 , 9 As shown in Figures 16 and 17, the first gate layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide... Figure 2The second gate drive signal terminal; the enable signal line EM can be used to provide Figure 2 The enable signal terminal; the first reset signal line Re1 can be used to provide Figure 2 The first reset signal terminal; the second reset signal line Re2 can be used to provide Figure 2 The second reset signal terminal is shown in the diagram. The orthographic projections of the second gate line G2, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate, and a portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate can cover the orthographic projection of the first active portion 71 on the substrate, and a portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 onto the substrate can cover the orthographic projections of the seventh active portion 77 and the eighth active portion 78 onto the substrate. A portion of the structure of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 onto the substrate covers the orthographic projection of the third active portion 73 onto the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. This display panel can utilize the first gate layer as a mask to perform conductive processing on the first active layer; that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductive structure.

[0161] like Figure 6 , 10 As shown in Figure 18, the second gate layer may include: a third gate line 2G1, a second conductive portion 22, a first connection portion 23, a fourth conductive portion 24, and a first initial signal line Vinit1. The orthogonal projection of the third gate line 2G1 onto the substrate extends along the first direction X. The third gate line 2G1 can be used to provide... Figure 2 The first gate drive signal terminal is located in the capacitor C. The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 is used to form the second electrode of the capacitor C. Adjacent second conductive portions 22 in the first direction X can be connected by the first connecting portion 23. The first initial signal line Vinit1 is used to provide... Figure 2The first initial signal terminal in the process.

[0162] like Figure 6 , 11 As shown in Figure 19, the second active layer may include an active portion 9, which may include a second active portion 92, a ninth active portion 99, a nineteenth active portion 919, and a twentieth active portion 920. The nineteenth active portion 919 is connected to the end of the second active portion 92 away from the ninth active portion 99, and the twentieth active portion 920 is connected to the end of the ninth active portion 99 away from the second active portion 92. The second active portion 92 is used to form the channel region of the second transistor T2, and the ninth active portion 99 is used to form the channel region of the ninth transistor T9. The orthogonal projection of the third gate line 2G1 on the substrate may cover the orthogonal projection of the second active portion 92 on the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2. The orthogonal projection of the fourth conductive portion 24 on the substrate may cover the orthogonal projection of the ninth active portion 99 on the substrate, and at least a portion of the structure of the fourth conductive portion 24 is used to form the bottom gate of the ninth transistor T9. The second active layer can be formed of indium gallium zinc oxide, and correspondingly, the second transistor T2 and the ninth transistor T9 can be N-type metal oxide thin film transistors.

[0163] like Figure 6 , 12 As shown in Figure 20, the third gate layer may include a first gate line 3G1, a second initial signal line Vinit2, a third initial signal line Vinit3, and a fifth conductive portion 35. The orthographic projections of the first gate line 3G1, the second initial signal line Vinit2, and the third initial signal line Vinit3 onto the substrate can all extend along the first direction X. The first gate line 3G1 can be used to provide... Figure 2 The first gate drive signal terminal, the orthogonal projection of the first gate line 3G1 on the substrate can cover the orthogonal projection of the second active part 92 on the substrate. A portion of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. Simultaneously, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the display panel bezel area. The second initial signal line Vinit2 can be used to provide... Figure 2 The second initial signal terminal and the third initial signal line Vinit3 can be used to provide... Figure 2The third initial signal terminal in the display panel. The orthographic projection of the fifth conductive portion 35 on the substrate covers the orthographic projection of the ninth active portion 99 on the substrate, and at least a portion of the structure of the fifth conductive portion 35 is used to form the top gate of the ninth transistor. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially coincide with the orthographic projection of the second reset signal line Re2 in the pixel driving circuit of the same row on the substrate, and the orthographic projection of the third initial signal line Vinit3 on the substrate can at least partially coincide with the orthographic projection of the enable signal line EM in the pixel driving circuit of the same row on the substrate. This arrangement can improve the light transmittance and integration of the display panel. In addition, the display panel can use the third gate layer as a mask to perform conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0164] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in the second gate layer, the first source / drain layer, etc.

[0165] like Figure 6 , 13As shown in Figure 21, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a ninth bridging portion 49, and a tenth bridging portion 410. The first bridging portion 41 can be connected to the fourth conductive portion 24 and the fifth conductive portion 35 via vias, respectively, to connect the bottom gate and top gate of the ninth transistor T9. The second bridging portion 42 can be connected to the twenty-first active portion 721, the nineteenth active portion 919, and the seventeenth active portion 717 via vias, respectively, to connect the second terminal of the first transistor T1, the second terminal of the second transistor T2, and the second terminal of the driving transistor T3. The third bridging portion 43 is connected to the eighteenth active portion 718 and the first initial signal line Vinit1 via vias, respectively, to connect the first terminal of the first transistor T1 and the first initial signal terminal. The fourth bridging section 44 connects to the fourteenth active section 714 and the second initial signal line Vinit2 via vias, thereby connecting the first electrode of the seventh transistor T7 and the second initial signal line. The fifth bridging section 45 connects to the thirteenth active section 713 via vias, thereby connecting the first electrode of the fourth transistor T4. The sixth bridging section 46 connects to the eleventh active section 711 and the tenth active section 710 via vias, thereby connecting the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridging section 47 connects to the first connecting section 23 and the fifteenth active section 715 via vias, thereby connecting the second electrode of the capacitor C and the first electrode of the fifth transistor T5. In the same repeating unit, two fifth active sections 75 can be connected through the fifteenth active section 715, and two pixel driving circuits in the same repeating unit can share the same seventh bridging section 47. The eighth bridging section 48 connects to the sixteenth active section 716 via vias, thereby connecting the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridging portion 49 connects the twentieth active portion 920 and the first conductive portion 11 via vias to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 221 can be formed on the second conductive portion 22, and the via connecting the ninth bridging portion 49 and the first conductive portion 11 passes through the opening 221. The tenth bridging portion 410 can connect the third initial signal line Vinit3 and the twelfth active portion 712 via vias to connect the first electrode of the eighth transistor and the third initial signal line Vinit3. In the same repeating unit, two eighth active portions 78 can be connected through the twelfth active portion 712, and two pixel driving circuits in the same repeating unit can share the same tenth bridging portion 410.

[0166] like Figure 6 , 13As shown in Figure 21, the first source / drain layer may further include column-directed initial signal lines Vinitx, whose orthographic projection on the substrate extends along the second direction Y. Multiple column-directed initial connection lines Vinitx can be provided. These Vinitx can be connected via vias to the same type of row-directed initial signal lines intersecting their orthographic projection on the substrate, forming a grid structure of the row-directed initial signal lines. This arrangement can reduce the voltage difference between the initial signal terminals at different locations on the display panel. The row-directed initial signal lines may include one or more of the aforementioned first, second, and third initial signal lines. For example, three adjacent column pixel driving circuits may each be provided with an initial connection line Vinitx, wherein one initial connection line Vinitx connects to the first initial signal line, one initial connection line Vinitx connects to the second initial signal line, and one initial connection line Vinitx connects to the third initial signal line.

[0167] like Figure 6 , 14 As shown in Figure 22, the second source / drain layer may include: an eleventh bridging section 511, a twelfth bridging section 512, a thirteenth bridging section 513, and a first power line VDD. The eleventh bridging section 511 can be connected to the first bridging section 41 via a via. The twelfth bridging section 512 can be connected to the fifth bridging section 45 via a via. The thirteenth bridging section 513 can be connected to the eighth bridging section 48 via a via. The first power line VDD can be used to provide... Figure 2 The first power supply terminal, the first power line VDD, can be projected onto the substrate along the second direction Y, and the first power line VDD can be connected to the seventh bridging part 47 through a via.

[0168] like Figure 6 , 15 As shown, the third source / drain layer may include: a data line Da, a fourth gate line G4, and a fourteenth bridging portion 614. The orthogonal projections of the data line Da and the fourth gate line G4 onto the substrate may extend along the second direction Y. The data line Da is used to provide... Figure 2 The data signal terminal in the middle, the fourth gate line G4 is used to provide Figure 2 The fourth gate drive signal terminal is located in the transistor. Data line Da can be connected to the twelfth bridge section 512 via a via to connect the data signal terminal and the first electrode of the fourth transistor. The fourth gate line G4 can be connected to the eleventh bridge section 511 via a via to connect to the gate of the ninth transistor T9. The fourteenth bridge section 614 can be connected to the thirteenth bridge section 513 via a via, and the fourteenth bridge section 614 can be used to connect to the first electrode of the light-emitting unit.

[0169] It should be noted that, as Figure 6 , 21As shown in Figure 22, the black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; the black squares drawn on the side of the third source / drain layer facing away from the substrate represent vias connecting the third source / drain layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. The different vias represented by the black squares at different positions can penetrate different insulating layers.

[0170] like Figure 23 As shown, Figure 6The diagram shows a partial cross-sectional view of the display panel taken along the dashed line BB. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, and a second planarization layer 109. The substrate 100, shielding layer, buffer layer 101, first active layer, second insulating layer 102, first gate layer, third insulating layer 103, second gate layer, fourth insulating layer 104, second active layer, fifth insulating layer 105, third gate layer, first dielectric layer 106, first source / drain layer, passivation layer 107, first planarization layer 108, second source / drain layer, second planarization layer 109, and third source / drain layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planarization layer 108 and the second planarization layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, second gate layer, and third gate layer can be molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked conductive layers. The materials of the first source / drain layer, second source / drain layer, and third source / drain layer can include metallic materials, for example, molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked layers, or titanium / aluminum / titanium stacked conductive layers. The sheet resistance of any one of the first source / drain layer, second source / drain layer, and third source / drain layer can be less than the sheet resistance of any one of the first gate layer, second gate layer, and third gate layer.

[0171] This exemplary embodiment also provides another display panel, which may also include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and a third source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. Figure 24-27 As shown, Figure 24 This is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the third gate layer in an exemplary embodiment of the display panel disclosed herein. Figure 25 for Figure 24 The diagram shows the structural layout of the shielding layer in the display panel. Figure 26 for Figure 24 The diagram shows the structural layout of the second gate layer in the display panel. Figure 27 for Figure 24 The diagram shows the structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel.

[0172] Compared to Figure 6 The embodiment shown, Figure 24 The shielding layer and the second gate layer in the display panel shown are different.

[0173] like Figure 24-27 As shown, compared to Figure 6 In the illustrated embodiment, the shielding layer further includes a sixth conductive portion 86. The conductive layer containing the sixth conductive portion 86 is located between the active layer containing the ninth active portion 99 and the substrate. The orthographic projection of the sixth conductive portion 86 on the substrate and the orthographic projection of the ninth active portion 99 on the substrate at least partially overlap. Optionally, the orthographic projection of the sixth conductive portion 86 on the substrate can cover the orthographic projection of the ninth active portion 99 on the substrate. The sixth conductive portion 86 can be connected to a stable power supply terminal, and the sixth conductive portion 86 can play a voltage stabilizing role, thereby reducing the gate-source capacitance of the ninth transistor and thus improving the aforementioned screen splitting problem. Figure 24-27 As shown, the shielding layer itself includes a first shielding portion 81 and a second connecting portion 82 connecting two adjacent first shielding portions 81 in the second direction Y. A sixth conductive portion 86 can be connected to the first shielding portion 81 and the second connecting portion 82. For example, the sixth conductive portion 86 can be a protrusion connected to the second connecting portion 82, and the orthographic projection of the sixth conductive portion 86 on the substrate is located on one side of the orthographic projection of the second connecting portion 82 on the substrate in the first direction X. Figure 24-27 As shown, compared to Figure 6 In the embodiment shown, the second gate layer does not have a fourth conductive portion.

[0174] It should be understood that, in other exemplary embodiments, the sixth conductive portion connected to the stable power supply terminal may also be located in other conductive layers. The sixth conductive portion may be located in any conductive layer on the side of the second active layer facing the substrate. For example, the sixth conductive portion may be located in the first gate layer, the second gate layer, etc. Furthermore, the sixth conductive portion may also be located in other additional conductive layers. For example, such as... Figure 47The diagram shows a cross-sectional view of another exemplary embodiment of the display panel of this disclosure, wherein the sixth conductive portion 86 is located in the second gate layer, and the sixth conductive portion 86 can be connected to the shielding layer via a via. In other exemplary embodiments, the sixth conductive portion 86 can also be connected to the first power line VDD in the second source / drain layer via a via. The sixth conductive portion located in the second gate layer and the ninth active portion 99 located in the second active layer are relatively close, thereby the sixth conductive portion can have a better voltage regulation effect on the ninth active portion 99. For example, as... Figure 48 The diagram shows a cross-sectional view of another exemplary embodiment of the display panel disclosed herein, wherein the sixth conductive portion 86 may be located in the first gate layer, and the sixth conductive portion 86 may be connected to a shielding layer via a via. In other exemplary embodiments, the sixth conductive portion 86 may also be connected to the first power line VDD in the second source / drain layer via a via. The sixth conductive portion located in other conductive layers may be connected to the shielding layer via a via to connect to a stable power supply terminal, and the sixth conductive portion located in other conductive layers may also be connected to the first power line VDD located in the second source / drain layer via a via to connect to a stable power supply terminal. Furthermore, the sixth conductive portion located in other conductive layers may also be connected to other stable power supply terminals in the display panel.

[0175] It should be noted that, Figure 24 The other structures of the display panel shown can be related to... Figure 6 The display panel shown is the same.

[0176] like Figure 28 The diagram shown is a structural schematic of another exemplary embodiment of the pixel driving circuit of this disclosure. Figure 2 Compared to the pixel driving circuit shown, Figure 28 The ninth transistor T9 in the pixel driving circuit shown is a P-type transistor.

[0177] This exemplary embodiment also provides another display panel, which may also include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and a third source / drain layer stacked sequentially. An insulating layer may be disposed between adjacent layers. Figure 29-45 As shown, Figure 29 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 30 for Figure 29 Structural layout of the middle shading layer, Figure 31 for Figure 29 The structural layout of the first active layer in the middle, Figure 32 for Figure 29 The structural layout of the first gate layer in the middle, Figure 33 for Figure 29 The structural layout of the second gate layer in the middle. Figure 34 for Figure 29The structural layout of the second active layer in the middle. Figure 35 for Figure 29 The structural layout of the third gate layer in the middle, Figure 36 for Figure 29 The structural layout of the first source / drain layer in the middle. Figure 37 for Figure 29 Structural layout of the second source / drain layer. Figure 38 for Figure 29 Structural layout of the third source / drain layer in the middle. Figure 39 for Figure 29 The structural layout of the middle shielding layer and the first active layer. Figure 40 for Figure 29 The structural layout of the middle shielding layer, the first active layer, and the first gate layer. Figure 41 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, and the second gate layer. Figure 42 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer. Figure 43 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer. Figure 44 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer. Figure 45 for Figure 29 The structural layout of the middle shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, the first source / drain layer, and the second source / drain layer.

[0178] The display panel may include multiple Figure 28 The pixel driving circuit shown has multiple pixel driving circuits arrayed in the first direction X and the second direction Y.

[0179] like Figure 29As shown, the plurality of pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X. At least a portion of the structures of the first pixel driving circuit P1 and the second pixel driving circuit P2 may be mirror-symmetrically arranged with a mirror symmetry plane AA. The mirror symmetry plane AA may be perpendicular to the substrate. Furthermore, at least a portion of the orthographic projections of the first pixel driving circuit P1 and the second pixel driving circuit P2 on the substrate may be symmetrically arranged with the intersection of the mirror symmetry plane AA and the substrate as the axis of symmetry. The first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit, and the display panel may include a plurality of repeating units arrayed in the first direction X and the second direction Y. The second direction Y and the first direction X may intersect; for example, the first direction X may be a row direction, and the second direction Y may be a column direction. In addition, in this exemplary embodiment, the display panel may have design errors and process errors, and the first pixel driving circuit P1 and the second pixel driving circuit P2 may be approximately mirror-symmetrical with respect to the mirror symmetry plane AA.

[0180] like Figure 29 , 30 As shown in Figure 39, the shielding layer includes a plurality of first shielding portions 81 and second connecting portions 82 distributed in an array along the first direction X and the second direction Y. The first shielding portions 81 are interconnected with each other through the second connecting portions 82.

[0181] like Figure 29 , 31As shown in 39 and 40, the first active layer may include: the first active section 71, the third active section 73, the fourth active section 74, the fifth active section 75, the sixth active section 76, the seventh active section 77, the eighth active section 78, the ninth active section 79, the twentieth active section 720, the twenty-first active section 721, the tenth active section 710, the eleventh active section 711, the twelfth active section 712, the thirteenth active section 713, the fourteenth active section 714, the fifteenth active section 715, the sixteenth active section 716, the seventeenth active section 717, and the eighteenth active section 718. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 can be used to form the channel region of the ninth transistor T9; the twenty-first active portion 721 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 and the twelfth active portion 721... Source section 712 is connected to both ends of the eighth source section 78; eleventh source section 711 is connected between the fourth source section 74 and the third source section 73; thirteenth source section 713 is connected to the side of the fourth source section 74 away from the third source section 73; fourteenth source section 714 is connected to the side of the seventh source section 77 away from the sixth source section 76; fifteenth source section 715 is connected to the side of the fifth source section 75 away from the third source section 73; sixteenth source section 716 is connected between the seventh source section 77 and the sixth source section 76; seventeenth source section 717 and eighteenth source section 718 are connected to both ends of the first source section 71; twentieth source section 720 and twenty-second source section 722 are connected to both ends of the ninth source section 79. The first active layer can be formed of polycrystalline silicon material. Correspondingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0182] The orthographic projection of the first shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The first shielding portion 81 can shield the third active portion 73 from light to improve the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure, and the shielding layer can be connected to a stable voltage source. The shielding layer can also act as a signal shield for the pixel driving circuit.

[0183] like Figure 29 , 30As shown in Figure 39, the shielding layer further includes a sixth conductive portion 86. The conductive layer containing the sixth conductive portion 86 is located between the active layer containing the ninth active portion 79 and the substrate. The orthographic projection of the sixth conductive portion 86 on the substrate and the orthographic projection of the ninth active portion 79 on the substrate at least partially overlap. Optionally, the orthographic projection of the sixth conductive portion on the substrate can cover the orthographic projection of the ninth active portion 79 on the substrate. The sixth conductive portion 86 can be connected to a stable power supply terminal. The sixth conductive portion 86 can play a voltage stabilizing role, thereby reducing the gate-source capacitance of the ninth transistor and thus improving the aforementioned screen splitting problem. The shielding layer itself includes a first shielding portion 81 and a second connecting portion 82 connected between two adjacent first shielding portions 81 in the second direction Y. The sixth conductive portion 86 can be connected to the first shielding portion 81 and the second connecting portion 82. For example, the sixth conductive part 86 can be a protrusion connected to the second connecting part 82, and the orthographic projection of the sixth conductive part 86 on the substrate can be located on one side of the orthographic projection of the second connecting part 82 on the substrate in the first direction X.

[0184] like Figure 29 , 32 As shown in Figure 40, the first gate layer may include: a first conductive portion 11, a fifth conductive portion 15, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide... Figure 2 The second gate drive signal terminal; the enable signal line EM can be used to provide Figure 2 The enable signal terminal; the first reset signal line Re1 can be used to provide Figure 2 The first reset signal terminal; the second reset signal line Re2 can be used to provide Figure 2The second reset signal terminal is shown in the diagram. The orthographic projections of the second gate line G2, the enable signal line EM, the first reset signal line Re1, and the second reset signal line Re2 on the substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projections of the fifth active portion 75 and the sixth active portion 76 on the substrate, and a portion of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate can cover the orthographic projection of the first active portion 71 on the substrate, and a portion of the structure of the first reset signal line Re1 is used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projections of the seventh active portion 77 and the eighth active portion 78 on the substrate. A portion of the structure of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. The orthographic projection of the fifth conductive portion 15 on the substrate covers the orthographic projection of the ninth active portion 79 on the substrate. At least a portion of the structure of the fifth conductive portion 15 is used to form the gate of the ninth transistor T9.

[0185] The display panel can use the first gate layer as a mask to conduct the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0186] like Figure 29 , 33 As shown in Figure 41, the second gate layer may include: a third gate line 2G1, a second conductive portion 22, a first connection portion 23, and a first initial signal line Vinit1. The orthogonal projection of the third gate line 2G1 onto the substrate extends along the first direction X. The third gate line 2G1 can be used to provide... Figure 28 The first gate drive signal terminal is located in the capacitor C. The orthographic projection of the second conductive portion 22 on the substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the substrate. The second conductive portion 22 is used to form the second electrode of the capacitor C. Adjacent second conductive portions 22 in the first direction X can be connected by the first connecting portion 23. The first initial signal line Vinit1 is used to provide... Figure 2 The first initial signal terminal in the process.

[0187] like Figure 29 , 34 As shown in Figure 42, the second active layer may include an active portion 9, which may include a second active portion 92, a nineteenth active portion 919, and a twenty-third active portion 923. The nineteenth active portion 919 and the twenty-third active portion 923 are connected to the two ends of the second active portion 92. The second active portion 92 is used to form the channel region of the second transistor T2. The orthogonal projection of the third gate line 2G1 on the substrate may cover the orthogonal projection of the second active portion 92 on the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and correspondingly, the second transistor T2 may be an N-type metal oxide thin film transistor.

[0188] like Figure 29 , 35 As shown in Figure 43, the third gate layer may include a first gate line 3G1, a second initial signal line Vinit2, and a third initial signal line Vinit3. The orthographic projections of the first gate line 3G1, the second initial signal line Vinit2, and the third initial signal line Vinit3 onto the substrate can all extend along the first direction X. The first gate line 3G1 can be used to provide... Figure 28 The first gate drive signal terminal, the orthogonal projection of the first gate line 3G1 on the substrate can cover the orthogonal projection of the second active part 92 on the substrate. A portion of the structure of the first gate line 3G1 can be used to form the top gate of the second transistor T2. Simultaneously, the first gate line 3G1 can be connected to the third gate line 2G1 through a via located in the display panel bezel area. The second initial signal line Vinit2 can be used to provide... Figure 28 The second initial signal terminal and the third initial signal line Vinit3 can be used to provide... Figure 28 The third initial signal terminal in the circuit. The orthographic projection of the second initial signal line Vinit2 on the substrate can at least partially coincide with the orthographic projection of the second reset signal line Re2 in the same row pixel driving circuit on the substrate, and the orthographic projection of the third initial signal line Vinit3 on the substrate can at least partially coincide with the orthographic projection of the enable signal line EM in the same row pixel driving circuit on the substrate. This arrangement can improve the light transmittance and integration of the display panel. In addition, the display panel can use the third gate layer as a mask to perform conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0189] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 may also be located in the second gate layer, the first source / drain layer, etc.

[0190] like Figure 29 , 36As shown in Figure 44, the first source / drain layer may include a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, a ninth bridging portion 49, a tenth bridging portion 410, and a fifteenth bridging portion 415. The first bridging portion 41 can be connected to the fifth conductive portion 15 via vias to connect to the gate of the ninth transistor T9. The second bridging portion 42 can be connected to the twenty-first active portion 721, the nineteenth active portion 919, and the seventeenth active portion 717 via vias to connect to the second terminals of the first transistor T1, the second transistor T2, and the driving transistor T3. The third bridging portion 43 can be connected to the eighteenth active portion 718 and the first initial signal line Vinit1 via vias to connect the first terminal of the first transistor T1 and the first initial signal terminal. The fourth bridging section 44 connects to the fourteenth active section 714 and the second initial signal line Vinit2 via vias, thereby connecting the first electrode of the seventh transistor T7 and the second initial signal line. The fifth bridging section 45 connects to the thirteenth active section 713 via vias, thereby connecting the first electrode of the fourth transistor T4. The sixth bridging section 46 connects to the eleventh active section 711 and the tenth active section 710 via vias, thereby connecting the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridging section 47 connects to the first connecting section 23 and the fifteenth active section 715 via vias, thereby connecting the second electrode of the capacitor C and the first electrode of the fifth transistor T5. In the same repeating unit, two fifth active sections 75 can be connected through the fifteenth active section 715, and two pixel driving circuits in the same repeating unit can share the same seventh bridging section 47. The eighth bridging section 48 connects to the sixteenth active section 716 via vias, thereby connecting the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridging portion 49 connects the twentieth active portion 920 and the first conductive portion 11 via vias to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2. An opening 221 can be formed on the second conductive portion 22, and the via connecting the ninth bridging portion 49 and the first conductive portion 11 passes through the opening 221. The tenth bridging portion 410 connects the third initial signal line Vinit3 and the twelfth active portion 712 via vias to connect the first electrode of the eighth transistor and the third initial signal line Vinit3. In the same repeating unit, two eighth active portions 78 can be connected through the twelfth active portion 712, and two pixel driving circuits in the same repeating unit can share the same tenth bridging portion 410. The fifteenth bridging portion 415 connects the twenty-third active portion 923 and the twenty-second active portion 722 via vias to connect the second electrode of the ninth transistor T9 and the first electrode of the second transistor T2.

[0191] like Figure 29 , 36As shown in Figure 44, the first source / drain layer may further include column-directed initial signal lines Vinitx, whose orthographic projection on the substrate extends along the second direction Y. Multiple column-directed initial connection lines Vinitx can be provided. These Vinitx can be connected via vias to the same type of row-directed initial signal lines intersecting their orthographic projection on the substrate, forming a grid structure of the row-directed initial signal lines. This arrangement can reduce the voltage difference between the initial signal terminals at different locations on the display panel. The row-directed initial signal lines may include one or more of the aforementioned first, second, and third initial signal lines. For example, three adjacent column pixel driving circuits may each be provided with an initial connection line Vinitx, wherein one initial connection line Vinitx connects to the first initial signal line, one initial connection line Vinitx connects to the second initial signal line, and one initial connection line Vinitx connects to the third initial signal line.

[0192] like Figure 29 , 37 As shown in Figure 45, the second source / drain layer may include: an eleventh bridging section 511, a twelfth bridging section 512, a thirteenth bridging section 513, and a first power line VDD. The eleventh bridging section 511 can be connected to the first bridging section 41 via a via. The twelfth bridging section 512 can be connected to the fifth bridging section 45 via a via. The thirteenth bridging section 513 can be connected to the eighth bridging section 48 via a via. The first power line VDD can be used to provide... Figure 2 The first power supply terminal, the first power line VDD, can be projected onto the substrate along the second direction Y, and the first power line VDD can be connected to the seventh bridging part 47 through a via.

[0193] like Figure 29 , 38 As shown, the third source / drain layer may include: a data line Da, a fourth gate line G4, and a fourteenth bridging portion 614. The orthogonal projections of the data line Da and the fourth gate line G4 onto the substrate may extend along the second direction Y. The data line Da is used to provide... Figure 2 The data signal terminal in the middle, the fourth gate line G4 is used to provide Figure 2 The fourth gate drive signal terminal is located in the transistor. Data line Da can be connected to the twelfth bridge section 512 via a via to connect the data signal terminal and the first electrode of the fourth transistor. The fourth gate line G4 can be connected to the eleventh bridge section 511 via a via to connect to the gate of the ninth transistor T9. The fourteenth bridge section 614 can be connected to the thirteenth bridge section 513 via a via, and the fourteenth bridge section 614 can be used to connect to the first electrode of the light-emitting unit.

[0194] It should be noted that, as Figure 29 , 44As shown in Figure 45, the black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; the black squares drawn on the side of the third source / drain layer facing away from the substrate represent vias connecting the third source / drain layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. The different vias represented by the black squares at different positions can penetrate different insulating layers.

[0195] like Figure 46 As shown, Figure 29The diagram shows a partial cross-sectional view of the display panel taken along the dashed line CC. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planarization layer 108, and a second planarization layer 109. The substrate 100, shielding layer, buffer layer 101, first active layer, second insulating layer 102, first gate layer, third insulating layer 103, second gate layer, fourth insulating layer 104, second active layer, fifth insulating layer 105, third gate layer, first dielectric layer 106, first source / drain layer, passivation layer 107, first planarization layer 108, second source / drain layer, second planarization layer 109, and third source / drain layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be single-layer or multi-layer structures, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; the materials of the first planarization layer 108 and the second planarization layer 109 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, second gate layer, and third gate layer can be molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked conductive layers. The materials of the first source / drain layer, second source / drain layer, and third source / drain layer can include metallic materials, for example, molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacked layers, or titanium / aluminum / titanium stacked conductive layers. The sheet resistance of any one of the first source / drain layer, second source / drain layer, and third source / drain layer can be less than the sheet resistance of any one of the first gate layer, second gate layer, and third gate layer.

[0196] like Figure 6 As shown, the area of ​​the orthographic projection of the ninth active portion 99 onto the substrate is smaller than the area of ​​the orthographic projection of the second active portion 92 onto the substrate. This exemplary embodiment can reduce the gate-source parasitic capacitance of the ninth transistor T9 by reducing the area of ​​the orthographic projection of the ninth active portion 99 onto the substrate, thereby improving the aforementioned screen splitting problem.

[0197] Optionally, the length of the channel region of the ninth transistor T9 is less than the length of the channel region of the second transistor T2; and / or, the width of the channel region of the ninth transistor T9 is less than the width of the channel region of the second transistor T2.

[0198] It should be understood that the approach of reducing the channel area of ​​the ninth transistor can also be applied. Figure 24 The display panel shown. That is, the solution to improve the screen splitting problem by reducing the area of ​​the orthogonal projection of the ninth active part 99 onto the substrate, and the solution to improve the screen splitting problem by stabilizing the voltage of the ninth active part 99 through the sixth conductive part, can be applied to the same display panel. Similarly, the solution to reduce the area of ​​the ninth transistor channel region can also be applied to... Figure 29 The display panel shown, correspondingly, Figure 29 In this case, the area of ​​the orthographic projection of the ninth active part on the substrate can be smaller than the area of ​​the orthographic projection of the first active part on the substrate.

[0199] In this exemplary embodiment, as Figure 6 , 24 As shown in Figure 29, in the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor T9 on the substrate is located between the orthographic projection of the second gate line G2 on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate.

[0200] In this exemplary embodiment, as Figure 6 , 24 As shown in Figure 29, in the first direction X of the same pixel driving circuit, the orthographic projection of the channel region of the ninth transistor T9 on the substrate is located between the orthographic projection of the channel region of the fourth transistor T4 on the substrate and the orthographic projection of the channel region of the second transistor T2 on the substrate.

[0201] In this exemplary embodiment, as Figure 6 , 24 As shown in Figures 2 and 29, the length direction of the channel region of the second transistor is the second direction, and the length direction of the channel region of the ninth transistor is the first direction.

[0202] In this exemplary embodiment, as Figure 6 , 24 As shown in Figure 29, the fourth gate line G4 is located in the third source / drain layer. It should be understood that in other exemplary embodiments, the fourth gate line G4 may also be located in other conductive layers such as the second source / drain layer and the first source / drain layer.

[0203] In this exemplary embodiment, as Figure 6 , 24 As shown in Figure 29, the orthographic projection of the fourth gate line G4 on the substrate and the orthographic projection of the first power line VDD on the substrate at least partially overlap. The first power line VDD can shield the fourth gate line G4 from interference with other signal terminals.

[0204] In this exemplary embodiment, as Figure 6 , 24 As shown in Figure 29, the first power line VDD includes: a first extension VDD1 and a second extension VDD2. The size of the orthographic projection of the first extension VDD1 on the substrate in the first direction X is greater than the size of the orthographic projection of the second extension VDD2 on the substrate in the first direction. The orthographic projections of the fourth gate line G4 on the substrate and the orthographic projections of the second extension VDD2 on the substrate at least partially overlap.

[0205] In this exemplary embodiment, as Figure 6 , 24 As shown in Figure 29, the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the channel region of the ninth transistor T9 on the substrate at least partially overlap. The first power line VDD can shield the ninth transistor T9 from light.

[0206] In this exemplary embodiment, as Figure 6 , 24 As shown in Figure 29, the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the second bridging portion 42 on the substrate at least partially overlap, and / or, the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the ninth bridging portion 49 on the substrate at least partially overlap. The first power line VDD can shield and regulate the voltage of the second bridging portion 42 and the ninth bridging portion 49.

[0207] In this exemplary embodiment, as Figure 6 , 24 As shown in Figure 29, the first gate line 3G1 includes a third extension 3G13 and a fourth extension 3G14. The third extension 3G13 forms the gate of the second transistor T2. The orthographic projection of the third extension 3G13 onto the substrate in the second direction Y is larger than the orthographic projection of the fourth extension 3G14 onto the substrate in the second direction Y. The second bridging portion 42 and the first gate line 3G1 are located in different conductive layers. The second bridging portion 42 includes a first sub-bridging portion 421. The orthographic projection of the first sub-bridging portion 421 onto the substrate extends along the second direction Y, and the orthographic projection of the first sub-bridging portion 421 onto the substrate intersects with the orthographic projection of the fourth extension 3G14 onto the substrate. This arrangement can reduce the parasitic capacitance between the second bridging portion 42 and the first gate line 3G1.

[0208] In this exemplary embodiment, as Figure 6 , 24As shown in Figure 29, the second bridging portion 42 further includes: a second sub-bridging portion 422 and a third sub-bridging portion 423. The second sub-bridging portion 422 is connected to the second terminal of the first transistor through a via. The third sub-bridging portion 423 is connected to the second terminal of the second transistor and the second terminal of the driving transistor through a via. The first sub-bridging portion 421 is connected between the second sub-bridging portion 422 and the third sub-bridging portion 423. The angle b between the orthographic projection of the first sub-bridging portion 421 on the substrate and the orthographic projection of the second sub-bridging portion 422 on the substrate is less than 180°. The angle a between the orthographic projection of the first sub-bridging portion 421 on the substrate and the orthographic projection of the third sub-bridging portion 423 on the substrate is less than 180°.

[0209] like Figure 24 , 29 As shown, the shielding layer may further include a seventh conductive portion 87. The orthographic projection of the seventh conductive portion 87 on the substrate covers the orthographic projection of the via between the ninth bridging portion 49 and the twentieth active portion 720 on the substrate. The via between the ninth bridging portion 49 and the twentieth active portion 720 has a positional error during formation, which can lead to different degrees of light shielding in different pixel driving circuits, resulting in inconsistent exposure sizes of the via. The seventh conductive portion 87 ensures that the via has consistent exposure levels and consistent via sizes during the exposure process.

[0210] In this exemplary embodiment, as Figure 49 The diagram shown is a structural layout of another exemplary embodiment of the display panel of this disclosure. The orthographic projection of the fourth gate line G4 on the substrate can be bent along the second direction Y. This arrangement can increase the overlap area of ​​the orthographic projection of the fourth gate line G4 on the substrate and the orthographic projection of the first power line VDD on the substrate, thereby further improving the shielding effect of the first power line VDD on the fourth gate line G4.

[0211] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0212] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0213] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0214] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel comprises: a substrate substrate; a plurality of pixel driving circuits, the orthogonal projection of the plurality of pixel driving circuits on the substrate substrate is arrayed along a first direction and a second direction, and the first direction and the second direction intersect; wherein the pixel driving circuit comprises a driving transistor, a second transistor and a ninth transistor, the first electrode of the ninth transistor is connected to the gate electrode of the driving transistor, the second electrode of the ninth transistor is connected to the first electrode of the second transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor; a first gate line, the orthogonal projection of the first gate line on the substrate substrate extends along the first direction, and the first gate line is used to provide a gate driving signal to the second transistor in the plurality of pixel driving circuits distributed along the first direction; a fourth gate line, the orthogonal projection of the fourth gate line on the substrate substrate extends along the second direction, and the fourth gate line is used to provide a gate driving signal to the ninth transistor in the plurality of pixel driving circuits distributed along the second direction.

2. The display panel of claim 1, wherein, The display panel further comprises: a ninth active part, the ninth active part is used to form a channel region of the ninth transistor; a sixth conductive part, the sixth conductive part is connected to a stable power supply end, the conductive layer where the sixth conductive part is located is located between the substrate substrate and the active layer where the ninth active part is located, and the orthogonal projection of the sixth conductive part on the substrate substrate and the orthogonal projection of the ninth active part on the substrate substrate at least partially overlap.

3. The display panel of claim 2, wherein, The display panel further comprises: a shielding layer located on one side of the substrate substrate, the shielding layer comprises a first shielding part; a first active layer located on the side of the shielding layer away from the substrate substrate, the first active layer comprises a third active part, the third active part is used to form a channel region of the driving transistor, and the orthogonal projection of the first shielding part on the substrate substrate and the orthogonal projection of the third active part on the substrate substrate at least partially overlap; wherein the sixth conductive part is located in the shielding layer.

4. The display panel of claim 3, wherein, The shielding layer further comprises: a second connecting part connected between two first shielding parts adjacent in the second direction; the sixth conductive part is connected to the second connecting part, and the orthogonal projection of the sixth conductive part on the substrate substrate is located on one side of the orthogonal projection of the second connecting part on the substrate substrate in the first direction.

5. The display panel of claim 1, wherein, The display panel further comprises: a second active part, the second active part is used to form a channel region of the second transistor; a ninth active part, the ninth active part is used to form a channel region of the ninth transistor; the second active part and the ninth active part are located in the same active layer, and the area of the orthogonal projection of the ninth active part on the substrate substrate is smaller than the area of the orthogonal projection of the second active part on the substrate substrate.

6. The display panel of claim 5, wherein, The length of the channel region of the ninth transistor is smaller than the length of the channel region of the second transistor; and / or, the width of the channel region of the ninth transistor is smaller than the width of the channel region of the second transistor.

7. The display panel of claim 1, wherein, The pixel driving circuit further comprises a first transistor, a first electrode of the first transistor is connected with a first initial signal line, a second electrode of the first transistor is connected with a second electrode of the driving transistor, and the display panel further comprises: a first active part for forming a channel region of the first transistor; a ninth active part for forming a channel region of the ninth transistor; The first active part and the ninth active part are located in the same active layer, and an area of a normal projection of the ninth active part on the substrate is smaller than an area of a normal projection of the first active part on the substrate.

8. The display panel according to any one of claims 1-7, wherein, The driving transistor and the ninth transistor are P-type transistors, and the display panel further comprises: a first active layer located on one side of the substrate, the first active layer comprises a third active part and a ninth active part, the third active part is used for forming a channel region of the driving transistor, and the ninth active part is used for forming a channel region of the ninth transistor.

9. The display panel according to any one of claims 1-7, wherein, The driving transistor is a P-type transistor, and the ninth transistor is an N-type transistor, and the display panel further comprises: a first active layer located on one side of the substrate, the first active layer comprises a third active part, and the third active part is used for forming a channel region of the driving transistor; a second active layer located on a side of the first active layer away from the substrate, the second active layer comprises a ninth active part, and the ninth active part is used for forming a channel region of the ninth transistor.

10. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit further comprises a first transistor and a fourth transistor, a first electrode of the first transistor is connected with a first initial signal line, a second electrode of the first transistor is connected with a second electrode of the driving transistor, a first electrode of the fourth transistor is connected with a data line, and a second electrode of the fourth transistor is connected with a first electrode of the driving transistor; The display panel further comprises: a first reset signal line located on one side of the substrate, a normal projection of the first reset signal line on the substrate extends along a first direction, and part of a structure of the first reset signal line is used for forming a gate electrode of the first transistor; a second gate line located on one side of the substrate, a normal projection of the second gate line on the substrate extends along the first direction, and part of a structure of the second gate line is used for forming a gate electrode of the fourth transistor; In the same pixel driving circuit, a normal projection of a channel region of the ninth transistor on the substrate is located between a normal projection of the second gate line on the substrate and a normal projection of the first reset signal line on the substrate.

11. The display panel according to any one of claims 1-7, wherein, The pixel driving circuit further comprises a fourth transistor, a first electrode of the fourth transistor is connected with a data line, and a second electrode of the fourth transistor is connected with a first electrode of the driving transistor; In the first direction of the same pixel driving circuit, a normal projection of a channel region of the ninth transistor on the substrate is located between a normal projection of a channel region of the fourth transistor on the substrate and a normal projection of a channel region of the second transistor on the substrate.

12. The display panel of any of claims 1-7, wherein, A length direction of a channel region of the second transistor is a second direction, and a length direction of a channel region of the ninth transistor is a first direction.

13. The display panel of any of claims 1-7, wherein, The display panel further includes: The first source-drain layer is located on one side of the substrate, and the first source-drain layer includes a ninth bridge portion, and the ninth bridge portion is connected to the first electrode of the ninth transistor and the gate electrode of the driving transistor through a via hole respectively. The second source-drain layer is located on a side of the first source-drain layer away from the substrate, and the second source-drain layer includes a first power supply line, and the first power supply line is configured to provide a high-level power supply signal to the pixel driving circuit. The third source-drain layer is located on a side of the second source-drain layer away from the substrate, and the third source-drain layer includes the fourth gate line.

14. The display panel according to any one of claims 1-7, wherein, The display panel further includes: The first power supply line is configured to provide a high-level power supply signal to the pixel driving circuit, and a projection of the first power supply line on the substrate extends along the second direction. A projection of the fourth gate line on the substrate and a projection of the first power supply line on the substrate at least partially overlap.

15. The display panel of claim 14, wherein, The first power supply line includes a first extension portion and a second extension portion, and a size of a projection of the first extension portion on the substrate in the first direction is greater than a size of a projection of the second extension portion on the substrate in the first direction. A projection of the fourth gate line on the substrate and a projection of the second extension portion on the substrate at least partially overlap.

16. The display panel of any of claims 1-7, wherein, The display panel further includes: The first power supply line is located on one side of the substrate, and the first power supply line is configured to provide a high-level power supply signal to the pixel driving circuit, and a projection of the first power supply line on the substrate and a projection of the channel region of the ninth transistor on the substrate at least partially overlap.

17. The display panel of any one of claims 1-7, wherein, The display panel further includes: The first source-drain layer is located on one side of the substrate, and the first source-drain layer includes a second bridge portion and a ninth bridge portion, and the second bridge portion is connected to the second electrode of the driving transistor and the second electrode of the second transistor through a via hole respectively, and the ninth bridge portion is connected to the first electrode of the ninth transistor and the gate electrode of the driving transistor through a via hole respectively. The second source-drain layer is located on a side of the first source-drain layer away from the substrate, and the second source-drain layer includes a first power supply line, and the first power supply line is configured to provide a high-level power supply signal to the pixel driving circuit. The first power supply line on the substrate and the second bridge portion on the substrate at least partially overlap, and / or the first power supply line on the substrate and the ninth bridge portion on the substrate at least partially overlap.

18. The display panel of any one of claims 1-7, wherein, The pixel driving circuit further includes a first transistor, and a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to the second electrode of the driving transistor. The display panel further includes: A second bridge portion is located at one side of the substrate, and the second bridge portion is connected to the second electrode of the driving transistor, the second electrode of the second transistor and the second electrode of the first transistor through vias respectively; The first gate line comprises a third extension portion and a fourth extension portion, the third extension portion is used for forming a gate electrode of the second transistor, and a size of a projection of the third extension portion on the substrate in the second direction is greater than a size of a projection of the fourth extension portion on the substrate in the second direction; The second bridge portion and the first gate line are located in different conductive layers, the second bridge portion comprises a first sub-bridge portion, a projection of the first sub-bridge portion on the substrate extends along the second direction, and the projection of the first sub-bridge portion on the substrate intersects with the projection of the fourth extension portion on the substrate.

19. The display panel of claim 18, wherein, The second bridge portion further comprises: A second sub-bridge portion, the second sub-bridge portion is connected to the second electrode of the first transistor through a via; A third sub-bridge portion, the third sub-bridge portion is connected to the second electrode of the second transistor and the second electrode of the driving transistor through a via; The first sub-bridge portion is connected between the second sub-bridge portion and the third sub-bridge portion, an included angle between the projection of the first sub-bridge portion on the substrate and the projection of the second sub-bridge portion on the substrate is less than 180°, and an included angle between the projection of the first sub-bridge portion on the substrate and the projection of the third sub-bridge portion on the substrate is less than 180°.

20. The display panel of any one of claims 1-7, wherein, The display panel further comprises a light emitting unit, the pixel driving circuit is used for driving the light emitting unit to emit light, and the pixel driving circuit further comprises: A first transistor, a first electrode of the first transistor is connected to a first initial signal line, and a second electrode of the first transistor is connected to the second electrode of the driving transistor; A fourth transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor; A fifth transistor, a first electrode of the fifth transistor is connected to a first power supply line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor; A sixth transistor, a first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to the light emitting unit; A seventh transistor, a first electrode of the seventh transistor is connected to a second initial signal line, and a second electrode of the seventh transistor is connected to the light emitting unit; An eighth transistor, a first electrode of the eighth transistor is connected to a third initial signal line, and a second electrode of the eighth transistor is connected to the first electrode of the driving transistor; A capacitor, a first electrode of the capacitor is connected to the gate electrode of the driving transistor, and a second electrode of the capacitor is connected to the first power supply line; The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor are P-type transistors, the second transistor is an N-type transistor, and the ninth transistor is an N-type transistor or a P-type transistor.

21. The display panel of claim 1, wherein, The pixel driving circuit comprises P-type transistors and N-type transistors, and the display panel further comprises: A first active layer is located at one side of the substrate, and part of the structure of the first active layer is used for forming a channel region of a P-type transistor in the pixel driving circuit; A first gate layer is located on a side of the first active layer away from the substrate, and part of the structure of the first gate layer is used to form a gate of a P-type transistor in the pixel driving circuit. A second gate layer is located on a side of the first gate layer away from the substrate, and part of the structure of the second gate layer is used to form a bottom gate of an N-type transistor in the pixel driving circuit. A second active layer is located on a side of the second gate layer away from the substrate, and part of the structure of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit. A third gate layer is located on a side of the second active layer away from the substrate, and part of the structure of the third gate layer is used to form a top gate of an N-type transistor in the pixel driving circuit. A first source-drain layer is located on a side of the third gate layer away from the substrate, and part of the structure of the first source-drain layer is used to form a bridge connecting different transistors.

22. A display device comprising: The display device comprises the display panel of any one of claims 1-21.

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