Gate driver, display device, and electronic apparatus

Abstract

The invention discloses a gate driver, a display device and an electronic apparatus. The display device includes: a display panel including a plurality of pixel rows arranged in a first direction and each including a plurality of pixels; a first gate driver including a first stage that generates a first gate signal as a first output to each of the plurality of pixel rows; and a second gate driver including second stages that generate a second gate signal as a second output to each of the plurality of pixel rows, the second stages being alternately arranged with the first stages in the first direction. The first gate driver and the second gate driver share a first clock signal. Each of the first stage and the second stage is connected to at least four pixel rows among the plurality of pixel rows.

Description

Technical Field

[0001] This disclosure relates to a display device. More specifically, this disclosure relates to a gate driver having low power consumption and a small area, a display device including the gate driver, and an electronic device including the display device. Background Technology

[0002] The display device may include a display panel for displaying images and a gate driver for providing gate signals to the display panel. The gate driver may include a first to an nth gate driver having stages for generating first to nth gate signals, where n is a natural number greater than 1.

[0003] As the number of stages included in the first to nth gate drivers increases, the power consumption of the gate drivers may increase, and therefore the power consumption of the display device may increase. Furthermore, when the first to nth gate drivers are arranged in the row direction, the area of ​​the gate drivers may increase, and the dead zone of the display device may also increase. Summary of the Invention

[0004] Embodiments of this disclosure provide a gate driver with low power consumption and small area.

[0005] Embodiments of this disclosure provide a display device with low power consumption and a small dead zone.

[0006] Embodiments of this disclosure provide an electronic device with low power consumption.

[0007] A display device according to an embodiment includes: a display panel including a plurality of pixel rows arranged in a first direction and each including a plurality of pixels; a first gate driver including a first stage that generates a first gate signal as a first output to each of the plurality of pixel rows; and a second gate driver including a second stage that generates a second gate signal as a second output to each of the plurality of pixel rows, the second stage being alternately arranged with the first stage in the first direction. The first gate driver and the second gate driver share a first clock signal. Each of the first stage and the second stage is connected to at least four of the plurality of pixel rows.

[0008] In an embodiment, each of the first and second levels can be connected to an even number of pixel rows in a plurality of pixel rows.

[0009] In an embodiment, each of the first and second levels can be connected to four, six, or eight pixel rows among a plurality of pixel rows.

[0010] In an embodiment, the display device may further include: a third gate driver, including a third stage that generates a third gate signal as a third output to each of a plurality of pixel rows; and a fourth gate driver, including a fourth stage that generates a fourth gate signal as a fourth output to each of the plurality of pixel rows, the fourth stage and the third stage being arranged alternately in a first direction. The third gate driver and the fourth gate driver may share a second clock signal. Each of the third stage and the fourth stage may be connected to at least four of the plurality of pixel rows.

[0011] In an embodiment, the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver may be positioned close to the first side of the plurality of pixel rows in a second direction that intersects the first direction.

[0012] In one embodiment, the first and second gate drivers may be positioned close to the first side of the plurality of pixel rows in a second direction intersecting the first direction. The third and fourth gate drivers may be positioned close to the second side of the plurality of pixel rows in the second direction opposite to the first side.

[0013] In an embodiment, the display device may further include a fifth gate driver, which includes a fifth stage that generates a fifth gate signal as a fifth output to a plurality of pixel rows. The fifth stage may include a plurality of sub-stages, each of which may be connected to a corresponding pixel row among the plurality of pixel rows.

[0014] In an embodiment, each of the pixels may include a light-emitting element, a first transistor that controls the drive current flowing through the light-emitting element, a second transistor that provides a data voltage to the gate of the first transistor in response to a fifth gate signal, a third transistor that provides a reference voltage to the gate of the first transistor in response to a fourth gate signal, a fourth transistor that provides an initialization voltage to the first electrode of the light-emitting element in response to a second gate signal, a fifth transistor that blocks the connection between the first electrode of the first transistor and the line providing the first power supply voltage in response to the first gate signal, and a sixth transistor that blocks the connection between the second electrode of the first transistor and the line providing the second power supply voltage in response to a third gate signal.

[0015] In an embodiment, each of the pixels may include a light-emitting element, a first transistor that controls the drive current flowing through the light-emitting element, a second transistor that provides a data voltage to the gate of the first transistor in response to a fifth gate signal, a third transistor that compensates for the threshold voltage of the first transistor in response to a fourth gate signal, a fourth transistor that provides a first initialization voltage to the gate of the first transistor in response to a third gate signal, a fifth transistor that blocks the connection between the first electrode of the first transistor and the line providing the first power supply voltage in response to the first gate signal, a sixth transistor that blocks the connection between the second electrode of the first transistor and the line providing the second power supply voltage in response to the first gate signal, and a seventh transistor that provides a second initialization voltage to the first electrode of the light-emitting element in response to a second gate signal.

[0016] In an embodiment, each of the pixels may further include an eighth transistor that provides a bias voltage to the first electrode of the first transistor in response to a second gate signal.

[0017] In this embodiment, the first clock signal can oscillate between low and high levels during the address scan period and the self-scan period. The second clock signal can oscillate between low and high levels during the address scan period and can remain at a low or high level during the self-scan period.

[0018] In an embodiment, the first stage may include: a first logic circuit that controls the signal of a first control node and the signal of a first inverting control node in response to a first input signal and a first clock signal; and a first buffer circuit that outputs a first gate signal in response to the signal of the first control node and the signal of the first inverting control node. The width of the first buffer circuit in a second direction intersecting the first direction may be greater than the width of the first logic circuit in the second direction.

[0019] In an embodiment, the second stage may include: a second logic circuit that controls the signal of the second control node and the signal of the second inverting control node in response to the second input signal and the first clock signal; and a second buffer circuit that outputs a second gate signal in response to the signal of the second control node and the signal of the second inverting control node. The width of the second buffer circuit in the second direction may be greater than the width of the second logic circuit in the second direction.

[0020] In this embodiment, each of the first stage and the second stage may include a plurality of transistors. Each of the transistors may be an N-type oxide semiconductor transistor.

[0021] A gate driver according to an embodiment includes: a first gate driver including a first stage that generates a first gate signal as a first output to each of a plurality of pixel rows; and a second gate driver including a second stage that generates a second gate signal as a second output to each of the plurality of pixel rows, the second stage and the first stage being arranged alternately in a first direction. The first gate driver and the second gate driver share a first clock signal. Each of the first stage and the second stage is connected to at least four pixel rows of the plurality of pixel rows.

[0022] In an embodiment, the gate driver may further include: a third gate driver, including a third stage that generates a third gate signal as a third output to each of the plurality of pixel rows; and a fourth gate driver, including a fourth stage that generates a fourth gate signal as a fourth output to each of the plurality of pixel rows, the fourth stage and the third stage being arranged alternately in a first direction. The third gate driver and the fourth gate driver may share a second clock signal. Each of the third stage and the fourth stage may be connected to at least four of the plurality of pixel rows.

[0023] In an embodiment, the gate driver may further include a fifth gate driver, which includes a fifth stage that generates a fifth gate signal as a fifth output to a plurality of pixel rows. The fifth stage may include a plurality of sub-stages, each of which may be connected to a corresponding pixel row among the plurality of pixel rows.

[0024] In this embodiment, the first clock signal can oscillate between low and high levels during the address scan period and the self-scan period. The second clock signal can oscillate between low and high levels during the address scan period and can remain at a low or high level during the self-scan period.

[0025] In an embodiment, the first stage may include: a first logic circuit that controls the signal of a first control node and the signal of a first inverting control node in response to a first input signal and a first clock signal; and a first buffer circuit that outputs a first gate signal in response to the signal of the first control node and the signal of the first inverting control node. The width of the first buffer circuit in a second direction intersecting the first direction may be greater than the width of the first logic circuit in the second direction.

[0026] An electronic device according to an embodiment includes a processor for generating image data and a display device for displaying an image based on the image data. The display device includes: a display panel including a plurality of pixel rows arranged in a first direction and each including a plurality of pixels; a first gate driver including a first stage that generates a first gate signal as a first output to each of the plurality of pixel rows; and a second gate driver including a second stage that generates a second gate signal as a second output to each of the plurality of pixel rows, the second stage being alternately arranged with the first stage in the first direction. The first gate driver and the second gate driver share a first clock signal. Each of the first stage and the second stage is connected to at least four of the plurality of pixel rows.

[0027] In the gate driver according to the embodiment, the stages of the first gate driver and the second gate driver are arranged alternately in the column direction, and each stage of the first gate driver and the second gate driver is connected to at least four pixel rows, thereby reducing the power consumption and area of ​​the gate driver.

[0028] The display device according to an embodiment includes a gate driver with low power consumption and a small area, such that the power consumption and dead zone of the display device can be similarly low and small, respectively.

[0029] The electronic device according to the embodiment includes a display device with low power consumption, such that the power consumption of the electronic device can be low. Attached Figure Description

[0030] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0031] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0032] Figure 2 It is shown Figure 1 An example diagram of a portion of a display device.

[0033] Figure 3 It is shown Figure 1 An example diagram of a portion of a display device.

[0034] Figure 4 It is shown Figure 1 An example diagram of a portion of a display device.

[0035] Figure 5 This is an example diagram showing a portion of a display device based on a comparison example.

[0036] Figure 6 It is shown Figure 1 An example diagram of a portion of a display device.

[0037] Figure 7 It is shown Figure 1 A circuit diagram of an example pixel.

[0038] Figure 8 It is shown that it is provided to Figure 7 Timing diagram of the gate signal of the pixel.

[0039] Figure 9 This shows that the first gate signal is provided to Figure 7 The first-stage circuit diagram of the pixel.

[0040] Figure 10 It is shown Figure 9 The first-level layout diagram.

[0041] Figure 11 This shows that the second gate signal is provided to Figure 7 The second-level circuit diagram of the pixel.

[0042] Figure 12 It is shown Figure 11 The second-level layout diagram.

[0043] Figure 13 It is shown Figure 1 A circuit diagram of an example pixel.

[0044] Figure 14 It is shown that it is provided to Figure 13 Timing diagram of the gate signal of the pixel.

[0045] Figure 15 This is a timing diagram illustrating the clock signal according to an embodiment.

[0046] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment. Detailed Implementation

[0047] The gate driver, display device, and electronic device according to illustrative embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The same or similar reference numerals may be used for the same or similar elements in the drawings.

[0048] Figure 1 The illustration shows a display device according to an embodiment, generally indicated by reference numeral 100.

[0049] See Figure 1 The display device 100 may include a display panel 110, a gate driver 120 connected to the display panel 110, a data driver 130 connected to the display panel 110, and a controller 140 connected to the gate driver 120 and the data driver 130.

[0050] Display panel 110 may include multiple pixel rows PXR. Each of the pixel rows PXR may include multiple pixels PX. Each pixel PX may emit light in response to a signal from gate driver 120 including a first gate signal GS1, a second gate signal GS2, a third gate signal GS3, a fourth gate signal GS4, and a fifth gate signal GS5, and a signal from data driver 130 including a data voltage VDAT.

[0051] The gate driver 120 may include a first gate driver 121, a second gate driver 122, a third gate driver 123, a fourth gate driver 124, and a fifth gate driver 125.

[0052] The first gate driver 121 can provide a first gate signal GS1 to the pixel row PXR. The first gate driver 121 can generate the first gate signal GS1 based on a first gate control signal GCNT1 from the controller 140. The first gate control signal GCNT1 may include a first clock signal and a first gate start signal.

[0053] The second gate driver 122 can provide a second gate signal GS2 to the pixel row PXR. The second gate driver 122 can generate the second gate signal GS2 based on a second gate control signal GCNT2 from the controller 140. The second gate control signal GCNT2 may include a first clock signal and a second gate start signal.

[0054] The third gate driver 123 can provide a third gate signal GS3 to the pixel row PXR. The third gate driver 123 can generate the third gate signal GS3 based on the third gate control signal GCNT3 from the controller 140. The third gate control signal GCNT3 may include a second clock signal and a third gate start signal.

[0055] The fourth gate driver 124 can provide a fourth gate signal GS4 to the pixel row PXR. The fourth gate driver 124 can generate the fourth gate signal GS4 based on the fourth gate control signal GCNT4 from the controller 140. The fourth gate control signal GCNT4 may include a second clock signal and a fourth gate start signal.

[0056] The fifth gate driver 125 can provide a fifth gate signal GS5 to the pixel row PXR. The fifth gate driver 125 can generate the fifth gate signal GS5 based on the fifth gate control signal GCNT5 from the controller 140. The fifth gate control signal GCNT5 may include a third clock signal and a fifth gate start signal.

[0057] Data driver 130 can provide a data voltage VDAT to pixel PX. Data driver 130 can generate data voltage VDAT based on data signal DATA and data control signal DCNT from controller 140. Data driver 130 can convert digital data signal DATA into analog data voltage VDAT. Data control signal DCNT may include data clock signal and / or load signal, etc.

[0058] The controller 140 can control the operation and / or drive of the gate driver 120 and the data driver 130. The controller 140 can provide first to fifth gate control signals GCNT1, GCNT2, GCNT3, GCNT4, and GCNT5 to the first to fifth gate drivers 121, 122, 123, 124, and 125 respectively, and can provide a data signal DATA and a data control signal DCNT to the data driver 130. The controller 140 can generate the first to fifth gate control signals GCNT1, GCNT2, GCNT3, GCNT4, and GCNT5, the data signal DATA, and the data control signal DCNT based on the received image data IMG and the received control signal CTRL. The controller 140 can convert the image data IMG into the data signal DATA. The control signal CTRL may include a master clock signal, a horizontal synchronization signal, a vertical synchronization signal, and / or a data enable signal, etc.

[0059] Figure 2 Illustration Figure 1 An example of a portion of the display device 100, generally indicated by reference numeral 200. Figure 3 Illustration Figure 1 An example of a portion of the display device 100, generally indicated by reference numeral 300. Additionally, Figure 4 Illustration Figure 1 An example of a portion of the display device 100, generally indicated by reference numeral 400.

[0060] See Figures 1 to 4 The pixel row PXR can be arranged on the first direction DR1. The first gate signal GS1, the second gate signal GS2, the third gate signal GS3, the fourth gate signal GS4, and the fifth gate signal GS5 can be applied to each of the pixel row PXR.

[0061] The first gate driver 121 may include a first stage ST1 that outputs a first gate signal GS1, and the second gate driver 122 may include a second stage ST2 that outputs a second gate signal GS2. The first stage ST1 and the second stage ST2 may be arranged alternately in the first direction DR1. Figure 2As shown in the figure, the first sub-stage ST1[1] in the first stage ST1 can output the first gate signal GS1[1], and the second sub-stage ST2[1] in the second stage ST2 can output the second gate signal GS2[1]. The first sub-stage ST1[1] and the second sub-stage ST2[1] can be arranged on the first direction DR1.

[0062] The first gate driver 121 and the second gate driver 122 can receive the first clock signal CK1 and can share the first clock signal CK1. The first clock signal CK1 may include a first clock signal CK1-1 and a first clock signal CK1-2. The first clock signal CK1-2 may be a signal in which the first clock signal CK1-1 is shifted by half a cycle of the first clock signal CK1-1.

[0063] The third gate driver 123 may include a third stage ST3 that outputs a third gate signal GS3, and the fourth gate driver 124 may include a fourth stage ST4 that outputs a fourth gate signal GS4. The third stage ST3 and the fourth stage ST4 may be arranged alternately in the first direction DR1. Figure 2 As shown in the figure, the third sub-stage ST3[1] in the third stage ST3 can output the third gate signal GS3[1], and the fourth sub-stage ST4[1] in the fourth stage ST4 can output the fourth gate signal GS4[1]. The third sub-stage ST3[1] and the fourth sub-stage ST4[1] can be arranged on the first direction DR1.

[0064] The third gate driver 123 and the fourth gate driver 124 can receive the second clock signal CK2 and can share the second clock signal CK2. The second clock signal CK2 can include the second-first clock signal CK2-1 and the second-second clock signal CK2-2. The second-second clock signal CK2-2 can be the second-first clock signal CK2-1 shifted by half a cycle of the second-first clock signal CK2-1.

[0065] Each of the first-level ST1, second-level ST2, third-level ST3, and fourth-level ST4 can be connected to at least four pixel rows of PXR. For example, each of the first-level ST1, second-level ST2, third-level ST3, and fourth-level ST4 can provide a corresponding gate signal to at least four pixel rows of PXR. In an embodiment, each of the first-level ST1, second-level ST2, third-level ST3, and fourth-level ST4 can be connected to an even number of pixel rows of PXR.

[0066] In an embodiment, such as Figure 2As illustrated in the figure, each of the first level ST1, the second level ST2, the third level ST3, and the fourth level ST4 can be connected to four pixel rows PXR[1] to PXR[4]. In an embodiment, as shown... Figure 3 As illustrated, each of the first level ST1, the second level ST2, the third level ST3, and the fourth level ST4 can be connected to six pixel rows PXR[1] through PXR[6]. In an embodiment, as shown... Figure 4 As shown in the figure, each of the first level ST1, the second level ST2, the third level ST3 and the fourth level ST4 can be connected to eight pixel rows PXR[1] to PXR[8].

[0067] The fifth gate driver 125 may include fifth sub-stages ST5[1] to ST5[4] that output fifth gate sub-signals GS5[1] to GS5[4] respectively. The fifth sub-stages ST5[1] to ST5[4] may be arranged on the first direction DR1.

[0068] Each of the fifth sub-levels ST5[1] to ST5[4] can be connected to a corresponding pixel row in pixel rows PXR[1] to PXR[4]. For example, the fifth sub-level ST5[3] can provide a fifth gate signal GS5[3] to a pixel row PXR[3].

[0069] like Figure 3 As illustrated, the fifth gate driver 125 may include fifth sub-stages ST5[1] to ST5[6] that respectively output fifth gate signals GS5[1] to GS5[6]. The fifth sub-stages ST5[1] to ST5[6] may be arranged on a first direction DR1. Each of the fifth sub-stages ST5[1] to ST5[6] may be connected to a corresponding pixel row in pixel rows PXR[1] to PXR[6]. For example, the fifth sub-stage ST5[5] may provide a fifth gate signal GS5[5] to a pixel row PXR[5], and the fifth sub-stage ST5[6] may provide a fifth gate signal GS5[6] to a pixel row PXR[6].

[0070] like Figure 4As illustrated, the fifth gate driver 125 may include fifth sub-stages ST5[1] to ST5[8] that respectively output fifth gate signals GS5[1] to GS5[8]. The fifth sub-stages ST5[1] to ST5[8] may be arranged on a first direction DR1. Each of the fifth sub-stages ST5[1] to ST5[8] may be connected to a corresponding pixel row in pixel rows PXR[1] to PXR[8]. For example, the fifth sub-stage ST5[7] may provide a fifth gate signal GS5[7] to a pixel row PXR[7], and the fifth sub-stage ST5[8] may provide a fifth gate signal GS5[8] to a pixel row PXR[8].

[0071] In an embodiment, the first gate driver 121 paired with the second gate driver 122 and the third gate driver 123 paired with the fourth gate driver 124 can both be positioned close to the first side of the pixel row PXR on the second direction DR2 that intersects the first direction DR1.

[0072] In an embodiment, the first gate driver 121 paired with the second gate driver 122 and the third gate driver 123 paired with the fourth gate driver 124 can be positioned close to the first side of the pixel row PXR in the second direction DR2 and close to the second side of the pixel row PXR opposite to the first side, respectively.

[0073] The fifth gate driver 125 may be positioned close to the first side of the pixel row PXR in the second direction DR2. In an embodiment, the fifth gate driver 125 may be positioned close to the first side of the pixel row PXR in the second direction DR2 and close to the second side of the pixel row PXR opposite to the first side.

[0074] Figure 5 The illustration is a portion of a display device based on a comparative example, the overall of which is indicated by reference numeral 500.

[0075] See Figure 5In the comparative example, the first sub-stages ST1[1] and ST1[2] can be arranged on the first direction DR1 and can receive the first clock signal CK1. The second sub-stages ST2[1] and ST2[2] can be arranged on the first direction DR1, can be adjacent to the first sub-stages ST1[1] and ST1[2] on the second direction DR2, and can receive the second clock signal CK2. The third sub-stages ST3[1] and ST3[2] can be arranged on the first direction DR1, can be adjacent to the second sub-stages ST2[1] and ST2[2] on the second direction DR2, and can receive the third clock signal CK3. The fourth sub-stages ST4[1] and ST4[2] can be arranged on the first direction DR1, can be adjacent to the third sub-stages ST3[1] and ST3[2] on the second direction DR2, and can receive the fourth clock signal CK4.

[0076] In the comparison example, each of the first sub-levels ST1[1] and ST1[2], the second sub-levels ST2[1] and ST2[2], the third sub-levels ST3[1] and ST3[2], and the fourth sub-levels ST4[1] and ST4[2] can be connected to two pixel rows PXR. For example, each of the first sub-levels ST1[2], the second sub-levels ST2[2], the third sub-levels ST3[2], and the fourth sub-levels ST4[2] can provide a corresponding gate signal GS1[2], GS2[2], GS3[2], or GS4[2] to two pixel rows PXR[3] and PXR[4].

[0077] In the comparative example, as the number of stages connected to pixel rows PXR[1] to PXR[4] increases (e.g., the number of first to fourth sub-stages ST1[1] to ST4[2] connected to four pixel rows PXR[1] to PXR[4] is 8), and the number of clock signals applied to each stage increases (e.g., first to fourth clock signals CK1 to CK4 are applied to the first to fourth sub-stages ST1[1] to ST4[2]), the power consumption of the gate driver may increase. In this embodiment, as the number of stages connected to pixel rows PXR is minimized (e.g., the number of first to fourth stages ST1 to ST4 connected to four pixel rows PXR is four instead of eight) and the number of clock signals applied to each stage is minimized (e.g., first clock signal CK1 and second clock signal CK2 are applied to the first to fourth stages ST1 to ST4), the power consumption of the gate driver 120 can be minimized. Since the display device 100 according to this embodiment includes a gate driver 120 with minimized power consumption, the power consumption of the display device 100 can also be minimized.

[0078] The power consumption P of the gate driver can be calculated using Equation 1:

[0079] [Equation 1]

[0080] P = nCV 2 f

[0081] In Equation 1, n is the number of wirings transmitting the clock signal, C is the capacitance of the gate driver, V is the voltage across the gate driver, and f is the frequency of the clock signal. In the comparative example, n can be 8, and f can be 120Hz. In this embodiment, since the first stage ST1 and the second stage ST2 share the first clock signal CK1, and the third stage ST3 and the fourth stage ST4 share the second clock signal CK2, n can be 4, and since the number of pixel rows connected to a stage in this embodiment is half the number of pixel rows connected to a stage in the comparative example, f can be 60Hz. Accordingly, the power consumption of the gate driver 120 according to this embodiment can be approximately 25% of the power consumption of the gate driver according to the comparative example.

[0082] In the comparative example, since the first side of levels ST1 to ST5 near pixel row PXR is located in five columns in the second direction DR2, the area of ​​the gate driver 120 may be large. In this embodiment, since the first side of levels ST1 to ST5 near pixel row PXR is located in three columns in the second direction DR2, the area of ​​the gate driver 120 can be minimized. Since the display device 100 according to this embodiment includes a gate driver 120 with a reduced area, the dead zone of the display device 100 can be minimized.

[0083] Figure 6 Illustration Figure 1 An example of a portion of the display device 100, generally indicated by reference numeral 600.

[0084] See Figure 1 and Figure 6 In an embodiment, the first gate driver 121 and the second gate driver 122 may be positioned close to the first side of the pixel row PXR in the second direction DR2, and the third gate driver 123 and the fourth gate driver 124 may be positioned close to the second side of the pixel row PXR in the second direction DR2.

[0085] Figure 7 Illustration Figure 1 An example of a pixel PX. Figure 8 The illustration is provided Figure 7 The timing of the gate signals EM, EMB, GR, GI and GW of the pixel PX.

[0086] See Figure 7 and Figure 8Pixel PX can receive the write gate signal GW, the reference gate signal GR, the initialization gate signal GI, the transmit signal EM, the inverted transmit signal EMB, and the data voltage VDAT. Reference Figures 1 to 6 The first gate signal GS1, the second gate signal GS2, the third gate signal GS3, the fourth gate signal GS4, and the fifth gate signal GS5 described can be the transmit signal EM, the initialization gate signal GI, the inverted transmit signal EMB, the reference gate signal GR, and the write gate signal GW, respectively, but are not limited to these. See the reference below. Figures 7 to 12 As described in the illustrative example, EM, GI, EMB, GR, and GW represent the first gate signal, the second gate signal, the third gate signal, the fourth gate signal, and the fifth gate signal, respectively.

[0087] Pixel PX may include a light-emitting element LED, a first transistor M1 connected to the light-emitting element LED, a second transistor M2 connected to the first transistor M1, a third transistor M3 connected to the second transistor M2, a fourth transistor M4 connected to a sixth transistor M6, a fifth transistor M5 connected to the first transistor M1, a sixth transistor M6 connected between the first transistor M1 and the light-emitting element LED, a storage capacitor CST connected between the first transistor M1 and the third transistor M3, a holding capacitor CHD connected to the storage capacitor CST, and a parasitic capacitor CPR connected across the two ends of the light-emitting element LED.

[0088] The light-emitting element (LED) can emit light with a brightness corresponding to the driving current. The LED may include a first electrode (e.g., an anode) connected to the fourth node N4 and a second electrode (e.g., a cathode) receiving a second power supply voltage ELVSS. In embodiments, the LED may be one of an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, and a micro-light-emitting diode.

[0089] The first transistor M1 can control the drive current flowing through the light-emitting element LED. The first transistor M1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. In an embodiment, the first transistor M1 may further include a back gate connected to the third node N3.

[0090] The second transistor M2 can provide a data voltage VDAT to the gate of the first transistor M1 in response to the fifth gate signal GW. The second transistor M2 may include a gate for receiving the fifth gate signal GW, a first electrode for receiving the data voltage VDAT, and a second electrode connected to the first node N1.

[0091] The third transistor M3 can provide a reference voltage VREF to the gate of the first transistor M1 in response to the fourth gate signal GR. The third transistor M3 may include a gate that receives the fourth gate signal GR, a first electrode that receives the reference voltage VREF, and a second electrode connected to the first node N1.

[0092] The fourth transistor M4 can provide an initialization voltage VINT to the first electrode of the light-emitting element LED in response to the second gate signal GI. The fourth transistor M4 may include a gate that receives the second gate signal GI, a first electrode that receives the initialization voltage VINT, and a second electrode connected to the fourth node N4.

[0093] The fifth transistor M5 can, in response to the first gate signal EM, block the connection between the first electrode of the first transistor M1 and the line providing the first power supply voltage ELVDD. The fifth transistor M5 may include a gate that receives the first gate signal EM, a first electrode that receives the first power supply voltage ELVDD, and a second electrode connected to the second node N2.

[0094] The sixth transistor M6 can, in response to the third gate signal EMB, block the connection between the second electrode of the first transistor M1 and the line providing the second power supply voltage ELVSS. The sixth transistor M6 may include a gate for receiving the third gate signal EMB, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0095] In the embodiments, each of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 may be an N-type oxide semiconductor transistor.

[0096] The storage capacitor CST can store the signal of the first node N1. The storage capacitor CST may include a first electrode connected to the first node N1 and a second electrode connected to the third node N3.

[0097] The holding capacitor CHD can store the signal of the third node N3. The holding capacitor CHD may include a first electrode connected to the third node N3 and a second electrode receiving the first power supply voltage ELVDD.

[0098] The parasitic capacitor CPR can be connected in parallel with the light-emitting element (LED). The parasitic capacitor CPR can be an internal capacitor of the LED.

[0099] During the address scan period when the data voltage VDAT is written to pixel PX, the first gate signal EM may include two pulses, and each of the second to fifth gate signals GI, EMB, GR, and GW may include its own pulse. During the address scan period, the first transistor M1 may be initialized by the pulse of the fourth gate signal GR, the light-emitting element LED may be initialized by the pulse of the second gate signal GI, the threshold voltage of the first transistor M1 may be compensated by the first pulse of the first gate signal EM in a source follower manner, the data voltage VDAT may be written to the first transistor M1 by the pulse of the fifth gate signal GW, and the drive current corresponding to the data voltage VDAT may flow through the light-emitting element LED by the pulses of the second pulse of the first gate signal EM and the pulse of the third gate signal EMB.

[0100] During the self-scanning period when the data voltage VDAT is not written to pixel PX, each of the first gate signal EM and the second gate signal GI may include a pulse, and each of the third to fifth gate signals EMB, GR, and GW does not need to include a pulse. During the self-scanning period, the light-emitting element LED can be initialized by the pulse of the second gate signal GI, and the drive current corresponding to the data voltage VDAT written during the address scan period can flow through the light-emitting element LED by the pulse of the first gate signal EM.

[0101] Figure 9 The diagram shows the first gate signal EM being provided to... Figure 7 The first level ST1 of the pixel PX. Figure 10 Further illustrations Figure 9 The first level, ST1.

[0102] See Figure 9 and Figure 10 The first stage ST1 can receive a first input signal EM_INS, a first clock signal CK1 including a first clock sub-signal (i.e., the first-first clock sub-signal (corresponding to the first-first clock signal described above) CK1-1 and the first-second clock sub-signal (corresponding to the first-second clock signal described above) CK1-2), a high gate voltage VGH, a first low gate voltage VGL1, a second low gate voltage VGL2, and a reset signal ESR. The first stage ST1 can output a first gate signal EM and a first carry signal EM_CR. The first stage ST1 may include a first logic circuit LC1 and a first buffer circuit BC1.

[0103] The first logic circuit LC1 can control the signals of the first-first control node EM_Q1, the first-second control node EM_Q2, and the first inverting control node EM_QB in response to the first input signal EM_INS and the first clock signal CK1 including the first clock sub-signals CK1-1 and CK1-2. The first-first control node EM_Q1 and the first-second control node EM_Q2 can be connected in series with the transistor connected between them. The first logic circuit LC1 may include: a first transistor T1 including first sub-transistors T1_1 and T1_2, a second transistor T2 including second sub-transistors T2_1 and T2_2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 including eighth sub-transistors T8_1 and T8_2, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a thirteenth transistor T13, a fifteenth transistor T15 including sub-transistors T15_1 and T15_2, a sixteenth transistor T16 including sub-transistors T16_1 and T16_2, a first capacitor C1, and a second capacitor C2.

[0104] The first transistor T1, including first sub-transistors T1_1 and T1_2, can transmit the first input signal EM_INS to the first control node EM_Q1 in response to the first-first clock sub-signal CK1-1. In an embodiment, the first transistor T1, including first sub-transistors T1_1 and T1_2, may include sub-transistors T1_1 and T1_2 connected in series.

[0105] The second transistor T2, including the second sub-transistors T2_1 and T2_2, can transmit the second low gate voltage VGL2 to the first-first control node EM_Q1 in response to the signal of the first inverting control node EM_QB. In an embodiment, the second transistor T2, including the second sub-transistors T2_1 and T2_2, may include the sub-transistors T2_1 and T2_2 connected in series.

[0106] The third transistor T3 may include a gate that receives a high gate voltage VGH, a first electrode connected to the first-first control node EM_Q1, and a second electrode connected to the first-second control node EM_Q2. The third transistor T3 may be an normally-on transistor (AOT).

[0107] The fourth transistor T4 can transmit the second low gate voltage VGL2 to the first inverting control node EM_QB in response to the signal from the first-first control node EM_Q1.

[0108] The fifth transistor T5 can transmit the first-second clock signal CK1-2 to the first electrode of the first capacitor C1 in response to the signal of the first-second control node EM_Q2.

[0109] The sixth transistor T6 can respond to the signal of the first-second control node EM_Q2 and output a high gate voltage VGH as the first carry signal EM_CR.

[0110] The seventh transistor T7 can transmit a high gate voltage VGH to the first electrode of the ninth transistor T9 in response to the first-first clock signal CK1-1.

[0111] The eighth transistor T8, including the eighth sub-transistors T8_1 and T8_2, can transmit the first clock signal CK1-1 to the first electrode of the ninth transistor T9 in response to the signal of the first-first control node EM_Q1. In an embodiment, the eighth transistor T8, including the eighth sub-transistors T8_1 and T8_2, may include the sub-transistors T8_1 and T8_2 connected in series.

[0112] The ninth transistor T9 may include a gate for receiving a high gate voltage VGH, a first electrode, and a second electrode connected to the first electrode of the second capacitor C2. The ninth transistor T9 may be an normally-on transistor (AOT).

[0113] The tenth transistor T10 can transmit the first-second clock signal CK1-2 to the second electrode of the second capacitor C2 in response to the signal at the first electrode of the second capacitor C2.

[0114] The eleventh transistor T11 can transmit a high gate voltage VGH to the first inverting control node EM_QB in response to the signal at the second electrode of the second capacitor C2.

[0115] The thirteenth transistor T13 can respond to the signal of the first inverting control node EM_QB and output a second low gate voltage VGL2 as the first carry signal EM_CR.

[0116] The fifteenth transistor T15, including sub-transistors T15_1 and T15_2, can transmit a high gate voltage VGH in response to a signal from the first-first control node EM_Q1 to the intermediate node of sub-transistors T1_1 and T1_2 of the first transistor T1, the intermediate node of sub-transistors T2_1 and T2_2 of the second transistor T2, and the intermediate node of sub-transistors T16_1 and T16_2 of the sixteenth transistor T16. In an embodiment, the fifteenth transistor T15, including sub-transistors T15_1 and T15_2, may include sub-transistors T15_1 and T15_2 connected in series.

[0117] The sixteenth transistor T16, including sub-transistors T16_1 and T16_2, can transmit a first low gate voltage VGL1 to the first-first control node EM_Q1 in response to a reset signal ESR. In an embodiment, the sixteenth transistor T16, including sub-transistors T16_1 and T16_2, may include sub-transistors T16_1 and T16_2 connected in series.

[0118] The first capacitor C1 can be connected between the gate and the second electrode of the fifth transistor T5. The second capacitor C2 can be connected between the gate and the second electrode of the tenth transistor T10.

[0119] The first buffer circuit BC1 can output a first gate signal EM in response to the signals of the first-first control node EM_Q1, the first-second control node EM_Q2, and the signal of the first inverting control node EM_QB. The first buffer circuit BC1 may include a twelfth transistor T12, a fourteenth transistor T14, a third capacitor C3, and a fourth capacitor C4.

[0120] The twelfth transistor T12 can respond to the signal of the first-second control node EM_Q2 and output a high gate voltage VGH as the first gate signal EM.

[0121] The fourteenth transistor T14 can respond to the signal of the first inverting control node EM_QB and output a first low gate voltage VGL1 as the first gate signal EM.

[0122] The third capacitor C3 can be connected between the gate and the second electrode of the twelfth transistor T12. The fourth capacitor C4 can be connected between the gate and the second electrode of the fourteenth transistor T14.

[0123] In this embodiment, each of the transistors included in the first stage ST1 may be an N-type oxide semiconductor transistor. For example, each of the following transistors included in the first stage ST1—a first transistor T1 including sub-transistors T1_1 and T1_2, a second transistor T2 including sub-transistors T2_1 and T2_2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 including sub-transistors T8_1 and T8_2, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 including sub-transistors T15_1 and T15_2, and a sixteenth transistor T16 including sub-transistors T16_1 and T16_2—may be an N-type oxide semiconductor transistor.

[0124] In this embodiment, the area of ​​the first buffer circuit BC1 can be larger than the area of ​​the first logic circuit LC1. The width of the first buffer circuit BC1 in the second direction DR2 can be larger than the width of the first logic circuit LC1 in the second direction DR2, and the length of the first buffer circuit BC1 in the first direction DR1 can be substantially equal to the length of the first logic circuit LC1 in the first direction DR1. Because the area of ​​the first buffer circuit BC1 is larger than the area of ​​the first logic circuit LC1, even if the number of pixel rows PXR connected to the first stage ST1 (e.g., the load of the first stage ST1) increases, the first gate signal EM can still be stably output to the pixel rows PXR.

[0125] In addition to receiving the third input signal and the second clock signal CK2, which includes the second clock sub-signal (i.e., the second-first clock sub-signal (corresponding to the second-first clock signal described above) CK2-1 and the second-second clock sub-signal (corresponding to the second-second clock signal described above) CK2-2), and outputting the third gate signal EMB and the third carry signal, the third stage ST3 can be connected to the reference... Figure 9 and Figure 10 The descriptions of the first level ST1 are substantially the same or similar. Accordingly, the substantially repetitive descriptions of the third level ST3 can be omitted.

[0126] Figure 11 The diagram shows the second gate signal GI being provided to... Figure 7 The second level ST2 of the pixel PX. Figure 12 Further illustrations Figure 11 The second level, ST2.

[0127] See Figure 11 and Figure 12 The second stage ST2 can receive the second input signal GI_INS, the first clock signal CK1 including the first clock sub-signals CK1-1 and CK1-2, the high gate voltage VGH, the first low gate voltage VGL1, the second low gate voltage VGL2, and the reset signal ESR, and can output the second gate signal GI and the second carry signal GI_CR. The second stage ST2 may include the second logic circuit LC2 and the second buffer circuit BC2.

[0128] The second logic circuit LC2 can control the signals of the second-first control node GI_Q1, the second-second control node GI_Q2, and the second inverting control node GI_QB in response to the second input signal GI_INS and the first clock signal CK1, which includes the first clock sub-signals CK1-1 and CK1-2. The second-first control node GI_Q1 and the second-second control node GI_Q2 can be connected in series with the transistor connected between them. The second logic circuit LC2 may include: a first transistor T1 including sub-transistors T1_1 and T1_2, a second transistor T2 including sub-transistors T2_1 and T2_2, a third transistor T3 including sub-transistors T3_1 and T3_2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8 including sub-transistors T8_1 and T8_2, an eleventh transistor T11, a twelfth transistor T12 including sub-transistors T12_1 and T12_2, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a first capacitor C1, and a third capacitor C3.

[0129] A first transistor T1, including sub-transistors T1_1 and T1_2, can transmit a second input signal GI_INS to a second-first control node GI_Q1 in response to a first clock sub-signal CK1-1. In an embodiment, the first transistor T1, including sub-transistors T1_1 and T1_2, may include sub-transistors T1_1 and T1_2 connected in series.

[0130] The second transistor T2, including sub-transistors T2_1 and T2_2, can transmit a high gate voltage VGH in response to a signal from the second-first control node GI_Q1 to the intermediate nodes of the sub-transistors T1_1 and T1_2 of the first transistor T1, the intermediate nodes of the sub-transistors T3_1 and T3_2 of the third transistor T3, and the intermediate nodes of the sub-transistors T8_1 and T8_2 of the eighth transistor T8. In an embodiment, the sub-transistors T2_1 and T2_2 of the second transistor T2 may include sub-transistors T2_1 and T2_2 connected in series.

[0131] The third transistor T3, including sub-transistors T3_1 and T3_2, can transmit the second low gate voltage VGL2 to the second-first control node GI_Q1 in response to the signal of the second inverting control node GI_QB. In an embodiment, the sub-transistors T3_1 and T3_2 of the third transistor T3 may include sub-transistors T3_1 and T3_2 connected in series.

[0132] The fourth transistor T4 may include a gate that receives a high gate voltage VGH, a first electrode connected to the second-first control node GI_Q1, and a second electrode connected to the second-second control node GI_Q2. The fourth transistor T4 may be an normally-on transistor (AOT).

[0133] The fifth transistor T5 can transmit the first-second clock sub-signal CK1-2 to the first electrode of the first capacitor C1 in response to the signal of the second-second control node GI_Q2.

[0134] The sixth transistor T6 can respond to the signal of the second-second control node GI_Q2 and output a high gate voltage VGH as the second carry signal GI_CR.

[0135] The seventh transistor T7 can respond to the signal of the second inverting control node GI_QB and output a second low gate voltage VGL2 as a second carry signal GI_CR.

[0136] The eighth transistor T8, including sub-transistors T8_1 and T8_2, can transmit a first low gate voltage VGL1 to the second-first control node GI_Q1 in response to a reset signal ESR. In an embodiment, the eighth transistor T8 may include sub-transistors T8_1 and T8_2 connected in series.

[0137] The eleventh transistor T11 can transmit the second low gate voltage VGL2 to the second inverting control node GI_QB in response to the signal of the second-first control node GI_Q1.

[0138] The twelfth transistor T12, including sub-transistors T12_1 and T12_2, may include a gate receiving a high gate voltage VGH, a first electrode receiving the high gate voltage VGH, and a second electrode connected to the first electrode of the third capacitor C3. Sub-transistors T12_1 and T12_2 of the twelfth transistor T12 may each be an normally-on transistor (AOT). In an embodiment, sub-transistors T12_1 and T12_2 of the twelfth transistor T12 may include sub-transistors T12_1 and T12_2 connected in series.

[0139] The thirteenth transistor T13 can transmit a high gate voltage VGH to the first electrode of the fourteenth transistor T14 in response to a signal from the second electrode of the twelfth transistor T12, which includes sub-transistors T12_1 and T12_2.

[0140] The fourteenth transistor T14 can transmit the signal from the second electrode of the thirteenth transistor T13 to the second inverting control node GI_QB in response to the first-second clock sub-signal CK1-2.

[0141] The fifteenth transistor T15 can transmit the first low gate voltage VGL1 to the first electrode of the third capacitor C3 in response to the signal of the second-first control node GI_Q1.

[0142] The first capacitor C1 can be connected between the gate and the second electrode of the fifth transistor T5. The third capacitor C3 can have a first terminal connected to each of the second electrode of the twelfth transistor T12 (including sub-transistors T12_1 and T12_2), the gate of the thirteenth transistor T13, and the second electrode of the fifteenth transistor T15; and the third capacitor C3 can have a second terminal connected to the second inverting control node GI_QB.

[0143] The second buffer circuit BC2 can output a second gate signal GI in response to the signals of the second-first control node GI_Q1, the second-second control node GI_Q2, and the second inverting control node GI_QB. The second buffer circuit BC2 may include a ninth transistor T9, a tenth transistor T10, and a second capacitor C2.

[0144] The ninth transistor T9 can respond to the signal of the second-second control node GI_Q2 and output a high gate voltage VGH as the second gate signal GI.

[0145] The tenth transistor T10 can respond to the signal of the second inverting control node GI_QB by outputting a first low gate voltage VGL1 as the second gate signal GI.

[0146] The second capacitor C2 can be connected between the gate and the second electrode of the ninth transistor T9.

[0147] In this embodiment, each of the transistors included in the second stage ST2 may be an N-type oxide semiconductor transistor, but is not limited thereto. For example, each of the sub-transistors T1_1 and T1_2 of the first transistor T1, the sub-transistors T2_1 and T2_2 of the second transistor T2, the sub-transistors T3_1 and T3_2 of the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the sub-transistors T8_1 and T8_2 of the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the sub-transistors T12_1 and T12_2 of the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 included in the second stage ST2 may be an N-type oxide semiconductor transistor.

[0148] In this embodiment, the area of ​​the second buffer circuit BC2 can be larger than the area of ​​the second logic circuit LC2. The width of the second buffer circuit BC2 in the second direction DR2 can be larger than the width of the second logic circuit LC2 in the second direction DR2, and the length of the second buffer circuit BC2 in the first direction DR1 can be substantially equal to the length of the second logic circuit LC2 in the first direction DR1. Because the area of ​​the second buffer circuit BC2 is larger than the area of ​​the second logic circuit LC2, even if the number of pixel rows PXR connected to the second stage ST2 (e.g., the load of the second stage ST2) increases, the second gate signal GI can still be stably output to the pixel rows PXR.

[0149] In addition to receiving the fourth input signal and the second clock signal CK2, which includes the second clock sub-signals CK2-1 and CK2-2, and outputting the fourth gate signal GR and the fourth carry signal, the fourth stage ST4 can interact with the reference... Figure 11 and Figure 12 The description of the second level ST2 is essentially the same or similar. Accordingly, the essentially repetitive description of the fourth level ST4 can be omitted.

[0150] Figure 13 Illustration Figure 1 An example of a pixel PX. Figure 14 The illustration is provided Figure 13 The timing of the gate signals EM, GI, GC, GW and GB of the pixel PX.

[0151] See Figure 13 and Figure 14 Pixel PX can receive the write gate signal GW, the compensation gate signal GC, the initialization gate signal GI, the transmit signal EM, the bypass gate signal GB, and the data voltage VDAT. (See reference...) Figures 1 to 6 The first gate signal GS1, the second gate signal GS2, the third gate signal GS3, the fourth gate signal GS4, and the fifth gate signal GS5 described can be the transmit signal EM, the bypass gate signal GB, the initialization gate signal GI, the compensation gate signal GC, and the write gate signal GW, respectively, but are not limited to these. See below for reference. Figure 13 and Figure 14 As described in the illustrative example, EM, GB, GI, GC, and GW represent the first gate signal, the second gate signal, the third gate signal, the fourth gate signal, and the fifth gate signal, respectively.

[0152] Pixel PX may include a light-emitting element LED, a first transistor M1 connected to the light-emitting element LED, a second transistor M2 connected to the first transistor M1, a third transistor M3 connected to the first transistor M1, a fourth transistor M4 connected to the third transistor M3, a fifth transistor M5 connected to the first transistor M1, a sixth transistor M6 connected to the first transistor M1, a seventh transistor M7 connected to the sixth transistor M6, an eighth transistor M8 connected to the second transistor M2, a storage capacitor CST connected to the third transistor M3, and a parasitic capacitor CPR connected across the two ends of the light-emitting element LED.

[0153] The light-emitting element (LED) can emit light with a brightness corresponding to the driving current. The LED may include a first electrode (e.g., an anode) connected to the fourth node N4 and a second electrode (e.g., a cathode) receiving a second power supply voltage ELVSS. In embodiments, the LED may be one of an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, and a micro-light-emitting diode.

[0154] The first transistor M1 can control the drive current flowing through the light-emitting element LED. The first transistor M1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. In an embodiment, the first transistor M1 may further include a back gate that receives a first power supply voltage ELVDD.

[0155] The second transistor M2 can provide a data voltage VDAT to the first electrode of the first transistor M1 in response to the fifth gate signal GW. The second transistor M1 may include a gate for receiving the fifth gate signal GW, a first electrode for receiving the data voltage VDAT, and a second electrode connected to the second node N2.

[0156] The third transistor M3 can compensate the threshold voltage of the first transistor M1 in response to the fourth gate signal GC. The third transistor M3 may include a gate for receiving the fourth gate signal GC, a first electrode connected to the third node N3, and a second electrode connected to the first node N1.

[0157] The fourth transistor M4 can provide a first initialization voltage VINT to the gate of the first transistor M1 in response to the third gate signal GI. The fourth transistor M4 may include a gate that receives the third gate signal GI, a first electrode that receives the first initialization voltage VINT, and a second electrode connected to the first node N1.

[0158] The fifth transistor M5 can, in response to the first gate signal EM, block the connection between the first electrode of the first transistor M1 and the line providing the first power supply voltage ELVDD. The fifth transistor M5 may include a gate that receives the first gate signal EM, a first electrode that receives the first power supply voltage ELVDD, and a second electrode connected to the second node N2.

[0159] The sixth transistor M6 can, in response to the first gate signal EM, block the connection between the second electrode of the first transistor M1 and the line providing the second power supply voltage ELVSS. The sixth transistor M6 may include a gate for receiving the first gate signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4.

[0160] The seventh transistor M7 can provide a second initialization voltage VAINT to the first electrode of the light-emitting element LED in response to the second gate signal GB. The seventh transistor M7 may include a gate that receives the second gate signal GB, a first electrode that receives the second initialization voltage VAINT, and a second electrode connected to the fourth node N4.

[0161] The eighth transistor M8 can provide a bias voltage VBIAS to the first electrode of the first transistor M1 in response to the second gate signal GB. The eighth transistor M8 may include a gate that receives the second gate signal GB, a first electrode that receives the bias voltage VBIAS, and a second electrode connected to the second node N2.

[0162] In the embodiments, each of the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 may be a P-type polysilicon transistor, and each of the third transistor M3 and the fourth transistor M4 may be an N-type oxide semiconductor transistor, but is not limited thereto.

[0163] The storage capacitor CST can store the signal of the first node N1. The storage capacitor CST may include a first electrode connected to the first node N1 and a second electrode receiving a first power supply voltage ELVDD.

[0164] The parasitic capacitor CPR can be connected in parallel with the light-emitting element (LED). The parasitic capacitor CPR can be an internal capacitor of the LED.

[0165] During the address scan period when the data voltage VDAT is written to pixel PX, each of the first gate signal EM, the third gate signal GI, and the fourth gate signal GC may include a pulse, and each of the second gate signal GB and the fifth gate signal GW may include two pulses. During the address scan period, the first transistor M1 can be initialized by the pulse of the third gate signal GI, the threshold voltage of the first transistor M1 can be compensated by the pulse of the fourth gate signal GC in a diode connection manner, the data voltage VDAT can be written to the first transistor M1 by the pulse of the fifth gate signal GW, the light-emitting element LED can be initialized by the pulse of the second gate signal GB, and the first transistor M1 can be turned on and biased by the pulse of the second gate signal GB. Furthermore, the drive current corresponding to the data voltage VDAT can flow through the light-emitting element LED by the pulse of the first gate signal EM.

[0166] During the self-scanning period when the data voltage VDAT is not written to pixel PX, the first gate signal EM may include a pulse, the second gate signal GB may include two pulses, and each of the third to fifth gate signals GI, GC, and GW does not need to include a pulse. During the self-scanning period, the light-emitting element LED can be initialized, and the first transistor M1 can be turned on and biased by the pulse of the second gate signal GB, and the drive current corresponding to the data voltage VDAT written during the address scan period can flow through the light-emitting element LED by the pulse of the first gate signal EM.

[0167] Figure 15 The diagram illustrates the timing of clock sub-signals CK1-1, CK1-2, CK2-1, and CK2-2 according to an embodiment.

[0168] See Figure 15 During the address scan period and the self-scan period, the first-to-first clock sub-signal CK1-1 and the first-to-second clock sub-signal CK1-2 can swing between low and high levels. For example... Figure 8 and Figure 14 The diagram in the image shows... Figure 8 The first gate signal EM and the second gate signal GI and Figure 14 Each of the second gate signals GB may include pulses during the address scan period and the self-scan period, and each of the first gate driver 121 and the second gate driver 122 may generate pulses of the gate signal based on the first-first clock sub-signal CK1-1 and the first-second clock sub-signal CK1-2, which swing between low and high levels, during the address scan period and the self-scan period.

[0169] The second-first clock sub-signal CK2-1 and the second-second clock sub-signal CK2-2 can swing between low and high levels during the address scan period, and can remain low or high during the self-scan period. For example... Figure 8 and Figure 14 The diagram in the image shows... Figure 8 The third gate signal EMB and Figure 14 The third gate signal GI and Figure 8 The fourth gate signal GR and Figure 14 Each of the fourth gate signals GC can include a pulse during the address scan period, but does not need to include a pulse during the self-scan period. Furthermore, each of the third gate driver 123 and the fourth gate driver 124 can generate a gate signal pulse during the address scan period based on the second-first clock sub-signal CK2-1 and the second-second clock sub-signal CK2-2, which swing between low and high levels, and does not need to generate a gate signal pulse during the self-scan period based on the second-first clock sub-signal CK2-1 and the second-second clock sub-signal CK2-2, which remain at a low or high level. Since the second-first clock sub-signal CK2-1 and the second-second clock sub-signal CK2-2 remain at a low or high level during the self-scan period, the power consumption of the gate driver 120 can be minimized.

[0170] Figure 16 The figure shows an electronic device 1000 according to an embodiment.

[0171] See Figure 16 The electronic device 1000 may include a processor 1010, a memory device 1020 connected to a bus 1002, a storage device 1030 connected to a bus 1002, an input / output (I / O) device 1040 connected to a bus 1002, a power supply 1050 connected to a bus 1002, and a display device 1060 connected to a bus 1002. The electronic device 1000 may further include multiple ports capable of communicating with graphics cards, sound cards, memory cards, and / or USB devices, or with other systems.

[0172] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 may be a microprocessor and / or a central processing unit (CPU), etc. Processor 1010 can be connected to other components via address buses, control buses, and / or data buses, etc. In embodiments, processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In embodiments, processor 1010 can generate... Figure 1 Image data IMG and Figure 1 The control signal CTRL can be provided to the display device 1060, and the image data IMG and the control signal CTRL can be provided to the display device 1060.

[0173] The memory device 1020 can store data associated with the operation of the electronic device 1000. For example, the memory device 1020 may include: non-volatile memory devices, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), and / or ferroelectric random access memory (FRAM); and / or volatile memory devices, such as dynamic random access memory (DRAM), static random access memory (SRAM), and / or mobile DRAM.

[0174] Storage device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), and / or CD-ROMs, etc. I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and / or mouse, and output devices such as speakers and / or printers. Power supply 1050 can provide sufficient power for the operation of electronic device 1000. Display device 1060 can be connected to other components via bus 1002 and / or other buses or communication links. Display device 1060 may correspond to... Figure 1 The display device 100. The display device 1060 can display images based on image data IMG.

[0175] In the gate driver included in the display device 1060, stages of the first gate driver and the second gate driver are arranged alternately in the column direction. Each stage of the first gate driver and the second gate driver is connected to at least four pixel rows, and the power consumption and / or area of ​​the gate driver can be minimized. The display device 1060 includes a gate driver with minimized power consumption and minimized area, and the power consumption and dead zone of the display device 1060 can also be minimized. Furthermore, the electronic device 1000 includes the display device 1060 with minimized power consumption, and the power consumption of the electronic device 1000 can also be minimized.

[0176] The display device according to the embodiments can be applied to display devices included in computers such as laptops, mobile phones, smartphones, smartboards, smartwatches, PMPs, PDAs, and / or MP3 players.

[0177] Although the gate driver, display device, and electronic device according to illustrative embodiments have been described by way of example with reference to the accompanying drawings, modifications and changes can be made to the embodiments by those skilled in the art or related fields without departing from the scope and spirit of the technology as defined by the claims.

Claims

1. A display apparatus comprising: a display panel including a plurality of pixel rows arranged in a first direction and each including a plurality of pixels; a first gate driver including first stages that generate first gate signals as first outputs to each of the plurality of pixel rows; and a second gate driver including second stages that generate second gate signals as second outputs to each of the plurality of pixel rows, the second stages being arranged alternately with the first stages in the first direction, wherein the first gate driver and the second gate driver share a first clock signal, and wherein each of the first stages and the second stages is connected to at least four of the plurality of pixel rows.

2. The display device according to claim 1, wherein each of the first stages and the second stages is connected to an even number of the plurality of pixel rows. 3.The display apparatus of claim 1, further comprising: a third gate driver including third stages that generate third gate signals as third outputs to each of the plurality of pixel rows; and a fourth gate driver including fourth stages that generate fourth gate signals as fourth outputs to each of the plurality of pixel rows, the fourth stages being arranged alternately with the third stages in the first direction, wherein the third gate driver and the fourth gate driver share a second clock signal, and wherein each of the third stages and the fourth stages is connected to at least four of the plurality of pixel rows.

4. The display device according to claim 3, wherein the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver are positioned close to a first side of the plurality of pixel rows in a second direction crossing the first direction.

5. The display device according to claim 3, wherein the first gate driver and the second gate driver are positioned close to the first side of the plurality of pixel rows in the second direction crossing the first direction, and wherein the third gate driver and the fourth gate driver are positioned close to a second side of the plurality of pixel rows in the second direction opposite to the first side. 6.The display apparatus of claim 3, further comprising: a fifth gate driver including fifth stages that generate fifth gate signals as fifth outputs to the plurality of pixel rows, wherein the fifth stages include a plurality of sub-stages, each of the plurality of sub-stages being connected to a respective one of the plurality of pixel rows.

7. The display device according to claim 3, wherein the first clock signal is toggled between a low level and a high level in an address scan period and a self scan period, and wherein the second clock signal is toggled between the low level and the high level in the address scan period and is maintained at the low level or the high level in the self scan period.

8. The display device according to claim 1, wherein the first stages include: a first logic circuit that controls a signal of a first control node and a signal of a first inverted control node in response to a first input signal and the first clock signal; and a first buffer circuit that outputs the first gate signals in response to the signal of the first control node and the signal of the first inverted control node, and the second stages include: a second logic circuit that controls a signal of a second control node and a signal of a second inverted control node in response to a second input signal and the first clock signal; and a second buffer circuit that outputs the second gate signals in response to the signal of the second control node and the signal of the second inverted control node. The first buffer circuit has a width in a second direction crossing the first direction that is greater than a width of the first logic circuit in the second direction.

9. A gate driver comprising: a first gate driver comprising a first stage that generates a first gate signal as a first output to each of a plurality of pixel rows; and a second gate driver comprising a second stage that generates a second gate signal as a second output to each of the plurality of pixel rows, the second stage being arranged in a first direction alternately with the first stage, wherein the first gate driver and the second gate driver share a first clock signal, and wherein each of the first stage and the second stage is connected to at least four of the plurality of pixel rows.

10. An electronic device comprising: a processor that generates image data; and the display device of any one of claims 1 to 8 displays an image based on the image data.

Images