Superconducting storage circuit and superconducting storage system

Abstract

The invention provides a superconducting storage circuit and a superconducting storage system. The superconducting storage circuit comprises a circulating storage module and a count reading module, the cyclic storage module is used for carrying out cyclic storage on the data signals, the count reading module is connected with the cyclic storage module and is used for counting the first clock signals and reading the data signals from the first bit to the last bit in sequence when a count value reaches a set value, and the first clock signals and the data signals are input at the same frequency. According to the superconducting storage circuit and the superconducting storage system provided by the invention, the problem that an existing superconducting storage is limited by capacity and speed and cannot be applied is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of superconducting circuit design, in particular to a superconducting storage circuit and a superconducting storage system. BACKGROUND

[0002] Single Flux Quantum (SFQ) circuit is a superconducting circuit based on Josephson junction, which has the advantages of high speed and low power consumption compared with traditional semiconductor circuits; the working frequency of SFQ circuit can reach GHZ or even hundred GHZ, and the power consumption is only in the order of 10-19 to 10-14 watts, and the power consumption of each unit gate is only in the order of nW, and its design and process are compatible with the EDA (Electronic Design Automation) and process of semiconductor.

[0003] With the gradual approach of semiconductor technology to the physical limit, SFQ circuit with the advantages of high speed and low power consumption is one of the solutions for future high-performance computing. Due to the advantages of high speed and low power consumption, SFQ circuit is not only used in computer systems, but also widely used in high-speed digital signal processing, quantum computer control, superconducting analog-to-digital converter, high-speed low-power digital circuit, neural network and artificial intelligence, and precision measurement and other fields.

[0004] The overall performance of SFQ computer system is limited by the memory, but there is no SFQ memory that can be developed to realize the application, and the development of some applications is also limited. Therefore, in data processing and high-performance computing applications, high-density high-speed SFQ memory is essential. Therefore, it is an urgent technical problem for those skilled in the art to develop SFQ memory with unlimited capacity and speed. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a superconducting storage circuit and a superconducting storage system, which can solve the problem that the existing superconducting memory is limited in capacity and speed and cannot realize the application.

[0006] To achieve the above-mentioned purposes and other related purposes, the present application provides a superconducting storage circuit, comprising a cyclic storage module and a counting and reading module.

[0007] The cyclic storage module is used for cyclically storing a data signal.

[0008] The counting and reading module is connected to the cyclic storage module and is used for counting a first clock signal and starting to read out the data signal in order from the first bit to the last bit when the counting value reaches a set value, wherein the first clock signal and the data signal are input at the same frequency.

[0009] Optionally, the circular storage module includes a bus buffer unit, M delay units, and a first shunt unit; the first input terminal of the bus buffer unit receives the data signal, the second input terminal is connected to the first output terminal of the first shunt unit, and the output terminal is connected to the input terminal of the first delay unit; the M delay units are cascaded, and the output terminal of the Mth delay unit is connected to the input terminal of the first shunt unit; the second output terminal of the first shunt unit serves as the output terminal of the circular storage module; wherein, the M delay units have the same delay time and M*tdelay≥n*1 / T, where M is the number of delay units, tdelay is the delay time of the delay unit, n is the number of bits of the data signal, and T is the period of the first clock signal.

[0010] Optionally, the delay unit is implemented using a Josephson transmission line.

[0011] Optionally, the circular storage module is also used to erase the data signal.

[0012] Optionally, the cyclic storage module further includes a switching unit connected between any two adjacent units in the cyclic storage module, and the data signal is erased by disconnecting the switching unit.

[0013] Optionally, the counting readout module includes a counter unit, a second shunt unit, a third shunt unit, a fourth shunt unit, a first non-destructive readout unit, a second non-destructive readout unit, and a third non-destructive readout unit; the input terminal of the counter unit is connected to the first clock signal, and the output terminal is connected to the input terminal of the second shunt unit; the first output terminal of the second shunt unit is connected to the input terminal of the third shunt unit, and the second output terminal is connected to the input terminal of the fourth shunt unit; the first output terminal of the third shunt unit is connected to the reset terminal of the first non-destructive readout unit, and the second output terminal is connected to the set terminal of the first non-destructive readout unit; the fourth shunt unit... The first output terminal of the unit is connected to the reset terminal of the second non-destructive readout unit, and the second output terminal is connected to the reset terminal of the third non-destructive readout unit; the clock terminal of the first non-destructive readout unit is connected to the first clock signal, and its output terminal is connected to the clock terminal of the second non-destructive readout unit; the set terminal of the second non-destructive readout unit is connected to the read signal, and its output terminal is connected to the set terminal of the third non-destructive readout unit; the clock terminal of the third non-destructive readout unit is connected to the output terminal of the circular storage module, and its output terminal serves as the output terminal of the counting readout module; wherein, the maximum count value of the counter unit is greater than or equal to n, where n is the number of bits in the data signal.

[0014] Optionally, the counter unit is replaced with N cascaded T flip-flops, where the input of the first T flip-flop is connected to the first clock signal, and the output of the Nth T flip-flop is connected to the input of the second shunt unit, wherein 2 N =n, where N is the number of T flip-flops.

[0015] The present invention also provides a superconducting memory system, including a data addressing circuit and several parallel superconducting memory circuits as described above;

[0016] The data addressing circuit is used to select one of the several parallel superconducting memory circuits according to the address signal, and input the data signal to the selected superconducting memory circuit.

[0017] Optionally, the data addressing circuit includes an address decoder, several parallel fourth non-destructive readout units, and several parallel D flip-flops, wherein the fourth non-destructive readout units, the D flip-flops, and the superconducting memory circuit correspond one-to-one; the address decoder generates several decoded addresses by decoding the address signal and outputs them to the set terminals of each of the fourth non-destructive readout units; the clock terminal of each of the fourth non-destructive readout units is connected to a second clock signal, the reset terminal is connected to an address clear signal, and the output terminals are respectively connected to the clock terminals of each of the D flip-flops; the input terminals of each of the D flip-flops are connected to the data signal, and the output terminals are respectively connected to the input terminals of each of the superconducting memory circuits.

[0018] Optionally, the data addressing circuit further includes a fifth shunt unit, used to shunt the input clock signal to obtain the first clock signal and the second clock signal.

[0019] As described above, the superconducting memory circuit and superconducting memory system of the present invention abandon the traditional memory array structure in the storage section, utilizing a delayed memory loop for data storage and even erasure, while the readout section ensures that the data sequence read out each time is the same as the input data sequence. Thus, high speed and high density (speeds up to 30 GHz and above) are achieved while reducing the area. Parallel expansion of the superconducting memory circuit of the present invention reduces the area increment without decreasing the speed, offering significant advantages in capacity expansion and multi-bit data storage. The present invention has a simple structure, low power consumption, and high speed, and can be applied to high-speed digital circuits (e.g., neuron circuits) to meet the requirements of high speed, high capacity, and low power consumption. Attached Figure Description

[0020] Figure 1 The diagram shown is a schematic of the superconducting memory circuit in Example 1.

[0021] Figure 2 The diagram shown is a circuit diagram of a circular storage module in Embodiment 1.

[0022] Figure 3 Displayed as implemented using Josephson transmission lines Figure 2 The circuit diagram corresponding to the function of the intermediate delay unit.

[0023] Figure 4 This is another circuit diagram of the circular storage module in Embodiment 1.

[0024] Figure 5 This is another circuit diagram of the circular storage module in Embodiment 1.

[0025] Figure 6 This is another circuit diagram of the circular storage module in Embodiment 1.

[0026] Figure 7 The diagram shows a port schematic of the bus buffer unit in Embodiment 1.

[0027] Figure 8 The diagram shows the state transition of the bus buffer unit in Embodiment 1.

[0028] Figure 9 The diagram shows a port schematic of the Josephson transmission line in Example 1.

[0029] Figure 10 The diagram shows the state transition of the Josephson transmission line in Example 1.

[0030] Figure 11 The diagram shows a port schematic of the splitter unit in Embodiment 1.

[0031] Figure 12 The diagram shows the state transition of the shunt unit in Embodiment 1.

[0032] Figure 13 The diagram shown is a circuit diagram of the counting and reading module in Embodiment 1.

[0033] Figure 14 This is another circuit diagram of the counting and reading module in Embodiment 1.

[0034] Figure 15 The diagram shows a port schematic of the non-destructive readout unit in Embodiment 1.

[0035] Figure 16 The diagram shows the state transition of the non-destructive readout unit in Embodiment 1.

[0036] Figure 17 The diagram shows the port layout of the T flip-flop in Example 1.

[0037] Figure 18 The diagram shows the state transition of the T flip-flop in Example 1.

[0038] Figure 19 The diagram shown is a structural schematic of the superconducting storage system in Example 2.

[0039] Figure 20 The diagram shows the port layout of the D flip-flop in Example 2.

[0040] Figure 21 The diagram shows the state transition of the D trigger in Example 2.

[0041] Component designation explanation

[0042] 10 Superconducting storage system

[0043] 100 Superconducting Storage Circuit

[0044] 110 Circular Storage Module

[0045] 111 Busbar Buffer Unit

[0046] 112 delay units

[0047] 112a Josephson transmission line

[0048] 113 First Diversion Unit

[0049] 114 Switching Unit

[0050] 120 Count Readout Module

[0051] 121 Counter Unit

[0052] 122 Second Diversion Unit

[0053] 123 Third Diversion Unit

[0054] 124 Fourth Diversion Unit

[0055] 125 First Non-destructive Readout Unit

[0056] 126 Second Non-destructive Readout Unit

[0057] 127 Third Non-destructive Readout Unit

[0058] 128 T trigger

[0059] 200 Data Addressing Circuit

[0060] 210 Address Decoder

[0061] 220 Fourth Non-destructive Readout Unit

[0062] 230 D trigger

[0063] 240 Fifth Diversion Unit Detailed Implementation

[0064] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] Please see Figures 1 to 21 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0066] Example 1

[0067] like Figure 1 As shown, this embodiment provides a superconducting storage circuit 100, including a cyclic storage module 110 and a counting readout module 120.

[0068] The circular storage module 110 is used to circularly store data signals, and further, it is also used to erase data signals so that they can be rewritten.

[0069] In practical applications, when the cyclic storage module 110 has a storage function but no erasure function, the superconducting storage circuit 100 it constitutes is a permanent storage circuit; when the cyclic storage module 110 has both storage and erasure functions, the superconducting storage circuit 100 it constitutes is an erasable circuit.

[0070] For the case where the circular storage module 110 has storage function but no erase function:

[0071] In one implementation, the circular storage module 110 includes one bus buffer unit 111, M delay units 112, and one first splitting unit 113, as follows: Figure 2 As shown.

[0072] The first input terminal of the bus buffer unit 111 serves as the input terminal of the cyclic storage module 110 (and also as the input terminal of the superconducting storage circuit 100) to receive data signals. The second input terminal of the bus buffer unit 111 is connected to the first output terminal of the first shunt unit 113, and the output terminal of the bus buffer unit 111 is connected to the input terminal of the first delay unit 112.

[0073] The bus buffer unit 111 includes an AI terminal, a BI terminal, and an ABO terminal. The AI ​​terminal serves as the first input terminal, the BI terminal as the second input terminal, and the ABO terminal as the output terminal. If either the AI ​​terminal or the BI terminal receives a signal, the ABO terminal will output a signal without any state change (it will always be in the "0" state), thus implementing the logical "OR" function. Figure 7 and Figure 8 As shown.

[0074] M delay units 112 are cascaded, wherein the output of the previous delay unit 112 is connected to the input of the next delay unit 112, the input of the first delay unit 112 is connected to the output of the bus buffer unit 111, and the output of the Mth delay unit 112 is connected to the input of the first shunt unit 113.

[0075] M delay units 112 have the same delay time; let the delay time of each delay unit 112 be denoted as tdelay. Then the number of delay units 112 M should satisfy M*tdelay≥n*1 / T. Furthermore, the number of delay units 112 M should satisfy n*1 / T≤M*tdelay≤(n+1)*1 / T, where n is the number of bits of the data signal and T is the period of the first clock signal.

[0076] As an example, delay unit 112 is implemented using Josephson transmission line 112a, such as Figure 3 As shown; of course, other unit circuit structures with delay functions are also feasible. The Josephson transmission line 112a includes an AI end and an AO end. The AI ​​end serves as the input end, and the AO end serves as the output end, realizing the signal transmission function, that is, transmitting the signal from the AI ​​end to the AO end for output, such as... Figure 9 and Figure 10 As shown.

[0077] The input terminal of the first shunt unit 113 is connected to the output terminal of the Mth delay unit 112. The first output terminal of the first shunt unit 113 is connected to the second input terminal of the bus buffer unit 111. The second output terminal of the first shunt unit 113 serves as the output terminal of the loop storage module 110 to output data signals.

[0078] The first splitting unit 113 includes an AI terminal, an AO1 terminal, and an AO2 terminal. The AI ​​terminal serves as the input terminal, the AO1 terminal as the first output terminal, and the AO2 terminal as the second output terminal. It splits the input of the AI ​​terminal into two outputs, AO1 and AO2. The outputs of AO1 and AO2 are identical to the input of the AI ​​terminal. Figure 11 and Figure 12 As shown.

[0079] In the above implementation, one bus buffer unit 111, M delay units 112, and one first splitting unit 113 constitute a delay storage loop; the data signal enters the delay storage loop, and the delay of the delay unit 112 is used to transmit the data signal in the delay storage loop to realize the cyclic storage of data; in addition, the data signal is also split to the counting readout module 120 through the first splitting unit 113 so that it can be read out, so as to realize the sequential reading of the data signal.

[0080] For cases where the circular storage module 110 has both storage and erase functions:

[0081] In one implementation, the circular storage module 110, in addition to the one bus buffer unit 111, M delay units 112, and one first shunt unit 113 as described above, also includes a switching unit 114, such as... Figure 4 to 6 As shown.

[0082] Switching unit 114 is connected between any two adjacent units in the circular storage module 110, for example, between bus buffer unit 111 and the first delay unit 112 (e.g.) Figure 4 ), connected between any two adjacent delay units 112 (e.g. Figure 5 ), connected between the Mth delay unit 112 and the first shunt unit 113 (e.g. Figure 6 The data signal is stored cyclically by closing the switch unit 114 and erased by opening the switch unit 114.

[0083] The counting and reading module 120 is connected to the circular storage module 110 and is used to count the first clock signal and start reading the data signal sequentially from the first bit to the last bit when the count value reaches the set value. The first clock signal and the data signal are input at the same frequency.

[0084] In one implementation, the counting and reading module 120 includes a counter unit 121, a second current splitting unit 122, a third current splitting unit 123, a fourth current splitting unit 124, a first non-destructive reading unit 125, a second non-destructive reading unit 126, and a third non-destructive reading unit 127, as follows: Figure 13 As shown.

[0085] The input terminal of the counter unit 121 is connected to the first clock signal CLK1, and the output terminal of the counter unit 121 is connected to the input terminal of the second shunt unit 122. The counter unit 121 counts the first clock signal CLK1 and generates an output when the count value reaches the set value, so as to enable the counting readout module 120 to read it.

[0086] The maximum count value of counter unit 121 is greater than or equal to n, where n is the number of bits in the data signal; as a preferred embodiment, the maximum count value of counter unit 121 is n. At this time, the set value is n; counter unit 121 counts the first clock signal CLK1 and generates an output when the count value reaches n, so as to enable the count readout module 120 to read the data. Counter unit 121 includes an AI terminal and an AO terminal, with the AI ​​terminal serving as the input terminal and the AO terminal as the output terminal; in practical applications, any unit circuit structure capable of implementing the corresponding counting is acceptable, and this embodiment does not impose any restrictions.

[0087] The input terminal of the second shunt unit 122 is connected to the output terminal of the counter unit 121, the first output terminal of the second shunt unit 122 is connected to the input terminal of the third shunt unit 123, and the second output terminal of the second shunt unit 122 is connected to the input terminal of the fourth shunt unit 124.

[0088] The input terminal of the third shunt unit 123 is connected to the first output terminal of the second shunt unit 122, the first output terminal of the third shunt unit 123 is connected to the reset terminal of the first non-destructive readout unit 125, and the second output terminal of the third shunt unit 123 is connected to the set terminal of the first non-destructive readout unit 125.

[0089] The input terminal of the fourth shunt unit 124 is connected to the second output terminal of the second shunt unit 122, the first output terminal of the fourth shunt unit 124 is connected to the reset terminal of the second non-destructive readout unit 126, and the second output terminal of the fourth shunt unit 124 is connected to the reset terminal of the third non-destructive readout unit 127.

[0090] The clock terminal of the first non-destructive readout unit 125 is connected to the first clock signal CLK, the reset terminal of the first non-destructive readout unit 125 is connected to the first output terminal of the third shunt unit 123, the set terminal of the first non-destructive readout unit 125 is connected to the second output terminal of the third shunt unit 123, and the output terminal of the first non-destructive readout unit 125 is connected to the clock terminal of the second non-destructive readout unit 126.

[0091] The clock terminal of the second non-destructive readout unit 126 is connected to the output terminal of the first non-destructive readout unit 125. The reset terminal of the second non-destructive readout unit 126 is connected to the first output terminal of the fourth shunt unit 124. The set terminal of the second non-destructive readout unit 126 is connected to the read signal RD. The output terminal of the second non-destructive readout unit 126 is connected to the set terminal of the third non-destructive readout unit 127.

[0092] The clock terminal of the third non-destructive readout unit 127 is connected to the output terminal of the circular storage module 110. The reset terminal of the third non-destructive readout unit 127 is connected to the second output terminal of the fourth shunt unit 124. The set terminal of the third non-destructive readout unit 127 is connected to the output terminal of the second non-destructive readout unit 126. The output terminal of the third non-destructive readout unit 127 serves as the output terminal of the counting readout module 120 and also as the output terminal of the superconducting storage circuit 100.

[0093] The first non-destructive readout unit 125, the second non-destructive readout unit 126, and the third non-destructive readout unit 127 are identical. The non-destructive readout unit includes a TI terminal, a RI terminal, a SI terminal, and a TO terminal. The TI terminal serves as the clock terminal, the RI terminal serves as the reset terminal, the SI terminal serves as the set terminal, and the TO terminal serves as the output terminal. By controlling the state of the control unit circuit through the signals of the RI terminal and the SI terminal, the output of the TO terminal is ultimately controlled.

[0094] Regardless of whether the current unit circuit is in state "0" or "1", when there is a signal input at the SI terminal, the unit circuit will switch to state "1", and when there is a signal input at the RI terminal, the unit circuit will switch to state "0". When the unit circuit is in state "0", the TO terminal does not generate an output when there is an input at the TI terminal (output logic "0"). When the unit circuit is in state "1", the TO terminal generates an output when there is an input at the TI terminal (the output at the TO terminal does not affect the state of the unit circuit, so this unit has the characteristic of non-destructive readout). Figure 15 and Figure 16 As shown.

[0095] In the above implementation, when the first clock signal CLK1 (input at the same frequency as the data signal) is input, the counter unit 121 counts the first clock signal CLK1 and generates an output when the count value reaches n: the first non-destructive readout unit 125 is switched to the "1" state due to the output of the counter unit 121, and generates an output at the TO terminal due to the input at the TI terminal; the second non-destructive readout unit 126 is in the "1" state due to the read signal RD, and generates an output at the TO terminal due to the input at the TI terminal; the third non-destructive readout unit 127 is switched to the "1" state due to the output of the second non-destructive readout unit 126, and reads the data signal in the delayed storage loop sequentially from the first bit to the last bit.

[0096] Meanwhile, the output of the counter unit 121 is transmitted to the reset terminal of each non-destructive readout unit via the second split unit 122, the third split unit 123, and the fourth split unit 124 with a certain delay. As the output of the counter unit 121 is switched to the "0" state, the TO terminal of each non-destructive readout unit no longer generates an output, so as to reset the counting readout module 120 and realize automatic stop reading after reading data.

[0097] In other implementations, N cascaded T flip-flops 128 are used to replace the counter unit 121 to achieve a maximum count value of 2. N The counting function; at this time, among the N T flip-flops 128, the output of the previous T flip-flop 128 is connected to the input of the next T flip-flop 128, the input of the first T flip-flop 128 is connected to the first clock signal CLK1, and the output of the Nth T flip-flop 128 is connected to the input of the second shunt unit 122, as shown below. Figure 14 As shown; where, 2 N =n, where N is the number of T flip-flops 130 and n is the number of bits in the data signal.

[0098] The T flip-flop includes an AI terminal and an AO terminal. The AI ​​terminal serves as the input, and the AO terminal as the output. Each time a signal is input to the AI ​​terminal, the state of the unit circuit toggles once. The first input signal toggles the state of the unit circuit from "0" to "1", and the AO terminal has no output. The second input signal toggles the state of the unit circuit from "1" to "0", and the AO terminal generates an output. This achieves binary counting, such as... Figure 17 and Figure 18 As shown.

[0099] Example 2

[0100] like Figure 19 As shown, this embodiment provides a superconducting storage system 10, including several parallel superconducting storage circuits 100 and data addressing circuits 200; wherein, the superconducting storage circuits 100 are implemented using the structure described in Embodiment 1, and the relevant details are as above, and will not be repeated here.

[0101] The data addressing circuit 200 selects one of several parallel superconducting memory circuits 100 according to the address signal and inputs the data signal into the selected superconducting memory circuit 100.

[0102] In one implementation, the data addressing circuit 200 includes an address decoder 210, several parallel fourth non-destructive readout units 220, and several parallel D flip-flops 230; wherein the fourth non-destructive readout units 220, D flip-flops 230, and superconducting storage circuit 100 correspond one-to-one.

[0103] Address decoder 210 receives address signals (e.g., address 1, address 2, etc.), and generates several decoded addresses by decoding the address signals, which are then output to the set terminals of each of the fourth non-destructive readout units 220.

[0104] The clock terminal of each fourth non-destructive readout unit 220 is connected to the second clock signal CLK2, the reset terminal of each fourth non-destructive readout unit 220 is connected to the address clear signal ACL, the set terminal of each fourth non-destructive readout unit 220 is connected to each output terminal of the address decoder 210, and the output terminal of each fourth non-destructive readout unit 220 is connected to the clock terminal of each D flip-flop 230.

[0105] The second clock signal CLK2 corresponding to each fourth non-destructive readout unit 220 and the first clock signal CLK1 corresponding to each superconducting storage circuit 100 can be the same clock or different clocks. When they are the same clock, the data addressing circuit 200 also includes a fifth shunt unit 240, which is used to shunt the input clock signal CLK to obtain the first clock signal CLK1 and the second clock signal CLK2. The input clock signal CLK, the first clock signal CLK1 and the second clock signal CLK2 are the same clock.

[0106] At this time, the input terminal of the fifth shunt unit 240 is connected to the input clock signal CLK, the first output terminal of the fifth shunt unit 240 is connected to the counting readout module 120 in each superconducting storage circuit 100 to provide the first clock signal CLK1, and the second output terminal of the fifth shunt unit 240 is connected to the clock terminal of each fourth non-destructive readout unit 220 to provide the second clock signal CLK2.

[0107] The clock terminals of each D flip-flop 230 are connected to the output terminals of each fourth non-destructive readout unit 220, the input terminals of each D flip-flop 230 are connected to data signals, and the output terminals of each D flip-flop 230 are connected to the input terminals of each superconducting storage circuit 100.

[0108] The D flip-flop 230 includes a TI terminal, an AI terminal, and an AO terminal. The TI terminal serves as the clock terminal, the AI ​​terminal as the input terminal, and the AO terminal as the output terminal. When a signal is input to the AI ​​terminal, the state of the unit circuit flips from "0" to "1". At this time, if a signal is input to the TI terminal, the AO terminal generates an output, such as... Figure 20 and Figure 21 As shown.

[0109] In the above implementation, the address signal is decoded by the address decoder 210 to generate a decoded address. Taking the superconducting memory circuit 100 located in the first row as an example, the decoded address output by the address decoder 210 is 100… At this time, the fourth non-destructive readout unit 220 located in the first row switches to the “1” state and generates an output when the second clock signal CLK2 arrives. This output causes the D flip-flop 230 located in the first row to generate an output, that is, the data signal is input to the superconducting memory circuit 100 located in the first row for data storage and readout. Before performing storage and readout operations on the superconducting memory circuits 100 located in other rows, the address information can be cleared according to the address clear signal ACL, and then the storage and readout operations on the superconducting memory circuits 100 in other rows can be performed.

[0110] In summary, the superconducting memory circuit and system of this invention abandon the traditional memory array structure in the storage section, utilizing a delayed storage loop for data storage and even erasure, while the read-out section ensures that the data sequence read out each time is identical to the input data sequence. Thus, high speed and high density (speeds up to 30 GHz and above) are achieved while reducing area. Parallel expansion of the superconducting memory circuit of this invention reduces area increment without decreasing speed, offering significant advantages in capacity expansion and multi-bit data storage. This invention features a simple structure, low power consumption, and high speed, making it applicable to high-speed digital circuits (e.g., neural network circuits) to meet the demands of high speed, high capacity, and low power consumption. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A superconducting memory circuit, comprising: The superconducting memory circuit comprises a cyclic storage module and a counting reading module. The cyclic storage module is used for cyclically storing a data signal. The counting reading module is connected with the cyclic storage module and is used for counting a first clock signal and starting to sequentially read out the data signal from the first bit to the last bit when the counting value reaches a set value, wherein the first clock signal is inputted with the same frequency as the data signal.

2. The superconducting memory circuit of claim 1, wherein, The cyclic storage module comprises a converging buffer unit, M delay units and a first diverging unit; the first input end of the converging buffer unit receives the data signal, the second input end is connected with the first output end of the first diverging unit, and the output end is connected with the input end of the first delay unit; the M delay units are cascaded, the output end of the Mth delay unit is connected with the input end of the first diverging unit; the second output end of the first diverging unit serves as the output end of the cyclic storage module; wherein the M delay units have the same delay time and M*tdelay≥n*1 / T, M is the number of delay units, tdelay is the delay time of the delay unit, n is the number of bits of the data signal, and T is the period of the first clock signal.

3. The superconducting memory circuit of claim 2, wherein, The delay unit is implemented by Josephson transmission line.

4. The superconducting storage circuit according to any one of claims 1 to 3, characterized by The cyclic storage module is also used for erasing the data signal.

5. The superconducting storage circuit of claim 4, wherein, The cyclic storage module further comprises a switch unit connected between any two adjacent units in the cyclic storage module, and the data signal is erased by disconnecting the switch unit.

6. The superconducting memory circuit of claim 1, wherein, The counting reading module comprises a counter unit, a second diverging unit, a third diverging unit, a fourth diverging unit, a first non-destructive reading unit, a second non-destructive reading unit and a third non-destructive reading unit; the input end of the counter unit is connected with the first clock signal, and the output end is connected with the input end of the second diverging unit; the first output end of the second diverging unit is connected with the input end of the third diverging unit, and the second output end is connected with the input end of the fourth diverging unit; the first output end of the third diverging unit is connected with the reset end of the first non-destructive reading unit, and the second output end is connected with the set end of the first non-destructive reading unit; the first output end of the fourth diverging unit is connected with the reset end of the second non-destructive reading unit, and the second output end is connected with the reset end of the third non-destructive reading unit; the clock end of the first non-destructive reading unit is connected with the first clock signal, and the output end is connected with the clock end of the second non-destructive reading unit; the set end of the second non-destructive reading unit is connected with a reading signal, and the output end is connected with the set end of the third non-destructive reading unit; the clock end of the third non-destructive reading unit is connected with the output end of the cyclic storage module, and the output end serves as the output end of the counting reading module; wherein the maximum counting value of the counter unit is greater than or equal to n, and n is the number of bits of the data signal.

7. The superconducting storage circuit of claim 6, wherein, The counter unit is replaced by N cascaded T flip-flops, an input terminal of a first T flip-flop is connected to the first clock signal, and an output terminal of an Nth T flip-flop is connected to an input terminal of the second shunt unit, wherein N = n, and N is the number of T flip-flops.

8. A superconducting memory system, comprising: The superconducting memory circuit comprises a cyclic storage module and a counting reading module. The superconducting memory circuit comprises a cyclic storage module and a counting reading module. The data addressing circuit is used for selecting one from a plurality of parallel superconducting memory circuits according to an address signal and inputting the data signal into the selected superconducting memory circuit.

9. The superconducting memory system of claim 8, wherein, The data addressing circuit comprises an address decoder, a plurality of parallel fourth non-destructive readout units and a plurality of parallel D flip-flops, wherein the fourth non-destructive readout units, the D flip-flops and the superconducting memory circuits are in one-to-one correspondence; the address decoder generates a plurality of decoded address outputs by decoding the address signal and outputs the decoded address outputs to the set ends of the fourth non-destructive readout units; the clock ends of the fourth non-destructive readout units are connected to a second clock signal, the reset ends are connected to an address clear signal, and the output ends are respectively connected to the clock ends of the D flip-flops; the input ends of the D flip-flops are connected to the data signal, and the output ends are respectively connected to the input ends of the superconducting memory circuits.

10. The superconducting memory system of claim 9, wherein, The data addressing circuit further comprises a fifth shunt unit for shunting an input clock signal to obtain the first clock signal and the second clock signal.

Images