Operating method of selector-only memory and selector-only memory

Abstract

The invention provides an operation method of a selector-only memory and the selector-only memory. The method comprises the following steps: determining a target unit from a plurality of storage units; setting operation is carried out on the target unit, and the setting operation comprises the steps that a first voltage signal is applied to the target unit, and the falling edge duration of the first voltage signal is a first preset duration; and performing a reset operation on the target unit, the reset operation comprising: applying a second voltage signal to the target unit, the falling edge duration of the second voltage signal being a second preset duration, and the second preset duration being greater than the first preset duration. Based on the technical scheme, the range of the reading window can be enlarged, so that the data reading process is more stable, and original storage data cannot be wrongly rewritten.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to an operation method of a selector-only memory and the selector-only memory. BACKGROUND

[0002] The selector-only memory is also called a pure selector memory (SOM), which is a new type of memory that saves information with the selector itself. The selector-only memory uses the "selector" as a "memory" at the same time, thereby completely eliminating the traditional resistance type storage medium (such as a phase change material). The selector-only memory has an extremely simple cell structure: only an array of storage cells, which has both a control on-off function (selection function) and a storage function. The storage cell has a read window, which refers to a "read voltage interval" that can reliably distinguish different data states (for example, "0" and "1"), and at the same time must ensure that when reading in this interval, the original data state is not accidentally rewritten into another state.

[0003] In the related art, the read window range of the selector-only memory is too small, which is easy to change the state of the data when reading the data, for example, rewriting the originally stored "1" into "0", resulting in a miswrite. SUMMARY

[0004] Embodiments of the present application provide an operation method of a selector-only memory and the selector-only memory to solve the technical problem of a too small read window range.

[0005] In order to achieve the above-mentioned purpose, according to a first aspect of the present application, an operation method of a selector-only memory is provided, the selector-only memory comprising a plurality of array-arranged storage cells, and the method comprises:

[0006] determining a target cell from the plurality of storage cells;

[0007] performing a set operation on the target cell, the set operation comprising: applying a first voltage signal to the target cell, a falling edge duration of the first voltage signal being a first preset time length;

[0008] performing a reset operation on the target cell, the reset operation comprising: applying a second voltage signal to the target cell, a falling edge duration of the second voltage signal being a second preset time length, the second preset time length being greater than the first preset time length.

[0009] In some embodiments, the selector-only memory further comprises a plurality of word lines and a plurality of bit lines, and the plurality of array-arranged storage cells are coupled between the word lines and the bit lines.

[0010] The first voltage signal includes a first word line voltage signal, which includes a first rising edge segment and a first falling edge segment following the first rising edge segment; setting the target cell includes:

[0011] The first word line voltage signal is applied to the word line coupled to the target unit, and the duration of the first falling edge segment is the first preset duration;

[0012] A first bit line voltage signal is applied to the bit line coupled to the target unit. The first bit line voltage signal includes a second falling edge segment and a second rising edge segment following the second falling edge segment.

[0013] The second voltage signal includes a third bit line voltage signal, which includes a sixth rising edge segment and a sixth falling edge segment following the sixth rising edge segment; resetting the target unit includes:

[0014] A third word line voltage signal is applied to the word line coupled to the target cell, the third word line voltage signal including: a fifth falling edge segment and a fifth rising edge segment after the fifth falling edge segment;

[0015] The third bit line voltage signal is applied to the bit line coupled to the target unit, and the duration of the sixth falling edge segment is the second preset duration.

[0016] In some embodiments, the first word line voltage signal further includes a first high-level segment between the first rising edge segment and the first falling edge segment; the first bit line voltage signal further includes a second low-level segment between the second falling edge segment and the second rising edge segment;

[0017] The third bit line voltage signal also includes a sixth high-level segment between the sixth rising edge segment and the sixth falling edge segment; the third word line voltage signal also includes a fifth low-level segment between the fifth falling edge segment and the fifth rising edge segment.

[0018] In some embodiments, the selector-only memory further includes multiple word lines and multiple bit lines, wherein the multiple array-arranged memory cells are coupled between the word lines and the bit lines;

[0019] The first voltage signal includes a second bit line voltage signal, which includes a fourth rising edge segment and a fourth falling edge segment following the fourth rising edge segment; setting the target unit includes:

[0020] A second word line voltage signal is applied to the word line coupled to the target cell. The second word line voltage signal includes a third falling edge segment and a third rising edge segment following the third falling edge segment.

[0021] The second bit line voltage signal is applied to the bit line coupled to the target unit, and the duration of the fourth falling edge segment is the first preset duration;

[0022] The second voltage signal includes a fourth word line voltage signal, which includes a seventh rising edge segment and a seventh falling edge segment following the seventh rising edge segment; resetting the target unit includes:

[0023] The fourth word line voltage signal is applied to the word line coupled to the target unit, and the duration of the seventh falling edge segment is the second preset duration;

[0024] A fourth bit line voltage signal is applied to the bit line coupled to the target unit. The fourth bit line voltage signal includes an eighth falling edge segment and an eighth rising edge segment following the eighth falling edge segment.

[0025] In some embodiments, the second bit line voltage signal further includes a fourth high-level segment between the fourth rising edge segment and the fourth falling edge segment; the second word line voltage signal further includes a third low-level segment between the third falling edge segment and the third rising edge segment;

[0026] The fourth bit line voltage signal also includes a seventh high-level segment between the seventh rising edge segment and the seventh falling edge segment; the fourth bit line voltage signal also includes an eighth low-level segment between the eighth falling edge segment and the eighth rising edge segment.

[0027] In some embodiments, the second preset duration is greater than twice the first preset duration and less than ten times the first preset duration.

[0028] In some embodiments, the first preset duration ranges from 5ns to 20ns, and the second preset duration ranges from 50ns to 100ns.

[0029] According to a second aspect of this application, a selector-only memory is provided, the selector-only memory including a plurality of arrayed memory cells and external circuitry, the external circuitry being configured to perform the steps of the selector-only memory operation method as described in any of the above embodiments.

[0030] According to a third aspect of this application, an electronic device is provided, including the selector-only memory described in the above embodiments.

[0031] According to a fourth aspect of this application, a storage medium is provided that stores computer instructions thereon, which, when executed by a selector-only memory, implement the steps of the selector-only memory operation method described in any of the above embodiments.

[0032] The technical solution of this application can achieve the following beneficial effects: This application provides an operation method for a selector memory. A short-duration falling edge is insufficient to cause the delocalized defect clusters inside the memory cell to revert to localized defect clusters. Therefore, after the first voltage signal is removed, a sufficient number of delocalized defect clusters will remain, thereby forming a reduced potential barrier, which leads to a further reduction in the first voltage threshold. A longer-duration falling edge provides sufficient time for the delocalized defect clusters to transform into localized defect clusters, resulting in a decrease in the number of delocalized defect clusters and a larger number of localized defect clusters, thereby forming a higher potential barrier. During the subsequent memory cell conduction process, this leads to a further increase in the second voltage threshold, making the voltage threshold distribution range (i.e., the range from the first voltage threshold to the second voltage threshold) wider and the read window range larger. Therefore, the data reading process is more stable, avoiding erroneous rewriting of the original stored data.

[0033] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0036] Figure 1 A waveform diagram illustrating the set and reset operations provided in one embodiment;

[0037] Figure 2 A schematic diagram of the structure of a selector-only memory provided in one embodiment;

[0038] Figure 3 A flowchart illustrating an operation method for a selector-only memory provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of the structure of the target unit provided in the embodiments of this application;

[0040] Figure 5 A waveform diagram of a set operation provided in an embodiment of this application;

[0041] Figure 6A waveform diagram of a set operation provided in an embodiment of this application;

[0042] Figure 7 This is a waveform diagram of a reset operation provided in an embodiment of this application;

[0043] Figure 8 This is a waveform diagram of a reset operation provided in an embodiment of this application;

[0044] Figure 9 A schematic diagram illustrating the effect of different falling edge durations on the relaxation mechanism of the target cell, provided for embodiments of this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0047] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0048] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not exclude the applicability to or configuration to devices performing additional tasks or steps. Additionally, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0049] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0050] See related technologies. Figure 1 As shown, the word line voltage signals during the set operation and the word line voltage signals during the reset operation of the selector memory are only opposite in polarity. During the set operation, the word line voltage signal LWL applied through the word line is equal to +Vwrite, and during the reset operation, the word line voltage signal LWL applied through the word line is equal to -Vwrite. The bit line voltage signals LBL during the set operation and LBL during the reset operation are only opposite in polarity. The current signal Iwrite "P" during the set operation and Iwrite "N" during the reset operation are only opposite in polarity. This makes it difficult to adjust the first voltage threshold and the second voltage threshold. The upper limit of the read window is between the first voltage threshold and the second voltage threshold, causing the read window to always remain in a small range.

[0051] To address the technical problems of small read window range and easy erroneous changes to data state, this application proposes an operation method for a selector-only memory and a selector-only memory to overcome the above problems.

[0052] On one hand, embodiments of this application provide an operation method for a selector-only memory, which can be executed by the selector-only memory. See also... Figure 2 As shown, the selector memory comprises multiple memory cells arranged in an array. For example... Figure 3 As shown, the method includes the following steps:

[0053] S101: Determine the target cell from multiple memory cells;

[0054] S102: Perform a setting operation on the target unit. The setting operation includes: applying a first voltage signal to the target unit. The duration of the falling edge of the first voltage signal is a first preset duration.

[0055] S103: Perform a reset operation on the target unit. The reset operation includes: applying a second voltage signal to the target unit. The duration of the falling edge of the second voltage signal is a second preset duration, which is longer than a first preset duration.

[0056] The working principle of the selector-only memory is explained below.

[0057] Selector-only memory is a type of memory that uses the selector itself to store information. It comprises multiple arrayed memory cells that function both as control switches (selection function) and as storage units. These memory cells include chalcogenide-based devices (i.e., bidirectional threshold switches, Ovonic Threshold Switches, OTS).

[0058] Operations on memory cells include set (SET), reset (RESET), and read (read operation). Set (SET) and reset (RESET) operations are collectively referred to as write operations.

[0059] The set operation (SET) changes a memory cell from an amorphous state (high resistance) to a crystalline state (low resistance). The corresponding storage logic is a change from 0 to 1, where 0 and 1 represent stored data. The set operation requires the application of a medium-strength, relatively long electrical pulse signal.

[0060] A reset operation changes a memory cell from a crystalline (low resistance) state to an amorphous (high resistance) state, corresponding to a change in memory logic from 1 to 0. The reset operation requires the application of a high-intensity, short-pulse electrical signal.

[0061] The read operation involves measuring the resistance of the current storage cell without changing the stored data to determine whether it is in a crystalline (low resistance) or amorphous (high resistance) state, and then reading whether it stores "0" or "1".

[0062] In the OTS, the voltage threshold drift phenomenon is caused by polarity induction. Specifically, the set operation electrical signal with the same polarity as the read operation electrical signal will result in a lower first voltage threshold, denoted as Vth1. At this time, the storage unit is in the SET state (crystalline state), and the first voltage threshold represents the conduction threshold of the storage unit in the SET state. The reset operation electrical signal with the opposite polarity to the read operation electrical signal will result in a higher second voltage threshold, denoted as Vth2, and Vth1 < Vth2. At this time, the storage unit is in the RESET state (amorphous state). The second voltage threshold represents the conduction threshold of the storage unit in the RESET state. Since the distances of different storage units from the driver (the driver is used to apply voltage signals and current signals to the storage units) are different, therefore, in the same selector-only memory, there are certain differences in the first voltage thresholds of different storage units, and there are certain differences in the second voltage thresholds of different storage units.

[0063] The lower limit of the read window is usually 0V, and the upper limit is denoted as V_read, where Vth1 < V_read < Vth2. During the read operation, a read operation electrical signal is applied, swept from 0V to V_read, and the resistance value of the storage unit is measured to determine whether it is in the crystalline state (low resistance) or the amorphous state (high resistance), and then whether the stored data is "0" or "1" is read, and the original stored data of the storage unit is not changed. Once the read operation electrical signal exceeds the read window, the original stored data of the storage unit may be changed. Therefore, the larger the range of the read window, the more conducive to stable storage and reading of data.

[0064] The following details an operation method of a selector-only memory provided by an embodiment of the present application.

[0065] S101: Determine a target unit from multiple storage units.

[0066] In some embodiments, the target unit refers to the storage unit that needs to perform a set operation and / or a reset operation.

[0067] S102: Perform a set operation on the target unit. The set operation includes: applying a first voltage signal to the target unit, and the duration of the falling edge of the first voltage signal is a first preset duration.

[0068] In some embodiments, as shown in Figure 2 the selector-only memory further includes multiple word lines (Word Line, WL) and multiple bit lines (Bit Line, BL), and multiple array-arranged storage units are coupled between the word lines and the bit lines.

[0069] As shown in Figure 4As shown, Lgoal = LWL - LBL, where Lgoal represents the total voltage applied to the target cell U, LWL represents the voltage signal applied to the target cell U through the word line WL, and LBL represents the voltage signal applied to the target cell U through the bit line BL. The direction of the read operation is the same as the direction of the set operation.

[0070] See Figure 5 As shown, the first voltage signal includes a first word line voltage signal, which includes a first rising edge segment, a first high-level segment after the first rising edge segment, and a first falling edge segment after the first high-level segment.

[0071] Setting the target cell includes:

[0072] A first word line voltage signal is applied to the word line coupled to the target cell, and the duration of the first falling edge segment is a first preset duration;

[0073] A first line voltage signal is applied to the bit line coupled to the target cell. The first line voltage signal includes: a second falling edge segment, a second low level segment after the second falling edge segment, and a second rising edge segment after the second low level segment.

[0074] The total voltage applied to the target cell is equal to the difference between the first word line voltage signal and the first bit line voltage signal, and the current applied to the target cell is equal to the first current signal.

[0075] The first word line voltage signal is a positive voltage signal, the first bit line voltage signal is a negative voltage signal, and the first current signal is a positive current signal.

[0076] The duration of the set operation is from time t1 to time t4. The duration of the first rising edge segment and the second falling edge segment is both from time t1 to time t2. The duration of the first high level segment (greater than 0V) and the second low level segment (less than 0V) is both from time t2 to time t3. The duration of the first falling edge segment and the second rising edge segment is both from time t3 to time t4.

[0077] From time t1 to time t2, the first current signal starts to rise from 0A. From time t2 to time t3, the first current signal is a positive current signal with a constant current value. From time t3 to time t4, the first current signal drops to 0A.

[0078] In some embodiments, see Figure 6 As shown, the first voltage signal includes a second bit line voltage signal, which includes a fourth rising edge segment, a fourth high-level segment after the fourth rising edge segment, and a fourth falling edge segment after the fourth high-level segment.

[0079] Setting the target cell includes:

[0080] A second word line voltage signal is applied to the word line coupled to the target cell. The second word line voltage signal includes: a third falling edge segment, a third low level segment after the third falling edge segment, and a third rising edge segment after the third low level segment.

[0081] A second bit line voltage signal is applied to the bit line coupled to the target unit, and the duration of the fourth falling edge segment is the first preset duration.

[0082] The total voltage applied to the target cell is equal to the difference between the second word line voltage signal and the second bit line voltage signal, and the current applied to the target cell is equal to the second current signal.

[0083] The second word line voltage signal is a negative voltage signal, the second bit line voltage signal is a positive voltage signal, and the second current signal is a negative current signal.

[0084] The duration of the set operation is from time t1 to time t4. The durations of the fourth rising edge segment and the third falling edge segment are both from time t1 to time t2. The durations of the fourth high-level segment (greater than 0V) and the third low-level segment (less than 0V) are both from time t2 to time t3. The durations of the fourth falling edge segment and the third rising edge segment are both from time t3 to time t4.

[0085] From time t1 to time t2, the second current signal starts to decrease from 0A. From time t2 to time t3, the second current signal is a negative current signal with a constant current value. From time t3 to time t4, the second current signal rises to 0A.

[0086] In some embodiments, the value of the first preset duration ranges from 10ns to 20ns.

[0087] In some embodiments, see Figure 7 As shown, the second voltage signal includes a third bit line voltage signal, which includes: a sixth rising edge segment, a sixth high-level segment after the sixth rising edge segment, and a sixth falling edge segment after the sixth high-level segment.

[0088] The reset operation for the target unit includes:

[0089] A third word line voltage signal is applied to the word line coupled to the target cell. The third word line voltage signal includes: a fifth falling edge segment, a fifth low level segment after the fifth falling edge segment, and a fifth rising edge segment after the fifth low level segment.

[0090] A third bit line voltage signal is applied to the bit line coupled to the target unit, and the duration of the sixth falling edge segment is the second preset duration.

[0091] The total voltage applied to the target cell is equal to the difference between the third word line voltage signal and the third bit line voltage signal, and the current applied to the target cell is equal to the third current signal.

[0092] The third word line voltage signal is a negative voltage signal, the third bit line voltage signal is a positive voltage signal, and the third current signal is a negative current signal.

[0093] The reset operation lasts from time t5 to t9. The durations of the sixth rising edge and the fifth falling edge are both from time t5 to t6. The duration of the fifth low-level segment (less than 0V) is from time t6 to t8. The duration of the sixth high-level segment (greater than 0V) is from time t6 to t7. The duration of the fifth rising edge is from time t8 to t9. The duration of the sixth falling edge is from time t7 to t9.

[0094] From time t5 to time t6, the third current signal starts to decrease from 0A. From time t6 to time t8, the third current signal is a negative current signal with a constant current value. From time t8 to time t9, the third current signal rises to 0A.

[0095] In some embodiments, see Figure 8 As shown, the second voltage signal includes a fourth word line voltage signal, which includes: a seventh rising edge segment, a seventh high-level segment after the seventh rising edge segment, and a seventh falling edge segment after the seventh high-level segment.

[0096] The reset operation for the target unit includes:

[0097] A fourth word line voltage signal is applied to the word line coupled to the target cell, and the duration of the seventh falling edge segment is the second preset duration;

[0098] A fourth bit line voltage signal is applied to the bit line coupled to the target cell. The fourth bit line voltage signal includes: an eighth falling edge segment, an eighth low level segment after the eighth falling edge segment, and an eighth rising edge segment after the eighth low level segment.

[0099] The total voltage applied to the target cell is equal to the difference between the fourth word line voltage signal and the fourth bit line voltage signal, and the current applied to the target cell is equal to the fourth current signal.

[0100] The fourth word line voltage signal is a positive voltage signal, the fourth bit line voltage signal is a negative voltage signal, and the fourth current signal is a positive current signal.

[0101] The reset operation lasts from time t5 to t9. The durations of the seventh rising edge and the eighth falling edge are both from time t5 to t6. The duration of the eighth low-level segment (less than 0V) is from time t6 to t8. The duration of the seventh high-level segment (greater than 0V) is from time t6 to t7. The duration of the eighth rising edge is from time t8 to t9. The duration of the seventh falling edge is from time t7 to t9.

[0102] From time t5 to time t6, the fourth current signal starts to rise from 0A. From time t6 to time t8, the fourth current signal is a positive current signal with a constant current value. From time t8 to time t9, the fourth current signal drops to 0A.

[0103] In some embodiments, the second preset duration is more than twice the first preset duration and less than ten times the first preset duration.

[0104] Specifically, if the first preset duration is 10ns, the second preset duration can be 30ns, 50ns, 70ns, or 90ns. If the first preset duration is 15ns, the second preset duration can be 40ns, 60ns, 80ns, or 100ns.

[0105] In some embodiments, the first preset duration ranges from 5ns to 20ns, and the second preset duration ranges from 50ns to 100ns.

[0106] Specifically, the first preset duration is 5ns, and the second preset duration is 50ns.

[0107] Specifically, the first preset duration is 10ns, and the second preset duration is 75ns.

[0108] Specifically, the first preset duration is 20ns, and the second preset duration is 100ns.

[0109] In some embodiments, for large-size selector-only memories, the falling edge duration can range from 100ns to 1000ns, or even at the μs level (e.g., 3.16μs or 10μs).

[0110] It should be noted that if the voltage signal on the word lines is positive and the voltage signal on the bit lines is negative during the set operation, then during the reset operation, the voltage signal on the word lines will be negative and the voltage signal on the bit lines will be positive. The direction of the current signal is the same as the direction of the voltage signal on the word lines.

[0111] It should be noted that the direction of the voltage signal during the read operation is the same as the direction of the voltage signal during the set operation.

[0112] Figure 9This diagram illustrates the impact of different falling edge durations on the relaxation mechanism of the target cell. Voltage represents the voltage value, Initial represents the initial state, Write represents the write operation (including set and reset operations), Read represents the read operation, and Time represents time. Based on the relaxation characteristics of the OTS, after the OTS is formed, some delocalized defect clusters remain. When a write operation signal is applied, under its influence, the localized defect clusters (immovable and non-conductive) transform into delocalized defect clusters (freely movable and highly conductive), causing the OTS to switch to a low-resistance state. With the removal of the write operation signal, these delocalized defect clusters lose stability and revert to their initial localized state. a represents the defect cluster distribution in the initial state of the target cell (which includes a bidirectional threshold switch OTS). b represents the defect cluster distribution when a voltage signal with a high-level segment is applied. c represents the first falling edge segment, the duration of which is a first preset time. d represents the sixth falling edge segment, the duration of which is the second preset duration. e represents the defect cluster distribution corresponding to c, and f represents the defect cluster distribution corresponding to d. From c and e, it can be seen that when a short first falling edge segment is used, it is insufficient to cause delocalized defect clusters to revert to localized defect clusters, similar to a quenching process. Therefore, after the voltage signal is removed, a sufficient number of delocalized defect clusters remain, forming a lower potential barrier, leading to a further reduction in the first voltage threshold. From d and f, it can be seen that when a longer sixth falling edge segment is used, sufficient time is provided for the delocalized defect clusters to transform into localized defect clusters. Furthermore, due to the thermal effect promoting OTS relaxation, the number of delocalized defect clusters decreases further, while the number of localized defect clusters increases, forming a higher potential barrier. In the subsequent OTS conduction process, this leads to a further increase in the second voltage threshold. g represents the defect cluster distribution after using the first falling edge segment, where there are more delocalized defect clusters. h represents the defect cluster distribution after the sixth falling edge, at which point there are more localized defect clusters. i represents the defect cluster distribution when a read operation signal is applied. The read operation signal causes the delocalized defect clusters to move and arrange themselves to form "conductive channels".

[0113] Based on the above embodiments, the distribution range of voltage thresholds can be made wider and wider, that is, the first voltage threshold becomes smaller and the second voltage threshold becomes larger and larger, thereby increasing the range of the read window. Therefore, the data reading process is more stable and will not erroneously rewrite the original stored data. Furthermore, since the first voltage threshold becomes smaller and more in line with the normal distribution characteristics, and the second voltage threshold becomes larger and more in line with the normal distribution characteristics, a more convergent voltage threshold distribution can be obtained, so that the first voltage threshold of each storage cell approaches a fixed value, and the second voltage threshold of each storage cell approaches a fixed value, thereby improving the consistency of the storage cell array. Users only need to use a unified first voltage threshold and a unified second voltage threshold to control the on / off state of all storage cells.

[0114] See Figure 2 As shown, this application provides a selector-only memory, which includes a plurality of arrayed memory cells and external circuitry. The external circuitry is configured to perform the steps of the selector-only memory operation method as described in any of the above embodiments.

[0115] In some embodiments, the array external circuitry is configured as follows:

[0116] The target cell is determined from multiple storage cells;

[0117] A setting operation is performed on the target unit. The setting operation includes: applying a first voltage signal to the target unit, wherein the duration of the falling edge of the first voltage signal is a first preset duration.

[0118] A reset operation is performed on the target unit. The reset operation includes applying a second voltage signal to the target unit. The duration of the falling edge of the second voltage signal is a second preset duration, which is longer than a first preset duration.

[0119] In some embodiments, see Figure 2 As shown, the selector memory also includes multiple word lines WL and multiple bit lines BL, with multiple array-arranged memory cells coupled between the word lines WL and the bit lines BL;

[0120] The first voltage signal includes a first word line voltage signal, which includes a first rising edge segment and a first falling edge segment following the first rising edge segment;

[0121] The array external circuitry is further configured to: apply a first word line voltage signal to the word line coupled to the target cell, wherein the duration of the first falling edge segment is the first preset duration; and apply a first bit line voltage signal to the bit line coupled to the target cell, wherein the first bit line voltage signal includes: a second falling edge segment and a second rising edge segment following the second falling edge segment.

[0122] The second voltage signal includes a third bit line voltage signal, which includes a sixth rising edge segment and a sixth falling edge segment following the sixth rising edge segment;

[0123] The array external circuitry is further configured to: apply a third word line voltage signal to the word line coupled to the target cell, the third word line voltage signal including: a fifth falling edge segment and a fifth rising edge segment following the fifth falling edge segment; apply the third bit line voltage signal to the bit line coupled to the target cell, the duration of the sixth falling edge segment being the second preset duration.

[0124] In some embodiments, the first voltage signal includes a second bit line voltage signal, the second bit line voltage signal including: a fourth rising edge segment and a fourth falling edge segment following the fourth rising edge segment;

[0125] The array external circuitry is further configured to: apply a second word line voltage signal to the word line coupled to the target cell, the second word line voltage signal including: a third falling edge segment and a third rising edge segment following the third falling edge segment; apply the second bit line voltage signal to the bit line coupled to the target cell, the duration of the fourth falling edge segment being the first preset duration;

[0126] The second voltage signal includes a fourth word line voltage signal, which includes a seventh rising edge segment and a seventh falling edge segment following the seventh rising edge segment;

[0127] The array external circuitry is further configured to: apply the fourth word line voltage signal to the word line coupled to the target cell, wherein the duration of the seventh falling edge segment is the second preset duration; and apply a fourth bit line voltage signal to the bit line coupled to the target cell, wherein the fourth bit line voltage signal includes: an eighth falling edge segment and an eighth rising edge segment following the eighth falling edge segment.

[0128] This application provides an electronic device including the selector-only memory described in any of the above embodiments.

[0129] This application provides a storage medium storing computer instructions, which, when executed by a selector-only memory, implement the steps of the selector-only memory operation method described in any of the above embodiments.

[0130] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0131] The above provides a detailed description of the operation method and the selector-only memory provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. An operation method of a selector-only memory, the method comprising: The only selector memory includes a plurality of arrayed memory cells, and the method comprises: determining a target cell from the plurality of memory cells; performing a set operation on the target cell, the set operation comprising: applying a first voltage signal to the target cell, a falling edge duration of the first voltage signal being a first preset time length; performing a reset operation on the target cell, the reset operation comprising: applying a second voltage signal to the target cell, a falling edge duration of the second voltage signal being a second preset time length, the second preset time length being greater than the first preset time length.

2. The method of claim 1, wherein, The only selector memory further comprises a plurality of word lines and a plurality of bit lines, and the plurality of arrayed memory cells are coupled between the word lines and the bit lines; The first voltage signal comprises a first word line voltage signal, and the first word line voltage signal comprises: a first rising edge section and a first falling edge section after the first rising edge section; the set operation on the target cell comprises: applying the first word line voltage signal to the word line coupled to the target cell, and a duration of the first falling edge section is the first preset time length; applying a first bit line voltage signal to the bit line coupled to the target cell, and the first bit line voltage signal comprises: a second falling edge section and a second rising edge section after the second falling edge section; The second voltage signal comprises a third bit line voltage signal, and the third bit line voltage signal comprises: a sixth rising edge section and a sixth falling edge section after the sixth rising edge section; the reset operation on the target cell comprises: applying a third word line voltage signal to the word line coupled to the target cell, and the third word line voltage signal comprises: a fifth falling edge section and a fifth rising edge section after the fifth falling edge section; applying the third bit line voltage signal to the bit line coupled to the target cell, and a duration of the sixth falling edge section is the second preset time length.

3. The method of claim 2, wherein, The first word line voltage signal further comprises a first high level section between the first rising edge section and the first falling edge section; and the first bit line voltage signal further comprises a second low level section between the second falling edge section and the second rising edge section; The third bit line voltage signal further comprises a sixth high level section between the sixth rising edge section and the sixth falling edge section; and the third word line voltage signal further comprises a fifth low level section between the fifth falling edge section and the fifth rising edge section.

4. The method of claim 1, wherein, The only selector memory further comprises a plurality of word lines and a plurality of bit lines, and the plurality of arrayed memory cells are coupled between the word lines and the bit lines; The first voltage signal comprises a second bit line voltage signal, and the second bit line voltage signal comprises: a fourth rising edge section and a fourth falling edge section after the fourth rising edge section; the set operation on the target cell comprises: applying a second word line voltage signal to the word line coupled to the target cell, and the second word line voltage signal comprises: a third falling edge section and a third rising edge section after the third falling edge section; applying the second bit line voltage signal to the bit line coupled to the target cell, and a duration of the fourth falling edge section is the first preset time length; The second voltage signal includes a fourth word line voltage signal, and the fourth word line voltage signal includes a seventh rising edge segment and a seventh falling edge segment after the seventh rising edge segment; the reset operation on the target cell includes: applying the fourth word line voltage signal to a word line coupled to the target cell, and a duration of the seventh falling edge segment is the second preset time length; applying a fourth bit line voltage signal to a bit line coupled to the target cell, and the fourth bit line voltage signal includes an eighth falling edge segment and an eighth rising edge segment after the eighth falling edge segment.

5. The method of claim 4, wherein, The second bit line voltage signal further includes a fourth high voltage segment between the fourth rising edge segment and the fourth falling edge segment; and the second word line voltage signal further includes a third low voltage segment between the third falling edge segment and the third rising edge segment. The fourth word line voltage signal further includes a seventh high voltage segment between the seventh rising edge segment and the seventh falling edge segment; and the fourth bit line voltage signal further includes an eighth low voltage segment between the eighth falling edge segment and the eighth rising edge segment.

6. The method according to any one of claims 1-5, characterized in that, The second preset time length is greater than 2 times of the first preset time length and less than 10 times of the first preset time length.

7. The method of claim 6, wherein, The first preset time length is in a range of 5 ns to 20 ns, and the second preset time length is in a range of 50 ns to 100 ns.

8. A select-only memory characterized by, The selector-only memory includes a plurality of array-arranged memory cells and an off-array circuit, and the off-array circuit is configured to perform the steps of the method in any one of claims 1 to 7.

9. An electronic device, comprising: The selector-only memory in claim 8.

10. A storage medium, characterized by A computer program product has computer instructions stored thereon, and the instructions are executed by the selector-only memory to implement the steps of the method in any one of claims 1 to 7.

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