Devices, systems, and methods of managing storage device configured to store plurality of codewords

Abstract

Devices, systems, and methods for managing a storage device configured to store a plurality of codewords, including obtaining a two-dimensional (2D) generalized concatenated code (GCC) codeword from the storage device; providing the codeword to a sequential decoder; based on detecting the first failure of the sequential decoder, updating the codeword and transposing the updated codeword to obtain a transposed codeword; providing the transposed codeword to a sequential decoder; and obtaining an information bit corresponding to the codeword based on a result obtained by the sequential decoder.

Description

Technical Field

[0001] The apparatus and methods consistent with the embodiments relate to managing storage devices, and more specifically to error correction decoding using two-dimensional generalized concatenated codes. Background Technology

[0002] Generally, flash memory devices can have a structure comprising word line (WL) blocks, where each WL includes bit lines (BL). Memory cells can be formed at the intersection of the WL and BL. To allow for fast access, each WL can be decomposed into random access units (RAUs). To allow for high-reliability access, each RAU can be protected with error-correcting codes (ECC).

[0003] A series of ECCs that can be used in flash memory devices are called generalized concatenated codes (GCCs). Some GCCs (e.g., GCCs involving general concatenation of Bose-Chaudhuri-Hocquenghem (BCH) and Reed-Solomon (RS) codes) can be implemented using relatively simple encoder schemes and decoder schemes that include sequential multi-stage decoders. However, there may not be a simple scheme to perform iterative decoding on these codes. Summary of the Invention

[0004] According to an aspect of this disclosure, a storage system includes: a storage device configured to store a plurality of codewords; a sequential decoder; and at least one processor configured to: obtain two-dimensional (2D) generalized concatenated code (GCC) codewords from the storage device; provide the codewords to the sequential decoder; update the codewords and transpose the updated codewords to obtain transposed codewords based on the detection of a first failure of the sequential decoder; provide the transposed codewords to the sequential decoder; and obtain information bits corresponding to the codewords based on the result obtained by the sequential decoder.

[0005] According to aspects of this disclosure, an apparatus for managing data stored in a storage device may include: a memory interface configured to communicate with the storage device; and at least one processor configured to: obtain codewords from a plurality of codewords stored in the storage device, wherein the codewords include a plurality of rows and a plurality of columns; generate a first transformed codeword by transforming each of the plurality of rows, wherein the first transformed codeword includes a plurality of first transformed rows and a plurality of first transformed columns; generate a second transformed codeword by transforming each of the plurality of columns, wherein the second transformed codeword includes a plurality of second transformed rows and a plurality of second transformed columns; and decode the codewords by performing iterative decoding based on the first transformed codewords and the second transformed codewords to obtain information bits corresponding to the codewords, wherein after the codewords are decoded, a first plurality of syndromes calculated based on the plurality of first transformed columns is equal to a second plurality of syndromes calculated based on the plurality of second transformed rows.

[0006] According to an aspect of this disclosure, a method for managing data stored in a storage device may include: obtaining a two-dimensional (2D) generalized concatenated code (GCC) codeword from the storage device; providing the codeword to a sequential decoder; updating the codeword and transposing the updated codeword to obtain a transposed codeword based on the detection of a first failure of the sequential decoder; providing the transposed codeword to the sequential decoder; and obtaining information bits corresponding to the codeword based on the result obtained by the sequential decoder.

[0007] According to an aspect of this disclosure, a method for controlling a storage system may include: obtaining codewords from a plurality of codewords stored in a storage device included in the storage system, wherein the codewords include a plurality of rows and a plurality of columns; generating a first transformed codeword by transforming each of the plurality of rows, wherein the first transformed codeword includes a plurality of first transformed rows and a plurality of first transformed columns; generating a second transformed codeword by transforming each of the plurality of columns, wherein the second transformed codeword includes a plurality of second transformed rows and a plurality of second transformed columns; and decoding the codewords by performing iterative decoding on the first transformed codewords and the second transformed codewords to obtain information bits corresponding to the codewords, wherein after the codewords are decoded, a first plurality of checksums calculated based on the plurality of first transformed columns are equal to a second plurality of checksums calculated based on the plurality of second transformed rows. Attached Figure Description

[0008] The above and other aspects, features, and accompanying advantages of certain embodiments of this disclosure will be better understood from the following description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is a block diagram of a computer system according to an embodiment;

[0010] Figure 2A This is a block diagram of a host storage system according to an embodiment;

[0011] Figure 2B This is a block diagram of the ECC engine according to an embodiment;

[0012] Figure 2C This is a block diagram of the ECC encoding circuit according to an embodiment;

[0013] Figure 3 This is a block diagram of a memory system according to an embodiment;

[0014] Figure 4 This is a block diagram of a memory device according to an embodiment;

[0015] Figure 5 This is a block diagram of a UFS system according to an embodiment;

[0016] Figure 6 This is a block diagram of a memory system according to an embodiment;

[0017] Figure 7 This is a diagram of a 3D V-NAND structure applicable to a UFS device according to an embodiment;

[0018] Figure 8 This is a block diagram of a memory system according to an embodiment;

[0019] Figure 9 An example of a NAND memory block according to an embodiment is shown.

[0020] Figure 10 An example code structure of a generalized concatenated code (GCC) according to an embodiment is shown;

[0021] Figure 11A This is a block diagram of a sequential decoder that can be used to perform GCC decoding according to an embodiment;

[0022] Figure 11B An example of a sequential decoding algorithm that can be used to perform GCC decoding according to an embodiment is shown;

[0023] Figure 11C An example decoding order according to an embodiment is shown;

[0024] Figure 11D This is a flowchart of the decoding process according to an embodiment;

[0025] Figures 12A to 12C An example of a code structure for a two-dimensional GCC (2D-GCC) code according to an embodiment is shown;

[0026] Figure 13AThis is a block diagram of a modified sequential decoder, according to an embodiment, that can be used to perform GCC decoding in an iterative 2D-GCC decoder;

[0027] Figure 13B An example of a sequential decoding algorithm, according to an embodiment, can be used to perform GCC decoding in an iterative 2D-GCC decoder;

[0028] Figure 13C This is a flowchart of the decoding process according to an embodiment;

[0029] Figures 14A to 14B This is a block diagram of an iterative 2D-GCC decoder according to an embodiment;

[0030] Figures 15A to 15B This is a flowchart of a process for controlling a storage system according to an embodiment;

[0031] Figure 16 An example of a 2D-GCC code structure corresponding to an example decoding process according to an embodiment is shown; and

[0032] Figure 17 This is a block diagram of a data center according to an embodiment. Detailed Implementation

[0033] In flash memory devices, data can be stored and retrieved at the granularity of random access units (RAUs). Error correction codes (ECC) can be applied to RAU data to provide fast reads with high reliability.

[0034] A series of ECC codes that can be used in flash memory devices are called Generalized Concatenated Codes (GCCs). Examples of this series involve a general concatenation of Bose-Chaudhuri-Hocquenghem (BCH) codes and Reed-Solomon (RS) codes, and can be referred to as GCCS-BCH codes. Particularly in low-quantization channels (such as HD (hard decision) channels) and for high-rate codes that can be used in flash memory controllers, this series allows for low-complexity decoding based on algebraic decoders while achieving relatively good results.

[0035] GCCS-BCH codes can be implemented using relatively simple encoder schemes and decoder schemes that include sequential multi-stage decoders. A desirable property of decoding is the ability to use message-passing algorithms and iterative decoding, but currently there is no simple scheme for performing iterative decoding on GCCS-BCH codes. For example, for codes in the Galois field… The RS codes defined above, including some structures of generalized concatenations of RS codes and GCC codes, can possess transpose properties, thus allowing iterative messages to be passed within the domain. However, for binary domains or binary subdomains... With extended domain There is no such solution for this combination, just like in the case of GCC S-BCH codes.

[0036] Therefore, embodiments may involve the structure of GCC codes, including the concatenation of BCH codes with specially designed generalized RS (GRS) codes. This structure can be implemented using a simple encoder scheme similar to conventional GCC schemes, and can allow the use of GCC sequential decoders as well as various versions of iterative decoders. As a result, embodiments may outperform standard GCC S-BCH codes and decoders, and may be suitable for flash memory controllers and other ECC applications.

[0037] According to an embodiment, a 2D-GCC S-BCH code can be represented as having dimension The binary matrix, as discussed in more detail below. (Refer to the reference below.) Figures 12A to 12C The generalized transpose theorem, discussed in more detail, states that a binary matrix can represent a GCC code consisting of a concatenation of BCH and GRS codes, and the transpose of the matrix can also represent a GCC code consisting of a concatenation of BCH and GRS codes. The choice of parameters for GRS codes allows for the use of error correction capabilities for correction. A faulty BCH decoder decodes 2D-GCC codewords, while RS codes, typically used in subdomains, have... The ability to correct.

[0038] As an example, the 2D-GCC SBCH encoder according to the embodiment can correspond to standard GCC encoding, and the 2D-GCC S-BCH decoder according to the embodiment can be an improvement on the standard GCC sequential decoder. For example, the 2D-GCC decoder can use multi-level iterative decoding applied in conjunction with a soft-input hard-output (SIHO) GCC decoder. As another example, the 2D-GCC decoder according to the embodiment can use turbo decoding applied in conjunction with a soft-input soft-output (SISO) GCC decoder.

[0039] Figure 1 This is a diagram of the system 1000 that can be applied in the embodiments. Figure 1 System 1000 can be, for example, a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 1 The system 1000 is not necessarily limited to mobile systems, and can be a PC, laptop computer, server, media player, or automotive device (e.g., navigation device).

[0040] refer to Figure 1System 1000 may include a main processor 1100, memory (e.g., 1200a and 1200b), and storage devices (e.g., 1300a and 1300b). Additionally, system 1000 may include at least one of an image capture device 1401, a user input device 1402, a sensor 1403, a communication device 1404, a display 1405, a speaker 1406, a power supply device 1407, and a connection interface 1408.

[0041] The main processor 1100 can control all operations of the system 1000, and more specifically, control the operations of other components included in the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0042] The main processor 1100 may include at least one CPU core 1101 and a controller 1102 configured to control memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator 1103, which is dedicated circuitry for high-speed data processing, such as artificial intelligence (AI) data processing. The accelerator 1103 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and is implemented as a chip physically separate from the other components of the main processor 1100.

[0043] Memory 1200a and 1200b can be used as the main memory device of system 1000. While each of memory 1200a and 1200b may include volatile memory, such as static random access memory (SRAM) and / or dynamic RAM (DRAM), each of memory 1200a and 1200b may also include non-volatile memory, such as flash memory, phase-change RAM (PRAM), and / or resistive RAM (RRAM). Memory 1200a and 1200b can be implemented in the same package as the main processor 1100.

[0044] Storage devices 1300a and 1300b can be used as non-volatile storage devices configured to store data regardless of power supply, and have a larger storage capacity than memories 1200a and 1200b. Storage devices 1300a and 1300b may each include storage controllers (STRG CTRL) 1301a and 1301b and non-volatile memory (NVM) 1302a and 1302b configured to store data via control of storage controllers 1301a and 1301b. Although NVMs 1320a and 1320b may include flash memory with a two-dimensional (2D) or three-dimensional (3D) V-NAND structure, embodiments are not limited thereto, and NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM.

[0045] Storage devices 1300a and 1300b may be physically separate from the main processor 1100 and included in the system 1000, or implemented in the same package as the main processor 1100. Additionally, storage devices 1300a and 1300b may be of SSD or memory card type and may be removably combined with other components of the system 1000 via an interface such as connection interface 1408 described below. Storage devices 1300a and 1300b may be devices applying standard protocols, such as Universal Flash Storage (UFS), eMMC, or Non-Volatile Memory Fast Channel (NVMe), but are not limited to these.

[0046] Image capture device 1401 can capture still images or moving images. Image capture device 1401 may include a camera, video camera, and / or webcam.

[0047] User input device 1402 can receive various types of data input by the user of system 1000, and includes a touchpad, keypad, keyboard, mouse and / or microphone.

[0048] Sensor 1403 can detect various physical quantities that can be obtained from outside the system 1000 and convert the detected physical quantities into electrical signals. Sensor 1403 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0049] Communication device 1404 can send and receive signals between other devices outside system 1000 according to various communication protocols. Communication device 1404 may include an antenna, transceiver, and / or modem.

[0050] The display 1405 and the speaker 1406 can be used as output devices, which are configured to output visual information and auditory information to the user of the system 1000, respectively.

[0051] The power supply device 1407 can suitably convert power from a battery embedded in the system 1000 and / or from an external power source, and provide the converted power to each of the components of the system 1000.

[0052] The connection interface 1408 provides a connection between the system 1000 and an external device that connects to the system 1000 and can send and receive data from the system. The connection interface 1408 can be implemented using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface.

[0053] Figure 2A This is a block diagram of a host storage system 10 according to an example embodiment.

[0054] The host storage system 10 may include a host 100 and a storage device 200. Furthermore, the storage device 200 may include a storage controller 210 and an NVM 220. According to an example embodiment, the host 100 may include a host controller 110 and host memory 120. The host memory 120 may be used as a buffer memory configured to temporarily store data to be sent to or received from the storage device 200.

[0055] Storage device 200 may include a storage medium configured to store data in response to a request from host 100. As an example, storage device 200 may include at least one of an SSD, embedded memory, and removable external memory. When storage device 200 is an SSD, it may be an NVMe-compliant device. When storage device 200 is embedded memory or external memory, it may be a UFS-compliant or eMMC-compliant device. Each of host 100 and storage device 200 may generate and send packets according to the adopted standard protocol.

[0056] When the NVM 220 of storage device 200 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 200 may include various other types of NVM. For example, storage device 200 may include magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FRAM), PRAM, RRAM, and various other types of memory.

[0057] According to embodiments, the host controller 110 and host memory 120 can be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and host memory 120 can be integrated into the same semiconductor chip. As an example, the host controller 110 can be any of a plurality of modules included in an application processor (AP). The AP can be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 120 can be embedded memory included in the AP or an NVM or memory module located outside the AP.

[0058] The host controller 110 can manage operations that store data (e.g., write data) in the buffer area of ​​the host memory 120 in the NVM 220 or operations that store data (e.g., read data) in the buffer area of ​​the NVM 220.

[0059] Storage controller 210 may include host interface 211, memory interface 212, and CPU 213. Additionally, storage controller 210 may include flash translation layer (FTL) 214, packet manager 215, buffer memory 216, ECC engine 217, and Advanced Encryption Standard (AES) engine 218. Storage controller 210 may also include working memory in which FTL 214 is loaded. CPU 213 can execute FTL 214 to control data write and read operations on NVM 220.

[0060] Host interface 211 can send packets to and receive packets from host 100. Packets sent from host 100 to host interface 211 may include commands or data to be written to NVM 220. Packets sent from host interface 211 to host 100 may include responses to commands or data read from NVM 220. Memory interface 212 can send data to NVM 220 to NVM 220 or receive data read from NVM 220. Memory interface 212 can be configured to conform to standard protocols such as Toggle or Open NAND Flash Interface (ONFI).

[0061] FTL 214 can perform various functions, such as address mapping operations, wear-leveling operations, and garbage collection operations. Address mapping operations can be operations that translate logical addresses received from host 100 into physical addresses used to actually store data in the NVM 220. Wear-leveling operations can be a technique used to prevent excessive degradation of specific blocks by allowing blocks in the NVM 220 to be used evenly. As an example, wear-leveling operations can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection operations can be a technique used to ensure available capacity in the NVM 220 by erasing existing blocks after copying valid data from existing blocks to new blocks.

[0062] The packet manager 215 can generate packets according to the protocol of the interface agreed upon by the host 100, or parse various types of information from packets received from the host 100. Additionally, the buffer memory 216 can temporarily store data to be written to or read from the NVM 220. Although the buffer memory 216 may be a component included in the storage controller 210, it may be located externally to the storage controller 210.

[0063] ECC engine 217 can perform error detection and correction operations on read data read from NVM 220. More specifically, ECC engine 217 can generate parity bits for write data to be written to NVM 220, and the generated parity bits can be stored in NVM 220 along with the write data. During data reading from NVM 220, ECC engine 217 can correct errors in the read data by using the parity bits read from NVM 220 along with the read data, and output the error-corrected read data.

[0064] The AES engine 218 can perform at least one of encryption and decryption operations on the data input to the storage controller 210 using a symmetric key algorithm.

[0065] Figure 2B yes Figure 2A Detailed diagrams of the ECC engine 217. (See reference) Figure 2BThe ECC engine 217 may include an ECC encoding circuit 510 and an ECC decoding circuit 520. In response to the ECC control signal ECC_CON, the ECC encoding circuit 510 may generate parity bits ECCP[0:7] for write data WData[0:63] to be written to memory cells in the memory cell array 221. The parity bits ECCP[0:7] may be stored in the ECC cell array 223. According to an embodiment, in response to the ECC control signal ECC_CON, the ECC encoding circuit 510 may generate parity bits ECCP[0:7] for write data WData[0:63] to be written to memory cells including defective cells in the memory cell array 221.

[0066] In response to the ECC control signal ECC_CON, the ECC decoding circuit 520 can correct erroneous bit data by using read data RData[0:63] read from the memory cells of the memory cell array 221 and parity check bits ECCP[0:7] read from the ECC cell array 223, and output the corrected data Data[0:63]. According to an embodiment, in response to the ECC control signal ECC_CON, the ECC decoding circuit 520 can correct erroneous bit data by using read data RData[0:63] read from the memory cells including the defective cells of the memory cell array 221 and parity check bits ECCP[0:7] read from the ECC cell array 223, and output the corrected data Data[0:63].

[0067] Figure 2C yes Figure 2B The diagram shows the ECC encoding circuit 510.

[0068] refer to Figure 2C The ECC encoding circuit 510 may include a parity generator 511 that receives 64-bit write data WData[0:63] and basis bits B[0:7] in response to the ECC control signal ECC_CON, and generates parity bits ECCP[0:7] using an XOR array operation. The basis bits B[0:7] may be bits used to generate the parity bits ECCP[0:7] for the 64-bit write data WData[0:63], for example, bit b'00000000. The basis bits B[0:7] may be replaced by other specific bits.

[0069] Figure 3 This is a block diagram of a memory system 15 according to an embodiment. (See reference...) Figure 3The memory system 15 may include a memory device 17 and a memory controller 16. The memory system 15 may support multiple channels CH1 to CHm, and the memory device 17 may be connected to the memory controller 16 through multiple channels CH1 to CHm. For example, the memory system 15 may be implemented as a storage device, such as an SSD.

[0070] Memory device 17 may include a plurality of NVM devices NVM11 to NVMmn. Each of the NVM devices NVM11 to NVMmn can be connected to one of a plurality of channels CH1 to CHm via a corresponding path. For example, NVM devices NVM11 to NVM1n can be connected to a first channel CH1 via paths W11 to W1n, and NVM devices NVM21 to NVM2n can be connected to a second channel CH2 via paths W21 to W2n. In an example embodiment, each of the NVM devices NVM11 to NVMmn can be implemented as an arbitrary memory cell that can be operated according to individual commands from memory controller 16. For example, each of the NVM devices NVM11 to NVMmn can be implemented as a chip or a die, but embodiments of this disclosure are not limited thereto.

[0071] The memory controller 16 can send signals to and receive signals from the memory device 17 through multiple channels CH1 to CHm. For example, the memory controller 16 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 17 through channels CH1 to CHm, or receive data DATAa to DATAm from the memory device 17.

[0072] The memory controller 16 can select one of the NVM devices NVM11 to NVMmn connected to one of the channels CH1 to CHm by using a corresponding channel from CH1 to CHm, and send signals to and receive signals from the selected NVM device. For example, the memory controller 16 can select NVM11 from NVM11 to NVM1n connected to the first channel CH1. The memory controller 16 can send command CMDa, address ADDRa, and data DATAa to the selected NVM device NVM11 through the first channel CH1, or receive data DATAa from the selected NVM device NVM11.

[0073] The memory controller 16 can send signals to and receive signals from the memory device 17 in parallel through different channels. For example, the memory controller 16 can send the command CMDb to the memory device 17 through the second channel CH2, while simultaneously sending the command CMDa to the memory device 17 through the first channel CH1. For example, the memory controller 16 can receive data DATAb from the memory device 17 through the second channel CH2, while simultaneously receiving data DATAa from the memory device 17 through the first channel CH1.

[0074] The memory controller 16 can control all operations of the memory device 17. The memory controller 16 can send signals to channels CH1 to CHm and control each of the NVM devices NVM11 to NVMmn connected to channels CH1 to CHm. For example, the memory controller 16 can send command CMDa and address ADDRa to the first channel CH1 and control one NVM device selected from NVM devices NVM11 to NVM1n.

[0075] Each of the NVM devices NVM11 to NVMmn can be operated via control of the memory controller 16. For example, NVM11 can program data DATAa based on command CMDa, address ADDRa, and data DATAa provided to the first channel CH1. For example, NVM21 can read data DATAb based on command CMDb and address ADDb provided to the second channel CH2, and send the read data DATAb to the memory controller 16.

[0076] although Figure 3 An example is shown in which memory device 17 communicates with memory controller 16 through m channels and includes n NVM devices corresponding to each of the channels, but the number of channels and the number of NVM devices connected to a channel can be varied.

[0077] Figure 4 This is a block diagram of a memory device 300 according to an example embodiment. (See reference...) Figure 4 The memory device 300 may include control logic circuitry 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. The memory device 300 may also include... Figure 6 The memory interface circuit 310 is shown. Additionally, the memory device 300 may also include column logic, a pre-decoder, a temperature sensor, a command decoder, and / or an address decoder.

[0078] The control logic circuit 320 can control all kinds of operations of the memory device 300. The control logic circuit 320 can output various control signals in response to commands CMD and / or addresses ADDR from the memory interface circuit 310. For example, the control logic circuit 320 can output voltage control signals CTRL_vol, row address X-ADDR, and column address Y-ADDR.

[0079] The memory cell array 330 may include multiple memory blocks BLK1 to BLKz (where z is a positive integer), and each memory block may include multiple memory cells. The memory cell array 330 can be connected to the page buffer 340 via the bit line BL, and to the line decoder 360 via the word line WL, the serial select line SSL, and the ground select line GSL.

[0080] In an example embodiment, the memory cell array 330 may include a 3D memory cell array comprising a plurality of NAND strings. Each of the NAND strings may include memory cells respectively connected to word lines vertically stacked on a substrate. The disclosures of U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648 are hereby incorporated by reference. In an example embodiment, the memory cell array 330 may include a 2D memory cell array comprising a plurality of NAND strings arranged along row and column directions.

[0081] Page buffer 340 may include multiple page buffers PB1 to PBn (here, n is an integer greater than or equal to 3), which may be connected to memory cells via multiple bit lines BL. Page buffer 340 may select at least one of the bit lines BL in response to column address Y-ADDR. Depending on the operating mode, page buffer 340 may operate as a write driver or a sense amplifier. For example, during a programming operation, page buffer 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer 340 may sense the current or voltage of the selected bit line BL and sense the data stored in the memory cell.

[0082] Voltage generator 350 can generate various voltages for programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 350 can generate programming voltage, read voltage, programming verification voltage, and erase voltage as word line voltage VWL.

[0083] The row decoder 360 can select one of a plurality of word lines WL and one of a plurality of string select lines SSL in response to the row address X-ADDR. For example, the row decoder 360 can apply a programming voltage and a programming verification voltage to the selected word line WL during a programming operation and a read voltage to the selected word line WL during a read operation.

[0084] Figure 5 This is a diagram of a UFS system 2000 according to an embodiment. The UFS system 2000 may be a system conforming to the UFS standard published by the Joint Electronic Equipment Committee (JEDEC) and includes a UFS host 2100, a UFS device 2200, and a UFS interface 2300. The above describes... Figure 1 The description of System 1000 can also be found in the following... Figure 5 The description applies within the scope of non-conflict. Figure 5 UFS system 2000.

[0085] refer to Figure 5 UFS host 2100 can connect to UFS device 2200 via UFS interface 2300. When Figure 1 When the main processor 1100 is an access point (AP), the UFS host 2100 can be implemented as part of the AP. The UFS host controller 2110 and host memory 2140 can respectively correspond to... Figure 1 The main processor 1100 includes a controller 1120 and memory 1200a and 1200b. The UFS device 2200 can correspond to... Figure 1 Storage devices 1300a and 1300b, and UFS device controller 2210 and NVM 2220 can respectively correspond to Figure 1 Storage controllers 1301a and 1301b, and NVM 1302a and 1302b.

[0086] UFS host 2100 may include UFS host controller 2110, application 2120, UFS driver 2130, host memory 2140, and UFS interconnect (UIC) layer 2150. UFS device 2200 may include UFS device controller 2210, NVM 2220, storage interface 2230, device memory 2240, UIC layer 2250, and regulator 2260. NVM 2220 may include multiple memory cells 2221. Although each of the memory cells 2221 may include V-NAND flash memory with a 2D or 3D structure, each of the memory cells 2221 may include another type of NVM, such as PRAM and / or RRAM. UFS device controller 2210 can be connected to NVM 2220 via storage interface 2230. Storage interface 2230 may be configured to comply with standard protocols such as Toggle or ONFI.

[0087] Application 2120 can refer to a program that wants to communicate with UFS device 2200 to use the functions of UFS device 2200. Application 2120 can send input / output requests (IORs) to UFS drive 2130 for input / output (I / O) operations on UFS device 2200. IORs can refer to data read requests, data storage (or write) requests, and / or data erase (or discard) requests, but are not limited to these.

[0088] UFS drive 2130 can manage UFS host controller 2110 via UFS-HCI (UFS-HCI). UFS drive 2130 can translate IOR generated by application 2120 into UFS commands defined by the UFS standard and send these UFS commands to UFS host controller 2110. One IOR can be translated into multiple UFS commands. Although UFS commands can be largely defined by the SCSI standard, they can also be UFS standard-specific commands.

[0089] The UFS host controller 2110 can send UFS commands, translated by the UFS driver 2130, to the UIC layer 2250 of the UFS device 2200 via the UIC layer 2150 and the UFS interface 2300. During the transmission of UFS commands, the UFS host register 2111 of the UFS host controller 2110 can be used as a command queue (CQ).

[0090] The UIC layer 2150 on the UFS host 2100 side may include the Mobile Industry Processor Interface (MIPI) M-PHY 2151 and MIPI UniPro 2152, and the UIC layer 2250 on the UFS device 2200 side may also include MIPI M-PHY 2251 and MIPI UniPro 2252.

[0091] The UFS interface 2300 may include a line configured to transmit a reference clock signal REF_CLK, a line configured to transmit a hardware reset signal RESET_n of the UFS device 2200, a pair of lines configured to transmit a pair of differential input signals DIN_t and DIN_c, and a pair of lines configured to transmit a pair of differential output signals DOUT_t and DOUT_c.

[0092] The frequency of the reference clock signal REF_CLK provided from the UFS host 2100 to the UFS device 2200 can be one of, but is not limited to, 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz. The UFS host 2100 can change the frequency of the reference clock signal REF_CLK during operation (i.e., during data transmission / reception operations between the UFS host 2100 and the UFS device 2200). The UFS device 2200 can generate clock signals of various frequencies based on the reference clock signal REF_CLK provided from the UFS host 2100 using a phase-locked loop (PLL). Furthermore, the UFS host 2100 can set the data rate between the UFS host 2100 and the UFS device 2200 by using the frequency of the reference clock signal REF_CLK. That is, the data rate can be determined based on the frequency of the reference clock signal REF_CLK.

[0093] The UFS interface 2300 can support multiple lanes, each of which can be implemented as a pair of differential lines. For example, the UFS interface 2300 may include at least one receive lane and at least one transmit lane. Figure 5 In this configuration, a pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C can form a receiving channel, while a pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C ​​can form a transmitting channel. Although Figure 5 The diagram shows one transmit channel and one receive channel, but the number of transmit channels and the number of receive channels can be changed.

[0094] The receive and transmit channels can be used to send data based on a serial communication scheme. Due to the separate receive and transmit channels, full-duplex communication between the UFS host 2100 and the UFS device 2200 can be achieved. That is, while receiving data from the UFS host 2100 via the receive channel, the UFS device 2200 can send data to the UFS host 2100 via the transmit channel. Furthermore, control data (e.g., commands) from the UFS host 2100 to the UFS device 2200, as well as user data to be stored by the UFS host 2100 in or read from the NVM 2220 of the UFS device 2200, can be transmitted via the same channel. Therefore, in addition to the pair of receive channels and the pair of transmit channels, it may not be necessary to provide additional separate channels for data transmission between the UFS host 2100 and the UFS device 2200.

[0095] The UFS device controller 2210 of the UFS device 2200 can control all operations of the UFS device 2200. The UFS device controller 2210 can manage the NVM 2220 by using logical units (LUs) 2211 as logical data storage units. The number of LUs 2211 can be eight, but is not limited to this. The UFS device controller 2210 may include an FTL and, by using the address mapping information of the FTL, translates logical data addresses (e.g., logical block addresses (LBAs)) received from the UFS host 2100 into physical data addresses (e.g., physical block addresses (PBAs)). Logical blocks configured to store user data in the UFS system 2000 can have sizes within a predetermined range. For example, the minimum size of a logical block can be set to 4Kbytes.

[0096] When a command from UFS host 2100 is applied to UFS device 2200 through UIC layer 2250, UFS device controller 2210 can perform an operation in response to the command and send a completion response to UFS host 2100 when the operation is completed.

[0097] As an example, when UFS host 2100 intends to store user data in UFS device 2200, UFS host 2100 can send a data storage command to UFS device 2200. When it receives a response from UFS device 2200 indicating that UFS host 2100 is ready to receive user data (transfer ready) (a 'transfer ready' response), UFS host 2100 can send the user data to UFS device 2200. UFS device controller 2210 can temporarily store the received user data in device memory 2240, and store the user data temporarily stored in device memory 2240 at a selected location in NVM 2220 based on FTL address mapping information.

[0098] As another example, when UFS host 2100 intends to read user data stored in UFS device 2200, UFS host 2100 can send a data read command to UFS device 2200. Upon receiving the command, UFS device controller 2210 can read the user data from NVM 2220 based on the data read command and temporarily store the read user data in device memory 2240. During the read operation, UFS device controller 2210 can detect and correct errors in the read user data using an embedded ECC engine. More specifically, the ECC engine can generate parity bits for the write data to be written to NVM 2220, and the generated parity bits can be stored in NVM 2220 along with the write data. During data reading from NVM 2220, the ECC engine can correct errors in the read data by using the parity bits read from NVM 2220 along with the read data, and output the error-corrected read data.

[0099] Additionally, the UFS device controller 2210 can send user data temporarily stored in the device memory 2240 to the UFS host 2100. Furthermore, the UFS device controller 2210 may also include an AES engine. The AES engine can perform at least one of encryption and decryption operations on the data sent to the UFS device controller 2210 using a symmetric key algorithm.

[0100] UFS host 2100 can sequentially store commands to be sent to UFS device 2200 in UFS host register 2111, which can be used as a common queue, and send commands to UFS device 2200 sequentially. In this case, even while a previously sent command is still being processed by UFS device 2200, that is, even before receiving notification that a previously sent command has been processed by UFS device 2200, UFS host 2100 can send the next command waiting in the CQ to UFS device 2200. Therefore, UFS device 2200 can also receive the next command from UFS host 2100 while processing a previously sent command. For example, the maximum number of commands (or queue depth) that can be stored in the CQ can be 32. Furthermore, the CQ can be implemented as a circular queue, where the start and end of the command lines stored in the queue are indicated by head pointers and tail pointers.

[0101] Each of the plurality of memory cells 2221 may include a memory cell array and control circuitry configured to control the operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include multiple memory cells. Although each of the memory cells is configured to store 1 bit of information as a single-level cell (SLC), each of the memory cells may be a cell configured to store 2 or more bits of information, such as a multi-level cell (MLC), a three-level cell (TLC), and a four-level cell (QLC). A 3D memory cell array may include vertical NAND strings, wherein at least one memory cell is vertically oriented and located on top of another memory cell.

[0102] Voltages VCC, VCCQ, and VCCQ2 can be applied as power supply voltages to the UFS device 2200. Voltage VCC can be the main power supply voltage of the UFS device 2200 and range from 2.4 V to 3.6 V. Voltage VCCQ can be a power supply voltage primarily used to supply a low voltage to the UFS device controller 2210 and range from 1.14 V to 1.26 V. Voltage VCCQ2 can be a power supply voltage primarily used to supply I / O interfaces (such as the MIPI M-PHY 2251) with a voltage lower than VCC and higher than VCCQ and range from 1.7 V to 1.95 V. The power supply voltages can be supplied to the corresponding components of the UFS device 2200 via regulator 2260. Regulator 2260 can be implemented as a set of unit regulators, each connected to one of the aforementioned power supply voltages.

[0103] Figure 6 This is a block diagram of a memory system 20 according to an embodiment. (See reference...) Figure 6 The memory system 20 may include a memory device 300 and a memory controller 400. The memory device 300 may correspond to one of the NVM devices NVM11 to NVMmn, which are based on... Figure 3 One of the multiple channels CH1 to CHm communicates with the memory controller 400. The memory controller 400 can correspond to... Figure 2A Storage controller 210.

[0104] The memory device 300 may include first pins P11 to eighth pins P18, memory interface circuitry 310, control logic circuitry 320, and memory cell array 330.

[0105] The memory interface circuit 310 can receive the chip enable signal nCE from the memory controller 400 via the first pin P11. In response to the chip enable signal nCE, the memory interface circuit 310 can send signals to and receive signals from the memory controller 400 via the second pin P12 to the eighth pin P18. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 310 can send signals to and receive signals from the memory controller 400 via the second pin P12 to the eighth pin P18.

[0106] The memory interface circuit 310 can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 400 via pins P12 to P14. The memory interface circuit 310 can receive or send the data signal DQ from the memory controller 400 via pin P17. Commands CMD, addresses ADDR, and data can be sent via the data signal DQ. For example, the data signal DQ can be sent via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to the multiple data signals DQ.

[0107] The memory interface circuit 310 can obtain the command CMD from the data signal DQ. This command CMD is received during the enable portion (e.g., a high-level state) of the command latch enable signal CLE based on the toggle timing of the write enable signal nWE. The memory interface circuit 310 can also obtain the address ADDR from the data signal DQ. This address ADDR is received during the enable portion (e.g., a high-level state) of the address latch enable signal ALE based on the toggle timing of the write enable signal nWE.

[0108] In the example embodiment, the write enable signal nWE can be maintained in a static state (e.g., high or low) and toggled between high and low. For example, the write enable signal nWE can be toggled in the portion where the command CMD or address ADDR is sent. Therefore, the memory interface circuit 310 can obtain the command CMD or address ADDR based on the switching time of the write enable signal nWE.

[0109] The memory interface circuit 310 can receive the read enable signal nRE from the memory controller 400 via its fifth pin P15. The memory interface circuit 310 can receive the data strobe signal DQS from the memory controller 400 or send the data strobe signal DQS to the memory controller 400 via its sixth pin P16.

[0110] In the data (DATA) output operation of memory device 300, memory interface circuit 310 can receive a read enable signal nRE switched via pin 5 P15 before outputting data DATA. Memory interface circuit 310 can generate a data strobe signal DQS, which switches based on the switching of the read enable signal nRE. For example, memory interface circuit 310 can generate data strobe signal DQS based on the switching start time of the read enable signal nRE, and this data strobe signal DQS begins switching after a predetermined delay (e.g., tDQSRE). Memory interface circuit 310 can transmit a data signal DQ including data DATA based on the switching time of data strobe signal DQS. Therefore, data DATA can be aligned with the switching time of data strobe signal DQS and sent to memory controller 400.

[0111] In the data (DATA) input operation of memory device 300, when a data signal DQ including data DATA is received from memory controller 400, memory interface circuit 310 can receive a switching data strobe signal DQS along with the data DATA from memory controller 400. Memory interface circuit 310 can obtain data DATA from data signal DQ based on the switching time point of data strobe signal DQS. For example, memory interface circuit 310 can sample data signal DQ at the rising and falling edges of data strobe signal DQS and obtain data DATA.

[0112] The memory interface circuit 310 can send a ready / busy output signal nR / B to the memory controller 400 via pin 8 P18. The memory interface circuit 310 can also send status information of the memory device 300 to the memory controller 400 via the ready / busy output signal nR / B. When the memory device 300 is in a busy state (i.e., when an operation is being performed on the memory device 300), the memory interface circuit 310 can send a ready / busy output signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (i.e., when no operation is being performed or completed on the memory device 300), the memory interface circuit 310 can send a ready / busy output signal nR / B indicating the ready state to the memory controller 400. For example, when memory device 300 is reading data DATA from memory cell array 330 in response to a page read command, memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state (e.g., low level) to memory controller 400. Similarly, when memory device 300 is programming data DATA into memory cell array 330 in response to a programming command, memory interface circuit 310 can send a ready / busy output signal nR / B indicating a busy state to memory controller 400.

[0113] Control logic circuit 320 can control all operations of memory device 300. Control logic circuit 320 can receive commands / addresses (CMD / ADDR) obtained from memory interface circuit 310. Control logic circuit 320 can generate control signals for controlling other components of memory device 300 in response to the received commands / addresses (CMD / ADDR). For example, control logic circuit 320 can generate various control signals for programming data DATA into or reading data DATA from memory cell array 330.

[0114] The memory cell array 330 can store data DATA obtained from the memory interface circuit 310 by controlling the control logic circuit 320. The memory cell array 330 can output the stored data DATA to the memory interface circuit 310 by controlling the control logic circuit 320.

[0115] The memory cell array 330 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, embodiments in which the memory cells are NAND flash memory cells will be described primarily.

[0116] The memory controller 400 may include first pins P21 to eighth pins P28 and controller interface circuitry 410. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 of the memory device 300, respectively.

[0117] The controller interface circuit 410 can send a chip enable signal nCE to the memory device 300 via the first pin P21. The controller interface circuit 410 can send signals to the memory device 300 selected by the chip enable signal nCE and receive signals from the memory device 300 via the second pin P22 to the eighth pin P28.

[0118] The controller interface circuit 410 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 300 via pins P22 to P24. The controller interface circuit 410 can send the data signal DQ to the memory device 300 or receive the data signal DQ from the memory device 300 via pin P27.

[0119] The controller interface circuit 410 can send a data signal DQ, including a command CMD or an address ADDR, along with a write enable signal nWE that can be switched, to the memory device 300. The controller interface circuit 410 can also send the data signal DQ, including a command CMD, to the memory device 300 by sending a command latch enable signal CLE with an enabled state. Furthermore, the controller interface circuit 410 can send the data signal DQ, including an address ADDR, to the memory device 300 by sending an address latch enable signal ALE with an enabled state.

[0120] The controller interface circuit 410 can send a read enable signal nRE to the memory device 300 via its fifth pin P25. The controller interface circuit 410 can receive a data strobe signal DQS from the memory device 300 or send a data strobe signal DQS to the memory device 300 via its sixth pin P26.

[0121] In the data (DATA) output operation of memory device 300, controller interface circuit 410 can generate a toggleable read enable signal nRE and send the read enable signal nRE to memory device 300. For example, before outputting data DATA, controller interface circuit 410 can generate the read enable signal nRE, which changes from a static state (e.g., high level or low level) to a toggle state. Therefore, memory device 300 can generate a toggleable data strobe signal DQS based on the read enable signal nRE. Controller interface circuit 410 can receive a data signal DQ including data DATA along with the toggleable data strobe signal DQS from memory device 300. Controller interface circuit 410 can obtain data DATA from data signal DQ based on the switching time of data strobe signal DQS.

[0122] During data (DATA) input operations of memory device 300, controller interface circuit 410 can generate a toggling data strobe signal DQS. For example, before sending data DATA, controller interface circuit 410 can generate data strobe signal DQS, which changes from a static state (e.g., high or low level) to a toggling state. Controller interface circuit 410 can send a data signal DQ including data DATA to memory device 300 based on the switching time of data strobe signal DQS.

[0123] The controller interface circuit 410 can receive the ready / busy output signal nR / B from the memory device 300 via pin 8 P28. The controller interface circuit 410 can determine the status information of the memory device 300 based on the ready / busy output signal nR / B.

[0124] Figure 7 This is a diagram of a 3D V-NAND structure applicable to a UFS device according to an embodiment. When the storage module of a UFS device is implemented as a 3D V-NAND flash memory, each of the plurality of memory blocks included in the storage module can be used... Figure 7 The equivalent circuit shown is illustrated.

[0125] Figure 7 The memory block BLKi shown can refer to a 3D memory block having a 3D structure formed on a substrate. For example, multiple NAND strings included in the memory block BLKi can be formed in a direction perpendicular to the substrate.

[0126] refer to Figure 7The memory block BLKi may include multiple memory NAND strings (e.g., NS11 to NS33) connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the memory NAND strings NS11 to NS33 may include a string select transistor SST, multiple memory cells (e.g., MC1, MC2, ..., and MC8), and a ground select transistor GST. Each of the memory NAND strings NS11 to NS33 in Figure 7 The memory is shown as including eight memory cells MC1, MC2, ..., and MC8, but is not limited thereto.

[0127] The string select transistor SST can be connected to its corresponding string select lines SSL1, SSL2, and SSL3. Each of the memory cells MC1, MC2, ..., and MC8 can be connected to a corresponding gate line among the gate lines GTL1, GTL2, ..., and GTL8. Gate lines GTL1, GTL2, ..., and GTL8 can each correspond to a word line, and some of the gate lines GTL1, GTL2, ..., and GTL8 can correspond to dummy word lines. The ground select transistor GST can be connected to its corresponding ground select lines GSL1, GSL2, and GSL3. The string select transistor SST can be connected to its corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0128] Word lines at the same level (e.g., WL1) can be connected together, while ground select lines GSL1, GSL2, and GSL3 and serial select lines SSL1, SSL2, and SSL3 can be separated from each other. Figure 7 The illustration shows a case where the memory block BLKi is connected to eight gate lines GTL1, GTL2, ..., and GTL8, and three bit lines BL1, BL2, and BL3, but it is not limited to this.

[0129] Figure 8 This is a block diagram of a memory system according to an embodiment. For example... Figure 8As shown, the memory system 800 may include a host 810, a memory controller 820, and a NAND device 830. The memory controller 820 may include a flash memory translation layer (FTL) 821, an ECC encoder module 822, a modulation module 823, a demodulation and signal processing module 825, and an ECC decoder module 824. In embodiments, the ECC encoder module 822 and the modulation module 823 may be referred to as the write path, while the demodulation and signal processing module 825 and the ECC decoder module 824 may be referred to as the read path. In embodiments, the memory system 800 may correspond to one or more of the elements discussed above, such as the host memory system 10, but embodiments are not limited thereto.

[0130] To write data to NAND device 830, host 810 can pass a logical address, such as a logical block address (LBA), to memory controller 820, and can transfer the data corresponding to the LBA to memory controller 820. Using FTL 821, memory controller 820 can break the data into ECC data words and set the corresponding physical address for NAND device 830.

[0131] The length of the ECC data word can be... In some embodiments, length It can have a value of four thousand bits (kb), however, the embodiments are not limited to this. The ECC encoder module 822 can receive... Bit ECC data, and redundant bits can be added to generate a length of [length missing]. ECC codewords. The ECC code rate can be expressed as... In some embodiments, The value can be, for example, 0.9; however, the embodiments are not limited to this.

[0132] In an embodiment, Bit codewords can be combined together and programmed or written to NAND device 830 via modulation module 823, which can use modulation such as single-level cell (SLC) modulation, multi-level cell (MLC) modulation, three-level cell (TLC) modulation and four-level cell (QLC) modulation, however, embodiments are not limited thereto.

[0133] To read data from NAND device 830, host 810 can request to read LBA from memory controller 820, which is then translated into a physical address by FTL 821. NAND device 830 can transmit the corresponding read data, which can be demodulated and processed by demodulation and signal processing module 825 to generate a length of [missing information]. ECC noise word. In an embodiment, ECC noise word may refer to an ECC codeword with some errors.

[0134] The basic operating mode can be fast reading from NAND device 830, where memory controller 820 can receive data from NAND. The ECC decoder module 824 can handle bits with errors. Bits are decoded and reconstructed or stored. This mode uses ECC data. It can be referred to as the Hard Decision (HD) mode.

[0135] If the process fails, additional measurements can be received from the NAND device 830. For example, the ECC decoder module 824 can receive values ​​representing ECC codewords. A vector of “soft” values, and can perform decisions with higher quality. This mode can be called soft decision (SD) mode, and can be associated with higher latency than HD mode, due to the time required to read from NAND and also because different signal processing or ECC operation modes can be performed with greater complexity.

[0136] Figure 9 An example of a NAND memory block according to an embodiment is shown. Generally, a NAND cell can store... Position, among which It depends on the specific type of NAND memory cell. For example, a flash memory device storing one bit per cell (BPC) can be called a single-level cell (SLC), a flash memory device storing two BPCs can be called a multi-level cell (MLC), a flash memory device storing three BPCs can be called a three-level cell (TLC), a flash memory device storing four BPCs can be called a four-level cell (QLC), and a flash memory device storing five BPCs can be called a five-level cell (PLC). For example, memory block 900 can be a TLC NAND memory block. As discussed above, NAND chips can have features including... A person with The structure of bars (WL) blocks, where each WL includes Bar lines (BL).

[0137] To allow for fast NAND access, each write line (WL) of a NAND memory device can be divided into Random Access Units (RAUs). Generally, if the number of bits to be stored in a RAU is... Then WL can be divided into Each sector will include A person with BL of RAU, meaning One of the bits, for example, could be the least significant bit (LSB), center significant bit (CSB), or most significant bit (MSB). Therefore, the number of RAUs in such a block would be... To allow for high-reliability access, each RAU can be protected with ECC. For example, the ECC code length of the RAU can be [length missing]. And can accommodate One information bit.

[0138] According to the embodiments, this document may use the notation shown in Equations 1 and 2 as follows:

[0139] (Equation 1)

[0140] (Equation 2)

[0141] Vectors can be represented as lowercase bold letters (e.g., ), and matrices can be represented as uppercase bold letters (e.g., ).

[0142] According to an embodiment, It can represent a Galois field primitive element. It can represent a length of Dimensions and error correction capability The BCH code. Additionally... It can represent a stage. The corresponding BCH transform.

[0143] According to an embodiment, It can represent a length of The RS code of (symbol), where .in addition, It can represent stages The corresponding RS transformation.

[0144] According to an embodiment, ) can represent a length of The RS code of (symbol), where And also includes parameters .

[0145] According to an embodiment, nested codes can be used as constant codes. Nested codes can refer to codes derived from a set of codes of length... And the dimension is The same series The code, of which for and , .

[0146] Typing It can be included in ( In, it can correspond to a coset. ( Nested keys can have the following properties: ( The code words in ) yes The codewords in the code satisfy linear constraints ,in This represents the coset operator. In the embodiment, and The relationship between the number of codewords in the codewords can be expressed by the following equation 3:

[0147] Equation 3

[0148] Transformation It can refer to the application applied to the composition of codewords It also returns the codeword coset, which can be referred to as the transformation space. The linear operations can be expressed according to the following equations 4 and 5:

[0149] Equation 4

[0150] Equation 5

[0151] According to the embodiment, the code It can be of length Dimensions And its error correction capability is BCH codes. The parity check matrix of this type of BCH code can be constructed using primitives. To define, as shown in Equation 6 below:

[0152] (Equation 6)

[0153] Typing ( On and The corresponding BCH checksum can be expressed according to the following Equation 7:

[0154] (Equation 7)

[0155] To use BCH codes as constituent codes, nested BCH codes and their transformations can be defined as follows. For a set of error correction parameters... , , making For the corresponding dimension A series of nested BCH codes can be represented as And it can be expressed according to the following equation 7-1:

[0156] (Equation 7-1)

[0157] For some BCH code Coset can be represented as It can be defined according to the following equation 8:

[0158] (Equation 8)

[0159] The BCH transform can then be defined according to Equation 9, where the corresponding transform space symbol is represented according to Equation 10, and the transform space is defined according to the following Equation 11:

[0160] (Equation 9)

[0161] (Equation 10)

[0162] (Equation 11)

[0163] According to the embodiment, the code It can be of length And the minimum distance is RS code.

[0164] The parity check matrix of this type of RS code can use primitives. This can be represented as shown in Equation 12 below:

[0165] (Equation 12)

[0166] Typing (and On and The corresponding RS checksum can be represented as And it can be expressed according to the following equation 13:

[0167] (Equation 13)

[0168] To use RS codes as constituent codes, nested RS codes and their transformations can be defined as follows. A set of error correction parameters can be represented as follows. , ,and Make This series of RS nested codes can be represented as And it can be expressed according to the following equation 14:

[0169] (Equation 14)

[0170] RS code Accompanying the set ( ) can be represented as And it can be expressed according to the following equation 15:

[0171] (Equation 15)

[0172] The RS transform can then be defined according to Equation 16, where the corresponding transform space symbol is represented according to Equation 17, and the transform space is defined according to the following Equation 18:

[0173] (Equation 16)

[0174] (Equation 17)

[0175] (Equation 18)

[0176] According to the embodiment, the code It can be a GRS code, which is a generalization of the RS code presented above, and has parameters. ( )and ( and The parity check matrix is ​​defined as follows.

[0177] The parity check matrix of this type of GRS code can be represented as shown in Equation 19 below:

[0178] (Equation 19)

[0179] As discussed in more detail below, the parameters of the GRS code can be specifically selected. and Therefore, a parity check matrix for GRS codes was specifically constructed. To construct 2D-GCC codes, the transpose operation described below is performed correctly for 2D-GCC decoding.

[0180] Typing (and On and The corresponding GRS checksum can be represented as And it can be expressed according to the following equation 20:

[0181] (Equation 20)

[0182] To use GRS codes as constituent codes, nested GRS codes and their transformations can be defined as follows. A set of error correction parameters can be represented as follows. , ,and Make This series of GRS nested codes can be represented as And it can be expressed according to the following equation 21:

[0183] (Equation 21)

[0184] GRS code Accompanying the set ( ) can be represented as And it can be expressed according to the following equation 22:

[0185] (Equation 22)

[0186] The GRS transform can then be defined according to Equation 23, where the corresponding transform space symbol is represented according to Equation 24, and the transform space is defined according to the following Equation 25:

[0187] (Equation 23)

[0188] (Equation 24)

[0189] (Equation 25)

[0190] According to an embodiment, GCC may be a code that includes several constituent codes belonging to a nested code series, a transformation to a transformation space, and a code list in the transformation space, wherein there is a mapping between codewords and transformation symbols.

[0191] Figure 10 An example code structure of the GCC S-BCH code according to an embodiment is shown. Figure 10 As shown, a GCC S-BCH code can refer to a concatenation of a BCH code and an RS code. For example, a GCC S-BCH code can be associated with a set of nested BCH codes, as shown in Equation 14 above, where... .

[0192] For length of of individual code characters ( The corresponding transformation space symbol can be represented as (for and ),in As defined in Equation 9 above. In the embodiment, This can be expressed according to the following equation 26:

[0193] (Equation 26)

[0194] For all Vector of symbols It can be defined as having a length of And the dimension is RS codeword ,in or equivalent to ( ,like Figure 10 As shown. The corresponding RS checksum can be represented as And it can be expressed according to the following equation 27:

[0195] (Equation 27)

[0196] (Binary) Vector This can be expressed according to the following equation 28, ( )vector This can be expressed according to the following equation 29:

[0197] (Equation 28)

[0198] (Equation 29)

[0199] Therefore, the GCC parity check matrix It can be defined according to Equation 27 above, and expressed according to Equation 30 below:

[0200] (Equation 30)

[0201] In The total number of equations in the equations can be This can be represented as an application to binary vectors. of A binary constraint, its definition [ ]x[ Binary parity check matrix . Some lines in the code may be related, therefore the code overhead may be... The upper limit of bits. The GCC S-BCH code can be represented as... .

[0202] In this embodiment, a parity check matrix can be used to define the GCC S-BCH encoder. For example, Gaussian elimination can be applied as a continuous row operation. Generate matrix , making ,in This represents a diagonal matrix containing 0s and 1s on its diagonal. The zero row can be omitted to obtain... matrix ,in Indicates size is The identity matrix. The codeword vector can be determined according to the following equation 31. Divided into information bits Parity bit It can be used to obtain equation 32.

[0203] (Equation 31)

[0204] (Equation 32)

[0205] In this embodiment, the GCC S-BCH encoder can be defined according to Equation 32 above.

[0206] Figures 11A to 11D Examples of GCC decoding procedures are provided for GCC codes, such as the GCC S-BCH codes discussed above. According to embodiments, the GCC decoding procedure may use one or more of the elements described above (e.g., those discussed above). Figure 2A The storage device discussed 200, and the above regarding... Figure 2B The ECC decoding circuit 520 discussed above, and the above regarding... Figure 8 The discussion involves using the ECC decoder module 824 or any other component to perform this.

[0207] Figure 11A An example of a sequential decoder system 1110 is shown, which can be used to decode GCC codes, such as the GCC S-BCH codes discussed above. In embodiments, the sequential decoder system 1110 may include one or more of the elements discussed above (e.g., those mentioned above regarding...). Figure 2A The storage device discussed 200, and the above regarding... Figure 2B The ECC decoding circuit 520 discussed above, and the above regarding... Figure 8 In the ECC decoder module 824 discussed, in an embodiment, the GCC S-BCH structure allows the use of a GCC decoding algorithm to decode the codeword, which may include sequential activation of the coset BCH decoder, followed by activation of the RS decoder, until the entire GCC codeword is decoded.

[0208] like Figure 11A As shown, the sequential decoder system 1110 may include a coset BCH decoder 1112, a transform module 1116, and an RS decoder 1117. The sequential decoder system 1110 can receive a noise codeword 1111, which can be represented as... ,in Is and action The corresponding length is The vector of log-likelihood ratios (LLRs). The coset of the BCH decoder 1112 can be used row-wise to be based on the LLR and the transform space 1115 (e.g., the coset of the decoded BCH codeword 1113, which can be represented as...). The generated decoded BCH codeword 1113 (can be represented as) ) and BCH symbol state 1114 (which can be represented as The transformation module 1116 can, for example, transform... The output of the coset BCH decoder 1112 is used to generate updated transform space symbols, which can be represented as follows: In this embodiment, the output of the co-set BCH decoder 1112 can be expressed according to the following equation 33:

[0209] (Equation 33)

[0210] According to Equation 33, for each row The co-set BCH decoder 1112 can return the decoding status. (in The instruction was successful, and (Indication failure) and the decoded BCH codeword ,in The following equation 34 must be satisfied:

[0211] (Equation 34)

[0212] Return line based on coset BCH decoder 1112 Decoding status The sequential decoder 1110 can update the corresponding BCH codeword of the decoded BCH codeword 1113 accordingly. The corresponding BCH symbol state of BCH symbol state 1114 .

[0213] RS decoder 1117 can receive RS symbols obtained based on transform space 1115. , and BCH symbol state 1114 (e.g., )and Each corresponds to an RS code. The RS decoder 1117 can perform RS decoding and output corrected symbols. and updated BCH symbol state For example, based on the BCH symbol state as However, if RS decoder 1117 detects an error, the BCH symbol state can be updated to... The RS decoder 1117 can also output the RS decoding status 1118, which can be represented as... .

[0214] The output of RS coder 1117 can be expressed according to the following equation 35:

[0215] (Equation 35)

[0216] Figure 11B An example of a sequential decoding algorithm that can be used to perform GCC decoding is shown, presented in pseudocode as Algorithm 1. In an embodiment, Algorithm 1 can be executed by the sequential decoder 1110 discussed above.

[0217] Figure 11C An example decoding sequence corresponding to the GCC decoding algorithm discussed above is shown.

[0218] like Figure 11C As shown, at t=0, the RS decoder 1117 can be omitted, and the coset BCH decoder 1112 can be applied even without coset values. Figure 11C In the example shown, four rows were successfully decoded at operation 1131B, and the corresponding part of the transform space 1115 was updated at operation 1131C.

[0219] For t=1, RS decoder 1117 can correct the missing symbol at operation 1132A, and can apply coset BCH decoder 1112 and a coset symbol to the remaining four rows at operation 1132B. Figure 11C In the example shown, both lines were successfully decoded at operation 1132B, and the corresponding part of the transform space 1115 was updated at operation 1132C.

[0220] For t=2, RS decoder 1117 can correct the missing symbols at operation 1133A, and can apply coset BCH decoder 1112 and two coset symbols to the remaining two lines at operation 1133B. Figure 11C In the example shown, the two remaining lines were successfully decoded at operation 1133B, and the corresponding part of the transform space was updated at operation 1133C.

[0221] For t=3, RS decoder 1117 can correct the missing symbols at operation 1134A. Figure 11C In the example shown, this could include simply verifying whether the symbol is valid, since no erased symbol remains, and therefore steps B and C of the GCC decoding algorithm are unnecessary.

[0222] For t=4, RS decoder 1117 can correct the missing symbols at operation 1135A. Figure 11C In the example shown, this could include simply verifying whether the symbol is valid, since no erased symbol remains, and therefore steps B and C of the GCC decoding algorithm are unnecessary.

[0223] Figure 11D This is a flowchart of the decoding process according to an embodiment. For example, such as... Figure 11D The illustrated process 1140 may correspond to some or all of the algorithm 1 discussed above. In an embodiment, some or all of process 1140 may be executed by the sequential decoder 1110 discussed above. For example, at operation 1141, process 1140 may include decoding the next BCH codeword (or, for example, the first BCH codeword). At operation 1142, process 1140 may include determining whether the decoding was successful. Based on the determination that the decoding was successful (yes at operation 1142), process 1140 may proceed to operation 1143 and update the transform space based on the decoded BCH codeword. Based on the determination that the decoding was unsuccessful (no at operation 1142), process 1140 may proceed to operation 1144, which may include determining whether all BCH codewords have been decoded. Based on the determination that all BCH codewords have been decoded (yes at operation 1144), process 1140 proceeds to operation 1145, at which point GCC decoding is successful and information bits can be output. Based on the determination that all BCH codewords have not yet been decoded (No at operation 1144), process 1140 may proceed to operation 1146, which may include determining whether the last BCH codeword has been reached. Based on the determination that the last BCH codeword has been reached (Yes at operation 1146), process 1140 may proceed to operation 1147. Based on the determination that the last BCH codeword has not yet been reached (No at operation 1146), process 1140 may return to operation 1141 and decode the next BCH codeword.

[0224] At operation 1147, process 1140 may include decoding the next BCH codeword (or, for example, the first RS codeword). At operation 1148, process 1140 may include determining whether the decoding was successful. Based on the determination that the decoding was successful (yes at operation 1148), process 1140 may return to operation 1141 and may begin the next round of the decoding algorithm. Based on the determination that the decoding was unsuccessful (no at operation 1148), process 1140 may proceed to operation 1149, at which point it can be determined that the GCC decoding failed.

[0225] Figures 12A to 12C An example code structure of a 2D-GCC code according to an embodiment is shown. For example... Figures 12A to 12C As shown, a 2D-GCC code can refer to a concatenation of a BCH code and a GRS code with specially selected parameters. For example, a 2D-GCC code according to an embodiment may include a GRS code. Its parameters can be defined according to the following equations 36 and 37, instead of the RS codes discussed above with reference to GCC S-BCH codes (e.g., ):

[0226] (Equation 36)

[0227] (Equation 37)

[0228] Character (and The corresponding GRS checksum on ) can be expressed by the following equation 38:

[0229] (Equation 38)

[0230] According to the embodiment, the use of those parameters applied to the binary word can produce a valid BCH code. Binary word (and The corresponding GRS checksum on ) can be expressed by the following equation 39:

[0231] (Equation 39)

[0232] Therefore, according to the following equation 40, the GRS code It can be considered as being applied to Word and (have RS codes (with the ability to correct for erasure) can also be considered as being applied to Characters (with) BCH code for (error correction capability):

[0233] (Equation 40)

[0234] According to an embodiment, the 2D-GCC S-BCH code can be expressed as: binary matrix , of which elements , The rows in this matrix can be represented as The columns in this matrix can be represented as For ease of description, this article describes one of them. These are examples of embodiments; however, the embodiments are not limited thereto. For example, embodiments may also be applied to them. In this case, it is also possible to use... or The degenerated RS code.

[0235] According to the embodiment, a 2D-GCC S-BCH code constructed using the GRS code discussed above is used for the binary matrix. It can be viewed as a GCC S-BCH code (e.g., from a binary matrix). (from the perspective of the corresponding rows), and for the transposed binary matrix It can also be viewed as a G-CC SBCH code (e.g., from a binary matrix). (From the corresponding angle of the column). For example... Figure 12A The example 2D-GCC codeword structure is shown from a row perspective. Figure 12B The corresponding 2D-GCC codeword structure is shown from a column perspective, while Figure 12C This indicates that the two angles are equivalent.

[0236] Figure 12A The example 2D-GCC codeword structure is shown from a row perspective. Specifically, Figure 12A This illustrates a GCC S-BCH code that includes a concatenation of BCH and GRS codes. The corresponding transformation space symbol. It can be defined according to the following equation 41, where Defined according to Equation 9, and .

[0237] , and (Equation 41)

[0238] Next, for all Vector of symbols It can be defined as having a length of R and a dimension of GRS codeword ,in or equivalently for , ( ).

[0239] Figure 12B The corresponding 2D-GCC codeword structure is shown from a column perspective. Specifically, Figure 12B This illustrates a GCC S-BCH code that includes a concatenation of BCH and GRS codes. The corresponding transformation space symbol. It can be defined according to the following equation 42, where Defined in Equation 9, and .

[0240] , and (Equation 42)

[0241] Next, for all Vector of symbols It can be defined as having a length of C and a dimension of GRS codeword ,in or equivalently for , ( ).

[0242] As discussed above, according to Figure 12A The row structure of the 2D-GCC S-BCH code and based on Figure 12B The column structure of the 2D-GCC S-BCH codes is the same. This can be seen by comparing the parity check matrices of the two GCC codes according to the embodiment. The following shows the application to the codeword. The parity check matrix includes all examples of GRS checksums in the transform space.

[0243] From a row perspective, the row transformation space (e.g., the coset of row BCH codewords) can be defined by BCH code transformation according to the following equation 43:

[0244] , (Equation 43)

[0245] The corresponding GRS column checksum can be defined according to the following equation 44:

[0246] , (Equation 44)

[0247] From a column perspective, the column transformation space (e.g., the coset of column BCH codewords) can be defined by BCH code transformations according to the following equation 45:

[0248] , (Equation 45)

[0249] The corresponding GRS row checksum can be defined according to the following equation 46:

[0250] j , (Equation 46)

[0251] To demonstrate the equivalence between the two perspectives, for all the following related... right: and Or alternative and ,show That might be enough.

[0252] This can be shown by applying equations 43, 44, 45, and 46 and changing the order of summation, as shown in equation 47 below:

[0253] (Equation 47)

[0254] This is Figure 12C The diagram is shown in the figure.

[0255] According to the embodiment, the encoder scheme for the 2D-GCC S-BCH code can be substantially similar to the encoder scheme discussed above with reference to the GCC S-BCH code. Furthermore, the parity check matrix of the 2D-GCC S-BCH code... The parity check matrix can be similar to that of GCC S-BCH codes, except that the parity check matrix of 2D-GCC S-BCH codes can use the GRS checksum defined according to Equation 44 or Equation 46 instead of the RS checksum used for GCC S-BCH codes, such that the following Equation 48 is satisfied:

[0256] , (Equation 48)

[0257] The 2D-GCC S-BCH code structure according to the embodiment can provide significant advantages over the GCC S-BCH codes discussed above because the 2D-GCC S-BCH codes can be decoded using a multi-level iterative decoder that iterates between a row-based GCC decoder and a column-based GCC decoder. See below for reference. Figures 13A to 13C An example of a modified GCC sequential decoder suitable for use in a 2D-GCC decoder is described, and references are made below. Figures 14A to 14BTwo specific examples of 2D-GCC decoders using a modified GCC sequential decoder as a building block are described.

[0258] Figures 13A to 13C This relates to an example of a modified GCC sequential decoder that can be used in a 2D-GCC decoder according to an embodiment. According to an embodiment, the GCC decoding process described below may use one or more of the elements described above (e.g., those mentioned above regarding…). Figure 2A The storage device discussed 200, and the above regarding... Figure 2B The ECC decoding circuit 520 discussed above, and the above regarding... Figure 8 The discussion involves using the ECC decoder module 824 or any other component to perform this.

[0259] Figure 13A An example of a sequential decoder system 1310 is shown, which can be used as a building block in a 2D-GCC decoder. In embodiments, the sequential decoder 1310 may include one or more of the elements discussed above (e.g., those mentioned above regarding...). Figure 2A The storage device discussed 200, and the above regarding... Figure 2B The ECC decoding circuit 520 discussed above, and the above regarding... Figure 8 The discussion is in the ECC decoder module 824.

[0260] In an embodiment, the sequential decoder 1310 may be similar to the one referenced above. Figure 11A The sequential decoder 1110 is discussed. For example, the sequential decoder 1310 may include: a coset BCH decoder 1312, which may correspond to coset BCH decoder 1112; and a transform module 1316, which may correspond to transform module 1116. Additionally, the sequential decoder 1310 may receive a noise codeword 1311, which may correspond to noise codeword 1111, while the coset BCH decoder 1312 may generate a decoded BCH codeword 1313, which may correspond to decoded BCH codeword 1113. Furthermore, the sequential decoder 1310 may generate a BCH symbol state 1314, which may correspond to BCH symbol state 1114; and may obtain a transform space 1315, which may correspond to transform space 1115. For ease of description, redundant or repeated descriptions of these elements may be omitted.

[0261] According to the embodiment, the sequential decoder 1310 differs from the sequential decoder 1110 in that, in addition to the output specified in Equation 33, the coset BCH decoder 1312 can also output an LLR value corresponding to each bit after decoding. Therefore, the output of the coset BCH decoder 1312 can be expressed according to the following equation 49:

[0262] (Equation 49)

[0263] In the embodiment, the LLR value It can be stored as an output LLR value 1319, which can be output by the sequential decoder 1310. In this embodiment, the output LLR value of 1319 may be useful in turbo decoding, as referenced below. Figure 14B An example of turbo decoding is described. Therefore, in some embodiments, the co-set BCH decoder 1312 can operate as a SISO decoder, but the embodiments are not limited thereto.

[0264] Additionally, the difference between sequential decoder 1310 and sequential decoder 1110 may be that it can output BCH row decoding state 1314 (e.g., ) and GRS column decoding status 1318 (e.g., This allows them to be used from one iteration of the 2D-GCC decoder to another. For example, a BCH codeword that has already been decoded may not be decoded again in a subsequent iteration. Furthermore, the transform space 1315 can be updated during each iteration (e.g., ), and can be decoded by the input and output of the sequential decoder 1310 (e.g., This allows them to be used as information in subsequent iterations. For example, if a BCH codeword is decoded through row iterations, it can be used to perform further decoding in subsequent column iterations.

[0265] Furthermore, sequential decoder 1310 differs from sequential decoder 1110 in that sequential decoder 1310 may include GRS decoder 1317 instead of RS decoder 1117. GRS decoder 1317 can receive GRS symbols obtained based on transform space 1315. and BCH symbol state 1314 (e.g., )and Each corresponds to a GRS code. The GRS decoder 1317 can output corrected symbols. and updated BCH symbol state For example, based on the BCH symbol state as However, if the GRS decoder 1317 detects an error, the BCH symbol state can be updated to... The GRS decoder 1317 can also output the GRS symbol state 1318, which can be represented as... .

[0266] The output of GRS coder 1317 can be expressed according to the following equation 50:

[0267] (Equation 50)

[0268] According to an embodiment, when used in a 2D-GCC decoder, the sequential decoder 1310 can be coupled with parameters. Together they are applied in row iteration and with parameters They are used together in column iteration.

[0269] Figure 13B An example of a sequential decoding algorithm that can be used to perform GCC decoding is shown, presented in pseudocode as Algorithm 2. In an embodiment, Algorithm 2 can be executed by the sequential decoder 1310 discussed above. Algorithm 2 can be similar to Algorithm 1, except that Algorithm 2 may include the variable is_first_time, which can be used to ensure that the coset BCH decoder 1312 is applied at least once. Additionally, if some of the codewords are known (e.g., ...), )(in If the expression means "not a number", then the corresponding likelihood ratio can be used. The absolute value is set to the maximum value (e.g., MAX), and can be determined based on the bits. Set the plus or minus sign.

[0270] Figure 13C This is a flowchart of the decoding process according to an embodiment. For example, such as... Figure 13CThe illustrated process 1330 may correspond to some or all of the algorithm 2 discussed above. In an embodiment, some or all of process 1330 may be executed by the sequential decoder 1310 discussed above. For example, at operation 1331, process 1330 may include decoding the next BCH codeword. At operation 1332, process 1330 may include determining whether the decoding was successful. Based on the determination that the decoding was successful (yes at operation 1332), process 1330 may proceed to operation 1333 and update the transform space based on the decoded BCH codeword. Based on the determination that the decoding was unsuccessful (no at operation 1332), process 1330 may proceed to operation 1334, which may include updating the BCH codeword based on the decoding result, and then proceed to operation 1335, which may include determining whether all BCH codewords have been decoded. Based on the determination that all BCH codewords have been decoded (yes at operation 1335), process 1330 proceeds to operation 1336, at which point GCC decoding is successful and information bits can be output. Based on the determination that all BCH codewords have not yet been decoded (no at operation 1335), process 1330 may proceed to operation 1337, which may include determining whether the last BCH codeword has been reached. Based on the determination that the last BCH codeword has been reached (yes at operation 1337), process 1330 may proceed to operation 1338. Based on the determination that the last BCH codeword has not yet been reached (no at operation 1337), process 1330 may return to operation 1331 and decode the next BCH codeword.

[0271] At operation 1338, process 1330 may include decoding the next RS codeword. At operation 1339, process 1330 may include determining whether the decoding was successful. Based on the determination that the decoding was successful (yes at operation 1339), process 1330 may return to operation 1331 and begin the next round of the decoding algorithm. Based on the determination that the decoding was unsuccessful (no at operation 1339), process 1330 may proceed to operation 1340, which may include determining whether process 1330 is in the first iteration. Based on the determination that process 1330 is in the first iteration (yes at operation 1340), process 1330 may return to operation 1331 and begin the next round of the decoding algorithm. Based on the determination that process 1330 is not in the first iteration (no at operation 1340), process 1330 may proceed to operation 1341, at which point it can be determined that the GCC decoding failed.

[0272] Figure 14A An example of a 2D-GCC iterative decoder performing soft-input hard-output (SIHO) decoding using a modified GCC sequential decoder is shown, while Figure 14BAn example of a 2D-GCC iterative decoder that performs soft-input soft-output (SISO) decoding using a modified GCC sequential decoder is shown.

[0273] like Figure 14A As shown, the iterative decoder 1410 may include a sequential decoder 1310A, a sequential decoder 1310B, a transpose module 1411, and a transpose module 1412.

[0274] In embodiments, each of sequential decoders 1310A and 1310B may correspond to the sequential decoder 1310 discussed above. For example, sequential decoder 1310A may be an example of sequential decoder 1310 applied according to the row angle of 2D-GCC codes, while sequential decoder 1310B may be an example of sequential decoder 1310 applied according to the column angle of 2D-GCC codes. Sequential decoder 1310A may generate and update row decoder state 1413 (which may be represented as...). ) and row coset 1414, while the sequential decoder 1310A can generate and update the column decoder state 1415 (which can be represented as ) and the list 1416.

[0275] In an embodiment, the input to the iterative decoder 1410 may be a channel LLR. The channel LLR It can be A real matrix, while the output of the iterative decoder 1410 can be codewords. The code It can be A binary matrix. Therefore, the iterative decoder 1410 can be a SIHO decoder. Therefore, the coset BCH encoder 1312 included in each of the sequential decoders 1310A and 1310B can be a SIHO BCH encoder.

[0276] In the embodiments, sequential decoders 1310A and 1310B can perform iterative operations on rows and columns, and can extract intermediate information (e.g., the codewords currently partially decoded) after each iteration. (e.g., decoded BCH codeword 1313) and transform space (e.g., transform space 1315)) are passed to each other. In an embodiment, transpose modules 1411 and 1412 can be used to transpose the codeword currently partially decoded. This allows it to be processed appropriately. For example, the sequential decoder 1310A can be configured to process codewords... Perform sequential decoding, and the sequential decoder 1310B can be configured to decode transposed codewords. Execute sequential decoding.

[0277] For example, iterative decoder 1410 can begin the first iteration of 2D-GCC decoding by providing the input noisy codeword to sequential decoder 1310A, which can perform GCC decoding from a row perspective according to process 1330 until GCC decoding fails. Then, the intermediate information generated by sequential decoder 1310A can be passed to sequential decoder 1310B, which can perform GCC decoding from a column perspective (e.g., for transposed codewords) according to process 1330. The process continues until GCC decoding fails, in which case intermediate information generated by sequential decoder 1310B can be passed to sequential decoder 1310A to begin another iteration. This can continue until the 2D-GCC codeword is fully decoded, or until 2D-GCC decoding fails.

[0278] In some embodiments, sequential decoders 1310A and 1310B may be implemented as a single sequential decoder 1310, and transpose modules 1411 and 1412 may be implemented as a single transpose module, but the embodiments are not limited thereto.

[0279] like Figure 14B As shown, the iterative decoder 1420 may include a sequential decoder 1310C, a sequential decoder 1310D, a transpose module 1421, and a transpose module 1422.

[0280] In embodiments, each of sequential decoders 1310C and 1310D may correspond to the sequential decoder 1310 discussed above. For example, sequential decoder 1310C may be an example of sequential decoder 1310 applied according to the row angle of 2D-GCC codes, while sequential decoder 1310D may be an example of sequential decoder 1310 applied according to the column angle of 2D-GCC codes. Sequential decoder 1310C can generate and update row decoder state 1423 (which may be represented as...). ) and row coset 1424, and the sequential decoder 1310C can generate and update the column decoder state 1425 (which can be represented as ) and the list 1426.

[0281] In this embodiment, the input to the iterative decoder 1420 may be a channel LLR. The channel LLR It can be A real number matrix, while the output of the iterative decoder 1420 can be codewords. ,Right now, A binary matrix. However, the decoded codewords. (or transposed codeword) It may be impossible to pass LLR values ​​between sequential decoder 1310C and sequential decoder 1310D. Alternatively, sequential decoder 1310C and sequential decoder 1310D can use the turbo messaging scheme to pass LLR values ​​between each other. and Therefore, the iterative decoder 1420 can be a SISO decoder. Therefore, the coset BCH encoder 1312 included in each of the sequential decoders 1310C and 1310D can be a SISO BCH encoder.

[0282] In the embodiment, the LLR value It can be based on the row input LLR provided to the sequential decoder 1310C and the output line LLR generated by the sequential decoder 1310C To determine, such as Figure 14B As shown. In the embodiment, the LLR value It can be based on the input column LLR provided to the sequential decoder 1310D and the output column LLR generated by the sequential decoder 1310D To determine, such as Figure 14B As shown.

[0283] In the embodiments, sequential decoders 1310C and 1310D can perform iterative operations on rows and columns, and can extract intermediate information (e.g., LLR values) after each iteration. and And the transformation space (e.g., transformation space 1315) is passed to each other. In an embodiment, transpose modules 1421 and 1422 can be used to transpose LLR values. and This allows them to be processed appropriately. For example, the sequential decoder 1310C can be configured to process LLR values. Perform sequential decoding, and the sequential decoder 1310D can be configured to process transposed LLR values. Execute sequential decoding.

[0284] For example, iterative decoder 1420 can begin the first iteration of 2D-GCC decoding by providing the input noisy codeword to sequential decoder 1310C, which performs GCC decoding from a row perspective according to process 1330 until GCC decoding fails. Then, the intermediate information generated by sequential decoder 1310C can be passed to sequential decoder 1310D, which can begin another iteration by performing GCC decoding from a column perspective according to process 1330, until GCC decoding fails. In this case, the intermediate information generated by sequential decoder 1310D can be passed to sequential decoder 1310C to begin another iteration. This can continue until the 2D-GCC codeword is fully decoded, or until 2D-GCC decoding fails.

[0285] In some embodiments, sequential decoders 1310C and 1310D can be implemented as a single sequential decoder 1310, and transpose modules 1421 and 1422 can be implemented as a single transpose module, but the embodiments are not limited thereto.

[0286] Figure 15A This is a flowchart of a process for controlling a storage system according to an embodiment. According to an embodiment, process 1510 may use one or more of the elements described above (e.g., those mentioned above regarding…). Figure 2A The storage device discussed 200, and the above regarding... Figure 2B The ECC encoding circuit 510 discussed above, and the above regarding... Figure 8 The ECC encoder module 822 discussed above, and the above regarding... Figure 13A The discussion of sequential decoder 1310, and the above regarding... Figures 14A to 14B The iterative decoders 1410 and 1420 (or any other components) discussed are used to perform this.

[0287] like Figure 15A As shown, at operation 1511, process 1510 may include obtaining a 2D-GCC codeword from a storage device.

[0288] like Figure 15A As further shown, at operation 1512, process 1510 may include providing a codeword to a sequential decoder. In some embodiments, the transposed codeword may be provided to a first sequential decoder included in the sequential decoder, and the first sequential decoder may correspond to one or more of the sequential decoders 1310, 1310A and 1310C discussed above.

[0289] like Figure 15AAs further shown, at operation 1513, process 1510 may include determining whether the sequential decoder has succeeded. Based on, for example, determining that the sequential decoder has not succeeded based on the detection of a sequential decoder failure (no at operation 1513), process 1510 may proceed to operation 1514, which may include updating the codeword and transposing the updated codeword to obtain the transposed codeword. Based on determining that the sequential decoder has succeeded (yes at operation 1513), process 1510 may proceed to operation 1518, where the information bits corresponding to the codeword can be obtained.

[0290] like Figure 15A As further shown, at operation 1515, process 1510 may include providing a transposed codeword to a sequential decoder. In some embodiments, the transposed codeword may be provided to a second sequential decoder included in the sequential decoder, and the second sequential decoder may correspond to one or more of the sequential decoders 1310, 1310B, and 1310D discussed above.

[0291] like Figure 15A Further, at operation 1516, process 1510 may include determining whether the sequential decoder has succeeded. Based on, for example, determining that the sequential decoder has not succeeded (no at operation 1516) based on the detection of a sequential decoder failure, process 1510 may proceed to operation 1517, which may include updating the transposed codeword and retransposing the updated transposed codeword to obtain a retransposed codeword. Then, process 1510 may return to operation 1512 to begin another iteration of 2D-GCC decoding. Based on determining that the sequential decoder has succeeded (yes at operation 1516), process 1510 may proceed to operation 1518, where the information bits corresponding to the codeword can be obtained.

[0292] In an embodiment, 2D-GCC codewords may be encoded based on 2D-GCC codes (which may be based on BCH codes and GRS codes).

[0293] In an embodiment, the first GRS checksum generated by the first sequential decoder based on the codeword can be equal to the second GRS checksum generated by the second sequential decoder based on the transposed codeword.

[0294] In an embodiment, process 1510 may further include: decoding one or more rows of a plurality of rows included in a codeword using a first sequential decoder based on a first code; transforming each row of the plurality of rows included in the codeword to obtain a transformed codeword; and decoding one or more columns of a plurality of columns included in the transformed codeword using a first sequential decoder based on a second code. In an embodiment, this may correspond to one or more operations of process 1330 applied from a row perspective.

[0295] In an embodiment, process 1510 may further include: decoding one or more rows of a plurality of rows included in the transposed codeword using a second sequential decoder based on a first code; transforming each row of the plurality of rows to obtain a transformed transposed codeword; and decoding one or more columns of a plurality of columns included in the transformed transposed codeword using a second sequential decoder based on a second code. In an embodiment, this may correspond to one or more operations of process 1330 applied from a column perspective.

[0296] In an embodiment, at least one of the sequential decoder, the first sequential decoder, and the second sequential decoder may include a SIHO decoder or a SISO decoder.

[0297] Figure 15B This is a flowchart of a process for controlling a storage system according to an embodiment. According to an embodiment, process 1520 may use one or more of the elements described above (e.g., those mentioned above regarding…). Figure 2A The storage device discussed 200, and the above regarding... Figure 2B The ECC encoding circuit 510 discussed above, and the above regarding... Figure 8 The ECC encoder module 822 discussed above, and the above regarding... Figure 13A The discussion of sequential decoder 1310, and the above regarding... Figures 14A to 14B The iterative decoders 1410 and 1420 (or any other components) discussed are used to perform this.

[0298] like Figure 15B As shown, at operation 1521, process 1520 may include obtaining a codeword from a plurality of codewords stored in a storage device included in the storage system. In an embodiment, the codeword may include a plurality of rows and a plurality of columns.

[0299] like Figure 15B Further, at operation 1522, process 1520 may include generating a codeword for a first transformation by transforming each of the plurality of rows. In an embodiment, the codeword for the first transformation may include a plurality of rows of the first transformation and a plurality of columns of the first transformation. In an embodiment, the codeword for the first transformation may correspond to... Figure 12A The row coset shown.

[0300] like Figure 15B Further, at operation 1523, process 1520 may include generating a codeword for a second transformation by transforming each of a plurality of columns. In an embodiment, the codeword for the second transformation may include a plurality of rows and a plurality of columns of the second transformation. In an embodiment, the codeword for the second transformation may correspond to... Figure 12B The column coset shown.

[0301] like Figure 15BAs further shown, at operation 1524, process 1520 may include decoding the codeword by performing iterative decoding on the codeword of the first transformation and the codeword of the second transformation to obtain the information bits corresponding to the codeword.

[0302] In an embodiment, iterative decoding may include: performing a first decoding operation on one or more rows of a plurality of rows, and updating the codeword of a first transform based on the result of the first decoding operation; and performing a second decoding operation on one or more columns of a plurality of first transforms.

[0303] In an embodiment, iterative decoding may further include: performing a third decoding operation on one or more columns of a plurality of columns, and updating the codeword of the second transform based on the result of the third decoding operation; and performing a fourth decoding operation on one or more rows of a plurality of rows of the second transform.

[0304] In an embodiment, the codeword may be encoded based on 2D-GCC codes (which may be based on BCH codes and GRS codes).

[0305] In an embodiment, multiple rows may correspond to multiple first BCH codewords, and multiple columns may correspond to multiple second BCH codewords. Multiple columns of the first transform may correspond to multiple first GRS codewords, and multiple rows of the second transform may correspond to multiple second GRS codewords. The multiple first GRS codewords may be used to compute a first plurality of checksums, and the multiple second GRS codewords may be used to compute a second plurality of checksums. In an embodiment, this may correspond to... Figure 12C The layout shown.

[0306] Figure 16 An example code structure of a 2D-GCC S-BCH code according to an embodiment is shown. Figure 16 The code structure shown can be used to illustrate the example 2D-GCC decoding process discussed below.

[0307] In an embodiment, Figure 16 The 2D-GCC S-BCH code structure shown can have row codes, which can be defined as follows: ,in The equivalent column key can be defined as... ,in .

[0308] Based on the 2D-GCC S-BCH decoding example, the binary input vector according to the following Equation 51 can be provided to Figure 14A The iterative decoder 1410 is shown.

[0309] (Equation 51)

[0310] In equation 51, This can indicate an error corresponding to the 2D-GCC S-BCH decoding example. Error matrix. At the beginning of the 2D-GCC S-BCH decoding example, the matrix... It can be expressed according to the following equation 52.

[0311] (Equation 52)

[0312] BCH decoding status from a line perspective RS decoding status from a row perspective BCH decoding status from a column perspective And RS decoding status from a column perspective Initialization can be performed according to the following equations 53 to 56:

[0313] (Equation 53)

[0314] (Equation 54)

[0315] (Equation 55)

[0316] (Equation 56)

[0317] Transformation space symbols from a row perspective Transformation space symbols from the perspective of columns The initialization can be performed according to the following equations 57 and 58:

[0318] (Equation 57)

[0319] (Equation 58)

[0320] The iterative decoder 1410 can begin the 2D-GCC S-BCH decoding process at iteration 0, which can be a row-type iteration. This can be a degenerate iteration because... .

[0321] exist At that time, the BCH decoder included in the sequential decoder 1310A is degenerate and all operations succeed. Therefore, and .

[0322] exist At that time, the BCH decoder included in the sequential decoder 1310A can be used as... And applied to line ,in Lines 1, 2, and 3 can be successfully decoded because they contain an error. As a result, for : and .

[0323] exist At that time, the RS decoder included in the sequential decoder 1310A may fail because there are four erases and .

[0324] Therefore, the resulting error matrix This can be expressed according to the following equation 59:

[0325] (Equation 59)

[0326] In equations 59 and below, the symbol " "Used to indicate rows and columns that have been successfully decoded. The iterative decoder 1410 can then proceed to iteration 1, which can be a column-type iteration. This can be a degenerate iteration because..." .exist At that time, all BCH decoders included in the sequential decoder 1310B succeeded. As a result, .

[0327] exist At that time, the BCH decoder included in the sequential decoder 1310B can be used as... And applied to columns ,in Columns 5 and 7 can be successfully decoded because they contain one error and zero errors, respectively. As a result, for and :

[0328] exist At that time, the RS decoder included in the sequential decoder 1310B may fail because there are five erases and .

[0329] Therefore, the resulting error matrix This can be expressed according to the following equation 60:

[0330] (Equation 60)

[0331] Then, the iterative decoder 1410 can continue to iteration 2, which can be a row-type iteration. At that time, the BCH decoder included in the sequential decoder 1310A can be used as... And applied to line ,in Line 4 can be successfully decoded because it contains an error. As a result, and .

[0332] Therefore, the resulting error matrix This can be expressed according to the following equation 61:

[0333] (Equation 61)

[0334] exist At that time, the BS decoder included in the sequential decoder 1310A can be used as And thus applied. Note. .because The RS decoder included in the sequential decoder 1310A can successfully and , It can be reproduced (and there is no) (Changes in the middle).

[0335] The BCH decoder included in the sequential decoder 1310A can be used as And applied to line ,in Line 7 can be successfully decoded because it contains two errors. As a result, and .

[0336] Therefore, the resulting error matrix This can be expressed according to the following equation 62:

[0337] (Equation 62)

[0338] exist At that time, the BS decoder included in the sequential decoder 1310A can be used as And thus applied. Note. .because The RS decoder included in the sequential decoder 1310A can successfully and , It can be reproduced (and there is no) (Changes in the middle).

[0339] The BCH decoder included in the sequential decoder 1310A BCH decoder can be used as... And applied to line ,in BCH decoding may fail because the number of errors may be greater than 3.

[0340] Then, the iterative decoder 1410 can continue to iteration 3, which can be a column-type iteration.

[0341] exist At that time, the BCH decoder included in the sequential decoder 1310B can be used as... And applied to columns ,in Columns 4 and 6 were successfully decoded. As a result, and .

[0342] Therefore, the resulting error matrix This can be expressed according to the following equation 63:

[0343] (Equation 63)

[0344] exist At that time, the BS decoder included in the sequential decoder 1310B can be used as... And thus applied. Note. .

[0345] because The RS decoder can succeed and , It can be reproduced (and there is no) (Changes in the middle).

[0346] The BCH decoder included in the sequential decoder 1310B can be used as And applied to columns ,in BCH decoding may work for all columns. All were successful because each column had two errors. Therefore, for This can indicate that the BCH decoder included in the sequential decoder 1310B is successful.

[0347] Therefore, the resulting error matrix It can be blank (clean), as shown in Equation 64 below, and the iterative decoder 1410 can successfully complete 2D-GCC S-BCH decoding.

[0348] (Equation 64)

[0349] Figure 17 This is a diagram of a data center 3000 using an application storage device according to an embodiment.

[0350] refer to Figure 17Data center 3000 can be a facility that collects various types of data and provides services, and can be referred to as a data storage center. Data center 3000 can be a system for operating search engines and databases, and can be a computing system used by companies such as banks or government agencies. Data center 3000 can include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m can be selected differently depending on the embodiment. The number of application servers 3100 to 3100n can differ from the number of storage servers 3200 to 3200m.

[0351] Application server 3100 or storage server 3200 may include at least one of processors 3110 and 3210 and memories 3120 and 3220. Storage server 3200 will now be described as an example. Processor 3210 may control all operations of storage server 3200, access memory 3220, and execute instructions and / or data loaded in memory 3220. Memory 3220 may be Double Data Rate Synchronous DRAM (DDRSDRAM), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), Dual In-line Memory Module (DIMM), Optane DIMM, and / or Non-Volatile DIMM (NVMDIMM). In some embodiments, the number of processors 3210 and memory 3220 included in storage server 3200 may be selected differently. In embodiments, processors 3210 and memory 3220 may provide processor-memory pairs. In embodiments, the number of processors 3210 may differ from the number of memories 3220. Processor 3210 may include a single-core processor or a multi-core processor. The above description of storage server 3200 can be similarly applied to application server 3100. In some embodiments, application server 3100 may not include storage device 3150. Storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 included in storage server 3200 may be selected differently depending on the embodiment.

[0352] Application servers 3100 to 3100n can communicate with storage servers 3200 to 3200m via network 3300. Network 3300 can be implemented using Fibre Channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission and uses optical switches with high performance and high availability. Storage servers 3200 to 3200m can be provided as file storage devices, block storage devices, or object storage devices depending on the access method of network 3300.

[0353] In this embodiment, network 3300 can be a storage-specific network, such as a storage area network (SAN). For example, the SAN can be an FC-SAN, which uses an FC network and is implemented according to the FC protocol (FCP). As another example, the SAN can be an Internet Protocol (IP)-SAN, which uses a Transmission Control Protocol (TCP / IP) network and is implemented according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocol. In another embodiment, network 3300 can be a general-purpose network, such as a TCP / IP network. For example, network 3300 can be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

[0354] The following text will primarily describe application server 3100 and storage server 3200. The description of application server 3100 can be applied to another application server 3100n, and the description of storage server 3200 can be applied to another storage server 3200m.

[0355] Application server 3100 can store data requested by users or clients to one of storage servers 3200 to 3200m via network 3300. Furthermore, application server 3100 can obtain data requested by users or clients from one of storage servers 3200 to 3200m via network 3300. For example, application server 3100 can be implemented as a web server or a database management system (DBMS).

[0356] Application server 3100 can access memory 3120n or storage device 3150n included in another application server 3100n via network 3300. Alternatively, application server 3100 can access memory 3220 to 3220m or storage device 3250 to 3250m included in storage servers 3200 to 3200m via network 3300. Therefore, application server 3100 can perform various operations on data stored in application servers 3100 to 3100n and / or storage servers 3200 to 3200m. For example, application server 3100 can execute instructions for moving or copying data between application servers 3100 to 3100n and / or storage servers 3200 to 3200m. In this scenario, data can be moved directly from storage devices 3250 to 3250m of storage servers 3200 to 3200m to storage devices 3220 to 3220m of application servers 3100 to 3100n, or directly from storage devices 3250 to 3250m of storage servers 3200 to 3200m to storage devices 3220 to 3220m of application servers 3120 to 3120n. Data moved over network 3300 may be encrypted for security or privacy reasons.

[0357] The description will now use storage server 3200 as an example. Interface 3254 can provide physical connectivity between processor 3210 and controller 3251, as well as physical connectivity between network interface card (NIC) 3240 and controller 3251. For example, interface 3254 can be implemented using a direct-attached storage (DAS) scheme in which storage device 3250 is directly connected to a dedicated cable. For example, interface 3254 can be implemented using various interface schemes such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and / or CF card interface.

[0358] Storage server 3200 may also include switch 3230 and NIC (Network Interconnect) 3240. Switch 3230 may selectively connect processor 3210 to storage device 3250 or selectively connect NIC 3240 to storage device 3250 via control of processor 3210.

[0359] In an embodiment, NIC 3240 may include a network interface card and a network adapter. NIC 3240 can be connected to network 3300 via a wired interface, wireless interface, Bluetooth interface, or fiber optic interface. NIC 3240 may include internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to processor 3210 and / or switch 3230 via the host bus interface. The host bus interface may be implemented as one of the examples of interface 3254 described above. In an embodiment, NIC 3240 may be integrated with at least one of processor 3210, switch 3230, and storage device 3250.

[0360] In storage servers 3200 to 3200m or application servers 3100 to 3100n, the processor can send commands to storage devices 3150 to 3150n and 3250 to 3250m or memories 3120 to 3120n and 3220 to 3220m and program or read data. In this case, the data may be data whose errors are corrected by the ECC engine. The data may be data to which a bus inversion (DBI) operation or a data masking (DM) operation has been performed, and may include cyclic redundancy check (CRC) information. The data may be encrypted for security or privacy reasons.

[0361] Storage devices 3150 to 3150n and 3250 to 3250m can send control signals and command / address signals to NAND flash memory devices 3252 to 3252m in response to read commands received from the processor. Therefore, when reading data from NAND flash memory devices 3252 to 3252m, a read enable (RE) signal can be input as a data output control signal, and thus data can be output to the DQ bus. The RE signal can be used to generate the data strobe signal DQS. Command and address signals can be latched into the page buffer depending on the rising or falling edge of the write enable (WE) signal.

[0362] Controller 3251 can control all operations of storage device 3250. In an embodiment, controller 3251 may include SRAM. Controller 3251 can write data to NAND flash memory device 3252 in response to a write command, or read data from NAND flash memory device 3252 in response to a read command. For example, write and / or read commands may be provided from processor 3210 of storage server 3200, processor 3210m of another storage server 3200m, or processors 3110 and 3110n of application servers 3100 and 3100n. DRAM 3253 may temporarily store (or buffer) data to be written to or read from NAND flash memory device 3252. In addition, DRAM 3253 may store metadata. Here, metadata may be user data or data generated by controller 3251 for managing NAND flash memory device 3252. Storage device 3250 may include a security element (SE) for security or privacy purposes.

[0363] As is customary in the art, embodiments are described and illustrated in the accompanying drawings according to functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., formed using semiconductor-based manufacturing techniques or other manufacturing processes. Where blocks, units, and / or modules are implemented by microprocessors, etc., they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware or implemented as a combination of dedicated hardware for performing certain functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, each block, unit, and / or module of the embodiments can be physically separated into two or more interactive and discrete blocks, units, and / or modules without departing from the scope of this invention. Furthermore, each block, unit, and / or module of the embodiments can be physically combined into more complex blocks, units, and / or modules without departing from the scope of this invention.

[0364] The various operations described above can be performed by any suitable component capable of performing the operations, such as various hardware and / or software components, circuits and / or modules.

[0365] Software may include an ordered list of executable instructions for implementing logical functions and may be embodied in any processor-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a single-core or multi-core processor or a system containing a processor.

[0366] The blocks or steps of methods, algorithms, and functions described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. If implemented in software, the functions may be stored as one or more instructions or code on or transmitted through a tangible, non-transitory computer-readable medium. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0367] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to these embodiments without substantially departing from the scope thereof.

Claims

1. A storage system comprising: a storage device configured to store a plurality of codewords; a sequential decoder; and at least one processor configured to: obtain, from the storage device, a two-dimensional (2D)-generalized concatenated (GCC) codeword; provide the codeword to the sequential decoder; based on detecting a first failure of the sequential decoder, update the codeword and transpose the updated codeword to obtain a transposed codeword; provide the transposed codeword to the sequential decoder; and based on a result obtained by the sequential decoder, obtain information bits corresponding to the codeword. the 2D-GCC codeword is encoded based on a 2D-GCC code, and wherein the 2D-GCC code comprises a Bose-Chaudhuri-Hocquenghem (BCH) code and a generalized Reed-Solomon (GRS) code.

2. The storage system of claim 1, wherein, a first GRS syndrome generated by the sequential decoder based on the codeword is equal to a second GRS syndrome generated by the sequential decoder based on the transposed codeword. the sequential decoder comprises a first sequential decoder and a second sequential decoder, and 3. The storage system of claim 2, wherein, wherein, to decode the codeword, the first sequential decoder is configured to:

4. The storage system of claim 1, wherein, decode one or more rows of a plurality of rows included in the codeword based on a first code; transform each row of the plurality of rows included in the codeword to obtain a transformed codeword; and decode one or more columns of a plurality of columns included in the transformed codeword based on a second code. the sequential decoder comprises a first sequential decoder and a second sequential decoder, and wherein, to decode the transposed codeword, the second sequential decoder is configured to:

5. The storage system of claim 1, wherein, decode one or more rows of a plurality of rows included in the transposed codeword based on a first code; transform each row of the plurality of rows to obtain a transformed transposed codeword; and decode one or more columns of a plurality of columns included in the transformed transposed codeword based on a second code. the at least one processor is further configured to: based on detecting a second failure of the sequential decoder, update the transposed codeword and transpose the updated transposed codeword to obtain a re-transposed codeword; 6. The storage system of claim 1, wherein, provide the re-transposed codeword to the sequential decoder; and based on a new result obtained by the sequential decoder, obtain the information bits.

7. The storage system of claim 1, wherein the sequential decoder comprises a soft-input hard-output (SIHO) decoder.

8. The storage system of claim 1, wherein the sequential decoder comprises a soft-input soft-output (SISO) decoder.

9. An apparatus for managing data stored in a storage device, the apparatus comprising: a memory interface configured to communicate with the storage device; and at least one processor configured to: obtain, from a plurality of codewords stored in the storage device, a codeword, wherein the codeword comprises a plurality of rows and a plurality of columns; ​ ​ ​ generating a first transformed codeword by transforming each row of the plurality of rows, wherein the first transformed codeword comprises a plurality of first transformed rows and a plurality of first transformed columns, generating a second transformed codeword by transforming each column of the plurality of columns, wherein the second transformed codeword comprises a plurality of second transformed rows and a plurality of second transformed columns, and decoding the codeword to obtain information bits corresponding to the codeword by performing iterative decoding based on the first transformed codeword and the second transformed codeword, wherein a first plurality of syndromes calculated based on the plurality of first transformed columns is equal to a second plurality of syndromes calculated based on the plurality of second transformed rows after the codeword is decoded.

10. The apparatus of claim 9, wherein, To perform the iterative decoding, the at least one processor is further configured to: perform a first decoding operation on one or more rows of the plurality of rows and update the first transformed codeword based on a result of the first decoding operation; and perform a second decoding operation on one or more first transformed columns of the plurality of first transformed columns.

11. The apparatus of claim 10, wherein, To perform the iterative decoding, the at least one processor is further configured to: perform a third decoding operation on one or more columns of the plurality of columns and update the second transformed codeword based on a result of the third decoding operation; and perform a fourth decoding operation on one or more second transformed rows of the plurality of second transformed rows.

12. The apparatus of claim 9, wherein, the codeword is encoded based on a two-dimensional (2D) generalized concatenated code (GCC) code, and wherein the 2D-GCC code comprises a Bose-Chaudhuri-Hocquenghem (BCH) code and a generalized Reed-Solomon (GRS) code.

13. The apparatus of claim 12, wherein, the plurality of rows correspond to a plurality of first BCH codewords, and wherein the plurality of columns correspond to a plurality of second BCH codewords.

14. The apparatus of claim 13, wherein, the plurality of first transformed columns correspond to a plurality of first GRS codewords, and wherein the plurality of second transformed rows correspond to a plurality of second GRS codewords.

15. The apparatus of claim 14, wherein, the plurality of first GRS codewords are used to calculate the first plurality of syndromes, and wherein the plurality of second GRS codewords are used to calculate the second plurality of syndromes.

16. A method of managing data stored in a storage device, the method comprising: obtaining a two-dimensional (2D) generalized concatenated code (GCC) codeword from the storage device; providing the codeword to a sequential decoder; based on detecting a first time of failure of the sequential decoder, updating the codeword and transposing the updated codeword to obtain a transposed codeword; providing the transposed codeword to the sequential decoder; based on a result obtained by the sequential decoder, obtaining information bits corresponding to the codeword. the 2D-GCC codeword is encoded based on a 2D-GCC code, and 17. The method of claim 16, wherein, wherein the 2D-GCC code comprises a Bose-Chaudhuri-Hocquenghem (BCH) code and a generalized Reed-Solomon (GRS) code. ​ 18. The method of claim 17, wherein, a first GRS syndrome generated by the sequential decoder based on the codeword is equal to a second GRS syndrome generated by the sequential decoder based on the transposed codeword.

19. The method of claim 16, wherein, the sequential decoder comprises a first sequential decoder and a second sequential decoder, and wherein the method further comprises: decoding, using the first sequential decoder, one or more rows of a plurality of rows included in the codeword based on a first code; transposing each row of the plurality of rows included in the codeword to obtain a transposed codeword; and decoding, using the first sequential decoder, one or more columns of a plurality of columns included in the transposed codeword based on a second code.

20. The method of claim 16, further comprising: based on detecting a second failure of the sequential decoder, updating the transposed codeword and transposing the updated transposed codeword to obtain a re-transposed codeword; providing the re-transposed codeword to the sequential decoder; and based on a new result obtained by the sequential decoder, decoding the codeword. ​

Images