Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, and the method comprises the steps: firstly executing a thermal oxidation technology, so as to form a buried oxide layer on a device sheet; and then, performing an ion implantation process on the device wafer from the surface of the buried oxide layer so as to form an ion implantation layer in the device wafer, and when the ion implantation process is performed, adjusting the total implantation dose of implanted ions according to the temperature of the thermal oxidation process. Therefore, the total injection dose of the injected ions can be correspondingly reduced or increased according to the temperature of the thermal oxidation process, so that nucleation and growth of defects in the device chip are reduced, and the number of the defects in the device chip is further reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] In the current preparation process of semiconductor devices, a buried oxide (BOX) layer is introduced between a silicon substrate and a device layer to effectively build an electrical isolation barrier. This structure can reduce parasitic capacitance, improve device switching speed, reduce leakage current, significantly optimize power consumption performance, and enhance radiation resistance. In the current preparation process of semiconductor devices, after the silicon substrate and the device layer are bonded, the device wafer forming the device layer needs to be peeled off. The main principle is to cause cross-section damage by ion implantation and then achieve layer peeling by thermal process. The quality of the device layer is the key to performance in the subsequent processing process. Poor device layer quality can cause problems such as lithography overlay failure, threshold voltage increase, and leakage current, thereby affecting device processing and performance. However, the current device wafer has a large number of defects, which affects the quality of the device layer. SUMMARY

[0003] The present application aims to provide a semiconductor device and a preparation method thereof to reduce the number of defects in the device wafer.

[0004] To achieve the above-mentioned purpose, the present application provides a preparation method of a semiconductor device, comprising:

[0005] providing a device wafer;

[0006] performing a thermal oxidation process to form a buried oxide layer on the device wafer;

[0007] performing an ion implantation process on the device wafer from the surface of the buried oxide layer to form an ion implantation layer in the device wafer, wherein when the ion implantation process is performed, the total implantation dose of the implanted ions is adjusted according to the temperature of the thermal oxidation process.

[0008] Optionally, in the preparation method of the semiconductor device, when the temperature of the thermal oxidation process is greater than or equal to 800℃ and less than 1000℃, the total implantation dose of the implanted ions has the following relationship with the temperature of the thermal oxidation process:

[0009] 10E15≤Y1≤(-0.2*X1+220)E15;

[0010] wherein Y1 represents the total implantation dose of the implanted ions, with the unit of atom / cm 2 , and X1 represents the temperature of the thermal oxidation process.

[0011] Optionally, in the method for manufacturing the semiconductor device, when the temperature of the thermal oxidation process is greater than or equal to 1000℃ and less than or equal to 1100℃, the total implantation dose of the implanted ions has the following relationship with the temperature of the thermal oxidation process:

[0012] 10E15≤Y1≤(-0.05*X1+70)E15;

[0013] wherein Y1 represents the total implantation dose of the implanted ions, in atom / cm 2 , and X1 represents the temperature of the thermal oxidation process.

[0014] Optionally, in the method for manufacturing the semiconductor device, the implanted ions used in the ion implantation process include hydrogen ions and helium ions, and the implantation dose of the hydrogen ions and the implantation dose of the helium ions are adjusted according to the temperature of the thermal oxidation process to adjust the total implantation dose of the implanted ions when the ion implantation process is performed.

[0015] Optionally, in the method for manufacturing the semiconductor device, the gas of the thermal oxidation process includes oxygen, and the gas flow of the oxygen is 1slm-10slm.

[0016] Optionally, in the method for manufacturing the semiconductor device, the gas of the thermal oxidation process further includes hydrogen, and the gas flow of the hydrogen is 0slm-20slm.

[0017] Optionally, in the method for manufacturing the semiconductor device, after the ion implantation process is performed, the method for manufacturing the semiconductor device further includes:

[0018] providing a support wafer;

[0019] bonding the support wafer with the device wafer, and the buried oxide layer is located between the device wafer and the support wafer;

[0020] performing a peeling process to peel off a partial thickness of the device wafer from the position of the ion implantation layer, so that the remaining device wafer, the buried oxide layer and the support wafer form a bonded wafer;

[0021] performing a thinning process to thin the thickness of the device wafer in the bonded wafer.

[0022] Optionally, in the method for manufacturing the semiconductor device, the thickness of the buried oxide layer is 0.01μm-1μm.

[0023] Based on the same inventive concept, the application also provides a semiconductor device including a support wafer, a device wafer and a buried oxide layer.

[0024] The device sheet is a device sheet formed by the method for manufacturing a semiconductor device, and is a remaining part after being peeled along the ion implantation layer;

[0025] The buried oxygen layer is located between the device sheet and the support sheet, and the buried oxygen layer, the device sheet and the support sheet are bonded as a whole.

[0026] Optionally, in the semiconductor device, the yield of the semiconductor device is greater than or equal to 80%.

[0027] In the method for manufacturing a semiconductor device, a thermal oxidation process is performed first to form a buried oxygen layer on a device sheet; then, an ion implantation process is performed on the device sheet from the surface of the buried oxygen layer to form an ion implantation layer in the device sheet, wherein when the ion implantation process is performed, the total implantation dose of the implanted ions is adjusted according to the temperature of the thermal oxidation process. In this way, the total implantation dose of the implanted ions can be reduced or increased according to the temperature of the thermal oxidation process, thereby reducing the nucleation and growth of defects in the device sheet, and further reducing the number of defects in the device sheet.

[0028] In the semiconductor device, the semiconductor device includes a support sheet, a device sheet and a buried oxygen layer; the device sheet is a device sheet formed by the method for manufacturing a semiconductor device, and is a remaining part after being peeled along the ion implantation layer; the buried oxygen layer is located between the device sheet and the support sheet, and the buried oxygen layer, the device sheet and the support sheet are bonded as a whole. In this way, the yield of the semiconductor device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0030] Figures 2 to 5 is a structural diagram formed in the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0031] Figure 6 and Figure 7 is a surface diagram of the device sheet in the first embodiment of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0032] Figure 8 and Figure 9 is a surface diagram of the device sheet in the first embodiment of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0033] Figure 10 and Figure 11 is a surface diagram of the device sheet in the second embodiment of the method for manufacturing a semiconductor device according to an embodiment of the present application;

[0034] Figure 12 and Figure 13is a surface schematic diagram of a device wafer in Embodiment Three of the preparation method of the semiconductor device of the present application;

[0035] Figure 14 and Figure 15 is a surface schematic diagram of a device wafer in Embodiment Four of the preparation method of the semiconductor device of the present application;

[0036] In the drawings, the reference signs are explained as follows:

[0037] 101 - device wafer; 102 - buried oxide layer; 103 - ion implantation layer; 104 - support wafer. DETAILED DESCRIPTION

[0038] The semiconductor device and the preparation method thereof proposed by the present application will be further described in detail below in combination with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are all in a very simplified form and all use non-precise proportions, only for the purpose of facilitating and clarifying the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing needs to be different, and sometimes different proportions are used.

[0039] Figure 1 is a flowchart of the preparation method of the semiconductor device provided by the present application. As shown in Figure 1 , the preparation method of the semiconductor device provided by the present application comprises:

[0040] Step S1: providing a device wafer;

[0041] Step S2: performing a thermal oxidation process to form a buried oxide layer on the device wafer;

[0042] Step S3: performing an ion implantation process on the device wafer from the surface of the buried oxide layer to form an ion implantation layer in the device wafer, wherein when the ion implantation process is performed, the total implantation dose of the implanted ions is adjusted according to the temperature of the thermal oxidation process.

[0043] Figures 2 to 5 is a structure schematic diagram formed in the preparation method of the semiconductor device of the present application; the preparation method of the semiconductor device provided by the present embodiment will be described in more detail below in combination with the drawings. Figures 2 to 5

[0044] First, as shown in Figure 2 , Step S1 is performed to provide a device wafer 101, and the material of the device wafer 101 can be silicon. In other specific embodiments, the material of the device wafer 101 can also be germanium silicon, germanium or compound semiconductor, etc.

[0045] ​Specifically, the method for forming the device includes: forming a silicon ingot using the Czochralski method, with the crystal growth direction being... <100> or <110> or <111> Then, the silicon ingot is edge-rolled to the target diameter. Afterwards, it undergoes slicing, dicing, grinding, polishing, and cleaning processes to form device wafer 101. The thickness of device wafer 101 can be 500 μm to 800 μm.

[0046] Next, a thermal oxidation process is performed to form a buried oxide layer 102 on the device wafer 101. The thickness of the buried oxide layer 102 can be 0.1 μm to 4 μm.

[0047] In some embodiments, the temperature of the thermal oxidation process is greater than or equal to 800°C and less than 1000°C. For example, the temperature of the thermal oxidation process can be 850°C, 900°C, or 950°C. Since the temperature of the thermal oxidation process is less than 1000°C, the stress rate development during the thermal oxidation process is slower, and the atomic diffusion rate in the device wafer 101 is low, limiting defect migration. This results in a smaller and more evenly distributed increase in oxidation-induced stress per unit time, reducing or avoiding defect nucleation caused by stress concentration exceeding the critical value. Therefore, the increase in defect size in the device wafer 101 can be controlled, and stress defect nucleation and growth caused by defect size can be reduced.

[0048] In some embodiments, the temperature of the thermal oxidation process is greater than or equal to 1000°C and less than or equal to 1100°C. For example, the temperature of the thermal oxidation process can be 1050°C.

[0049] In this embodiment, when performing the thermal oxidation process, the gas used in the thermal oxidation process includes oxygen, and the flow rate of the oxygen is 1 slm to 10 slm.

[0050] In addition, the gas used in the thermal oxidation process may also include hydrogen, with a flow rate of 0 slm to 20 slm.

[0051] Next, as Figure 3 As shown, in step S3, an ion implantation process is performed on the device wafer 101 from the surface of the buried oxide layer 102 to form an ion implantation layer 103 in the device wafer 101. During the ion implantation process, the total implantation dose of the implanted ions is adjusted according to the temperature of the thermal oxidation process. Thus, the total implantation dose of the implanted ions can be reduced or increased accordingly based on the temperature of the thermal oxidation process, thereby reducing the nucleation and growth of defects in the device wafer 101, and consequently reducing the number of defects in the device wafer 101.

[0052] In some embodiments, when the temperature of the thermal oxidation process is greater than or equal to 800°C and less than 1000°C, the total implantation dose of the implanted ions has a relationship with the temperature of the thermal oxidation process as follows:

[0053] 10E15≤Y1≤(-0.2*X1+220)E15;

[0054] wherein Y1 represents the total implantation dose of the implanted ions, in atom / cm 2 and X1 represents the temperature of the thermal oxidation process, and 800°C≤X1<1000°C.

[0055] That is, when the buried oxide layer 102 is formed by using a low-temperature thermal oxidation process (greater than or equal to 800°C and less than 1000°C), a high-dose ion implantation is used in the ion implantation process. Since the buried oxide layer 102 grows fast but has low density when oxidized at low temperature, the residual thermal expansion stress in the device wafer 101 can be compensated by high-dose ion implantation, so that the defect diffusion is limited, and the subsequent heat treatment repair is facilitated.

[0056] In some embodiments, when the temperature of the thermal oxidation process is greater than or equal to 1000°C and less than or equal to 1100°C, the total implantation dose of the implanted ions has a relationship with the temperature of the thermal oxidation process as follows:

[0057] 10E15≤Y1≤(-0.05*X1+70)E15;

[0058] wherein Y1 represents the total implantation dose of the implanted ions, in atom / cm 2 and X1 represents the temperature of the thermal oxidation process, and 1000°C≤X1≤1100°C.

[0059] That is, when the buried oxide layer is formed by using a high-temperature thermal oxidation process (greater than or equal to 1000°C and less than or equal to 1100°C), the buried oxide layer has good density, and the stress in the device wafer 101 can be quickly released. Therefore, when the ion implantation is performed, a low-dose ion implantation is used to reduce defect overlap, which is beneficial to ensure the lattice integrity, thereby controlling the defects in the device wafer 101, reducing the defect nucleation and growth in the device wafer 101, and improving the yield of the subsequently formed bonded wafer.

[0060] In this embodiment, the implanted ions used in the ion implantation process include hydrogen ions and helium ions. When the ion implantation process is performed, the hydrogen ions can be implanted first and then the helium ions are implanted, or the helium ions can be implanted first and then the hydrogen ions are implanted.

[0061] During the ion implantation process, the implantation dose of hydrogen ions and the implantation dose of helium ions are adjusted according to the temperature of the thermal oxidation process to adjust the total implantation dose of the implanted ions. That is, during the ion implantation process, the total implantation dose of the implanted ions is the sum of the implantation dose of hydrogen ions and the implantation dose of helium ions (the sum of the implantation dose of hydrogen ions and the implantation dose of helium ions is the total implantation dose Y1 in the above relationship).

[0062] In some embodiments, the implantation dose of hydrogen ions and the implantation dose of helium ions may be equal when performing the ion implantation process. In some embodiments, the implantation dose of hydrogen ions and the implantation dose of helium ions may not be equal when performing the ion implantation process; for example, the implantation dose of hydrogen ions may be greater than the implantation dose of helium ions, or the implantation dose of hydrogen ions may be less than the implantation dose of helium ions.

[0063] In this embodiment, after performing the ion implantation process, the method for fabricating the semiconductor device further includes: as follows: Figure 4 As shown, a support sheet 104 is provided; the support sheet 104 is bonded to the device sheet 101, and the buried oxide layer 102 is located between the device sheet 101 and the support sheet 104.

[0064] Next, as Figure 5 As shown, a stripping process is performed to peel off a portion of the thickness of the device wafer 101 from the location of the ion implantation layer 103, so that the remaining device wafer 101, the buried oxide layer 102, and the support sheet 104 form a bonding wafer; then, a thinning process is performed to reduce the thickness of the device wafer 101 in the bonding wafer.

[0065] The following five embodiments further illustrate the fabrication method of the semiconductor device provided in this embodiment.

[0066] Table 1 Comparison of the five embodiments

[0067]

[0068] As shown in Table 1, in the above five embodiments, the silicon ingot first grown by the Czochralski method has the following crystal growth direction: <100> The ingot is edge-rolled to the target diameter and cut into segments, with the notch direction being... <110> Then, the crystal segment is sliced ​​and then ground, polished and cleaned in sequence to obtain a silicon wafer as a device wafer; another crystal segment is provided and then ground, polished and cleaned in sequence to obtain a final silicon wafer as a support wafer.

[0069] In Embodiment One, the thickness of the device sheet is 778 μm; a thermal oxidation process is performed on the device sheet to form a buried oxide layer on the device sheet, the oxidation temperature of the thermal oxidation process is 1000 °C, the gas flow of oxygen in the thermal oxidation process is 4 slm, the gas flow of hydrogen is 6 slm, and the thickness of the buried oxide layer is 180 nm; an ion implantation process is performed on the device sheet from the surface of the buried oxide layer to form an ion implantation layer in the device sheet, and the total implantation dose of hydrogen ions and helium ions (the sum of the implantation dose of hydrogen ions and the implantation dose of helium ions) is 2E16 atom / cm 2 A support sheet is provided, the thickness of the support sheet is 781 μm, the device sheet and the support sheet are bonded, and the buried oxide layer is located between the device sheet and the support sheet; then, a reinforcement heat treatment and a peeling treatment are sequentially performed, a partial thickness of the device sheet is peeled off from the position of the ion implantation layer, and a thinning process is performed to obtain the required thickness of the device sheet, and the thickness of the device sheet after the thinning process is 100 nm.

[0070] Then, as shown in Figure 6 and Figure 7 , the quality of the device sheet (or device layer) in the bonded wafer is observed by a scanning electron microscope and a surface particle detector, the number of device sheet surface particles is 31, and the yield is 95.6%.

[0071] In Embodiment Two, the thickness of the device sheet is 777 μm; a thermal oxidation process is performed on the device sheet to form a buried oxide layer on the device sheet, the oxidation temperature of the thermal oxidation process is 800 °C, the gas flow of oxygen in the thermal oxidation process is 4 slm, the gas flow of hydrogen is 6 slm, and the thickness of the buried oxide layer is 196 nm; an ion implantation process is performed on the device sheet from the surface of the buried oxide layer to form an ion implantation layer in the device sheet, and the total implantation dose of hydrogen ions and helium ions is 6E16 atom / cm 2 A support sheet is provided, the thickness of the support sheet is 780 μm, the device sheet and the support sheet are bonded, and the buried oxide layer is located between the device sheet and the support sheet; then, a reinforcement heat treatment and a peeling treatment are sequentially performed, a partial thickness of the device sheet is peeled off from the position of the ion implantation layer, and a thinning process is performed to obtain the required thickness of the device sheet, and the thickness of the device sheet after the thinning process is 101 nm.

[0072] Then, as shown in Figure 8 and Figure 9 , the quality of the device sheet (or device layer) in the bonded wafer is observed by a scanning electron microscope and a surface particle detector, the number of device sheet surface particles is 148, and the yield is 85.1%.

[0073] In Example Three, the thickness of the device sheet is 776 μm; a thermal oxidation process is performed on the device sheet to form a buried oxide layer on the device sheet, the oxidation temperature of the thermal oxidation process is 1000 °C, the gas flow of oxygen in the thermal oxidation process is 4 slm, the gas flow of hydrogen is 6 slm, and the thickness of the buried oxide layer is 194 nm; an ion implantation process is performed on the device sheet from the surface of the buried oxide layer to form an ion implantation layer in the device sheet, and the total implantation dose of hydrogen ions and helium ions is 2.15E16 atom / cm 2 A support sheet is provided, the thickness of the support sheet is 779 μm, the device sheet and the support sheet are bonded, and the buried oxide layer is located between the device sheet and the support sheet; then, a reinforcement heat treatment and a peeling treatment are sequentially performed, a partial thickness of the device sheet is peeled off from the position of the ion implantation layer, and a thinning process is performed to obtain the required thickness of the device sheet, and the thickness of the device sheet after the thinning process is 98 nm.

[0074] Then, as shown in Figure 10 and Figure 11 , the quality of the device sheet (or device layer) in the bonded wafer is observed by a scanning electron microscope and a surface particle detector, the number of device sheet surface particles is 10054, and the yield is 25.9%.

[0075] In Example Four, the thickness of the device sheet is 782 μm; a thermal oxidation process is performed on the device sheet to form a buried oxide layer on the device sheet, the oxidation temperature of the thermal oxidation process is 1100 °C, the gas flow of oxygen in the thermal oxidation process is 4 slm, the gas flow of hydrogen is 6 slm, and the thickness of the buried oxide layer is 176 nm; an ion implantation process is performed on the device sheet from the surface of the buried oxide layer to form an ion implantation layer in the device sheet, and the total implantation dose of hydrogen ions and helium ions is 1.50E16 atom / cm 2 A support sheet is provided, the thickness of the support sheet is 782 μm, the device sheet and the support sheet are bonded, and the buried oxide layer is located between the device sheet and the support sheet; then, a reinforcement heat treatment and a peeling treatment are sequentially performed, a partial thickness of the device sheet is peeled off from the position of the ion implantation layer, and a thinning process is performed to obtain the required thickness of the device sheet, and the thickness of the device sheet after the thinning process is 101 nm.

[0076] Then, as shown in Figure 12 and Figure 13 , the quality of the device sheet (or device layer) in the bonded wafer is observed by a scanning electron microscope and a surface particle detector, the number of device sheet surface particles is 198, and the yield is 82.4%.

[0077] In the fifth embodiment, the thickness of the device sheet is 779 μm; a thermal oxidation process is performed on the device sheet to form a buried oxide layer on the device sheet, the oxidation temperature of the thermal oxidation process is 1100°C, the gas flow of oxygen in the thermal oxidation process is 4 slm, the gas flow of hydrogen is 6 slm, and the thickness of the buried oxide layer is 186 nm; an ion implantation process is performed on the device sheet from the surface of the buried oxide layer to form an ion implantation layer in the device sheet, and the total implantation dose of hydrogen ions and helium ions is 1.65E16 atom / cm 2 ; a support sheet is provided, the thickness of the support sheet is 776 μm, the device sheet and the support sheet are bonded, and the buried oxide layer is located between the device sheet and the support sheet; then, a reinforcement heat treatment and a peeling treatment are sequentially performed, a partial thickness of the device sheet is peeled off from the position of the ion implantation layer, and a thinning process is performed to obtain the required thickness of the device sheet, and the thickness of the device sheet after the thinning process is 99 nm.

[0078] Then, as shown in Figure 14 and Figure 15 , the quality of the device sheet (or device layer) in the bonded wafer is observed by a scanning electron microscope and a surface particle detector, the number of particles on the surface of the device sheet is 5643, and the yield is 52.4%.

[0079] In combination with the above five embodiments, it can be seen that the number of particles on the surface of the device sheet in the first, second and fourth embodiments is small, that is, the preparation method of the semiconductor device provided in the embodiments reduces the nucleation and growth of defects in the device sheet, thereby reducing the number of defects in the device sheet, and can effectively improve the surface roughness of the bonded wafer and reduce the surface roughness of the bonded wafer.

[0080] The present embodiment also provides a semiconductor device prepared by the preparation method of the semiconductor device provided in the present embodiment. Referring to Figure 5 and in combination with Figure 3 , the semiconductor device comprises a support sheet 104, a device sheet 101 and a buried oxide layer 102, the device sheet 101 is a part of the device sheet formed by the preparation method of the semiconductor device provided in the present embodiment and left after peeling off the ion implantation layer; the buried oxide layer 102 is located between the device sheet 101 and the support sheet 104, and the buried oxide layer 102, the device sheet 101 and the support sheet 104 are bonded as a whole, i.e. constitute a bonded wafer.

[0081] In a conventional semiconductor device manufacturing process, when forming an ion implantation layer, the total implantation dose of the implanted ions is not adjusted according to the temperature of the thermal oxidation process for forming the buried oxide layer, resulting in a low yield (less than 80%) of the final semiconductor device. In the embodiment, the device wafer 101 is the remaining part of the device wafer after the ion implantation layer is peeled off, which is formed by the semiconductor device manufacturing method provided in the embodiment. Specifically, when forming the ion implantation layer 103, the total implantation dose of the implanted ions is adjusted according to the temperature of the thermal oxidation process for forming the buried oxide layer 102, which can reduce the nucleation and growth of defects in the device wafer 101, thereby reducing the number of defects in the device wafer 101, reducing the roughness of the surface of the device wafer remaining after the ion implantation layer is peeled off, and improving the yield of the semiconductor device.

[0082] Further, the yield of the semiconductor device is greater than or equal to 80%.

[0083] As can be seen from the above, in the semiconductor device and the manufacturing method thereof provided in the embodiment, a thermal oxidation process is first performed to form a buried oxide layer on a device wafer, and then an ion implantation process is performed on the device wafer from the surface of the buried oxide layer to form an ion implantation layer in the device wafer, wherein when performing the ion implantation process, the total implantation dose of the implanted ions is adjusted according to the temperature of the thermal oxidation process. In this way, the total implantation dose of the implanted ions can be reduced or increased according to the temperature of the thermal oxidation process, thereby reducing the nucleation and growth of defects in the device wafer, further reducing the number of defects in the device wafer, and improving the yield of the semiconductor device.

[0084] It should be noted that the embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts of each embodiment can be referred to each other. In addition, the different parts of each embodiment can also be used in combination with each other, and the present application is not limited in this regard.

[0085] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or modification made by a person skilled in the art according to the above disclosure is within the scope of protection of the claims.

Claims

1. A method of manufacturing a semiconductor device, characterized by, include: Provide component chips; A thermal oxidation process is performed to form a buried oxide layer on the device wafer; An ion implantation process is performed on the device wafer from the surface of the buried oxide layer to form an ion implantation layer in the device wafer, wherein the total implantation dose of implanted ions is adjusted according to the temperature of the thermal oxidation process during the ion implantation process.

2. The method of producing a semiconductor device according to Claim 1, wherein When the temperature of the thermal oxidation process is greater than or equal to 800℃ and less than 1000℃, the total implantation dose of the implanted ions has the following relationship with the temperature of the thermal oxidation process: 10E15≤Y1≤(-0.2*X1+220)E15; wherein Y1represents the total implant dose of the implanted ions in atom / cm 2 X1represents the temperature of the thermal oxidation process.

3. The method of producing a semiconductor device according to Claim 1, wherein When the temperature of the thermal oxidation process is greater than or equal to 1000℃ and less than or equal to 1100℃, the total implantation dose of the implanted ions has the following relationship with the temperature of the thermal oxidation process: 10E15≤Y1≤(-0.05*X1+70)E15; wherein Y1represents the total implant dose of the implanted ions in atom / cm 2 X1represents the temperature of the thermal oxidation process.

4. The method of producing a semiconductor device according to any one of claims 1 to 3, wherein The ion implantation process uses hydrogen ions and helium ions. When performing the ion implantation process, the implantation dose of hydrogen ions and the implantation dose of helium ions are adjusted according to the temperature of the thermal oxidation process to adjust the total implantation dose of the implanted ions.

5. The method of producing a semiconductor device according to Claim 1, wherein The gas used in the thermal oxidation process includes oxygen, and the oxygen flow rate is 1 slm to 10 slm.

6. The method of producing a semiconductor device according to claim 1 or 5, wherein The gas used in the thermal oxidation process also includes hydrogen, and the flow rate of the hydrogen is 0 slm to 20 slm.

7. The method of producing a semiconductor device according to Claim 1, wherein After performing the ion implantation process, the method for fabricating the semiconductor device further includes: Provide support plates; The support sheet is bonded to the device sheet, and the buried oxide layer is located between the device sheet and the support sheet; A stripping process is performed to peel off a portion of the device wafer from the location of the ion implantation layer, so that the remaining device wafer, the buried oxide layer, and the support wafer form a bonded wafer; A thinning process is performed to reduce the thickness of the device wafer in the bonding wafer.

8. The method of producing a semiconductor device according to Claim 1, wherein The thickness of the buried oxide layer is 0.01 μm to 1 μm.

9. A semiconductor device, characterized by Includes support sheet, device sheet, and buried oxide layer; The device wafer is the portion remaining after the semiconductor device is peeled off along the ion implantation layer, formed by the method of semiconductor device fabrication as described in any one of claims 1 to 8. The buried oxide layer is located between the device wafer and the support wafer, and the buried oxide layer, the device wafer, and the support wafer are bonded together as a single unit.

10. The semiconductor device of claim 9, wherein, The yield of the semiconductor device is greater than or equal to 80%.

Images