Chip bonding pad preparation method and chip bonding method

Abstract

The application provides a chip bonding pad preparation method and a chip bonding method, and belongs to the technical field of microelectronics. The preparation method comprises the following steps: depositing an adhesion layer and a seed layer on a bonding surface of a chip, wherein the bonding surface of the chip is provided with a bonding pad; coating photoresist on the adhesion layer and the seed layer, exposing a bonding pad area on the bonding pad by using a patterning process, and sequentially depositing a gold layer and a silver layer on the bonding pad area by electroplating; removing the remaining photoresist and etching to remove the exposed adhesion layer and seed layer; selectively irradiating the silver layer by using a laser, so that the silver layer and the gold layer are selectively alloyed by laser to form an alloyed part and a non-alloyed part based on the silver layer and the gold layer; and performing a dealloying treatment to expose the gold layer of the non-alloyed part and make the alloyed part form a nano-modified layer, thereby forming a chip bonding pad.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a method for preparing chip bonding pads for three-dimensional chip integration and a chip bonding method. Background Technology

[0002] Traditional 3D chip stacking integration requires interconnects between chips. Existing technologies include: copper pillar microbumps using SnAg solder, transient liquid phase bonding using Cu / Sn or Au / In as bonding materials, and hybrid bonding using Cu / SiO2. In 3D stacking applications involving compound chips, especially compound RF functional chips, the interconnect technology needs to simultaneously meet the requirements of large-area ground planes and small-sized pads for bonding, efficient heat dissipation, and compatibility with the ultra-thin and large warpage characteristics of compound chips. Existing chip stacking interconnect technologies cannot simultaneously meet all these requirements. Summary of the Invention

[0003] In view of this, and in order to address the technical problems mentioned above and meet the requirements for three-dimensional stacking of compound chips, this invention proposes a method for preparing chip bonding pads and a chip bonding method. This method can simply and reliably prepare chip bonding pads with nano-modification layers. Furthermore, based on the prepared chip bonding pads, a chip bonding method with high compression uniformity is provided, thereby improving the consistency of the bonding process and the bonding quality.

[0004] According to one aspect of the present invention, a method for preparing chip bonding pads is provided, comprising:

[0005] An adhesion layer and a seed layer are deposited on the side of the chip to be bonded, wherein bonding pads are formed on the side of the chip to be bonded. Photoresist is coated on the adhesion layer and the seed layer, and a patterning process is used to expose the bonding pad area located on the bonding pad. A gold layer and a silver layer are sequentially electroplated and deposited on the bonding pad area. The remaining photoresist is removed, and the exposed adhesion layer and seed layer are etched away. The silver layer is selectively irradiated with a laser to selectively alloy the silver layer with the gold layer, so as to form an alloyed part and an unalloyed part based on the silver layer and the gold layer. Then, a dealloying process is performed to expose the unalloyed part of the gold layer, and the alloyed part forms a nano-modification layer to form the chip bonding pad.

[0006] According to another aspect of the present invention, a chip bonding method is provided, comprising:

[0007] A first chip is provided, the surface of which has a first chip bonding pad, the first chip bonding pad being obtained by the preparation method described above;

[0008] A second chip is provided, the surface of which has second chip bonding pads, and a gold layer is provided on the second chip bonding pads; and

[0009] The first chip and the second chip are aligned and thermo-bonded, which allows the nano-modification layer of the first chip bonding pad and the gold layer of the second chip bonding pad to diffuse, thereby achieving bonding interconnection between the first chip and the second chip.

[0010] According to the chip bonding pad preparation method provided by the present invention, the gold and silver layers formed on the bonding pads on the bonding side of the chip are selectively alloyed by laser. After dealloying during the dealloying process, a patterned nano-modification layer is formed. By optimizing the pattern design of the nano-modification layer, the compression amount of the nano-modification layer during the bonding process can be easily and precisely controlled, thereby achieving chip bonding with high uniformity and improving the consistency and quality of the bonding process. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of the present invention and are not intended to limit the present invention.

[0012] Figure 1 A flowchart illustrating a method for preparing chip bonding pads according to an embodiment of the present invention;

[0013] Figures 2A-2F This is a schematic diagram illustrating the fabrication process of the chip bonding pads provided in an embodiment of the present invention.

[0014] Figure 3A A schematic diagram of the alloyed and unalloyed portions provided in an embodiment of the present invention;

[0015] Figure 3B A schematic diagram of the alloyed and unalloyed portions provided in another embodiment of the present invention; and

[0016] Figures 4A-4B This is a schematic diagram of the thermo-bonding of a first chip and a second chip according to an embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures:

[0018] 1-Chip; 2-Passivation layer; 3-Pad; 4-Adhesion layer and seed layer; 5-Photoresist; 6-Gold layer; 7-Silver layer; 8-Alloyed portion; 9-Nano-modification layer; 10-Unalloyed portion; 11-Unalloyed portion located inside the alloyed portion; A-First chip; B-Second chip; 12-Compressed nano-modification layer; 13-Gold layer of the second chip bonding pad of the second chip. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. However, this invention can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the invention thorough and complete, and to fully convey the scope of the invention to those skilled in the art. In the accompanying drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0021] In related technologies, due to limitations in wiring structure and fabrication processes, the surface of compound chips is typically uneven compared to silicon-based chips. Bonding on such uneven surfaces can easily lead to uneven compression during the bonding process. Furthermore, since compound chips, such as RF chips, often require large-area grounding, inconsistent bonding pad sizes, uneven bonding position distribution, and unbalanced bonding pressure can result in inconsistent bonding.

[0022] Nano-modified chip pad bonding, leveraging the low-temperature, low-pressure bonding properties of nanomaterials, has gained industry attention. This technology enables low-temperature, low-pressure, and low-stress chip stacking and bonding, while exhibiting low thermal resistance at the bonding interface and relatively high tolerance for chip warpage and surface undulations, making it a preferred solution for the three-dimensional stacking and integration of compound chips.

[0023] However, existing nano-modified chip pad bonding technologies face unresolved technical bottlenecks. First, there is a lack of simple and reliable selective nano-modification processes for bonding pads. Some proposed methods are non-selective and cannot meet the requirements for fabricating patterned nano-metal modification layers for chip pads. Furthermore, the fabrication of metal nanorod modification layers for pads in some studies requires multiple photolithography steps, resulting in a long process flow and the risk of photoresist residue contamination. Second, controlling the uniformity of bonding compression in nano-metal layers is difficult, especially in situations such as co-bonding large-area ground planes with small-sized pads or bonding ultra-thin, highly warped chips. Uneven pressure distribution is unavoidable, leading to poor bonding consistency. Specifically, this manifests as insufficient uniformity of nano-metal bonding compression, low bonding strength in low-compression regions, and high residual stress at the bonding interface, severely impacting bonding quality. Solutions to these technical bottlenecks remain a gap in the industry.

[0024] In view of this, the present invention proposes a method for preparing chip bonding pads and a chip bonding method to achieve chip bonding with high compression uniformity and improve bonding process consistency and bonding quality.

[0025] The chip bonding pad preparation method and chip bonding method proposed in this invention are particularly suitable for compound chips.

[0026] Figure 1 A flowchart illustrating a method for preparing chip bonding pads according to an embodiment of the present invention.

[0027] Figures 2A-2F This is a schematic diagram illustrating the fabrication process of the chip bonding pads provided in an embodiment of the present invention.

[0028] According to an exemplary embodiment of the present invention, the present invention provides a method for preparing chip bonding pads, referring to... Figure 1 , Figures 2A-2F As shown, it includes: operations S1 to S5.

[0029] Operation S1 deposits an adhesion layer and a seed layer 4 on the side of chip 1 to be bonded, wherein a bonding pad 3 is formed on the side of chip 1 to be bonded.

[0030] In some embodiments, a passivation layer 2 surrounding the pad 3 is also formed on the side of the chip 1 to be bonded (hereinafter referred to as the bonding side).

[0031] refer to Figure 2A , Figure 2B As shown, the adhesion layer and seed layer 4 are formed on the passivation layer 2 and the pad 3.

[0032] In an embodiment of the present invention, the bonding surface of chip 1 can be the front side or the back side of the chip.

[0033] In embodiments of the present invention, the adhesion layer and seed layer 4 include an adhesion layer and a seed layer located on the adhesion layer. The material of the adhesion layer includes Ti or TiW. The thickness of the adhesion layer is 50 nm to 200 nm, for example, 50 nm, 100 nm, 150 nm, 180 nm, 200 nm, but is not limited to the values ​​listed. The adhesion layer can be deposited by, for example, magnetron sputtering.

[0034] In some embodiments, the seed layer material includes Au, and the thickness of the seed layer is 50nm to 200nm, for example, 50nm, 100nm, 150nm, 180nm, 200nm, but not limited to the values ​​mentioned.

[0035] In some embodiments, the material of the pad 3 includes Au and Al.

[0036] In embodiments of the present invention, the adhesion layer is used to adhere the native pads 3 of chip 1 to the gold pads (i.e., gold layer 6) to be electroplated subsequently, and to prevent diffusion between aluminum and gold (when the material of pad 3 is Al). Excessive diffusion between aluminum and gold can cause volume changes in the metal and create voids at the interface (Kirkendall voids), which in turn can lead to a decrease in the mechanical properties and deterioration in the electrical properties of the chip bonding pads.

[0037] In embodiments of the present invention, the seed layer is mainly used to conduct electricity during the electroplating process of the gold layer 6.

[0038] In operation S2, photoresist 5 is coated on the adhesion layer and seed layer 4, and the bonding pad area on the pad 3 is exposed by patterning process. Gold layer 6 and silver layer 7 are deposited sequentially on the bonding pad area by electroplating.

[0039] In an embodiment of the present invention, reference is made to... Figure 2C The thickness of gold layer 6 is greater than 5 μm. If the thickness of gold layer 6 is too thin (e.g., less than 5 μm), the prepared gold nanoparticles (nano-modified layer 9) will be insufficient in thickness, affecting the bonding effect.

[0040] In embodiments of the present invention, the thickness of the silver layer 7 is 2μm to 6μm, for example, it can be 2μm, 3μm, 4μm, 5μm, or 6μm, but is not limited to these values. The entire silver layer 7 participates in alloying, and the thickness of the silver layer 7, together with the thickness of the gold layer participating in alloying, determines the total thickness of the alloy layer. If the thickness of the silver layer 7 is too large (e.g., greater than 6μm), the laser energy penetrating the silver layer is insufficient to alloy part of the gold layer, resulting in a smaller thickness of the gold layer participating in alloying, and consequently, a smaller thickness of the nano-modification layer 9, affecting the bonding effect. If the thickness of the silver layer 7 is too small (e.g., less than 2μm), the thickness of the nano-modification layer 9 formed after dealloying will be too small, also affecting the bonding effect.

[0041] Operation S3 removes the remaining photoresist 5 and etches away the exposed adhesion layer and seed layer 4.

[0042] In an embodiment of the present invention, a reactive ion etching system is used to etch and remove the exposed adhesion layer and seed layer 4, as shown in the reference. Figure 2D .

[0043] In operation S4, the silver layer 7 is selectively irradiated with a laser, causing the silver layer 7 and the gold layer 6 to be selectively alloyed by laser, so as to form an alloyed portion 8 and an unalloyed portion based on the silver layer 7 and the gold layer 6.

[0044] In embodiments of the present invention, laser selective alloying refers to selectively irradiating the surface of the silver layer in the bonding pad area with a laser, causing the silver layer to alloy with the gold layer located beneath it under the action of the laser thermal effect. A region is defined for selective laser irradiation; an alloyed portion 8 (Au-Ag alloy) is formed in the laser-irradiated region, and an unalloyed portion is formed in the un-irradiated region, as shown in the reference. Figure 2E .

[0045] In embodiments of the present invention, a variable spot laser system or a digital micromirror (DMD) laser system is used for selective laser irradiation to achieve high-precision selective laser irradiation.

[0046] In embodiments of the present invention, blue laser or green laser is selected to achieve a high absorption rate of laser on the surface of the silver layer.

[0047] In embodiments of the present invention, the ratio of the thickness of the gold layer alloyed with the silver layer 7 to the thickness of the silver layer 7 is (0.5~1):1, for example, 0.5:1, 0.6:1, 0.7:1, 0.8:1, 0.9:1, 1:1, but not limited to the values ​​listed. This ratio represents the volume ratio of gold and silver in the alloy layer formed by the silver layer 7 and the gold layer 6, which determines the porosity of the remaining nano-gold after dealloying. The lower the proportion of gold, the more porous the nano-gold. Excessive porosity leads to structural instability of the nano-modified layer, while insufficient porosity makes dealloying difficult, resulting in failure to prepare the nano-modified layer. By controlling the ratio of the thickness of the gold layer alloyed with the silver layer 7 to the thickness of the silver layer 7 within the above-mentioned range, a structurally stable nano-modified layer 9 can be successfully prepared.

[0048] In some embodiments, the thickness of the silver layer 7 is 4 μm. By adjusting the laser pulse power, pulse width and pulse number, the thickness of the gold layer alloyed with the silver layer is made to reach about 2 μm. At this time, the thickness of the Au-Ag alloy is about 6 μm (4 μm + 2 μm = 6 μm).

[0049] In some embodiments, by selectively irradiating the Au-Ag alloy with lasers once or multiple times, the mass percentage of Au on the exposed surface is increased to greater than or equal to 20%, thus preventing the nano-gold from becoming too porous and losing its self-supporting ability after dealloying and falling off the pads.

[0050] Figure 3A This is a schematic diagram of the alloyed and unalloyed portions provided in an embodiment of the present invention.

[0051] In an embodiment of the present invention, reference is made to... Figure 3AAs shown, the silver layer 7 and the gold layer form an alloyed portion 8 and an unalloyed portion 10 located on the outer periphery of the alloyed portion 8. The width W1 of the unalloyed portion 10 is 5μm to 50μm, for example, 10μm.

[0052] In an embodiment of the present invention, the diameter of the inscribed circle of the alloyed portion 8 is less than or equal to d, where d is 100 μm to 500 μm.

[0053] Figure 3B This is a schematic diagram of the alloyed portion and the unalloyed portion provided for another embodiment of the present invention.

[0054] In an embodiment of the present invention, reference is made to... Figure 3B As shown, the silver layer 7 and the gold layer form an alloyed portion and an unalloyed portion 10 located on the outer periphery of the alloyed portion. The width W1 of the unalloyed portion 10 is 5 μm to 50 μm. Furthermore, the silver layer 7 and the gold layer also form an unalloyed portion 11 located inside the alloyed portion. The width W2 of the unalloyed portion 11 located inside the alloyed portion is 5 μm to 50 μm, for example, 10 μm, such that the diameter of the inscribed circle of the alloyed portion 8 is less than or equal to d, where d is 100 μm to 500 μm.

[0055] The unalloyed portion acts as a limit during the bonding process, preventing the nano-modified layer 9 from being over-compressed, thus ensuring that the nano-modified layer 9 is compressed to the same degree, which helps to improve the consistency of the bonding process.

[0056] In an embodiment of the present invention, see Figure 3B As shown, the diameter of the inscribed circle of the alloyed portion 8 actually represents the maximum distance between the two unalloyed portions. Too large a distance will weaken the limiting effect when the chip warps, especially since compound RF chips are generally only 100μm thick. Bonding forces can cause chip deformation, so the distance between the two limiting points cannot be too large.

[0057] If the distance between the other two limiting sites is too small, the limiting sites will occupy too much bonding area, resulting in insufficient bonding strength. By controlling the diameter of the inscribed circle of the alloyed portion 8 to be less than or equal to d, better bonding uniformity can be achieved while ensuring bonding strength.

[0058] In embodiments of the present invention, the alloyed portion contains an unalloyed portion, which helps to solve the problem of inconsistent compression of the nano-modification layer caused by chip warping during chip bonding.

[0059] Operation S5 performs a dealloying process to expose the unalloyed portion of the gold layer 6, and allows the alloyed portion 8 to form a nano-modification layer 9, forming a chip bonding pad.

[0060] The nano-modification layer 9 comprises a nanostructure composed of nanoparticles.

[0061] In an embodiment of the present invention, the dealloying process includes placing the chip 1 in a nitric acid solution with a mass concentration of 10%~20% and a temperature of 20℃~80℃ for 1~10 hours, so that the silver in the alloyed portion (Au-Ag alloy) 8 is fully dissolved and removed, and a nano-modification layer 9 is formed by dealloying; the silver layer in the unalloyed portion dissolves, exposing the gold layer 6, as shown in the reference. Figure 2F .

[0062] In some embodiments, the mass concentration of the nitric acid solution is, for example, 10%, 12%, 15%, 18%, or 20%, but not limited to these values; the temperature is, for example, 20°C, 30°C, 50°C, 60°C, or 80°C, but not limited to these values; the processing time is, for example, 1 hour, 2 hours, 5 hours, 8 hours, or 10 hours, but not limited to these values. If the mass concentration of the nitric acid solution is too high (e.g., greater than 20%), the dealloying reaction is too rapid, and the nano-modified layer 9 is prone to cracking, leading to a decrease in mechanical properties. If the mass concentration of the nitric acid solution is too low (e.g., less than 10%), the dealloying reaction is incomplete, which is detrimental to improving bonding quality. If the temperature is too high, the nanoparticles in the nano-modified layer are prone to abnormal growth, resulting in a decrease in the strength of the nano-modified layer. If the temperature is too low, the dealloying reaction is incomplete, and the structure of the formed nano-modified layer is uneven. By controlling the dealloying parameters (mass concentration of nitric acid solution, temperature, and processing time) within the range required by this invention, a nano-modified layer 9 with superior performance can be obtained.

[0063] In some embodiments, the surface of the nano-modified layer 9 is higher than the unalloyed portion of the gold layer, forming a certain height difference, which is approximately equal to or slightly less than 4 μm.

[0064] In some embodiments, after dealloying, the chip 1 is further annealed in a vacuum oven at a temperature of 30°C to 100°C for 0.5 to 2 hours to increase the ligament size of the nano-modification layer 9 to the range of 50 nm to 100 nm. The annealing process allows the excessively small nanostructures to sinter and fuse together, forming a uniform nanostructure and making the nano-modification layer more stable.

[0065] Figures 4A-4B This is a schematic diagram of the thermo-bonding of a first chip and a second chip according to an embodiment of the present invention.

[0066] According to an exemplary embodiment of the present invention, the present invention provides a chip bonding method, referring to... Figure 4A , Figure 4B As shown, it includes: operations S10 to S30.

[0067] In operation S10, a first chip A is provided, the surface of which has a first chip bonding pad, which is obtained by the above-described preparation method;

[0068] In operation S20, a second chip B is provided, the surface of which has a second chip bonding pad, and the surface of the second chip bonding pad has a gold layer.

[0069] In other words, the second chip bonding pad of the second chip B does not contain a nano-modification layer.

[0070] In operation S30, the first chip A and the second chip B are aligned and thermo-bonded, so that the nano-modification layer of the first chip bonding pad of the first chip A and the gold layer 13 of the second chip bonding pad of the second chip diffuse, thereby realizing the bonding interconnection between the first chip A and the second chip B.

[0071] In an embodiment of the present invention, aligning the first chip A and the second chip B means placing the first chip bonding pad of the first chip A in the orthographic projection area of ​​the first chip A, and placing the second chip bonding pad of the second chip B in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip B in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the second chip B in the orthographic projection area of ​​the second chip B in the orthographic projection area of ​​the first chip B in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first ... A in the orthographic projection area of ​​the first chip B in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip B in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first chip A in the orthographic projection area of ​​the first

[0072] In embodiments of the present invention, the bonding temperature for hot-press bonding is 150°C to 250°C, for example, 150°C, 180°C, 200°C, 220°C, or 250°C, but is not limited to these values. The bonding pressure for hot-press bonding is 0.1 MPa to 10 MPa, for example, 0.1 MPa, 0.5 MPa, 1 MPa, 2 MPa, 5 MPa, or 10 MPa, but is not limited to these values. The holding time for hot-press bonding is 1 min to 5 min, for example, 1 min, 2 min, 3 min, 4 min, or 5 min, but is not limited to these values.

[0073] In an embodiment of the present invention, reference is made to... Figure 4B As shown, the nano-modification layer 9 of the first chip bonding pad of the first chip A and the gold layer 13 of the second chip bonding pad of the second chip diffuse together to form a compressed nano-modification layer 12.

[0074] The area of ​​the first chip A without the nano-modified layer makes contact with the surface of the second bonding pad of the second chip B. At this time, the compression of the nano-modified layer 9 reaches the upper limit and is consistent.

[0075] In embodiments of the present invention, the first chip A and the second chip B are one of a compound chip, a silicon-based chip, and a through-silicon via (TSV) adapter board. The first chip A and the second chip B can be the same type of chip or different types of chips.

[0076] In an embodiment of the present invention, after the first chip A is diced and sharded, it is bonded to the second chip B in wafer form (i.e., die-to-wafer bonding) to achieve bonding between the first chip A and the second chip B. Using the method of the present invention, the bonding pads of the first chip A and the second chip B do not require very high symmetry within the chip to achieve very uniform bonding, providing greater freedom in the design of the bonded chip.

[0077] In embodiments of the present invention, both the first chip A and the second chip B are diced and then bonded (i.e., die-to-die bonding), or both the first chip A and the second chip B are bonded in wafer form (i.e., wafer-to-wafer bonding). Both of these methods can be used and achieve the same effect.

[0078] According to an embodiment of the present invention, a patterned nano-modification layer is formed by laser selective alloying-dealloying, which is simple, reliable and has low preparation cost.

[0079] According to an embodiment of the present invention, during the hot-press bonding process, the area of ​​the first chip bonding pad of the first chip A without the nano-modified layer is in contact with and limited by the surface of the second chip bonding pad of the second chip B, preventing the nano-modified layer from being over-compressed, thereby achieving a consistent compression amount. This solves the problem in related technologies where it is difficult to control the uniformity of the bonding compression amount of the nano-metal layer, resulting in uncontrollable bonding quality.

[0080] According to embodiments of the present invention, the chip bonding method of the present invention is particularly suitable for the synergistic bonding of large-area ground planes and small-sized pads, and the three-dimensional stacking bonding of ultra-thin chips with large warpage, offering advantages such as a large process window and controllable bonding quality. Specifically, the bonding compression of nano-metals is highly dependent on the bonding pressure. If the bonding pads on the chip are not evenly distributed, it will lead to uneven pressure distribution, resulting in inconsistent bonding. Furthermore, chip warpage can also cause uneven pressure, leading to similar problems. In the method of the present invention, through patterned nano-metal fabrication, regions without nano-modified layers are set as limits, thereby achieving consistent compression.

[0081] The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify the corresponding elements does not imply that the element has any ordinal number, nor does it represent the order of one element with another element, or the order of manufacturing methods. The use of these ordinal numbers is only to enable a named element to be clearly distinguished from another element with the same name.

[0082] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method of preparing a die bonding pad, characterized by, The method comprises: depositing an adhesion layer and a seed layer (4) on a side of a chip (1) to be bonded, wherein the side of the chip (1) to be bonded is provided with a pad (3); applying photoresist (5) on the adhesion layer and the seed layer (4), exposing a bonding pad area on the pad (3) by using a patterning process, and sequentially depositing a gold layer (6) and a silver layer (7) on the bonding pad area by electroplating; removing the remaining photoresist (5) and etching to remove the exposed adhesion layer and seed layer (4); selectively irradiating the silver layer (7) by using a laser, so that the silver layer (7) and the gold layer (6) are selectively alloyed by laser to form an alloyed portion (8) and a non-alloyed portion based on the silver layer (7) and the gold layer (6); and performing dealloying treatment to expose the gold layer (6) of the non-alloyed portion and form a nano-modified layer (9) of the alloyed portion (8) to form a chip bonding pad. The thickness of the gold layer (6) is greater than 5 μm.

2. The production method according to claim 1, characterized by, The thickness of the silver layer (7) is 2 μm to 6 μm.

3. The preparation method according to claim 1, characterized in that, The ratio of the thickness of the gold layer alloyed with the silver layer (7) to the thickness of the silver layer (7) is (0.5-1):

1.

4. The method of claim 1, wherein, The mass percentage of Au on the surface of the alloyed portion (8) is greater than or equal to 20%.

5. The preparation method according to claim 1, characterized in that, The non-alloyed portion is arranged around the alloyed portion (8), and the width of the non-alloyed portion is 5 μm to 50 μm.

6. The method of claim 1, wherein, The non-alloyed portion is also formed inside the alloyed portion, so that the diameter of the inscribed circle of the alloyed portion is less than or equal to 100 μm to 500 μm.

7. The preparation method according to claim 6, characterized in that, The dealloying treatment comprises:

8. The method of claim 1, wherein, placing the chip (1) in a nitric acid solution with a mass concentration of 10% to 20% and a temperature of 20°C to 80°C for 1 h to 10 h. The method comprises:

9. A die bonding method, characterized by, providing a first chip (A) having a first chip bonding pad on the surface thereof, wherein the first chip bonding pad is obtained by using the preparation method according to any one of claims 1 to 8; providing a second chip (B) having a second chip bonding pad on the surface thereof, wherein the second chip bonding pad is provided with a gold layer; aligning the first chip (A) with the second chip (B) and performing thermal compression bonding, so that the nano-modified layer of the first chip bonding pad and the gold layer of the second chip bonding pad are metallurgically diffused to realize the bonding and interconnection of the first chip (A) and the second chip (B). The bonding temperature of the thermal compression bonding is 150°C to 250°C. The bonding pressure of the thermal compression bonding is 0.1 MPa to 10 MPa.

10. The die bonding method according to claim 9, wherein The bonding time of the thermal compression bonding is 1 min to 5 min. ​ ​

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