Semiconductor device and manufacturing method and packaging structure thereof

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a packaging structure. The semiconductor device comprises a conductive structure which extends along a first direction; the dummy first conductive layer is positioned on at least one side of the conductive structure along the second direction; wherein the first direction is perpendicular to the second direction; the dummy conductive contact is positioned on at least one side of the conductive structure along the second direction and is also positioned on one side of the dummy first conductive layer along the first direction; wherein the dummy conductive contact is connected to the dummy first conductive layer; the second conductive layer is positioned on one side of the conductive structure along the first direction, and the dummy conductive contact is positioned between the dummy first conductive layer and the second conductive layer; wherein the same second conductive layer is connected with the conductive structure and the dummy conductive contact at the same time.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor device, its manufacturing method, and its packaging structure. Background Technology

[0002] Through Silicon Via (TSV) technology is a core technology for achieving chip stacking interconnection in the field of 3D integrated circuits. It enables electrical connections between chips through conductive channels that vertically penetrate the silicon substrate. Vertical conductive channels can make full use of metal wiring layers, provide flexible wiring, help optimize signal paths, reduce latency, lower power consumption, and improve overall chip performance. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the same, and a packaging structure thereof.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising: a conductive structure extending along a first direction; a dummy first conductive layer located on at least one side of the conductive structure along a second direction; wherein the first direction and the second direction are perpendicular to each other; a dummy conductive contact located on at least one side of the conductive structure along the second direction and also located on one side of the dummy first conductive layer along the first direction; wherein the dummy conductive contact is connected to the dummy first conductive layer; a second conductive layer located on one side of the conductive structure along the first direction, and the dummy conductive contact located between the dummy first conductive layer and the second conductive layer; wherein the same second conductive layer is simultaneously connected to the conductive structure and the dummy conductive contact.

[0005] In some embodiments, the semiconductor device further includes: a semiconductor layer located on the side of the dummy first conductive layer opposite to the dummy conductive contact, wherein the conductive structure extends into the semiconductor layer; wherein the conductive structure and the semiconductor layer are electrically isolated.

[0006] In some embodiments, the semiconductor device further includes: a device located on one side of the semiconductor layer along the first direction; a contact structure located on one side of the device along the first direction; wherein the contact structure is connected to the device; a first conductive layer, a conductive contact, and a third conductive layer arranged sequentially along the first direction, the first conductive layer being located between the contact structure and the conductive contact; wherein the device is connected sequentially through the contact structure, the first conductive layer, the conductive contact, and the third conductive layer.

[0007] In some embodiments, the semiconductor device further includes: a first dielectric layer, a second dielectric layer, a third dielectric layer, and a fourth dielectric layer stacked along the first direction; wherein the first dielectric layer is located between the semiconductor layer and the second dielectric layer, the device and the contact structure are both located in the first dielectric layer, the dummy first conductive layer and the first conductive layer are both located in the second dielectric layer, the dummy conductive contact and the conductive contact are both located in the third dielectric layer, and the second conductive layer and the third conductive layer are both located in the fourth dielectric layer.

[0008] In some embodiments, the second dielectric layer includes: a first sub-dielectric layer and a second sub-dielectric layer stacked along the first direction; wherein the first sub-dielectric layer is located between the first dielectric layer and the second sub-dielectric layer, and the hardness of the first sub-dielectric layer is greater than the hardness of the second sub-dielectric layer.

[0009] In some embodiments, the semiconductor device further includes: a plurality of dummy conductive contacts, wherein the plurality of dummy conductive contacts are arranged at intervals around the conductive structure.

[0010] In some embodiments, the cross-sectional dimension of the conductive structure along the direction perpendicular to the first direction is larger than the cross-sectional dimension of the dummy conductive contact along the direction perpendicular to the first direction.

[0011] In a second aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a dummy first conductive layer; forming a conductive structure extending along a first direction, the dummy first conductive layer being located on at least one side of the conductive structure along a second direction; wherein the first direction and the second direction are perpendicular to each other; forming a dummy conductive contact, the conductive contact being located on at least one side of the conductive structure along the second direction and also on one side of the dummy first conductive layer along the first direction; wherein the dummy conductive contact is connected to the dummy first conductive layer; forming a second conductive layer, the second conductive layer being located on one side of the conductive structure along the first direction, and the dummy conductive contact being located between the dummy first conductive layer and the second conductive layer; wherein the same second conductive layer is simultaneously connected to the conductive structure and the dummy conductive contact.

[0012] In some embodiments, before forming the dummy first conductive layer, the method further includes: providing a semiconductor structure, the semiconductor structure including an initial semiconductor layer, a first dielectric layer located on the initial semiconductor layer, a device located in the first dielectric layer, and a contact structure; wherein the device and the contact structure are connected.

[0013] In some embodiments, forming a dummy first conductive layer includes: forming a second dielectric layer covering the first dielectric layer; etching the second dielectric layer to form a first groove and a second groove; wherein the bottom of the first groove exposes the first dielectric layer, and the bottom of the second groove exposes the contact structure; filling the first groove and the second groove with conductive material to form a dummy first conductive layer and a first conductive layer, respectively; wherein the first conductive layer and the contact structure are connected.

[0014] In some embodiments, forming a conductive structure includes: forming a third dielectric layer covering the dummy first conductive layer and the first conductive layer; etching the third dielectric layer, the second dielectric layer, the first dielectric layer and the initial semiconductor layer to form a first etched hole; forming an isolation layer covering the sidewalls and bottom of the first etched hole; and filling the first etched hole with a conductive material to form a conductive structure.

[0015] In some embodiments, forming a dummy conductive contact includes: etching the third dielectric layer to form a second etched hole and a third etched hole; wherein the bottom of the second etched hole exposes the dummy first conductive layer, and the bottom of the third etched hole exposes the first conductive layer; filling the second etched hole and the third etched hole with conductive material to form a dummy conductive contact and a conductive contact, respectively; wherein the conductive contact is connected to the first conductive layer.

[0016] In some embodiments, forming the second conductive layer includes: forming a fourth dielectric layer covering the conductive structure, the dummy conductive contact, and the conductive contact; etching the fourth dielectric layer to form a third groove and a fourth groove, respectively; wherein the bottom of the third groove exposes the conductive structure and the dummy conductive contact, and the bottom of the fourth groove exposes the conductive contact; filling the third groove and the fourth groove with conductive material to form the second conductive layer and the third conductive layer, respectively; wherein the third conductive layer and the conductive contact are connected.

[0017] In some embodiments, after forming the second conductive layer, the method further includes: thinning the initial semiconductor layer to form a semiconductor layer and expose the conductive structure.

[0018] Thirdly, embodiments of this disclosure provide a packaging structure, the packaging structure comprising: a packaging substrate; a logic chip located on one side of the packaging substrate along a first direction, the logic chip including semiconductor devices as described in the above technical solutions; and a plurality of memory chips stacked along the first direction, the logic chip being located between the packaging substrate and the plurality of memory chips.

[0019] This disclosure provides a semiconductor device, its manufacturing method, and packaging structure. In this embodiment, the same second conductive layer is simultaneously connected to a conductive structure and a dummy conductive contact. While ensuring that the wiring layer in the back-end process can be fully utilized, the second conductive layer is fixed using a dummy first conductive layer and dummy conductive contacts, thus avoiding peeling between the conductive structure and the second conductive layer. Attached Figure Description

[0020] Figures 1 to 5 A cross-sectional structural diagram of a semiconductor device during the manufacturing process, provided as a first example;

[0021] Figures 6 to 10 A cross-sectional structural diagram of a semiconductor device during the manufacturing process, provided for the second example;

[0022] Figure 11 Top view of conductive pillars, first metal layer and second metal contact provided for some examples;

[0023] Figure 12 A schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure;

[0024] Figure 13 A top view of the conductive structure, dummy conductive contacts, and second conductive layer provided in an embodiment of this disclosure;

[0025] Figure 14 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0026] Figures 15 to 24 This disclosure provides a schematic cross-sectional view of a semiconductor device during its manufacturing process.

[0027] Figure 25 This is a schematic diagram of the packaging structure provided in an embodiment of the present disclosure. Detailed Implementation

[0028] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0029] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0030] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0031] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0032] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0033] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0034] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0035] Depending on the stage of the TSV fabrication process, TSVs can be classified as: First TSV, Middle TSV (MTSV), and Last TSV. First TSVs are formed by etching on a blank silicon wafer, Middle TSVs are formed by etching on a silicon wafer before the Back End of Line (BEOL) process, and Last TSVs are formed by etching on the back side of a thinned silicon wafer after the BEOL process.

[0036] Here, we first define the various directions that may be involved in the following text. The thickness direction of the substrate (or semiconductor layer) is defined as the first direction, which can also be called the vertical direction. A second direction is defined in the plane containing the substrate (or semiconductor layer), which can also be called the horizontal direction. The first and second directions are perpendicular to each other. The first direction can be the Z-direction shown in the following figures, and the second direction can be any direction perpendicular to the Z-direction, including either the X-direction or the Y-direction shown in the following figures.

[0037] refer to Figures 1 to 5 , Figures 1 to 5 This is a cross-sectional structural diagram of a semiconductor device during the manufacturing process, provided as a first example. The following will combine... Figures 1 to 5 The manufacturing method of the semiconductor device provided in the first example will be described.

[0038] like Figure 1As shown, a transistor structure 104 is formed on a substrate 102. The transistor structure 104 includes a source 106 and a drain 108 located in the substrate 102, and a gate 110 located on the substrate 102. The source 106 and the drain 108 are respectively located on opposite sides of the gate 110 along the X direction. A first insulating layer 112 is formed to cover the substrate 102 and the transistor structure 104. A source contact structure 114, a drain contact structure 116, and a gate contact structure 118 extending along the Z direction are formed in the first insulating layer 112. The source contact structure 114, the drain contact structure 116, and the gate contact structure 118 are respectively connected to the source 106, the drain 108, and the gate 110, and are respectively used to extract electrical signals from the source 106, the drain 108, and the gate 110 in the transistor structure 104.

[0039] here, Figure 1 The dashed circle in the middle illustrates the relative positional relationship between the source 106 and the drain 108. The channel region in the transistor structure 104 is located between the source 106 and the drain 108.

[0040] like Figure 2 As shown, a second insulating layer 120 is formed covering the first insulating layer 112; a plurality of first metal lines 122 are formed in the second insulating layer 120, and the first metal lines 122 penetrate the second insulating layer 120 along the Z direction; wherein, three of the first metal lines 122 are respectively connected to the source contact structure 114, the drain contact structure 116, and the gate contact structure 118.

[0041] Here, the materials of the first insulating layer 112 and the second insulating layer 120 can be the same or different. Figure 2 The dashed line is only used to illustrate the relative positional relationship between the first insulating layer 112 and the second insulating layer 120. In fact, when the materials of the first insulating layer 112 and the second insulating layer 120 are the same, there is no interface between the first insulating layer 112 and the second insulating layer 120.

[0042] like Figure 3 As shown, a third insulating layer 124 is formed covering the second insulating layer 120; a plurality of first metal contacts 126 are formed in the third insulating layer 124, and the first metal contacts 126 penetrate the third insulating layer 124 along the Z direction; wherein, three first metal contacts 126 are respectively connected to three first metal wires 122.

[0043] Here, the materials of the first insulating layer 112, the second insulating layer 120, and the third insulating layer 124 can be the same or different. Figure 3The dashed line is only used to illustrate the relative positional relationship between the first insulating layer 112, the second insulating layer 120, and the third insulating layer 124. In fact, when the materials of the first insulating layer 112, the second insulating layer 120, and the third insulating layer 124 are the same, there is no interface between the first insulating layer 112, the second insulating layer 120, and the third insulating layer 124.

[0044] like Figure 4 As shown, a fourth insulating layer 128 is formed covering the third insulating layer 124; an initial conductive post 134S is formed extending along the Z direction through the third insulating layer 124, the second insulating layer 120, the first insulating layer 112 and into the substrate 102; wherein the initial conductive post 134S and the substrate 102 are electrically isolated; and a fifth insulating layer 136 is formed covering the initial conductive post 134S.

[0045] Here, the bottom and sidewalls of the initial conductive pillar 134S are covered with an initial first barrier layer 132S, and the bottom and sidewalls of the initial first barrier layer 132S are covered with an initial padding layer 130S. The initial padding layer 130S electrically isolates the initial conductive pillar 134S from the substrate 102. The initial padding layer 130S, the initial first barrier layer 132S, and the initial conductive pillar 134S are sequentially included in the radial inward direction.

[0046] Here, the materials of the first insulating layer 112, the second insulating layer 120, the third insulating layer 124 and the initial padding layer 130S stacked along the Z direction can be the same or different. Figure 4 The dashed line is only used to illustrate the relative positional relationship between the first insulating layer 112, the second insulating layer 120, the third insulating layer 124, and the initial padding layer 130S. In fact, when the materials of the first insulating layer 112, the second insulating layer 120, the third insulating layer 124, and the initial padding layer 130S are the same, there is no interface between the first insulating layer 112, the second insulating layer 120, the third insulating layer 124, and the initial padding layer 130S.

[0047] like Figure 5 As shown, multiple first metal layers 140 (M1 Layer) are formed in the fourth insulating layer 128 and the fifth insulating layer 136; among them, a portion of the first metal layers 140 are connected to the first metal contacts 126, for example, three first metal layers 140 are respectively connected to three first metal contacts 126, and are used to lead out electrical signals to the source 106, drain 108 and gate 110 in the transistor structure 104; another portion of the first metal layers 140 are connected to the conductive pillars 134, and are used to lead out electrical signals to the conductive pillars 134.

[0048] Here, the bottom and sidewalls of the first metal layer 140 are covered with a second barrier layer 138.

[0049] It should be noted that during the formation of multiple first metal layers 140, a portion of the initial conductive pillars 134S, a portion of the initial first barrier layer 132S, and a portion of the pad layer 130 are etched away to form conductive pillars 134, first barrier layer 132, and pad layer 130, respectively. The height of the initial conductive pillars 134S, initial first barrier layer 132S, and pad layer 130 along the Z direction is reduced from the surface height of the fourth insulating layer 128 to the surface height of the third insulating layer 124.

[0050] Here, substrate 102 may include, but is not limited to, silicon.

[0051] Here, the first insulating layer 112, the second insulating layer 120, the third insulating layer 124, the fifth insulating layer 136, and the padding layer 130 may include, but are not limited to, silicon oxide (SiO2). The fourth insulating layer 128 may include, but is not limited to, silicon nitride (Si3N4).

[0052] Here, the source contact structure 114, drain contact structure 116, gate contact structure 118, first metal line 122 and first metal contact 126 may include, but are not limited to, titanium (Ti), tungsten (W) or titanium nitride (TiN).

[0053] Here, the conductive pillar 134 and the first metal layer 140 may include, but are not limited to, metallic copper (Cu).

[0054] Here, the first barrier layer 132 and the second barrier layer 138 may include, but are not limited to, tantalum (Ta) or tantalum nitride (TaN).

[0055] In the first example above, after completing the front end of line (FEOL) and contact structure, a first metal line 122 (W Metal Layer) and a first metal contact 126 (W Via Layer) made of tungsten are additionally introduced. The contact structure is then led out via the first metal line 122 and the first metal contact 126 to facilitate the extraction of electrical signals from the source 106, drain 108, and gate 110 in the transistor structure 104, respectively. Next, a copper conductive pillar 134 is formed, followed by a copper first metal layer 140. The conductive pillar 134 and the first metal layer 140 are connected. That is, the conductive pillar 134 rests on the first metal layer 140, and the connection point between the conductive pillar 134 and the first metal layer 140 is located on the first metal layer 140.

[0056] The above-mentioned signal output of transistor structure 104 requires the additional introduction of a first metal line 122 made of tungsten and a first metal contact 126 made of tungsten, which adds an extra process step to form the first metal line 122 and the first metal contact 126, increasing manufacturing costs.

[0057] refer to Figures 6 to 10 , Figures 6 to 10 This is a cross-sectional structural diagram of the semiconductor device during the manufacturing process, provided for the second example. The following will combine... Figures 6 to 10 The manufacturing method of the semiconductor device provided in the second example will be described.

[0058] like Figure 6 As shown, a transistor structure 204 is formed on a substrate 202. The transistor structure 204 includes a source 206 and a drain 208 located in the substrate 202, and a gate 210 located on the substrate 202. The source 206 and the drain 208 are respectively located on opposite sides of the gate 210 along the X direction. A first isolation layer 212 is formed to cover the substrate 202 and the transistor structure 204. A source contact structure 214, a drain contact structure 216, and a gate contact structure 218 extending along the Z direction are formed in the first isolation layer 212. The source contact structure 214, the drain contact structure 216, and the gate contact structure 218 are respectively connected to the source 206, the drain 208, and the gate 210, and are respectively used to extract electrical signals from the source 206, the drain 208, and the gate 210 in the transistor structure 204.

[0059] here, Figure 6 The dashed circle in the middle illustrates the relative positional relationship between the source 206 and the drain 208. The channel region in the transistor structure 204 is located between the source 206 and the drain 208.

[0060] like Figure 7 As shown, a second isolation layer 242 is formed covering the first isolation layer 212.

[0061] Here, the materials of the first isolation layer 212 and the second isolation layer 242 can be the same or different. Figure 7 The dashed line is only used to illustrate the relative positional relationship between the first isolation layer 212 and the second isolation layer 242. In fact, when the materials of the first isolation layer 212 and the second isolation layer 242 are the same, there is no interface between the first isolation layer 212 and the second isolation layer 242.

[0062] like Figure 8As shown, an initial conductive pillar is formed extending along the Z direction through the second isolation layer 242 and the first isolation layer 212 and into the substrate 202; the initial conductive pillar and the second isolation layer 242 are planarized to form a conductive pillar 234 and expose the first isolation layer 212.

[0063] Here, the bottom and sidewalls of the conductive post 234 are covered with a second barrier layer 238, and the bottom and sidewalls of the second barrier layer 238 are covered with a padding layer 230. The padding layer 230 electrically isolates the conductive post 234 from the substrate 202. The padding layer 230, the first barrier layer 232, and the conductive post 234 are sequentially arranged in the radial inward direction.

[0064] Here, the materials of the first isolation layer 212 and the padding layer 230 can be the same or different. Figure 8 The dashed line is only used to indicate the relative positional relationship between the first isolation layer 212 and the padding layer 230. In fact, when the materials of the first isolation layer 212 and the padding layer 230 are the same, there is no interface between the first isolation layer 212 and the padding layer 230.

[0065] like Figure 9 As shown, a third insulating layer 236 is formed covering the conductive pillar 234.

[0066] Here, the materials of the first isolation layer 212 and the third isolation layer 236 can be the same or different. Figure 9 The dashed line is only used to indicate the relative positional relationship between the first isolation layer 212 and the third isolation layer 236. In fact, when the materials of the first isolation layer 212 and the third isolation layer 236 are the same, there is no interface between the first isolation layer 212 and the third isolation layer 236.

[0067] like Figure 10 As shown, a plurality of first metal layers 240 are formed in the third isolation layer 236; among them, a portion of the first metal layers 240 are connected to contact structures, for example, three first metal layers 240 are respectively connected to the source contact structure 214, the drain contact structure 216, and the gate contact structure 218, and are used to lead out electrical signals to the source 206, the drain 208, and the gate 210 in the transistor structure 204; another portion of the first metal layers 240 are connected to conductive pillars 234, and are used to lead out electrical signals to the conductive pillars 234.

[0068] Here, the bottom and sidewalls of the first metal layer 240 are covered with a second barrier layer 238.

[0069] Here, substrate 202 may include, but is not limited to, silicon.

[0070] Here, the first isolation layer 212, the second isolation layer 242 and the third isolation layer 236 may include, but are not limited to, silicon oxide.

[0071] Here, the source contact structure 214, the drain contact structure 216, and the gate contact structure 218 may be, but are not limited to, titanium, tungsten, or titanium nitride.

[0072] Here, the conductive pillar 234 and the first metal layer 240 may include, but are not limited to, copper.

[0073] Here, the first barrier layer 232 and the second barrier layer 238 may include, but are not limited to, tantalum or tantalum nitride.

[0074] In the second example above, after completing the front-end process and contact structure, a second isolation layer 242 (e.g., silicon oxide) is formed as a buffer layer and a stop layer for planarizing the initial conductive pillars. Then, a copper conductive pillar 234 is formed, followed by a copper first metal layer 240. The conductive pillar 234 and the first metal layer 240 are connected. That is, the conductive pillar 234 rests on the first metal layer 240, and the connection point between the conductive pillar 234 and the first metal layer 240 is located on the first metal layer 240.

[0075] In the second example described above, firstly, the second isolation layer 242 (e.g., silicon oxide) can serve as a stop layer for planarizing the initial conductive pillars (e.g., chemical mechanical polishing, CMP). However, due to insufficient hardness of the silicon oxide, excessive CMP may occur, potentially affecting the transistor structure 204. Secondly, hydrogen ions from the first metal layer 240 (e.g., copper) and subsequent processes may diffuse into the transistor structure 204, potentially impacting its performance or reliability.

[0076] In both the first and second examples described above, the conductive pillars rest on the first metal layer. The thermal expansion coefficients of the materials of the conductive pillars (e.g., copper), the semiconductor layer (e.g., silicon), and the insulating or isolating layer (e.g., silicon oxide) are mismatched. When the temperature changes, these materials expand or contract to different degrees, generating thermomechanical stress inside and around the conductive pillars. This stress increases significantly with the height of the conductive pillar along the Z-direction and the cross-sectional dimension perpendicular to the Z-direction, potentially leading to film peeling between the first metal layer and the conductive pillars, thus affecting electrical performance.

[0077] refer to Figure 11 , Figure 11 A top view of the conductive pillars, the first metal layer, and the second metal contact provided for some examples. Figure 11 This can be viewed as a perspective view of the conductive pillar 334, the first metal layer 340, and the second metal contact 344. (Example) Figure 11As shown, the conductive post 334, the first metal layer 340, and the second metal contact 344 are arranged sequentially along the Z-direction. The conductive post 334 is connected to the first metal layer 340, and the first metal layer 340 is connected to the second metal contact 344. The second metal contact 344 is used to connect to the subsequently fabricated second metal layer (M2 Layer). The conductive post 334 can be referenced... Figure 5 The conductive post 134 shown in the diagram or Figure 10 The conductive pillar 234 and the first metal layer 340 shown in the diagram can be referenced. Figure 5 The first metal layer 140 shown is Figure 10 The first metal layer 240 is shown in the diagram.

[0078] In both the first and second examples described above, the conductive posts 334 are positioned on the first metal layer 340, and the second metal contacts 344 used to connect the first metal layer 340 and the second metal layer are distributed in a corner of the first metal layer. Furthermore, the number of second metal contacts 344 is relatively small; if any individual second metal contact 344 malfunctions, the connection between the first metal layer 340 and the second metal layer can easily be affected.

[0079] To address at least one of the aforementioned technical problems, this disclosure provides a semiconductor device, a method for manufacturing the same, and a packaging structure thereof.

[0080] refer to Figure 12 , Figure 12 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure. Figure 12 As shown, in a first aspect, embodiments of this disclosure provide a semiconductor device 400, comprising: a conductive structure 444 extending along the Z direction; a dummy first conductive layer 432 located on at least one side of the conductive structure 444 along the X direction (or, any direction perpendicular to the Z direction); a dummy conductive contact 458 located on at least one side of the conductive structure 444 along the X direction and also on one side of the dummy first conductive layer 432 along the Z direction; wherein the dummy conductive contact 458 is connected to the dummy first conductive layer 432; and a second conductive layer 470 located on one side of the conductive structure 444 along the Z direction, with the dummy conductive contact 458 located between the dummy first conductive layer 432 and the second conductive layer 470; wherein the same second conductive layer 470 is simultaneously connected to the conductive structure 444 and the dummy conductive contact 458.

[0081] In this embodiment, the same second conductive layer 470 is simultaneously connected to the conductive structure 444 and the dummy conductive contact 458. While ensuring that the wiring layer in the back-end process can be fully utilized, the dummy first conductive layer 432 and the dummy conductive contact 458 are used to fix the second conductive layer 470, thereby preventing the conductive structure 444 and the second conductive layer 470 from peeling off.

[0082] In some embodiments, the semiconductor device 400 further includes: a semiconductor layer 402, which is located on the side of the dummy first conductive layer 432 away from the dummy conductive contact 458, and a conductive structure 444 extends into the semiconductor layer 402; wherein the conductive structure 444 and the semiconductor layer 402 are electrically isolated.

[0083] Here, the conductive structure 444 includes a first end and a second end disposed opposite to each other along the Z direction, the first end and the second conductive layer 470 are connected, and the second end is located in the semiconductor layer 402.

[0084] In some embodiments, the semiconductor layer 402 specifically includes at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It may also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, etc. In this embodiment, the semiconductor layer 402 may include silicon.

[0085] In some embodiments, the semiconductor device 400 further includes: a device located on one side of the semiconductor layer 402 along the Z direction; and a contact structure located on one side of the device along the Z direction; wherein the contact structure and the device are connected.

[0086] This document uses a device including a transistor structure 404 and contact structures including a source contact structure 414, a drain contact structure 416, and a gate contact structure 418 as examples for illustration.

[0087] For example, the transistor structure 404 includes a source 406 and a drain 408 located in the semiconductor layer 402, and a gate 410 located above the semiconductor layer 402; wherein the source 406 and the drain 408 are respectively located on opposite sides of the gate 410 along the X direction, and the gate 410 is located in the first dielectric layer 412. Figure 12The dashed circle in the middle illustrates the relative positional relationship between the source 406 and the drain 408. The channel region in the transistor structure 404 is located between the source 406 and the drain 408.

[0088] For example, the contact structure includes a source contact structure 414, a drain contact structure 416, and a gate contact structure 418 located in the first dielectric layer 412; wherein the source contact structure 414, the drain contact structure 416, and the gate contact structure 418 are respectively connected to the source 406, the drain 408, and the gate 410, and are respectively used to extract electrical signals from the source 406, the drain 408, and the gate 410 in the transistor structure 404.

[0089] In some embodiments, the semiconductor device 400 further includes a gate dielectric layer located between the semiconductor layer 402 and the gate 410.

[0090] In some embodiments, the semiconductor device 400 further includes a first conductive layer 426, a conductive contact 452, and a third conductive layer 476 arranged sequentially along the Z direction, wherein the first conductive layer 426 is located between the contact structure and the conductive contact 452; wherein the device (e.g., transistor structure 404) is connected sequentially through the contact structure, the first conductive layer 426, the conductive contact 452, and the third conductive layer 476.

[0091] Here, transistor structure 404, source contact structure 414, drain contact structure 416, gate contact structure 418, first conductive layer 426, conductive contact 452, and third conductive layer 476 are all located on the same side of semiconductor layer 402 along the Z direction. Furthermore, all of these structures, along with the dummy first conductive layer 432, dummy conductive contact 458, and second conductive layer 470, are located on the same side of semiconductor layer 402 along the Z direction.

[0092] In some embodiments, the semiconductor device 400 further includes a first dielectric layer 412, a second dielectric layer 420, a third dielectric layer 438, and a fourth dielectric layer 464 stacked sequentially along the Z direction; wherein the first dielectric layer 412 is located between the semiconductor layer 402 and the second dielectric layer 420.

[0093] In some embodiments, the second dielectric layer 420 includes a first sub-dielectric layer 422 and a second sub-dielectric layer 424 stacked along the Z direction; wherein the first sub-dielectric layer 422 is located between the first dielectric layer 412 and the second sub-dielectric layer 424, and the hardness of the first sub-dielectric layer 422 is greater than that of the second sub-dielectric layer 424. Here, the first sub-dielectric layer 422 and the second sub-dielectric layer 424 are made of different materials; compared to the second sub-dielectric layer 424, the first sub-dielectric layer 422 has a greater hardness and a stronger ability to block the diffusion of conductive materials and hydrogen ions.

[0094] In some embodiments, the third dielectric layer 438 includes a third sub-dielectric layer 440 and a fourth sub-dielectric layer 442 stacked along the Z direction; wherein the third sub-dielectric layer 440 is located between the second dielectric layer 420 and the fourth sub-dielectric layer 442. Here, the third sub-dielectric layer 440 and the fourth sub-dielectric layer 442 are made of different materials. Compared with the fourth sub-dielectric layer 442, the third sub-dielectric layer 440 has greater hardness and a stronger ability to block the diffusion of conductive materials and hydrogen ions.

[0095] In some embodiments, the fourth dielectric layer 464 includes a fifth sub-dielectric layer 466 and a sixth sub-dielectric layer 468 stacked along the Z direction; wherein the fifth sub-dielectric layer 466 is located between the third dielectric layer 438 and the sixth sub-dielectric layer 468. Here, the fifth sub-dielectric layer 466 and the sixth sub-dielectric layer 468 are made of different materials. Compared with the sixth sub-dielectric layer 468, the fifth sub-dielectric layer 466 has greater hardness and a stronger ability to block the diffusion of conductive materials and hydrogen ions.

[0096] Here, the second dielectric layer 420, the third dielectric layer 438 and the fourth dielectric layer 464 are set as a composite dielectric layer, and the first sub-dielectric layer 422, the third sub-dielectric layer 440 and the fifth sub-dielectric layer 466 are used as an isolation layer to prevent the diffusion of subsequently deposited conductive materials (such as copper) and hydrogen ions into the transistor structure 404 and affect the performance of the transistor structure 404.

[0097] In some embodiments, the first dielectric layer 412, the second sub-dielectric layer 424, the fourth sub-dielectric layer 442, and the sixth sub-dielectric layer 468 may include, but are not limited to, silicon oxide.

[0098] In some embodiments, the first sub-dielectric layer 422, the third sub-dielectric layer 440, and the fifth sub-dielectric layer 466 may include, but are not limited to, silicon nitride or silicon nitride doped carbon (NDC).

[0099] In some embodiments, the device and the contact structure are both located in the first dielectric layer 412; the dummy first conductive layer 432 and the first conductive layer 426 are both located in the second dielectric layer 420, and the dummy first conductive layer 432 and the first conductive layer 426 both penetrate the second dielectric layer 420 along the Z direction; the dummy conductive contact 458 and the conductive contact 452 are both located in the third dielectric layer 438, and the dummy conductive contact 458 and the conductive contact 452 both penetrate the third dielectric layer 438 along the Z direction; the second conductive layer 470 and the third conductive layer 476 are both located in the fourth dielectric layer 464, and the second conductive layer 470 and the third conductive layer 476 both penetrate the fourth dielectric layer 464 along the Z direction.

[0100] In some embodiments, the dummy first conductive layer 432 includes a dummy first sub-conductive layer 434 and a dummy second sub-conductive layer 436. The dummy first sub-conductive layer 434 covers the sidewalls and bottom of the dummy second sub-conductive layer 436. A portion of the dummy first sub-conductive layer 434 is located between the dummy second sub-conductive layer 436 and the second dielectric layer 420, while the remaining portion of the dummy first sub-conductive layer 434 is located between the dummy second sub-conductive layer 436 and the first dielectric layer 412.

[0101] In some embodiments, the first conductive layer 426 includes a first sub-conductive layer 428 and a second sub-conductive layer 430. The first sub-conductive layer 428 covers the sidewalls and bottom of the second sub-conductive layer 430. A portion of the first sub-conductive layer 428 is located between the second sub-conductive layer 430 and the second dielectric layer 420, while other portions of the first sub-conductive layer 428 are located between the second sub-conductive layer 430 and the contact structure.

[0102] In some embodiments, the dummy conductive contact 458 includes a dummy first sub-conductive contact 460 and a dummy second sub-conductive contact 462. The dummy first sub-conductive contact 460 covers the sidewall and bottom of the dummy second sub-conductive contact 462. A portion of the dummy first sub-conductive contact 460 is located between the dummy second sub-conductive contact 462 and the third dielectric layer 438, while other portions of the dummy first sub-conductive contact 460 are located between the dummy second sub-conductive contact 462 and the dummy first conductive layer 432.

[0103] In some embodiments, the conductive contact 452 includes a first sub-conductive contact 454 and a second sub-conductive contact 456. The first sub-conductive contact 454 covers the sidewall and bottom of the second sub-conductive contact 456. A portion of the first sub-conductive contact 454 is located between the second sub-conductive contact 456 and the third dielectric layer 438, while other portions of the first sub-conductive contact 454 are located between the second sub-conductive contact 456 and the first conductive layer 426.

[0104] In some embodiments, the second conductive layer 470 includes a third sub-conductive layer 472 and a fourth sub-conductive layer 474. The third sub-conductive layer 472 covers the sidewalls and bottom of the fourth sub-conductive layer 474. A portion of the third sub-conductive layer 472 is located between the fourth sub-conductive layer 474 and the fourth dielectric layer 464, while other portions of the third sub-conductive layer 472 are located between the fourth sub-conductive layer 474 and the dummy conductive contact 458, the conductive structure 444, and the third dielectric layer 438.

[0105] In some embodiments, the third conductive layer 476 includes a fifth sub-conductive layer 478 and a sixth sub-conductive layer 480. The fifth sub-conductive layer 478 covers the sidewalls and bottom of the sixth sub-conductive layer 480. A portion of the fifth sub-conductive layer 478 is located between the sixth sub-conductive layer 480 and the fourth dielectric layer 464, while other portions of the fifth sub-conductive layer 478 are located between the sixth sub-conductive layer 480 and the conductive contact 452.

[0106] In some embodiments, the conductive structure 444 extends along the Z direction and penetrates the semiconductor layer 402, the first dielectric layer 412, the second dielectric layer 420, and the third dielectric layer 438. The conductive structure 444 includes a first sub-conductive structure 446 and a second sub-conductive structure 448. The first sub-conductive structure 446 covers the sidewall of the second sub-conductive structure 448 and is located between the second sub-conductive structure 448 and the semiconductor layer 402, the first dielectric layer 412, the second dielectric layer 420, and the third dielectric layer 438.

[0107] In some embodiments, the dummy first sub-conductive layer 434, the first sub-conductive layer 428, the dummy first sub-conductive contact 460, the first sub-conductive contact 454, the third sub-conductive layer 472, the fifth sub-conductive layer 478, and the first sub-conductive structure 446 may include, but are not limited to, tantalum or tantalum nitride.

[0108] In some embodiments, the dummy second sub-conductive layer 436, the second sub-conductive layer 430, the dummy second sub-conductive contact 462, the second sub-conductive contact 456, the fourth sub-conductive layer 474, the sixth sub-conductive layer 480, and the second sub-conductive structure 448 may include, but are not limited to, copper.

[0109] In some embodiments, the semiconductor device 400 further includes an isolation layer 450 covering the sidewalls of the conductive structure 444, and the isolation layer 450 being located between the conductive structure 444 and the semiconductor layer 402, the first dielectric layer 412, the second dielectric layer 420, and the third dielectric layer 438. Here, the isolation layer 450 can be used to achieve electrical isolation between the conductive structure 444 and the semiconductor layer 402.

[0110] In some embodiments, the isolation layer 450 may include, but is not limited to, silicon oxide. It should be noted that... Figure 12 The dashed lines in the middle indicate the relative positions of the isolation layer 450, the second sub-dielectric layer 424, the fourth sub-dielectric layer 442, and the sixth sub-dielectric layer 468. In fact, when the materials of the isolation layer 450, the second sub-dielectric layer 424, the fourth sub-dielectric layer 442, and the sixth sub-dielectric layer 468 are the same, there is no interface between the above material layers.

[0111] In some embodiments, the cross-sectional shape of the conductive contact 452, the dummy conductive contact 458, and the conductive structure 444 along the direction perpendicular to Z may include a circle, an ellipse, a triangle, a positive direction, or other shapes, etc., and this disclosure does not have any special limitations in this regard.

[0112] In some embodiments, the spacing between the first conductive layer 426 and the semiconductor layer 402 is the same as the spacing between the dummy first conductive layer 432 and the semiconductor layer 402, that is, the first conductive layer 426 and the dummy first conductive layer 432 are located at the same height along the Z direction. The spacing between the conductive contact 452 and the semiconductor layer 402 is the same as the spacing between the dummy conductive contact 458 and the semiconductor layer 402, that is, the conductive contact 452 and the dummy conductive contact 458 are located at the same height along the Z direction. The spacing between the second conductive layer 470 and the semiconductor layer 402 is the same as the spacing between the third conductive layer 476 and the semiconductor layer 402, that is, the second conductive layer 470 and the third conductive layer 476 are located at the same height along the Z direction.

[0113] In some embodiments, the dummy first conductive layer 432 and the first conductive layer 426 can be formed in the same process; the dummy conductive contact 458 and the conductive contact 452 can be formed in the same process; and the second conductive layer 470 and the third conductive layer 476 can be formed in the same process. This reduces the number of process steps and saves manufacturing costs.

[0114] In this embodiment, the transistor structure 404 can be electrically connected sequentially through a contact structure, a first conductive layer 426, a conductive contact 452, and a third conductive layer 476. All three can transmit electrical signals. Specifically, the first conductive layer 426 and the third conductive layer 476 transmit electrical signals horizontally, while the contact structure and the conductive contact 452 transmit electrical signals vertically. The conductive structure 444 can be electrically connected to the second conductive layer 470, and both can transmit electrical signals. The conductive structure 444 transmits electrical signals vertically, while the second conductive layer 470 transmits electrical signals horizontally. A dummy first conductive layer 432 can be connected to the second conductive layer 470 via a dummy conductive contact 458; however, the dummy first conductive layer 432 and the dummy conductive contact 458 do not actually transmit electrical signals.

[0115] Here, the dummy first conductive layer 432 and the first conductive layer 426 can also be referred to as the first metal layer (M1 Layer), and the second conductive layer 470 and the third conductive layer 476 can also be referred to as the second metal layer (M2 Layer). The dummy conductive contact 458 and the conductive contact 452 serve as a connecting via layer between two adjacent metal layers along the Z direction, and the conductive contact 452 and the dummy conductive contact 458 can also be referred to as the first connecting via layer (Via1).

[0116] It should be noted that the semiconductor device provided in this disclosure may include more metal layers and more interconnecting via layers, and two adjacent metal layers are connected by conductive contacts (or, interconnecting via layers).

[0117] refer to Figure 13 , Figure 13 This is a top view of the conductive structure, dummy conductive contacts, and second conductive layer provided in an embodiment of this disclosure. Figure 13 This can be viewed as a perspective view of the conductive structure 444, the dummy conductive contact 458, and the second conductive layer 470. For example... Figure 13 As shown, the conductive structure 444 is connected to the second conductive layer 470, and multiple dummy conductive contacts 458 are located around the conductive structure 444, and the dummy conductive contacts 458 are also connected to the second conductive layer 470. That is, the connection point between the conductive structure 444 and the second conductive layer 470 is located on the second conductive layer 470, and the connection point between the dummy conductive contacts 458 and the second conductive layer 470 is also located on the second conductive layer 470.

[0118] In some embodiments, the semiconductor device 400 further includes a plurality of dummy conductive contacts 458, which are arranged at intervals around the conductive structure 444. Here, the plurality of dummy conductive contacts 458 can be evenly arranged around the conductive structure 444, which helps to disperse the mechanical stress of the conductive structure 444, further strengthen the second conductive layer 470, and prevent peeling between the conductive structure 444 and the second conductive layer 470. This disclosure does not impose any special limitation on the arrangement of the dummy conductive contacts 458 around the conductive structure 444; the plurality of dummy conductive contacts 458 can surround the conductive structure 444 to form a circle, square, or other shapes.

[0119] In some embodiments, the cross-sectional dimension of the conductive structure 444 along the Z-direction is larger than the cross-sectional dimension of the dummy conductive contact 458 along the Z-direction.

[0120] In some embodiments, the number of dummy conductive contacts 458 may be increased; and / or, the cross-sectional area of ​​the dummy conductive contacts along the Z-direction may be increased. This further disperses the mechanical stress of the conductive structure 444 and reinforces the second conductive layer 470, preventing peeling between the conductive structure 444 and the second conductive layer 470.

[0121] This disclosure also provides a method for manufacturing the above-described semiconductor device. The method for manufacturing the semiconductor device also possesses the same technical effects as the described semiconductor device, and will not be elaborated further here.

[0122] refer to Figure 14 , Figure 14 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Figure 14 As shown, in a second aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising:

[0123] Step S510: Form a dummy first conductive layer;

[0124] Step S520: Form a conductive structure that extends along a first direction, and dummy first conductive layer is located on at least one side of the conductive structure along a second direction; wherein the first direction and the second direction are perpendicular to each other.

[0125] Step S530: Form a dummy conductive contact, the conductive contact being located on at least one side of the conductive structure along the second direction, and also on one side of the dummy first conductive layer along the first direction; wherein, the dummy conductive contact and the dummy first conductive layer are connected;

[0126] Step S540: Form a second conductive layer, which is located on one side of the conductive structure along the first direction, and the dummy conductive contact is located between the dummy first conductive layer and the second conductive layer; wherein, the same second conductive layer is simultaneously connected to the conductive structure and the dummy conductive contact.

[0127] refer to Figures 15 to 24 , Figures 15 to 24 This disclosure provides a cross-sectional structural diagram of a semiconductor device during its manufacturing process. The following will be combined with... Figure 14 and Figures 15 to 24 The present disclosure describes a method for manufacturing a semiconductor device according to embodiments thereof.

[0128] like Figure 15 As shown, in some embodiments, before step S510, the method further includes: providing a semiconductor structure, the semiconductor structure including an initial semiconductor layer 402S; a first dielectric layer 412 located on the initial semiconductor layer 402S; a device and a contact structure located on the initial semiconductor layer 402S and in the first dielectric layer 412; wherein the device and the contact structure are connected.

[0129] This document uses a device including a transistor structure 404 and contact structures including a source contact structure 414, a drain contact structure 416, and a gate contact structure 418 as examples for illustration.

[0130] For example, forming a transistor structure 404 may include the following steps: forming a gate dielectric material layer and a gate material layer covering an initial semiconductor layer 402S; forming a patterned photoresist layer covering the gate material layer; etching the gate material layer and the gate dielectric material layer using the patterned photoresist layer to form a gate dielectric layer and a gate 410; and doping the initial semiconductor layers on opposite sides of the gate 410 along the X direction to form a source 406 and a drain 408, respectively.

[0131] For example, forming a contact structure may include the following steps: forming a first dielectric layer 412 covering the initial semiconductor layer 402S and the gate 410; etching the first dielectric layer 412 to form a first contact hole, a second contact hole, and a third contact hole, wherein the bottom of the first contact hole exposes the source 406, the bottom of the second contact hole exposes the drain 408, and the bottom of the third contact hole exposes the gate 410; filling the first contact hole, the second contact hole, and the third contact hole with conductive material to form a source contact structure 414, a drain contact structure 416, and a gate contact structure 418, respectively, wherein the first dielectric layer 412 exposes the source contact structure 414, the drain contact structure 416, and the gate contact structure 418.

[0132] In some embodiments, the process for forming the first dielectric layer 412 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0133] In some embodiments, the etching process for forming the first contact hole, the second contact hole, and the third contact hole may include, but is not limited to, a dry etching process.

[0134] In this embodiment of the present disclosure, a dummy first conductive layer is formed in step S510.

[0135] like Figure 16 As shown, in some embodiments, step S510 includes forming a second dielectric layer 420 covering the first dielectric layer 412, the source contact structure 414, the drain contact structure 416, and the gate contact structure 418. For example, the first sub-dielectric layer 422 can be formed first, and then the second sub-dielectric layer 424 can be formed.

[0136] In some embodiments, the formation of the first sub-dielectric layer 422 and the second sub-dielectric layer 424 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0137] Still Figure 16 As shown, in some embodiments, step S510 further includes: etching the second dielectric layer 420 along the Z direction to form a first groove 602 and a second groove 604; wherein the bottom of the first groove 602 exposes the first dielectric layer 412, and the bottom of the second groove 604 exposes the contact structure. Figure 16 The diagram shows that the bottom of the two first grooves 602 exposes the first dielectric layer 412, and the bottom of the three second grooves 604 exposes the source contact structure 414, the drain contact structure 416, and the gate contact structure 418, respectively.

[0138] like Figure 17 As shown, in some embodiments, step S510 further includes: filling the first groove 602 and the second groove 604 with conductive material to form a dummy first conductive layer 432 and a first conductive layer 426, respectively; wherein the first conductive layer 426 is connected to the contact structure.

[0139] For example, forming a dummy first conductive layer 432 and a first conductive layer 426 may include the following steps: filling a first conductive material in a first groove 602 and a second groove 604 to form a dummy first sub-conductive layer 434 covering the sidewalls and bottom of the first groove 602 and a first sub-conductive layer 428 covering the sidewalls and bottom of the second groove 604; filling a second conductive material in a first groove 602 and a second groove 604 to form a dummy second sub-conductive layer 436 in the first groove 602 and a second sub-conductive layer 430 in the second groove 604, wherein the dummy second sub-conductive layer 436 fills the first groove 602 and the second sub-conductive layer 430 fills the second groove 604; wherein a second dielectric layer 420 exposes the first conductive layer 426 and the dummy first conductive layer 432.

[0140] Here, during the process of filling the first conductive material and the second conductive material into the first groove 602 and the second groove 604, excess first conductive material and second conductive material covering the surface of the second dielectric layer 420 can be removed by planarization to expose the second dielectric layer 420. Planarization may include, but is not limited to, CMP processing.

[0141] In some embodiments, forming a dummy first conductive layer 432 and a first conductive layer 426 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0142] In this embodiment of the present disclosure, in step S520, a conductive structure is formed, the conductive structure extends along a first direction, and a dummy first conductive layer is located on at least one side of the conductive structure along a second direction; wherein the first direction and the second direction are perpendicular to each other.

[0143] like Figure 18 As shown, in some embodiments, step S520 includes forming a third dielectric layer 438 covering the second dielectric layer 420, the first conductive layer 426, and the dummy first conductive layer 432. For example, the third sub-dielectric layer 440 can be formed first, and then the fourth sub-dielectric layer 442 can be formed.

[0144] In some embodiments, the formation of the third sub-dielectric layer 440 and the fourth sub-dielectric layer 442 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0145] Still Figure 18 As shown, in some embodiments, step S520 further includes etching the third dielectric layer 438, the second dielectric layer 420, the first dielectric layer 412 and the initial semiconductor layer 402S along the Z direction to form the first etched hole 610.

[0146] like Figure 19 As shown, in some embodiments, step S520 further includes: forming an isolation layer 450 covering the sidewalls and bottom of the first etched hole 610; filling the first etched hole 610 with conductive material to form a conductive structure 444; wherein the conductive structure 444 and the initial semiconductor layer 402S are electrically isolated from each other by the isolation layer 450.

[0147] For example, forming the conductive structure 444 may include the following steps: filling the first etched hole 610 with a first conductive material to form a first sub-conductive structure 446 covering the sidewalls and bottom of the first etched hole 610; filling the first etched hole 610 with a second conductive material to form a second sub-conductive structure 448, the second sub-conductive structure 448 filling the first etched hole 610; wherein, the third dielectric layer 438 exposes the conductive structure 444.

[0148] Here, during the process of filling the first conductive material and the second conductive material into the first etched hole 610, excess first conductive material and second conductive material covering the surface of the third dielectric layer 438 can be removed by planarization to expose the third dielectric layer 438. Planarization may include, but is not limited to, CMP processing.

[0149] In some embodiments, the formation of the isolation layer 450 and the conductive structure 444 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0150] In this embodiment of the present disclosure, in step S530, a dummy conductive contact is formed. The conductive contact is located on at least one side of the conductive structure along the second direction and also on one side of the dummy first conductive layer along the first direction; wherein the dummy conductive contact and the dummy first conductive layer are connected.

[0151] like Figure 20 As shown, in some embodiments, step S530 further includes: etching a third dielectric layer 438 along the Z direction to form a second etched hole 612 and a third etched hole 614; wherein the bottom of the second etched hole 612 exposes a dummy first conductive layer 432, and the bottom of the third etched hole 614 exposes a first conductive layer 426.

[0152] like Figure 21 As shown, in some embodiments, step S530 further includes: filling the second etched hole 612 and the third etched hole 614 with conductive material to form a dummy conductive contact 458 and a conductive contact 452, respectively; wherein the dummy conductive contact 458 is connected to the dummy first conductive layer 432, and the conductive contact 452 is connected to the first conductive layer 426.

[0153] For example, forming dummy conductive contacts 458 and conductive contacts 452 may include the following steps: filling the second etched hole 612 and the third etched hole 614 with a first conductive material to form a dummy first sub-conductive contact 460 covering the sidewalls and bottom of the second etched hole 612 and a first sub-conductive contact 454 covering the sidewalls and bottom of the third etched hole 614; filling the second etched hole 612 and the third etched hole 614 with a second conductive material to form a dummy second sub-conductive contact 462 in the second etched hole 612 and a second sub-conductive contact 456 in the third etched hole 614, wherein the dummy second sub-conductive contact 462 fills the second etched hole 612 and the second sub-conductive contact 456 fills the third etched hole 614; wherein the third dielectric layer 438 exposes the dummy conductive contacts 458 and conductive contacts 452.

[0154] Here, during the process of filling the second etched hole 612 and the third etched hole 614 with the first conductive material and the second conductive material, excess first conductive material and second conductive material covering the surface of the third dielectric layer 438 can be removed by planarization to expose the third dielectric layer 438. Planarization may include, but is not limited to, CMP processing.

[0155] In some embodiments, forming dummy conductive contacts 458 and conductive contacts 452 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0156] In this embodiment of the present disclosure, in step S540, a second conductive layer is formed. The second conductive layer is located on one side of the conductive structure along the first direction, and the dummy conductive contact is located between the dummy first conductive layer and the second conductive layer. The second conductive layer is simultaneously connected to the conductive structure and the dummy conductive contact.

[0157] like Figure 22 As shown, in some embodiments, step S540 includes forming a fourth dielectric layer 464 covering the third dielectric layer 438, the conductive structure 444, the dummy conductive contact 458, and the conductive contact 452. For example, a fifth sub-dielectric layer 466 can be formed first, followed by the formation of a sixth sub-dielectric layer 468.

[0158] In some embodiments, the formation of the fifth sub-dielectric layer 466 and the sixth sub-dielectric layer 468 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0159] Still Figure 22 As shown, in some embodiments, step S540 includes: etching the fourth dielectric layer 464 along the Z direction to form the third groove 606 and the fourth groove 608; wherein the bottom of the third groove 606 exposes the dummy conductive contact 458, the conductive structure 444 and the third dielectric layer 438, and the bottom of the fourth groove 608 exposes the conductive contact 452.

[0160] like Figure 23 As shown, in some embodiments, step S570 includes: filling the third groove 606 and the fourth groove 608 with conductive material to form a second conductive layer 470 and a third conductive layer 476, respectively; wherein the same second conductive layer 470 is simultaneously connected to the dummy conductive contact 458 and the conductive structure 444, and the third conductive layer 476 is connected to the conductive contact 452.

[0161] For example, forming the second conductive layer 470 and the third conductive layer 476 may include the following steps: filling the third groove 606 and the fourth groove 608 with a first conductive material to form a third sub-conductive layer 472 covering the sidewalls and bottom of the third groove 606 and a fifth sub-conductive layer 478 covering the sidewalls and bottom of the fourth groove 608; filling the third groove 606 and the fourth groove 608 with a second conductive material to form a fourth sub-conductive layer 474 in the third groove 606 and a sixth sub-conductive layer 480 in the fourth groove 608, wherein the fourth sub-conductive layer 474 fills the third groove 606 and the sixth sub-conductive layer 480 fills the fourth groove 608; wherein the fourth dielectric layer 464 exposes the second conductive layer 470 and the third conductive layer 476.

[0162] Here, during the process of filling the third groove 606 and the fourth groove 608 with the first conductive material and the second conductive material, excess first conductive material and second conductive material covering the surface of the fourth dielectric layer 464 can be removed by planarization to expose the fourth dielectric layer 464. The planarization process may include, but is not limited to, CMP processing.

[0163] In some embodiments, the etching process for forming the first groove 602, the second groove 604, the third groove 606, the fourth groove 608, the first etched hole 610, the second etched hole 612 and the third etched hole 614 includes, but is not limited to, dry etching process.

[0164] In some embodiments, the formation of the second conductive layer 470 and the third conductive layer 476 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0165] like Figure 24 As shown, in some embodiments, the method further includes thinning the initial semiconductor layer 402S to form the semiconductor layer 402 and expose the second end of the conductive structure 444. Here, the conductive structure 444 can serve as part of a vertical conductive channel, for example, through which an electrical signal can be applied.

[0166] In some embodiments, the thinning process may include, but is not limited to, CMP processing.

[0167] In this embodiment of the disclosure, after the front-end process and the contact structure process are completed, firstly, a second dielectric layer 420 is formed, especially a first sub-dielectric layer 422 (e.g., silicon nitride or carbon-doped silicon nitride) as an isolation layer between the back-end process and the back-end process to prevent conductive materials (e.g., copper) and hydrogen ions in the back-end process from diffusing to the transistor structure 404; then, the back-end process is entered, and the first conductive layer 426 and the dummy first conductive layer 432 are fabricated through photolithography, etching, deposition and CMP processing, etc.; in the design, some dummy first conductive layers 432 can be set around the conductive structure 444 as a structure to reinforce the dummy conductive contacts 458.

[0168] After the first conductive layer 426 and the dummy first conductive layer 432 are fabricated, a third dielectric layer 438 is introduced using a deposition process, especially a third sub-dielectric layer 440 (e.g., silicon nitride or carbon-doped silicon nitride); then, the conductive structure 444 is fabricated by photolithography, etching, deposition and CMP processing.

[0169] After the conductive structure 444 is fabricated, conductive contacts 452 and dummy conductive contacts 458 are completed through photolithography, etching, deposition, and CMP processes. The first conductive layer 426 is connected through the conductive contacts 452. The dummy first conductive layer 432 surrounding the conductive structure 444 can also be connected through the dummy conductive contacts 458. The second conductive layer 470 and the third conductive layer 476 are completed through photolithography, etching, deposition, and CMP processes. The second conductive layer 470 is connected to the dummy conductive contacts 458 and the conductive structure 444, and the third conductive layer 476 is connected to the conductive contacts 452. Among these, while meeting design rules, the larger the size of the dummy conductive contacts 458, the larger the contact area between the dummy conductive contacts 458 and the second conductive layer 470, and the better the reinforcement effect.

[0170] refer to Figure 25 , Figure 25 This is a schematic diagram of the packaging structure provided in an embodiment of this disclosure. Figure 25 As shown, in a third aspect, embodiments of this disclosure provide a packaging structure 700, which includes: a packaging substrate 702; a logic chip 704 (Logic Die), also known as a base chip, the logic chip 704 being located on one side of the packaging substrate 702 along the Z direction, the logic chip 704 including the aforementioned semiconductor device; and a plurality of memory chips 706 stacked along the Z direction, the logic chip 704 being located between the packaging substrate 702 and the plurality of memory chips 706.

[0171] Here, the package substrate 702 may include, for example, a printed circuit board (PCB). The logic chip 704 can act as a "bridge" between the package structure and external devices, performing signal conversion, command parsing, and data buffering. The memory chip 706 may include, for example, dynamic random access memory (DRAM). Two adjacent memory chips 706 can be electrically connected via microbumps.

[0172] In some embodiments, the package structure 700 further includes an interposer 708, which is located between the package substrate 702 and the logic chip 704. Here, the interposer 708 can be connected to the package substrate 702 via package bumps.

[0173] In some embodiments, the above-described package structure 700 further includes a controller 710, which is located above the interposer layer 708. Here, the logic chip 704 and the controller 710 include a physical layer interface, and data can be transmitted between the logic chip 704 and the controller 710 through the interposer layer 708. The controller 710 may include, for example, a central processing unit (CPU) or a graphics processing unit (GPU).

[0174] In some embodiments, the package structure 700 may include high-bandwidth memory (HBM).

[0175] In this embodiment of the disclosure, the conductive structure can be a mid-section TSV in a logic chip. A mid-section TSV in a logic chip refers to a TSV manufactured after the front-end transistor structure portion is manufactured and before or between the rear-end metal wiring layer. For example... Figure 12 The conductive structure 444 is illustrated in the diagram. In process flow design, MTSV is typically connected to the first or second metal layer, for example, Figure 12 The diagram illustrates the connection between conductive structure 444 and the second metal layer. A vertical conductive channel can be established using MTSV, making full use of all metal wiring layers in the back-end process.

[0176] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0177] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a conductive structure extending along a first direction; a dummy first conductive layer located at least one side of the conductive structure along a second direction; wherein the first direction and the second direction are perpendicular to each other; a dummy conductive contact located at least one side of the conductive structure along the second direction and also located at one side of the dummy first conductive layer along the first direction; wherein the dummy conductive contact and the dummy first conductive layer are connected; a second conductive layer located at one side of the conductive structure along the first direction and the dummy conductive contact is located between the dummy first conductive layer and the second conductive layer; wherein the same second conductive layer is connected with the conductive structure and the dummy conductive contact.

2. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: a semiconductor layer located at one side of the dummy first conductive layer away from the dummy conductive contact, and the conductive structure extends into the semiconductor layer; wherein the conductive structure and the semiconductor layer are electrically isolated.

3. The semiconductor device of claim 2, wherein, The semiconductor device further comprises: a device located at one side of the semiconductor layer along the first direction; a contact structure located at one side of the device along the first direction; wherein the contact structure and the device are connected; a first conductive layer, a conductive contact and a third conductive layer arranged in sequence along the first direction, the first conductive layer is located between the contact structure and the conductive contact; wherein the device is connected in sequence through the contact structure, the first conductive layer, the conductive contact and the third conductive layer.

4. The semiconductor device according to claim 3, wherein The semiconductor device further comprises: a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer stacked along the first direction; wherein the first dielectric layer is located between the semiconductor layer and the second dielectric layer, the device and the contact structure are located in the first dielectric layer, the dummy first conductive layer and the first conductive layer are located in the second dielectric layer, the dummy conductive contact and the conductive contact are located in the third dielectric layer, and the second conductive layer and the third conductive layer are located in the fourth dielectric layer.

5. The semiconductor device of claim 4, wherein, The second dielectric layer comprises: a first sub-dielectric layer and a second sub-dielectric layer stacked along the first direction; wherein the first sub-dielectric layer is located between the first dielectric layer and the second sub-dielectric layer, and the hardness of the first sub-dielectric layer is greater than that of the second sub-dielectric layer.

6. The semiconductor device of claim 1, wherein The semiconductor device further comprises: a plurality of dummy conductive contacts, which are arranged at intervals around the conductive structure.

7. The semiconductor device of claim 1, wherein The cross-sectional dimension of the conductive structure perpendicular to the first direction is greater than the cross-sectional dimension of the dummy conductive contact perpendicular to the first direction.

8. A method of manufacturing a semiconductor device, characterized by The method comprises: forming a dummy first conductive layer; forming a conductive structure extending along a first direction, and the dummy first conductive layer is located at least one side of the conductive structure along a second direction; wherein the first direction and the second direction are perpendicular to each other; forming a dummy conductive contact, the dummy conductive contact being located at least one side of the conductive structure along the second direction and also being located at one side of the dummy first conductive layer along the first direction; wherein the dummy conductive contact and the dummy first conductive layer are connected; forming a second conductive layer, the second conductive layer being located at one side of the conductive structure along the first direction and the dummy conductive contact being located between the dummy first conductive layer and the second conductive layer; wherein the same second conductive layer is connected with the conductive structure and the dummy conductive contact.

9. The production method according to claim 8, wherein Before the forming of the dummy first conductive layer, the method further comprises: providing a semiconductor structure, the semiconductor structure comprising an initial semiconductor layer, a first dielectric layer located on the initial semiconductor layer, a device and a contact structure located in the first dielectric layer; wherein the device and the contact structure are connected.

10. The manufacturing method according to claim 9, wherein The forming of the dummy first conductive layer comprises: forming a second dielectric layer covering the first dielectric layer; etching the second dielectric layer to form a first recess and a second recess; wherein the bottom of the first recess exposes the first dielectric layer and the bottom of the second recess exposes the contact structure; filling conductive material in the first recess and the second recess to form a dummy first conductive layer and a first conductive layer respectively; wherein the first conductive layer and the contact structure are connected.

11. The manufacturing method according to claim 10, wherein The forming of the conductive structure comprises: forming a third dielectric layer covering the dummy first conductive layer and the first conductive layer; etching the third dielectric layer, the second dielectric layer, the first dielectric layer and the initial semiconductor layer to form a first etching hole; forming an isolation layer covering the side wall and the bottom of the first etching hole; filling conductive material in the first etching hole to form a conductive structure.

12. The manufacturing method according to claim 11, wherein The forming of the dummy conductive contact comprises: etching the third dielectric layer to form a second etching hole and a third etching hole; wherein the bottom of the second etching hole exposes the dummy first conductive layer and the bottom of the third etching hole exposes the first conductive layer; filling conductive material in the second etching hole and the third etching hole to form a dummy conductive contact and a conductive contact respectively; wherein the conductive contact and the first conductive layer are connected.

13. The manufacturing method according to claim 12, wherein The forming of the second conductive layer comprises: forming a fourth dielectric layer covering the conductive structure, the dummy conductive contact and the conductive contact; etching the fourth dielectric layer to form a third recess and a fourth recess respectively; wherein the bottom of the third recess exposes the conductive structure and the dummy conductive contact and the bottom of the fourth recess exposes the conductive contact; filling conductive material in the third recess and the fourth recess to form a second conductive layer and a third conductive layer respectively; wherein the third conductive layer and the conductive contact are connected.

14. The manufacturing method according to claim 9, wherein After the forming of the second conductive layer, the method further comprises: performing a thinning process on the initial semiconductor layer to form a semiconductor layer and expose the conductive structure.

15. A package structure, comprising: The packaging structure comprises: a packaging substrate; a logic chip located on one side of the package substrate along a first direction, the logic chip including the semiconductor device according to any one of claims 1 to 7; a plurality of memory chips stacked along the first direction, the logic chip being located between the package substrate and the plurality of memory chips.

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