Memory chip and chip stacking structure

Abstract

The invention provides a storage chip and a chip stacking structure, the storage chip comprises a storage unit, an interconnection area and a non-functional area arranged in the storage chip, a plurality of first silicon through holes penetrating through the storage chip are formed in the interconnection area, and the first silicon through holes are formed in the non-functional area. The first through silicon vias are used for providing interconnection channels for logic chips stacked above the memory chips. The logic chip is arranged above the storage chip, and heat generated by the logic chip can be directly transmitted to the heat dissipation layer, so that the heat dissipation efficiency is greatly improved; a logic chip above a memory chip is electrically connected to a substrate below the memory chip by arranging an interconnection region with a silicon through hole.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a storage chip and a chip stacking structure. BACKGROUND

[0002] With the rapid iteration of artificial intelligence, high-performance computing, and consumer electronics, the computing power density of main logic chips (such as AI chips, computing power chips, mobile phone / computer main chips, etc.) continues to rise, and the connection efficiency of main logic chips and cache memories (DRAM / pSRAM, etc.) is required to have high bandwidth, low latency, low cost, and optimal heat dissipation. The current industry mainstream connection and packaging schemes mainly include: 3D / 2.5D hybrid bonding packaging of HBM and main chips, GDDR / DDR6 discrete packaging, and TSV-equipped DRAM wafer / chip stacking packaging, all of which have technical bottlenecks that are difficult to break through and cannot fully adapt to the scene requirements, as follows: For 3D / 2.5D hybrid bonding packaging of HBM and main chips, HBM is stacked through multiple layers of DRAM wafers, combined with first through silicon vias (TSVs) to achieve high-density interconnection in the vertical direction. Although it has a significant advantage in bandwidth, the complex process design results in high costs, and the wafer surface flatness and bonding precision are extremely high, making it difficult to improve yield. For GDDR / DDR6 discrete packaging, which is the mainstream choice for low-end computing power scenarios, the main chip and the cache chip are independently packaged, and then connected through wires on the PCB for signal and power transmission. The packaging process is simple, but its fatal flaw is that the transmission bandwidth is limited and the delay is high, which can only barely meet the needs of low-end computing power products. For TSV-equipped DRAM wafer / chip stacking packaging, TSV-equipped DRAM is used as the cache, and the wafer-to-wafer stacking process is used to stack the DRAM directly above the main logic chip. TSV is used as a vertical interconnection channel to enable direct signal transmission between the internal layers of the DRAM and the main chip. It performs excellently in bandwidth and delay, and has lower process complexity than HBM hybrid bonding. However, since the DRAM is stacked above the main chip, the heat dissipation path of the main chip is blocked, and the heat of the main chip cannot be quickly dissipated to the external heat dissipation structure, which will eventually lead to high-temperature failure of the main chip. SUMMARY

[0003] In view of the problems in the prior art described above, the present application provides a storage chip and a chip stacking structure.

[0004] To achieve the above object and other related objects, one aspect of the present application provides a storage chip, comprising a functional area and a non-functional area, the storage chip comprising: a storage unit, disposed in the functional area; An interconnection region is arranged in the non-functional region, and a plurality of first through silicon vias are formed in the interconnection region and penetrate the memory chip, and the first through silicon vias are used to provide an interconnection channel for a logic chip stacked above the memory chip.

[0005] Optionally, the interconnection region is arranged on at least one side of the memory unit.

[0006] Optionally, the interconnection region is arranged on two adjacent sides of the memory unit and has an L-shaped layout.

[0007] Optionally, the memory unit further comprises a plurality of second through silicon vias, and the second through silicon vias are used to electrically connect the memory array and the logic chip.

[0008] Another aspect of the present application provides a chip stacking structure, comprising: a substrate, in which an interconnection circuit is formed; a memory chip arranged on the substrate, the memory chip comprising a memory unit and an interconnection region, and the interconnection region comprising a plurality of first through silicon vias; a logic chip arranged on a side of the memory chip away from the substrate, the logic chip comprising an I / O interface, the I / O interface being arranged corresponding to the interconnection region, and the I / O interface being electrically connected to the substrate through the first through silicon vias of the memory chip.

[0009] Optionally, the chip stacking structure comprises a plurality of memory chips arranged side by side on the substrate, and the interconnection regions of the plurality of memory chips are cooperatively distributed and correspond to the I / O interface of the logic chip.

[0010] Optionally, the I / O interface of the logic chip has a cross-shaped distribution. The chip stacking structure comprises four memory chips, and the interconnection regions of the four memory chips are arranged on two adjacent sides of the memory unit and have an L-shaped distribution. The interconnection regions of the memory chips are spliced to form a cross-shaped interconnection region, and the cross-shaped interconnection region corresponds to the I / O interface.

[0011] Optionally, a redistribution layer is arranged between the memory chip and the logic chip, and the redistribution layer is used to electrically connect the I / O interface of the logic chip to the first through silicon vias of the interconnection region.

[0012] Optionally, a second through silicon via is arranged in the memory chip, and the second through silicon via is used to electrically connect the memory array and the logic chip.

[0013] The storage chip and the manufacturing method thereof, the chip stacking structure and the manufacturing method thereof provided by the application have at least the following beneficial technical effects: The storage chip of the application forms an interconnection area in the non-functional area of the storage chip, and a plurality of through silicon vias are arranged in the interconnection area.

[0014] The chip stacking structure of the application arranges the logic chip above the storage chip, and the heat generated by the logic chip can be directly transmitted to the heat dissipation layer, greatly improving the heat dissipation efficiency. The interconnection area with through silicon vias is arranged to electrically connect the logic chip above the storage chip to the substrate below, and there is no electrical connection between the interconnection area and the storage unit. The interconnection area is located in the non-functional area of the storage chip, and the interconnection area will not affect the storage capacity of the storage unit. The number of through silicon vias in the interconnection area can be adjusted according to the I / O interface of the logic chip, and can be specifically configured as a power via, a ground via and a signal transmission via. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A storage chip structure provided by embodiment one is shown.

[0016] Figure 2 A first storage chip structure provided by embodiment one is shown.

[0017] Figure 3 A second storage chip structure provided by embodiment one is shown.

[0018] Figure 4 A third storage chip structure provided by embodiment one is shown.

[0019] Figure 5 A chip stacking structure provided by embodiment two is shown.

[0020] Figure 6 A structure diagram showing the bonding of the storage chip and the logic chip is shown.

[0021] Reference signs: 10, storage chip; 11, storage unit; 12, interconnection area; 13, first through silicon via; 131, insulating layer; 14, first interconnection structure; 15, second through silicon via; 20, substrate; 21, logic chip; 211, second interconnection structure; 212, I / O interface; 22, redistribution layer. DETAILED DESCRIPTION

[0022] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0023] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components, the shape, quantity, positional relationship and proportion of each component can be arbitrarily changed under the premise of realizing the technical solution of this invention, and the layout of the components may also be more complex.

[0024] Example 1 This embodiment provides a memory chip, such as Figure 1 As shown, the memory chip 10 of this embodiment includes a functional area and a non-functional area. The functional area is provided with memory cells 11, and the non-functional area is provided with an interconnect area 12. The interconnect area 12 is located outside the memory cells 11, and a plurality of first through silicon vias 13 are formed in the interconnect area 12, which penetrate the memory chip 10. The first through silicon vias 13 are used to provide interconnect channels for logic chips stacked on top of the memory chip 10.

[0025] Generally, the storage cell 11 is the core functional area of ​​the storage chip 10. The storage chip 10 integrates multiple storage cells 11 arranged in an array. Specifically, the storage chip 10 includes n×m storage cells 11, where n and m are integers greater than or equal to 1, and n and m can be equal. Figure 1 As shown, in this embodiment, the memory chip 10 is described as having 2×2 memory units 11.

[0026] Interconnect region 12 is located in the gap area between two adjacent memory cells 11. Generally, interconnect region 12 is located in the scribe line area and / or surrounding area of ​​memory chip 10, making full use of the gap area of ​​memory chip 10. The scribe line area and / or surrounding area itself does not contain active circuitry, and the arrangement of the first through-silicon via can improve the utilization rate of chip area.

[0027] Specifically, such as Figure 2 As shown, this embodiment provides a schematic diagram of a first type of memory chip structure. Generally, the memory cell 11 has a square or rectangular structure, and the side length of a single memory cell 11 is between 500 μm and 2000 μm. Generally, the interconnect region 12 is located around the memory cell 11, and the interconnect region 12 is continuously distributed along the perimeter of the memory cell 11 to form a closed frame; optionally, as... Figure 3As shown, the second storage chip structure provided by the embodiment is shown in the schematic diagram; the interconnection area 12 is located on one side of the storage unit 11; optionally, as shown in the figure Figure 4 As shown, the third storage chip structure provided by the embodiment is shown in the schematic diagram; the interconnection area 12 is located on both sides of the storage unit 11, and the storage chip 10 is in a square structure, so the interconnection area 12 is in an L-shaped layout. Specifically, the width of the interconnection area 12 is between 100 μm and 500 μm, and the specific width is adjusted according to the number of TSVs required. The more the number of TSVs, the wider the width of the interconnection area 12.

[0028] Since the interconnection area 12 is located in the gap area of the storage unit 11 of the storage chip 10, it will not conflict with the functional circuit inside the storage unit 11. Generally, the number of first through silicon vias 13 in the interconnection area 12 is between 10 and 10,000. Specifically, the number of first through silicon vias 13 is set according to actual functional requirements. Generally, the first through silicon via 13 is configured as a power via, a ground via, or a signal transmission via.

[0029] Specifically, an insulating layer 131 is also formed in the sidewall of the first through silicon via 13. The material of the insulating layer 131 includes silicon dioxide or silicon nitride. Generally, the overall thickness of the storage chip 10 is between 50 μm and 100 μm.

[0030] The interconnection area is formed in the non-functional area of the storage chip, a plurality of through silicon vias are arranged in the interconnection area, and the layout of the interconnection area can be adjusted according to the logic chip to meet the interconnection requirements in different scenarios.

[0031] The embodiment provides a storage chip manufacturing method, which comprises the following steps: S1: providing a wafer, and dividing a storage unit area and an interconnection area on the wafer according to the position of an I / O interface in a logic chip, wherein the interconnection area corresponds to the position of the I / O interface in the logic chip; S2: forming a storage unit in the storage unit area; S3: etching in the interconnection area to form a blind hole; S4: depositing an insulating layer on the inner wall of the blind hole and filling a conductive material; S5: thinning the back of the wafer until the conductive material is exposed, thereby forming a first through silicon via penetrating through the wafer.

[0032] Specifically, the storage unit area and the interconnection area are divided on the wafer according to the position and size of the I / O interface 212 in the logic chip 21. For the logic chip 21 using a peripheral layout I / O interface 212, the I / O interface 212 is concentrated on the edge of the chip. Therefore, the interconnection area 12 of the lower storage chip 10 should be correspondingly planned on the periphery or one side / two sides of the storage unit 11 (as shown in the figure Figure 3、 Figure 4 As shown in FIG. 1, the interconnection region 12 of the memory chip 10 is arranged in a ring layout to ensure the vertical alignment of the first TSV 13 and the I / O interface 212 above, forming an efficient connection path; for high-performance logic chips (such as GPU, AI processing unit) using array layout I / O, the I / O interfaces 212 are evenly distributed on the entire bottom surface of the chip. At this time, the interconnection region 12 of the memory chip 10 below optimally adopts a ring layout (as shown in FIG. 2), which can maximize the docking of the array I / O interface 212 of the logic chip above, providing extremely high interconnection density and bandwidth. In order to shorten the key information line, the I / O interfaces 212 are concentratedly distributed on the central region of the logic chip 21, including cross-shaped arrangement, linear arrangement, for such logic chip 21, the interconnection region 12 on the memory chip 10 adopts a distributed splicing strategy, for the central cross-shaped arrangement of the I / O interface 212, the interconnection region 12 of the memory chip 10 below is arranged in an L shape (as shown in FIG. 3), which splices the interconnection region 12 into a cross-shaped structure; for the central linear arrangement of the I / O interface 212, the interconnection region 12 of the memory chip 10 below is arranged in a single-sided arrangement (as shown in FIG. 4). Figure 2 As shown in FIG. 1, the interconnection region 12 of the memory chip 10 is arranged in a ring layout to ensure the vertical alignment of the first TSV 13 and the I / O interface 212 above, forming an efficient connection path; for high-performance logic chips (such as GPU, AI processing unit) using array layout I / O, the I / O interfaces 212 are evenly distributed on the entire bottom surface of the chip. At this time, the interconnection region 12 of the memory chip 10 below optimally adopts a ring layout (as shown in FIG. 2), which can maximize the docking of the array I / O interface 212 of the logic chip above, providing extremely high interconnection density and bandwidth. In order to shorten the key information line, the I / O interfaces 212 are concentratedly distributed on the central region of the logic chip 21, including cross-shaped arrangement, linear arrangement, for such logic chip 21, the interconnection region 12 on the memory chip 10 adopts a distributed splicing strategy, for the central cross-shaped arrangement of the I / O interface 212, the interconnection region 12 of the memory chip 10 below is arranged in an L shape (as shown in FIG. 3), which splices the interconnection region 12 into a cross-shaped structure; for the central linear arrangement of the I / O interface 212, the interconnection region 12 of the memory chip 10 below is arranged in a single-sided arrangement (as shown in FIG. 4). Figure 4 As shown in FIG. 1, the interconnection region 12 of the memory chip 10 is arranged in a ring layout to ensure the vertical alignment of the first TSV 13 and the I / O interface 212 above, forming an efficient connection path; for high-performance logic chips (such as GPU, AI processing unit) using array layout I / O, the I / O interfaces 212 are evenly distributed on the entire bottom surface of the chip. At this time, the interconnection region 12 of the memory chip 10 below optimally adopts a ring layout (as shown in FIG. 2), which can maximize the docking of the array I / O interface 212 of the logic chip above, providing extremely high interconnection density and bandwidth. In order to shorten the key information line, the I / O interfaces 212 are concentratedly distributed on the central region of the logic chip 21, including cross-shaped arrangement, linear arrangement, for such logic chip 21, the interconnection region 12 on the memory chip 10 adopts a distributed splicing strategy, for the central cross-shaped arrangement of the I / O interface 212, the interconnection region 12 of the memory chip 10 below is arranged in an L shape (as shown in FIG. 3), which splices the interconnection region 12 into a cross-shaped structure; for the central linear arrangement of the I / O interface 212, the interconnection region 12 of the memory chip 10 below is arranged in a single-sided arrangement (as shown in FIG. 4). Figure 3 As shown in FIG. 1, the interconnection region 12 of the memory chip 10 is arranged in a ring layout to ensure the vertical alignment of the first TSV 13 and the I / O interface 212 above, forming an efficient connection path; for high-performance logic chips (such as GPU, AI processing unit) using array layout I / O, the I / O interfaces 212 are evenly distributed on the entire bottom surface of the chip. At this time, the interconnection region 12 of the memory chip 10 below optimally adopts a ring layout (as shown in FIG. 2), which can maximize the docking of the array I / O interface 212 of the logic chip above, providing extremely high interconnection density and bandwidth. In order to shorten the key information line, the I / O interfaces 212 are concentratedly distributed on the central region of the logic chip 21, including cross-shaped arrangement, linear arrangement, for such logic chip 21, the interconnection region 12 on the memory chip 10 adopts a distributed splicing strategy, for the central cross-shaped arrangement of the I / O interface 212, the interconnection region 12 of the memory chip 10 below is arranged in an L shape (as shown in FIG. 3), which splices the interconnection region 12 into a cross-shaped structure; for the central linear arrangement of the I / O interface 212, the interconnection region 12 of the memory chip 10 below is arranged in a single-sided arrangement (as shown in FIG. 4).

[0033] Specifically, forming the memory cell 11 in the memory cell region includes specific steps of forming a gate oxide, an active region, a word line, a bit line, and an electrode, etc. Please refer to the prior art, and the present embodiment will not be described in detail.

[0034] Specifically, step S3, etching in the interconnection region to form a blind hole; coating photoresist on the passivation layer of the extension region, the thickness of the photoresist is between 5-10 μm, the position and diameter of the blind hole are defined by photolithography, the diameter of the blind hole is between 1-10 μm, and the distance between two adjacent blind holes is between 5-20 μm, and the area of the passivation layer to be etched is exposed after development. Specifically, the position of the blind hole corresponds to the I / O interface 212 one by one.

[0035] Specifically, step S4, depositing an insulating layer 131 on the inner wall of the blind hole and filling a conductive material; the material of the insulating layer 131 includes silicon dioxide or silicon nitride. Optionally, a barrier layer and a seed layer are deposited on the insulating layer 131. Specifically, step S5, thinning the back surface of the wafer to expose the conductive material, forming a first TSV 13 penetrating through the wafer.

[0036] Optionally, the step of forming a second TSV 15 in the memory chip 10 can be completed synchronously with the formation of the first TSV 13.

[0037] Embodiment Two The present embodiment provides a chip stacking structure, as shown in FIG. 6. Figure 5As shown, the chip stacking structure of the embodiment includes a substrate 20, a memory chip 10 and a logic chip 21. The memory chip 10 includes the memory chip as described in Embodiment One, and is located on the substrate 20. The memory chip 10 includes a memory unit 11 and an interconnection region 12, and the interconnection region 12 includes a plurality of first through silicon vias 13. The logic chip 21 is located on the side of the memory chip 10 away from the substrate 20, and includes an I / O interface 212 corresponding to the interconnection region 12. The I / O interface 212 is electrically connected to the substrate 20 through the first through silicon vias 13 of the memory chip 10.

[0038] The substrate 20 serves as a support base for the stacking structure, and is internally provided with complex interconnection lines, such as Figure 3 As shown, the substrate 20 includes a ball grid array, and the memory chip 10 and the logic chip 21 are connected to the lines in the substrate 20 through the ball grid array. The substrate 20 provides mechanical support, power distribution and external signal interaction for the entire stack.

[0039] The memory chip 10 is located on the packaging substrate 20. Optionally, the memory chip 10 adopts the structure as described in Embodiment One, i.e., includes a memory unit 11 and an interconnection region 12. The front side (i.e., the active circuit side) of the memory chip 10 is flip-chip bonded on the substrate 20 through a first interconnection structure 14. The TSV interconnection region 12 is provided with a plurality of first through silicon vias 13. The first through silicon vias 13 can be configured as power vias, ground vias, signal transmission vias (for transmitting various I / O signals such as data, clock and control) according to their functional requirements. Specifically, an insulating layer 131 is deposited on the sidewall of each first through silicon via 13.

[0040] Generally, the size of the logic chip 21 is greater than that of the memory chip 10. One logic chip 21 is bonded with at least one memory chip 10. Optionally, one logic chip 21 is bonded with two memory chips 10; optionally, one logic chip 21 is bonded with three memory chips 10. Generally, the area of the logic chip 21 is between 300 mm 2 ~600 mm 2Generally, one logic chip 21 needs to be configured with 4 memory chips 10, which are arranged in the plane of the active area. In the traditional 3D stacking scheme, directly stacking multiple small-sized memory chips on the logic chip will leave a blank area on the surface of the logic chip that is not covered by the memory chips, resulting in wafer area waste. The present application places the memory chips 10 under the logic chip 21 and re-plans the layout of the memory chips 10 to convert the above-mentioned blank area into a functional interconnection area 12 in the plane of the memory chips 10. Specifically, the interconnection area 12 is mainly located in the scribe lane and the peripheral area of the memory chip 10. A high-density (e.g. 100 to 10,000) first through-silicon via 13 is made in this area. The first through-silicon via 13 serves as a vertical interconnection channel and undertakes the task of delivering power supply, ground, and transmitting high-speed I / O signals for the upper logic chip 21. The logic chip 21 is located on the side of the memory chip 10 away from the substrate 20, and a heat dissipation device can be provided on the side of the logic chip 21 away from the substrate 20. The heat dissipated by the logic chip 21 can be dissipated without passing through the memory chip 10, which is conducive to improving the heat dissipation of the logic chip 21.

[0041] As shown in Figure 5 , the chip stacking structure in the present embodiment includes one logic chip 21 and four memory chips 10. The I / O interface 212 of the logic chip 21 is distributed in a cross shape, and the interconnection areas 12 on the four memory chips 10 are located on the two sides adjacent to the memory units 11, respectively, and are distributed in an L shape. The memory units 11 of the four memory chips 10 are spliced into a cross-shaped interconnection area, which corresponds to the I / O interface 212.

[0042] The second through-silicon via 15 is formed inside the memory chip 10, which is located inside the memory chip 10 and is used to realize the electrical connection between the internal circuit of the memory chip 10 and the logic chip 21.

[0043] Optionally, a redistribution layer 22 is also formed between the logic chip 21 and the memory chip 10. The redistribution layer 22 is located on the back of the memory chip 10, i.e. the side that exposes the first through-silicon via 13 after grinding and thinning. The redistribution layer 22 is composed of a dielectric layer and a metal wiring, and its purpose is to re-arrange and fan out the electrical connection of the I / O interface 212 (usually with small pitch and concentrated distribution) of the upper logic chip 21, so that it can be accurately aligned with the first through-silicon via 13 on the back of the lower memory chip 10 and the interconnection points for direct communication.

[0044] Optionally, the side of the logic chip 21 close to the memory chip 10 also includes a second interconnection structure 211.

[0045] The stack structure provided by the embodiment forms a double-path interconnection. The first path is: part of the I / O interface 212 (including a signal transmission interface, a power supply, etc.) of the logic chip 21 enters the re-distribution layer 22 through the second interconnection structure 211, then vertically passes through the memory chip 10 via the first through-silicon via 13 in the interconnection area 12, and is connected to the packaging substrate 20 through the first interconnection structure 14. This path solves the problem that the signals of the logic chip 21 cannot be directly transmitted downward when the logic chip 21 is on the upper part of the memory chip 10. The second path is: the logic chip 21 is directly connected with the second through-silicon via 15 through the second interconnection structure 211 and the re-distribution layer 22, so as to realize data exchange between the logic chip 21 and the memory chip 10. The transmission distance of the second path is relatively short, and the second path is suitable for high-bandwidth communication.

[0046] Optionally, a heat dissipation layer is formed on the side of the logic chip 21 away from the substrate 20. The heat generated by the logic chip 21 can be directly transmitted to the heat dissipation layer.

[0047] The logic chip is arranged above the memory chip. The heat generated by the logic chip can be directly transmitted to the heat dissipation layer, greatly improving the heat dissipation efficiency. The interconnection area with the through-silicon via is arranged to electrically connect the logic chip above the memory chip to the substrate below. The interconnection area is not electrically connected with the memory unit. The interconnection area is located in the non-functional area of the memory chip, and the interconnection area does not affect the storage capacity of the memory unit. The number of the through-silicon via in the interconnection area can be adjusted according to the I / O interface of the logic chip, and the through-silicon via can be configured as a power supply via, a grounding via, or a signal transmission via.

[0048] The embodiment provides a manufacturing method of a chip stack structure, and specifically includes the following steps. S1: providing a wafer, and preparing a plurality of memory chips on the wafer, wherein the memory chip includes a memory unit and an interconnection area, and a plurality of first through-silicon vias are formed in the interconnection area; S2: thinning the back of the wafer to expose the first through-silicon via; S3: providing a logic chip, wherein the logic chip includes an I / O interface; S4: bonding the memory chip and the logic chip, so that the I / O interface of the logic chip is electrically connected with the first through-silicon via in the interconnection area; Specifically, the step of manufacturing the memory chip includes the manufacturing method of the memory chip in the embodiment three, which will not be described here.

[0049] As Figure 6As shown, a structure diagram showing the bonding of the memory chips and the logic chip is shown, and the interconnection region of the memory chip is bonded with the I / O interface; specifically, according to the size of the logic chip and the memory chip, one logic chip bonds at least one memory chip, and in the embodiment, one logic chip bonds four memory chips is taken as an example.

[0050] Generally, the I / O interfaces 212 of the logic chip 21 are not uniformly distributed or limited to the edge, and in the embodiment, a cross-shaped arrangement is taken as an example, and the I / O resources are concentrated on the central region and the symmetry axis of the logic chip 2, the global interconnection delay is shortened, and the power supply network is optimized. The I / O interfaces 212 of the logic chip 21 are arranged in a cross shape, and therefore the interconnection region 12 of the memory chip 10 is arranged corresponding to the position of the I / O interface 212 of the logic chip 21, and the interconnection region 12 of the memory chip 10 is arranged on the adjacent two sides of the chip in an L shape, and the interconnection regions 12 of the four memory chips 10 form a cross-shaped arrangement corresponding to the position of the I / O interface 212 of the logic chip 21.

[0051] Specifically, the specific steps of bonding the memory chip 10 with the logic chip 21 include: aligning the side of the logic chip 21 having the I / O interface 212 with the four memory chips 10 (still on the wafer or already mounted on the substrate) below which the re-distribution layer has been prepared with high precision. Ensure that each I / O point of the logic chip is accurately aligned with the first through silicon via 13 in the interconnection region 12 of the memory chip below. The logic chip 21 and the memory chip 10 are bonded together through advanced processes such as thermal compression bonding or hybrid bonding. The structure after bonding is as shown in Figure 1 As shown, the I / O signals, power and ground of the logic chip 21 can be directly connected to the first through silicon via 13 of the memory chip 10 through micro-bumps, and then vertically conducted to the packaging substrate. For the method of forming a re-distribution layer, bonding, etc., please refer to the prior art.

[0052] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A memory chip comprising a functional area and a non-functional area, characterized in that, The storage chip comprises: a storage unit comprising a storage array and a peripheral circuit, the storage unit being arranged in the functional area; an interconnection area arranged in the non-functional area, the interconnection area being insulated from the storage unit, a plurality of first through silicon vias penetrating the storage chip being formed in the interconnection area, the first through silicon vias being used to provide an interconnection channel for a logic chip stacked above the storage chip.

2. The memory chip of claim 1, wherein, The interconnection area is arranged at least on one side of the storage unit.

3. The memory chip of claim 1, wherein, The interconnection area is arranged on two sides adjacent to the storage unit, in an L-shaped layout.

4. The memory chip of claim 1, wherein, The storage unit further comprises a plurality of second through silicon vias, the second through silicon vias being used to electrically connect the storage array and the logic chip.

5. A chip stack structure, characterized by Comprise: a substrate with interconnection lines formed inside; a storage chip on the substrate, the storage chip comprising a storage unit and an interconnection area, the interconnection area comprising a plurality of first through silicon vias; a logic chip on a side of the storage chip away from the substrate, the logic chip comprising an I / O interface, the I / O interface being arranged corresponding to the interconnection area, the I / O interface being electrically connected to the substrate through the first through silicon vias of the storage chip.

6. The chip stack structure of claim 5, wherein, The chip stacking structure comprises a plurality of storage chips arranged side by side on the substrate, the interconnection areas of the plurality of storage chips being cooperatively distributed corresponding to the I / O interface of the logic chip.

7. The chip stacking structure of claim 6, wherein: the I / O interface of the logic chip is distributed in a cross shape; the chip stacking structure comprises four storage chips, the interconnection areas of the four storage chips being arranged on two sides adjacent to the storage unit in an L-shaped distribution; the interconnection areas of the storage chips are spliced to form a cross-shaped interconnection area corresponding to the I / O interface.

8. The chip stack structure of claim 5, wherein, Further comprising a rewiring layer between the storage chip and the logic chip, the rewiring layer being used to electrically connect the I / O interface of the logic chip to the first through silicon vias of the interconnection area.

9. The chip stack structure of claim 5, wherein, Further comprising a second through silicon via in the storage chip, the second through silicon via being used to electrically connect the storage array and the logic chip.

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