QFN packaging chip

Abstract

The invention provides a QFN packaging chip, and belongs to the technical field of packaging. The QFN packaging chip comprises a packaging body, a lead frame, a bare chip, four rows of first packaging bonding pads and at least one group of enhanced packaging bonding pads. The lead frame and the bare chip are packaged in the packaging body, and the grounding bonding pad of the bare chip is electrically connected with the lead frame. Each group of enhanced packaging pads is located at a corner of the bottom of the packaging body, each group of enhanced packaging pads comprises a first enhanced packaging pad and a second enhanced packaging pad, and the distance between the first enhanced packaging pad and the vertex of the corner is greater than the distance between the second enhanced packaging pad and the vertex. The first enhanced packaging bonding pad is electrically connected with the lead frame, and the second enhanced packaging bonding pad is electrically connected with the lead frame or is in signal suspension. The second enhanced packaging bonding pad is closer to the vertex, so that the second enhanced packaging bonding pad can protect the first enhanced packaging bonding pad, the welding reliability of the first enhanced packaging bonding pad is improved, and the reliability of the QFN packaging chip is further improved.

Description

Technical Field

[0001] This disclosure relates to the field of packaging technology, and in particular to a QFN packaged chip. Background Technology

[0002] Quad flat no-lead (QFN) packaged chips are square or rectangular. The bottom of the QFN packaged chip has four rows of pads on its four sides. These pads are used to solder to pads on a printed circuit board (PCB) to achieve fixation and electrical connection between the QFN packaged chip and the PCB.

[0003] When a QFN packaged chip is subjected to stress, the four corners of the bottom of the QFN packaged chip are prone to cracking, which reduces the reliability of the QFN packaged chip. Summary of the Invention

[0004] This disclosure provides a quad flat no-lead package (QFN) chip. The bottom corners of the QFN chip include a first and a second reinforced package pad arranged at intervals. These first and second reinforced package pads improve the soldering strength of the corners of the QFN chip, thereby enhancing its reliability. The technical solution for the QFN chip is described below.

[0005] This disclosure provides a QFN packaged chip. The QFN packaged chip includes a package body, a lead frame, a bare die, four rows of first package pads, and at least one set of reinforcement package pads. The lead frame and the bare die are packaged in the package body, and the ground pad of the bare die is electrically connected to the lead frame. The four rows of first package pads are located on the four sides of the bottom of the package body, and the first package pads are electrically connected to the signal pads or ground pads of the bare die. Each set of reinforcement package pads is located at one corner of the bottom of the package body. Each set of reinforcement package pads includes at least a first reinforcement package pad and a second reinforcement package pad, and the distance from the first reinforcement package pad to the vertex of the corner is greater than the distance from the second reinforcement package pad to the vertex. The first reinforcement package pad is electrically connected to the lead frame, and the second reinforcement package pad is either electrically connected to the lead frame or left floating.

[0006] The package is a plastic encapsulation. The leadframe forms the skeleton of the QFN packaged chip and is used to electrically connect the various grounded package pads together. A bare die refers to an unpackaged chip, also known as a die or bare die. A bare die includes pads, which are used to make electrical connections between the bare die and the leadframe or package pads (such as the first package pad). The pads of a bare die include ground pads and signal pads. The ground pads are used for grounding, and the signal pads are used for transmitting high-speed signals. If at least a portion of the ground pads of the bare die are electrically connected to the leadframe, the leadframe is grounded, and the package pads (such as the reinforced package pads) connected to the leadframe are grounded.

[0007] Four rows of first-package pads are exposed on the four sides of the bottom of the package, used to fix and electrically connect the QFN packaged chip to the printed circuit board (PCB). The first-package pads are divided into signal package pads and ground package pads. The signal package pads are electrically connected to the signal pads of the bare chip for transmitting high-speed signals. The ground package pads are electrically connected to the ground pads of the bare chip to ensure signal return and prevent signal crosstalk. The ground package pads can be electrically connected to the ground pads of the bare chip by connecting the ground package pads to the lead frame (e.g., through an integrated connection or via an electrical connection wire). Reinforcement package pads are exposed at the bottom corners of the package for soldering to pads on the PCB.

[0008] In the technical solution provided in this disclosure, each group of reinforced packaging pads includes at least a first reinforced packaging pad and a second reinforced packaging pad arranged at intervals. The probability of both the first and second reinforced packaging pads cracking simultaneously is low. Furthermore, because the first and second reinforced packaging pads are arranged at intervals, cracking of one reinforced packaging pad will not directly lead to cracking of the other. This improves the reliability of the reinforced packaging pad soldering, thereby improving the reliability of the reinforced packaging pads in protecting the first packaging pad, and in other words, improving the reliability of the first packaging pad soldering.

[0009] Furthermore, since the first reinforced package pad is electrically connected to the lead frame, it is grounded. This allows the first reinforced package pad to also ensure signal return and reduce crosstalk. Moreover, because the second reinforced package pad is closer to the corner apex of the package than the first reinforced package pad, it generally cracks before the first reinforced package pad. In other words, the second reinforced package pad can protect the first reinforced package pad, which improves the reliability of the first reinforced package pad's grounding.

[0010] In one possible implementation, the second reinforced package pad is electrically connected to the lead frame. Thus, the second reinforced package pad is grounded, and it also serves to ensure signal return and reduce signal crosstalk. Furthermore, since both the first and second reinforced package pads are grounded, if one reinforced package pad (such as the second reinforced package pad) cracks, the other reinforced package pad (such as the first reinforced package pad) can still prevent signal crosstalk from the first package pad near the corner.

[0011] In one possible implementation, the side length of the QFN packaged chip is greater than or equal to 10 mm and less than or equal to 14 mm.

[0012] In one possible implementation, the QFN packaged chip has dimensions of 10mm×10mm, 11mm×11mm, 12mm×12mm, 13mm×13mm, or 14mm×14mm.

[0013] In one possible implementation, the leadframe includes a main frame and at least one branch frame. A bare die is fixed to the main frame, and the ground pad of the bare die is electrically connected to the main frame. One end of each branch frame is connected to the main frame, and the other end extends towards a corner of the package. At least two regions of the branch frame are exposed at the bottom of the package, and these at least two regions form at least a first reinforced package pad and a second reinforced package pad. That is, the first and second reinforced package pads are integrally formed with the leadframe. The leadframe is made of metal.

[0014] In one possible implementation, the two first package pads closest to the first enhanced package pad are designated as the first edge package pad and the second edge package pad. The first edge package pad and the second edge package pad are located on two adjacent sides of the package body. A first reference line is tangent to both the first edge package pad and the second edge package pad, and the first edge package pad and the second edge package pad are located on the side of the first reference line closer to its vertex. The first reference line intersects with the first enhanced package pad. Both the first edge package pad and the second edge package pad are signal package pads.

[0015] The technical solution provided in this disclosure, when the second reinforced package pad cracks, the first edge package pad, the second edge package pad, and the first reinforced package pad are simultaneously subjected to stress. Therefore, the first edge package pad, the second edge package pad, and the first reinforced package pad assist each other, improving the reliability of their soldering. Furthermore, it also facilitates the first reinforced package pad in reducing signal crosstalk between the first edge package pad and the second edge package pad.

[0016] It should be noted that if the second reinforced package pad cracks, and any one of the first edge package pads, second edge package pads, or first reinforced package pads also cracks, the QFN packaged chip will become unusable. Specifically, cracking of the first and second edge package pads results in signal loss, while cracking of the first reinforced package pad renders the QFN packaged chip unusable due to severe signal crosstalk. Therefore, the first edge package pad, second edge package pad, and first reinforced package pad are all equally important.

[0017] In one possible implementation, the first reinforced package pad is located on the side of the first reference line closer to the vertex. Thus, generally speaking, the first reinforced package pad will crack before the first edge package pad and the second edge package pad; that is, the first reinforced package pad can protect the first edge package pad and the second edge package pad.

[0018] In one possible implementation, the first and second reinforced package pads are located diagonally at the bottom of the package. This results in more even stress distribution on the QFN package chip, reducing the likelihood of cracking of the package pads due to uneven stress.

[0019] In one possible implementation, the reinforced package pads further include a third and a fourth reinforced package pad. The third and fourth reinforced package pads are located on opposite sides of a diagonal line, and are electrically connected to the lead frame or left floating. The distance from the third and fourth reinforced package pads to the vertex of their respective corners is less than the distance from the vertex of the first reinforced package pad. In this way, the second, third, and fourth reinforced package pads can all protect the first reinforced package pad, achieving a "multiple protections for one" effect, significantly reducing the possibility of cracking of the first reinforced package pad, and thus improving the reliability of the grounding of the first reinforced package pad.

[0020] Furthermore, this disclosure increases the reinforced area of ​​the reinforcing pads by using multiple small-area reinforced package pads spaced apart in a corner, compared to using a large-area reinforced package pad in the corner. This is because, to prevent solder from the reinforced package pads from crossing onto the first package pad, a minimum gap is required between the reinforced package pads and the first package pad. The larger the area of ​​the reinforced package pad, the greater the amount of solder required, necessitating a larger gap. Therefore, compared to a large-area reinforced package pad, the small-area reinforced package pads can be closer to the first package pad, thereby increasing the area of ​​the reinforced region.

[0021] In one possible implementation, the third and fourth reinforced package pads are electrically connected to the lead frame. Thus, as long as one of the first, second, third, or fourth reinforced package pads remains grounded, signal crosstalk can be prevented, ensuring the signal integrity of the QFN packaged chip.

[0022] In one possible implementation, the third reinforced package pad is located on the first side of the bottom of the package, and the fourth reinforced package pad is located on the second side of the bottom of the package. The distance between the third reinforced package pad and the second side (away from the second side) is less than 1 mm, and the distance between the fourth reinforced package pad and the first side (away from the first side) is less than 1 mm. This ensures that the third and fourth reinforced package pads are close to their corresponding sides, allowing the four rows of first package pads to be arranged normally as if there were no reinforced package pads in the corners of the package, without needing to remove some first package pads to obtain a sufficiently large corner area for multiple reinforced package pads. In other words, the arrangement of the reinforced package pads does not occupy the resources of the first package pads (signal package pads). However, since the closer to the corner vertex, the greater the possibility of package pad cracking, it is generally required that the distance between the first package pad and its corresponding side be greater than 1 mm.

[0023] In one possible implementation, the distance between the third reinforced package pad and the second side on the side furthest from the second side is less than 0.95 mm, and the distance between the fourth reinforced package pad and the first side on the side furthest from the first side is less than 0.95 mm.

[0024] In one possible implementation, the second reference line is tangent to both the third and fourth reinforced package pads, with the second and fourth reinforced package pads located on the side of the second reference line closer to its vertex. The first and second reinforced package pads are positioned on opposite sides of the second reference line. Thus, the predetermined cracking sequence is that the second reinforced package pad cracks first, followed by the third and fourth reinforced package pads, and finally the first reinforced package pad cracks last.

[0025] In one possible implementation, the QFN packaged chip further includes four rows of second package pads, located within the area enclosed by four rows of first package pads and respectively opposite to the four rows of first package pads. The second package pads are electrically connected to the signal pads or ground pads of the bare chip. A third reference line extends along the row direction of the second package pads and is tangent to the side of the second package pad furthest from the first package pads. A fourth reference line extends along the row direction of the second package pads and is tangent to the side of the second package pad closest to the first package pads. At least a portion of the first enhanced package pad is located between the third and fourth reference lines. Thus, the first enhanced package pad can also reduce signal crosstalk of the second package pads.

[0026] In one possible implementation, each set of reinforced package pads includes one first reinforced package pad and two second reinforced package pads. The first reinforced package pad is located on the bottom diagonal of the package, and the two second reinforced package pads are located on either side of the diagonal.

[0027] In one possible implementation, each set of reinforced package pads includes two first reinforced package pads and one second reinforced package pad. The second reinforced package pad is located on the bottom diagonal of the package, and the two first reinforced package pads are located on either side of the diagonal.

[0028] In one possible implementation, the QFN package chip includes four sets of reinforced package pads, located at the four corners of the bottom of the package. This ensures high reliability of soldering at all four corners of the QFN package chip. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a QFN packaged chip in related technologies;

[0030] Figure 2 This is a schematic diagram of the top of a QFN packaged chip provided in an embodiment of this disclosure;

[0031] Figure 3 yes Figure 2 The diagram shows the internal structure of the QFN packaged chip.

[0032] Figure 4 This is a schematic diagram of the bottom of a QFN packaged chip provided in an embodiment of this disclosure;

[0033] Figure 5 yes Figure 4 The diagram shows the internal structure of the QFN packaged chip.

[0034] Figure 6 This is a schematic diagram of the internal structure of a QFN packaged chip provided in an embodiment of this disclosure;

[0035] Figure 7 This is a schematic diagram of the bottom of a QFN packaged chip provided in an embodiment of this disclosure;

[0036] Figure 8 This is a partial schematic diagram of a corner of a QFN packaged chip provided in an embodiment of this disclosure;

[0037] Figure 9 This is a partial schematic diagram of a corner of a QFN packaged chip provided in an embodiment of this disclosure;

[0038] Figure 10 This is a partial schematic diagram of a corner of a QFN packaged chip provided in an embodiment of this disclosure;

[0039] Figure 11 This is a partial schematic diagram of a corner of a QFN packaged chip provided in an embodiment of this disclosure;

[0040] Figure 12 This is a partial schematic diagram of a corner of a QFN packaged chip provided in an embodiment of this disclosure;

[0041] Figure 13 This is a partial schematic diagram of a corner of another QFN packaged chip provided in an embodiment of this disclosure;

[0042] Figure 14 This is a partial schematic diagram of a corner of another QFN packaged chip provided in an embodiment of this disclosure;

[0043] Figure 15 This is a partial schematic diagram of a corner of another QFN packaged chip provided in an embodiment of this disclosure;

[0044] Figure 16 This is a three-dimensional schematic diagram of a lead frame provided in an embodiment of this disclosure;

[0045] Figure 17 This is a three-dimensional schematic diagram of a branch frame of a lead frame provided in an embodiment of this disclosure.

[0046] Legend

[0047] 1. Encapsulation body; 10. Vertex; 11. First edge; 12. Second edge;

[0048] 2. Lead frame, 21. Main frame, 22. Branch frame, 220. Opening, 221. Main branch frame, 222. Sub-branch frame;

[0049] 3. Bare chip; 31. Ground pad; 32. Signal pad;

[0050] 4. First package pad; 41. First edge package pad; 42. Second edge package pad;

[0051] 5. Enhanced package pad; 51. First enhanced package pad; 52. Second enhanced package pad; 53. Third enhanced package pad; 54. Fourth enhanced package pad;

[0052] 6. Second package pad;

[0053] 7. Center pad;

[0054] A. First reference line, B. Second reference line, C. Third reference line, D. Fourth reference line, E. Fifth reference line, F. Sixth reference line, G. Seventh reference line, X. Diagonal line. Detailed Implementation

[0055] Quad flat no-lead package (QFN) chips have short internal conductive paths, low self-inductance, and low internal wiring resistance, thus providing superior electrical performance and making them suitable for high-speed signal applications such as 10G LTE-DES. Figure 1 As shown, the QFN packaged chip is square or rectangular. The bottom of the QFN packaged chip has four rows of first package pads 4 on its four sides. The four rows of first package pads 4 are used to solder to the pads on the printed circuit board (PCB) to achieve the fixation and electrical connection between the QFN packaged chip and the PCB.

[0056] Because the pads at the four corners of the bottom of a QFN packaged chip are prone to cracking, related technologies typically use a first package pad 4 that avoids these four corners. Simultaneously, a large-area reinforcing package pad 5 is provided at each of the four corners. The reinforcing package pads 5 protect the first package pad 4, thereby improving the reliability of the soldering of the first package pad 4.

[0057] However, the technical solutions in the related technologies have at least the following technical problems. First, in some solutions, the signal of the enhanced package pad 5 is left floating, only used to protect the first package pad 4. However, this occupies the package pad resources of the QFN package chip. Furthermore, although the area of ​​the enhanced package pad 5 is large, the enhanced package pad 5 is still highly likely to crack. This is because if a part of the enhanced package pad 5 cracks, it will quickly lead to the cracking of the entire enhanced package pad 5.

[0058] Second, in some designs, the reinforced package pad 5 is grounded. However, since the reinforced package pad 5 is located in the bottom corner of the packaged chip, it is still highly likely to crack. If the grounded reinforced package pad 5 cracks, signal return cannot be guaranteed, leading to severe signal crosstalk on the first package pads 4 located on either side of the reinforced package pad 5, causing the QFN packaged chip to malfunction.

[0059] In view of the above-mentioned technical problems, this disclosure provides a QFN packaged chip. Figure 2 This is a schematic diagram of the top of a QFN packaged chip provided in an embodiment of this disclosure. Figure 3 yes Figure 2 The diagram shows the internal structure of the QFN packaged chip. Figure 4 This is a schematic diagram of the bottom of a QFN packaged chip provided in an embodiment of this disclosure. Figure 5 yes Figure 4 The diagram shows the internal structure of a QFN packaged chip. Figures 2-5 As shown, the QFN packaged chip includes a package body 1, a lead frame 2, a bare die 3, four rows of first package pads 4, and at least one set of reinforced package pads 5. The lead frame 2 and the bare die 3 are packaged in the package body 1. Figure 6 This is a schematic diagram of the internal structure of a QFN packaged chip provided in an embodiment of this disclosure. Figure 7 This is a schematic diagram of the bottom of a QFN packaged chip provided in an embodiment of this disclosure. Figure 6 As shown, the ground pad 31 of the bare chip 3 is electrically connected to the lead frame 2. (As indicated...) Figure 6 and Figure 7 As shown, four rows of first package pads 4 are located on the four sides of the bottom of the package body 1, and the first package pads 4 are electrically connected to the signal pads 32 or ground pads 31 of the bare chip 3. Each group of reinforcement package pads 5 is located in one corner of the bottom of the package body 1, and each group of reinforcement package pads 5 includes at least two reinforcement package pads arranged at intervals. For example, as shown... Figure 8 As shown, each group of reinforced package pads 5 includes at least a first reinforced package pad 51 and a second reinforced package pad 52 arranged at intervals.

[0060] In this disclosure, the dimensions of the QFN packaged chip are not limited. In some examples, the side length of the QFN packaged chip is greater than or equal to 10 mm and less than or equal to 14 mm. For example, the dimensions of the QFN packaged chip are 10 mm × 10 mm, 11 mm × 11 mm, 12 mm × 12 mm, 13 mm × 13 mm, or 14 mm × 14 mm.

[0061] Package 1 can be a plastic package. Lead frame 2 forms the skeleton of the QFN package chip and is used to electrically connect the various grounded package pads together.

[0062] The bare die 3 refers to an unpackaged chip, also known as a die or bare die. The bare die 3 includes die pads used to establish electrical connections between the bare die 3 and the lead frame 2 or package pads (such as the first package pad 4). The die pads of the bare die 3 include a ground pad 31 and a signal pad 32. The ground pad 31 is used for grounding, and the signal pad 32 is used for transmitting high-speed signals. If at least a portion of the ground pad 31 of the bare die 3 is electrically connected to the lead frame 2, then the lead frame 2 is grounded, and all package pads connected to the lead frame 2 are grounded.

[0063] Four rows of first package pads 4 are exposed on the four sides of the bottom of the package body 1, used to fix and electrically connect the QFN packaged chip on the PCB. The first package pads 4 include signal package pads and ground package pads. The signal package pads are electrically connected to the signal pads 32 of the bare chip 3 for transmitting high-speed signals. The ground package pads are electrically connected to the ground pads 31 of the bare chip 3 to ensure signal return and prevent signal crosstalk. Figure 6 As shown, the grounding package pad is electrically connected to the grounding pad 31 of the bare chip 3, which can be achieved by electrically connecting the grounding package pad to the lead frame 2 (such as an integral connection or a connection via an electrical connection wire). The reinforced package pad 5 is exposed at the bottom corner of the package body 1 for soldering to pads on the PCB.

[0064] In the technical solution provided in this disclosure, each group of enhanced packaging pads 5 includes at least two enhanced packaging pads 5 arranged at intervals, which is more efficient than... Figure 1 The technical solution, which includes only one reinforced package pad 5 at each corner, reduces the likelihood of both reinforced package pads 5 cracking simultaneously. Furthermore, because the two reinforced package pads 5 are spaced apart, cracking of one reinforced package pad 5 will not directly lead to cracking of the other. This improves the reliability of the reinforced package pads 5 in protecting the first package pad 4, thus improving the reliability of the soldering of the first package pad 4.

[0065] In some examples, such as Figure 8As shown, both the first reinforced package pad 51 and the second reinforced package pad 52 are electrically connected to the lead frame 2, and therefore both are grounded. In this way, in addition to protecting the first package pad 4, the first reinforced package pad 51 and the second reinforced package pad 52 also ensure signal return and reduce signal crosstalk. Furthermore, since the first reinforced package pad 51 and the second reinforced package pad 52 are located in the same corner of the package body 1, they are relatively close. Therefore, even if one of the first reinforced package pad 51 and the second reinforced package pad 52 cracks, the other can still ensure signal return and reduce signal crosstalk, allowing the QFN packaged chip to still function normally. This enables the QFN packaged chip provided in this embodiment to meet the package reliability requirements and the signal integrity (SI) requirements for high-speed signals such as 10G SERDES.

[0066] It is understandable that, such as Figure 1 As shown, in the related technical solutions, since each corner has only one grounded reinforced package pad 5, if the reinforced package pad 5 located at the corner cracks, the signal crosstalk between the first package pad 4 near the corner of the QFN package chip will deteriorate rapidly, causing the QFN package chip to become unusable.

[0067] In other examples, the signals of both the first reinforced package pad 51 and the second reinforced package pad 52 are left floating, in which case the reinforced package pad 5 is used only to protect the first reinforced package pad 4.

[0068] In other examples, such as Figure 8 and Figure 9 As shown, the distance from the first enhanced package pad 51 to the vertex 10 of its corner is greater than the distance from the second enhanced package pad 52 to the vertex 10. Alternatively, the first enhanced package pad 51 and the second enhanced package pad 52 are positioned along a reference line (e.g., Figure 9 The first enhanced package pad 51 is close to the center point of the package body 1, and the second enhanced package pad 52 is close to the vertex 10. The first enhanced package pad 51 is electrically connected to the lead frame 2.

[0069] The technical solution provided in this disclosure, because the distance between the first reinforced package pad 51 and the vertex 10 is greater than the distance between the second reinforced package pad 52 and the vertex 10, the second reinforced package pad 52 is located on the outer periphery of the bottom of the package body 1 compared to the first reinforced package pad 51. Generally, the second reinforced package pad 52 will crack before the first reinforced package pad 51, that is, the second reinforced package pad 52 can protect the first reinforced package pad 51, which improves the reliability of the grounding of the first reinforced package pad 51.

[0070] In some examples, the signal of the second reinforced package pad 52 is left floating, and the second reinforced package pad 52 is used only to protect the first reinforced package pad 51 and the first package pad 4.

[0071] In other examples, such as Figure 8 As shown, the second reinforced package pad 52 is electrically connected to the lead frame 2, and thus the second reinforced package pad 52 is grounded. The second reinforced package pad 52 is used to protect the first reinforced package pad 51, ensure signal return, and reduce signal crosstalk.

[0072] In some examples, such as Figures 3-7 As shown, the QFN packaged chip includes four sets of enhanced packaging pads 5, which are located at the four corners of the bottom of the package body 1. This ensures high soldering reliability at each corner of the QFN packaged chip, thereby improving the overall reliability of the QFN packaged chip.

[0073] In other examples, the QFN packaged chip includes two sets of reinforced package pads 5, which are located at opposite corners of the bottom of the package body 1.

[0074] The location of the second enhanced package pad 52 will be illustrated below.

[0075] When the pads of a QFN packaged chip crack, the outer pads typically crack first, followed by the inner pads. Specifically, create a reference line perpendicular to the diagonal X of package body 1. For example, Figure 9 The first reference line A is in the package. This reference line is aligned with the vertex 10 of the corner and translated towards the center of the package body 1. The contact sequence between the reference line and each package pad is the cracking sequence of each package pad.

[0076] Based on the above cracking sequence, in some examples, such as Figure 9 As shown, the two first package pads 4 closest to the first enhanced package pad 51 are designated as the first edge package pad 41 and the second edge package pad 42. The first edge package pad 41 and the second edge package pad 42 are located on two adjacent sides of the package body 1, respectively. Figure 9 As shown, assume that the first reference line A is tangent to both the first edge package pad 41 and the second edge package pad 42, and that the first edge package pad 41 and the second edge package pad 42 are located on the side of the first reference line A closer to vertex 10. Then, the second enhanced package pad 52 is located on the side of the first reference line A closer to vertex 10. The first edge package pad 41 and the second edge package pad 42 are signal package pads.

[0077] Furthermore, in some examples, such as Figure 9 As shown, the fifth reference line E passes through the center point of the first edge package pad 41 and the center point of the second edge package pad 42, and the second reinforced package pad 52 is located on the side of the fifth reference line E closer to vertex 10. Thus, the second reinforced package pad 52 will generally crack before the first edge package pad 41 and the second edge package pad 42, allowing the second reinforced package pad 52 to protect the first edge package pad 41 and the second edge package pad 42.

[0078] Furthermore, in some examples, such as Figure 9 As shown, assume that the seventh reference line G is tangent to both the first edge package pad 41 and the second edge package pad 42, and that the first edge package pad 41 and the second edge package pad 42 are located on the side of the seventh reference line G away from vertex 10. Then, the second reinforced package pad 52 is located on the side of the seventh reference line G closer to vertex 10.

[0079] The location of the first enhanced package pad 51 will be illustrated below.

[0080] In some examples, such as Figure 9 As shown, the first reference line A intersects with the first reinforced package pad 51. Thus, when the outer second reinforced package pad 52 cracks, the first reinforced package pad 51, the first edge package pad 41, and the second edge package pad 42 will all be subjected to stress simultaneously. This mutual reinforcement between the first edge package pad 41, the second edge package pad 42, and the first reinforced package pad 51 improves the reliability of their soldering. Furthermore, this positional relationship also facilitates the first reinforced package pad 51 in reducing signal crosstalk between the first edge package pad 41 and the second edge package pad 42.

[0081] It should be noted that if the second reinforced package pad 52 cracks, cracking of any one of the first edge package pads 41, 42, and 51 will render the QFN packaged chip unusable. Specifically, cracking of the first edge package pad 41 and 42 results in signal loss, while cracking of the first reinforced package pad 51 renders the QFN packaged chip unusable due to severe signal crosstalk. Therefore, the first edge package pad 41, 42, and 51 are all equally important.

[0082] Of course, in other examples, the first enhanced package pad 51 is located on the side of the first reference line A closer to vertex 10 (e.g., as shown in the example). Figure 15 (As shown). In this way, the first reinforced package pad 51 can protect the first edge package pad 41 and the second edge package pad 42.

[0083] In some examples, such as Figure 10 As shown, the fifth reference line E intersects with the first enhanced package pad 51. Of course, in other examples, the first enhanced package pad 51 may also be located on the side of the fifth reference line E closer to vertex 10.

[0084] In some examples, such as Figures 8-13 As shown, the first enhanced packaging pad 51 and the second enhanced packaging pad 52 are located on the diagonal X at the bottom of the package body 1. This makes the stress on the corners of the package body 1 more uniform, reducing the possibility of cracking of the QFN package chip's packaging pads due to uneven stress.

[0085] In some examples, such as Figures 8-13 As shown, the first enhanced package pad 51 and the second enhanced package pad 52 are symmetrically distributed about the diagonal X of the bottom of the package body 1.

[0086] In addition to the first enhanced package pad 51 and the second enhanced package pad 52, in some examples, such as Figures 8-12 As shown, each set of reinforced package pads 5 also includes a third reinforced package pad 53 and a fourth reinforced package pad 54. The third reinforced package pad 53 and the fourth reinforced package pad 54 are located on opposite sides of the diagonal X, and the third reinforced package pad 53 and the fourth reinforced package pad 54 are electrically connected to the lead frame 2 or left floating.

[0087] In some examples, such as Figures 8-12 As shown, the distances of the third enhanced package pad 53 and the fourth enhanced package pad 54 from the vertex 10 are less than the distances of the first enhanced package pad 51 from the vertex 10.

[0088] In this way, the second reinforced package pad 52, the third reinforced package pad 53, and the fourth reinforced package pad 54 can all protect the first reinforced package pad 51, achieving a "multiple protections for one" effect. This significantly reduces the possibility of cracking of the first reinforced package pad 51 and improves the grounding reliability of the first reinforced package pad 51. Furthermore, it also reduces the possibility of cracking of the first package pad 4. In fact, actual measurements show that compared to not having reinforced package pads 5 at the corners, the placement of the first reinforced package pad 51, the second reinforced package pad 52, the third reinforced package pad 53, and the fourth reinforced package pad 54 improves the reliability of the solder joints on the first package pad 4 by 24%.

[0089] In some examples, such as Figures 8-12 As shown, both the third reinforced package pad 53 and the fourth reinforced package pad 54 are electrically connected to the lead frame 2. Thus, as long as any one of the first reinforced package pad 51, the second reinforced package pad 52, the third reinforced package pad 53, or the fourth reinforced package pad 54 is grounded, effective signal return can be guaranteed.

[0090] It should be added that, such as Figure 11 As shown, compared to the large-area reinforced packaging pad 5 in related technologies, the technical solution provided in this disclosure uses multiple small-area reinforced packaging pads 5 arranged at intervals to replace the large-area reinforced packaging pad 5. The reinforced area of ​​the large-area reinforced packaging pad 5 is as follows... Figure 11 The area outlined by the dashed box is shown. It can be seen that, compared to large-area reinforced package pads 5, this embodiment uses multiple small-area reinforced package pads 5 spaced apart, which increases the area of ​​the reinforced region, thereby further improving solder joint reliability. This is because, to prevent solder from the reinforced package pads 5 from crossing onto the first package pad 4, a minimum gap is required between the reinforced package pads 5 and the first package pad 4. The larger the area of ​​the reinforced package pads 5, the greater the amount of solder required, and thus the larger the required gap. Therefore, compared to large-area reinforced package pads 5, the small-area reinforced package pads 5 in this embodiment are closer to the first package pad 4, thereby increasing the area of ​​the reinforced region.

[0091] The relative positions of the first enhanced package pad 51, the second enhanced package pad 52, the third enhanced package pad 53, and the fourth enhanced package pad 54 will be illustrated below.

[0092] In some examples, such as Figure 9 As shown, the second reference line B is tangent to both the third reinforced package pad 53 and the fourth reinforced package pad 54, with the third and fourth reinforced package pads 53 and 54 located on the side of the second reference line B closest to vertex 10. The first reinforced package pad 51 and the second reinforced package pad 52 are positioned on opposite sides of the second reference line B. Thus, when cracking occurs, the second reinforced package pad 52 cracks first, followed by the third and fourth reinforced package pads 53 and 54, with the first reinforced package pad 51 cracking last.

[0093] In some examples, such as Figure 10 As shown, the sixth reference line F passes through the center point of the third enhanced package pad 53 and the center point of the fourth enhanced package pad 54. The first enhanced package pad 51 and the second enhanced package pad 52 are located on both sides of the sixth reference line F.

[0094] In some examples, such as Figure 12 As shown, the third reinforced package pad 53 is located on the first side 11 of the bottom of the package body 1, and the fourth reinforced package pad 54 is located on the second side 12 of the bottom of the package body 1. The distance d1 between the side of the third reinforced package pad 53 away from the second side 12 and the second side 12 is less than 1 mm, and the distance d1 between the side of the fourth reinforced package pad 54 away from the first side 11 and the first side 11 is less than 1 mm.

[0095] In this way, the distance between the third enhanced package pad 53 and the fourth enhanced package pad 54 and the vertex 10 is relatively close, which does not hinder the normal arrangement of the first package pad 4. This means that the QFN package chip does not need to remove part of the first package pad 4 to accommodate the third enhanced package pad 53 and the fourth enhanced package pad 54. Generally, the distance between the first package pad 4 and the vertex 10 should not be less than 1 mm. In some examples, d1 and d2 are less than 0.9 mm.

[0096] In some examples, such as Figure 6 and Figure 7 As shown, the QFN packaged chip also includes four rows of second package pads 6, which are located within the area enclosed by four rows of first package pads 4 and are respectively opposite to the four rows of first package pads 4. The second package pads 6 are electrically connected to the signal pads 32 or ground pads 31 of the bare chip 3. This increases the density of package pads on the QFN packaged chip.

[0097] In some examples, such as Figure 9 and Figure 10 As shown, the third reference line C extends along the row direction of the second package pads 6 and is tangent to the side of the second package pads 6 away from the first package pads 4. The fourth reference line D extends along the row direction of the second package pads 6 and is tangent to the side of the second package pads 6 closer to the first package pads 4. At least a portion of the first reinforced package pad 51 is located between the third reference line C and the fourth reference line D. In this way, the grounded first reinforced package pad 51 can also prevent signal crosstalk to the second package pads 6 on both sides, allowing the first reinforced package pad 51 to be shared by two rows of first package pads 4 and two rows of second package pads 6, reducing the number of grounded first package pads 4 and second package pads 6 required.

[0098] It should be noted that each set of enhanced package pads 5 provided in this embodiment may also exclude the third enhanced package pad 53 and the fourth enhanced package pad 54. In some examples, such as Figure 13 As shown, each set of reinforced package pads 5 includes a first reinforced package pad 51 and a second reinforced package pad 52. The first reinforced package pad 51 and the second reinforced package pad 52 are located on the diagonal X at the bottom of the package body 1.

[0099] In some examples, such as Figure 14 As shown, each set of reinforced package pads 5 includes one first reinforced package pad 51 and two second reinforced package pads 52. The first reinforced package pad 51 is located on the diagonal X at the bottom of the package body 1, and the two second reinforced package pads 52 are located on both sides of the diagonal X.

[0100] It should be noted that, Figure 14 The two second-enhanced package pads 52 in the middle can also be considered as Figures 8-12 The third enhanced package pad 53 and the fourth enhanced package pad 54 in the middle, then Figures 8-12 The description of the dimensions and positions of the third reinforced package pad 53 and the fourth reinforced package pad 54 in the original text also applies to... Figure 14 The two second enhanced package pads 52 in the package are not described in detail here.

[0101] In some examples, such as Figure 15 As shown, each set of reinforced package pads 5 includes two first reinforced package pads 51 and one second reinforced package pad 52. The second reinforced package pad 52 is located on the diagonal X at the bottom of the package body 1, and the two first reinforced package pads 51 are located on both sides of the diagonal X.

[0102] It should be noted that, Figure 15 The two first enhanced package pads 51 in the middle can also be considered as Figures 8-12 The third enhanced package pad 53 and the fourth enhanced package pad 54 in the middle, then Figures 8-12 The description of the dimensions and positions of the third reinforced package pad 53 and the fourth reinforced package pad 54 in the original text also applies to... Figure 15 The two first enhanced package pads 51 in the design are not described in detail here.

[0103] The following is an exemplary description of how the enhanced packaging pad 5 is implemented.

[0104] In some examples, such as Figure 16 As shown, the lead frame 2 includes a main frame 21 and at least one branch frame 22. Figure 2 As shown, the bare chip 3 is fixed to the main frame 21, and the ground pad 31 of the bare chip 3 is electrically connected to the main frame 21. One end of each branch frame 22 is connected to the main frame 21, and the other end extends toward a corner of the package 1. At least two regions of the branch frame 22 are exposed at the bottom of the package 1, and at least two regions form at least a first reinforced package pad 51 and a second reinforced package pad 52. Alternatively, it can be understood that each reinforced package pad 5 is integrally connected to the branch frame 22.

[0105] The lead frame 2 is formed as follows: a metal sheet is attached to a film, the metal sheet is etched, and the remaining part after etching forms the lead frame 2, the first encapsulation pad 4, and the second encapsulation pad 6, respectively.

[0106] In some examples, such as Figure 16As shown, four regions of the branch frame 22 are exposed. The four regions form the first reinforced package pad 51, the second reinforced package pad 52, the third reinforced package pad 53, and the fourth reinforced package pad 54, respectively.

[0107] In some examples, such as Figure 17 As shown, the branch frame 22 includes a main branch frame 221 and three sub-branch frames 222. One end of the main branch frame 221 is connected to the main frame 21, and the other end is connected to the three sub-branch frames 222. The exposed area of ​​the main branch frame 221 forms a first reinforced package pad 51, and the exposed areas of the three branch frames 222 form a second reinforced package pad 52, a third reinforced package pad 53, and a fourth reinforced package pad 54, respectively.

[0108] In some examples, such as Figure 12 As shown, the branch frame 22 includes an opening 220, and a first reinforced package pad 51, a second reinforced package pad 52, a third reinforced package pad 53 and a fourth reinforced package pad 54 surround the opening 220.

[0109] In some examples, such as Figure 15 As shown, three regions of the branch frame 22 are exposed. The three regions form two first reinforced package pads 51 and one second reinforced package pad 52, respectively.

[0110] In some examples, such as Figure 15 As shown, the branch frame 22 includes a main branch frame 221 and three sub-branch frames 222. One end of the main branch frame 221 is connected to the main frame 21, and the other end is connected to the three sub-branch frames 222. The exposed areas of the three sub-branch frames 222 respectively form two first reinforced package pads 51 and one second reinforced package pad 52. Figure 15 As shown, the exposed area of ​​the sub-branch frame 222 located in the middle of the three sub-branch frames 222 forms a second reinforced encapsulation pad 52.

[0111] In some examples, such as Figure 14 As shown, three regions of the branch frame 22 are exposed. The three regions form a first reinforced package pad 51 and two second reinforced package pads 52, respectively.

[0112] In some examples, such as Figure 14 As shown, the branch frame 22 includes a main branch frame 221 and two sub-branch frames 222. One end of the main branch frame 221 is connected to the main frame 21, and the other end is connected to the two sub-branch frames 222. The exposed area of ​​the main branch frame 221 forms a first reinforced package pad 51, and the exposed portions of the two sub-branch frames 222 respectively form two second reinforced package pads 52.

[0113] In some examples, such as Figure 4 , Figure 5 , Figure 7 and Figure 16 As shown, the QFN packaged chip also includes a central pad 7, which is located at the bottom of the package body 1, and four rows of first package pads 4 surround the central pad 7. The central pad 7 is used for heat dissipation and grounding.

[0114] In some examples, the intermediate pad 7 is integrally connected to the main branch frame 221. Alternatively, it can be understood that at least one region of the main branch frame 221 is exposed at the bottom of the package 1, and the exposed region forms the intermediate pad 7.

[0115] The terminology used in the embodiments of this disclosure is for illustrative purposes only and is not intended to limit the scope of this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The above descriptions are merely optional embodiments of this disclosure and are not intended to limit the disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A QFN packaged chip, characterized by, The QFN package chip comprises a package body (1), a lead frame (2), a bare chip (3), four rows of first package pads (4) and at least one group of enhanced package pads (5); The lead frame (2) and the bare chip (3) are packaged in the package body (1), and the ground pad (31) of the bare chip (3) is electrically connected with the lead frame (2); The four rows of first package pads (4) are respectively located on four edges of the bottom of the package body (1), and the first package pads (4) are electrically connected with the ground pad (31) or the signal pad (32) of the bare chip (3); Each group of the enhanced package pads (5) is located in a corner of the bottom of the package body (1), each group of the enhanced package pads (5) comprises at least a first enhanced package pad (51) and a second enhanced package pad (52), the distance between the first enhanced package pad (51) and the vertex (10) of the corner is greater than the distance between the second enhanced package pad (52) and the vertex (10), the first enhanced package pad (51) is electrically connected with the lead frame (2), and the second enhanced package pad (52) is electrically connected with the lead frame (2) or the signal is suspended.

2. The QFN packaged chip of claim 1, wherein, The lead frame (2) comprises a main frame (21) and at least one branch frame (22); The bare chip (3) is fixed to the main frame (21), and the ground pad (31) of the bare chip (3) is electrically connected with the main frame (21); One end of each branch frame (22) is connected with the main frame (21), and the other end extends towards a corner of the package body (1), at least two regions of the branch frame (22) are exposed on the bottom of the package body (1), and the at least two regions form at least the first enhanced package pad (51) and the second enhanced package pad (52).

3. The QFN packaged chip of claim 1 or 2, wherein, Supposing that the two first package pads (4) closest to the first enhanced package pad (51) are a first edge package pad (41) and a second edge package pad (42), the first edge package pad (41) and the second edge package pad (42) are respectively located on two adjacent edges of the package body (1); Supposing that a first reference line (A) is tangent to the first edge package pad (41), the second edge package pad (42) and the first enhanced package pad (51), and the first edge package pad (41) and the second edge package pad (42) are located on one side of the first reference line (A) close to the vertex (10); The first reference line (A) intersects the first enhanced package pad (51), or the first enhanced package pad (51) is located on one side of the first reference line (A) close to the vertex (10).

4. The QFN packaged chip of any of claims 1-3, wherein, The first enhanced package pad (51) and the second enhanced package pad (52) are located on a diagonal line (X) of the bottom of the package body (1).

5. The QFN packaged chip of claim 4, wherein, Each group of the enhanced package pads (5) further comprises a third enhanced package pad (53) and a fourth enhanced package pad (54); The third and fourth reinforcing package pads (53, 54) are located on two sides of the diagonal line (X), the distance from the third and fourth reinforcing package pads (53, 54) to the vertex (10) is greater than the distance from the first reinforcing package pad (51) to the vertex (10), and the third and fourth reinforcing package pads (53, 54) are electrically connected to the lead frame (2) or signal suspended.

6. The QFN packaged chip of claim 5, wherein the QFN packaged chip is configured to be mounted on a printed circuit board (PCB) in a flip-chip manner. The third reinforcing package pad (53) is located on the first side (11) of the bottom of the package body (1), and the fourth reinforcing package pad (54) is located on the second side (12) of the bottom of the package body (1). The distance from the side of the third reinforcing package pad (53) away from the second side (12) to the second side (12) is less than 1mm, and the distance from the side of the fourth reinforcing package pad (54) away from the first side (11) to the first side (11) is less than 1mm.

7. The QFN packaged chip of claim 5 or 6, wherein, A second reference line (B) is tangent to the third and fourth reinforcing package pads (53, 54), and the third and fourth reinforcing package pads (53, 54) are located on the side of the second reference line (B) close to the vertex (10). The first and second reinforcing package pads (51, 52) are arranged on two sides of the second reference line (B).

8. The QFN packaged chip of any of claims 1-7, wherein, The QFN package chip further comprises four rows of second package pads (6), the four rows of second package pads (6) are located in the area surrounded by the four rows of first package pads (4), and the second package pads (6) are electrically connected to the signal pads (32) or ground pads (31) of the bare chip (3). A third reference line (C) extends along the direction of the row of second package pads (6) and is tangent to the side of the second package pad (6) away from the first package pad (4), and a fourth reference line (D) extends along the direction of the row of second package pads (6) and is tangent to the side of the second package pad (6) close to the first package pad (4). At least a part of the first reinforcing package pad (51) is located between the third and fourth reference lines (C, D).

9. The QFN packaged chip of any of claims 1-3, wherein, Each group of reinforcing package pads (5) comprises one first reinforcing package pad (51) and two second reinforcing package pads (52). The one first reinforcing package pad (51) is located on the diagonal line (X) of the bottom of the package body (1), and the two second reinforcing package pads (52) are located on two sides of the diagonal line (X).

10. The QFN packaged chip of any of claims 1-3, wherein, Each group of reinforcing package pads (5) comprises two first reinforcing package pads (51) and one second reinforcing package pad (52). The one second reinforcing package pad (52) is located on the diagonal line (X) of the bottom of the package body (1), and the two first reinforcing package pads (51) are located on two sides of the diagonal line (X).

11. The QFN packaged chip of any of claims 1-10, wherein, The QFN package chip comprises four groups of reinforced package pads (5) respectively located at four corners of the bottom of the package body (1).

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