Semiconductor structure and forming method thereof
By simultaneously forming capacitor structures and electrical interconnect structures within the first dielectric layer of a semiconductor structure, the problems of metal residue and short-circuit leakage caused by density and height differences are solved, parasitic capacitance and RC delay of the semiconductor structure are reduced, and performance is improved.
Patent Information
- Application Number
- CN202410867282.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-28
- Publication Date
- 2025-12-30
AI Technical Summary
Existing technologies have flatness issues in the process of forming MIM capacitors due to differences in device structure density and height, resulting in residual metal materials and short-circuit leakage. Furthermore, the large number of semiconductor stacked layers leads to parasitic capacitance and RC delay.
The capacitor structure and the first electrical interconnect structure are formed simultaneously within the first dielectric layer of the semiconductor structure, so that the device structure density and height tend to be consistent and formed on the same process layer. The lower electrode layer is protected by an anti-reflection layer to avoid tip discharge and reduce metal residue and parasitic capacitance.
It improves the flatness of the semiconductor structure, reduces the risk of short-circuit leakage, reduces the parasitic capacitance and RC delay of the semiconductor structure, and improves performance.
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Figure CN121237773A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND
[0002] Capacitors are commonly used passive components in ultra large scale integrated circuits. The capacitors mainly include Polysilicon-Insulator-Polysilicon (PIP) capacitor, Metal-Insulator-Silicon (MIS) capacitor and Metal-Insulator-Metal (MIM) capacitor.
[0003] With the rapid development of wireless communication technology, people strongly hope to implant high performance decoupling and bypass capacitors suitable for system on chip (SoC) into the copper interconnection end process of integrated circuits to obtain powerful radio frequency systems. This further requires that the implanted capacitors should have high capacitance density, ideal voltage linearity value, precise capacitance value control and high reliability, etc. The traditional PIP structure, MIS structure and MOS structure have been difficult to meet the performance requirements.
[0004] Since the MIM capacitor causes less interference to the transistor and can provide better linearity and symmetry, the use of MIM capacitor will be the development trend of radio frequency and analog / mixed signal integrated circuits.
[0005] However, there are still many problems in the prior art in the process of forming the MIM capacitor. SUMMARY
[0006] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof, which improves the performance of the device structure.
[0007] To solve the above problems, the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a capacitor region and a non-capacitor region; a capacitor structure located on the capacitor region, the capacitor structure comprising a lower plate layer, an insulating layer located on the lower plate layer, and an upper plate layer located on the insulating layer; a first dielectric layer located on the substrate, the first dielectric layer covering the capacitor structure; a first electrical interconnection structure located in the first dielectric layer, and the first electrical interconnection structure is located on the non-capacitor region.
[0008] Optionally, it further comprises: a second dielectric layer located on the first dielectric layer; a second electrical interconnection structure located in the first dielectric layer and the second dielectric layer, and the second electrical interconnection structure is electrically connected with the first electrical interconnection structure and the capacitor structure respectively.
[0009] Optionally, the lower electrode layer is a composite stack.
[0010] Optionally, the lower electrode layer includes: a first sub-electrode layer, a second sub-electrode layer located on the first sub-electrode layer, and a third sub-electrode layer located on the second sub-electrode layer.
[0011] Optionally, the material of the second sub-electrode layer includes aluminum; the materials of the first sub-electrode layer and the third sub-electrode layer include titanium nitride.
[0012] Optionally, the material of the upper electrode layer includes titanium nitride.
[0013] Optionally, the first electrical interconnect structure includes: a first conductive plug, and a first conductive layer located on and electrically connected to the first conductive plug.
[0014] Optionally, the second electrical interconnect structure includes: a second conductive plug located within the second dielectric layer, the second conductive plug being electrically connected to the first conductive layer; a third conductive plug located within the first dielectric layer and the second dielectric layer, the third conductive plug being electrically connected to the lower electrode layer; and a fourth conductive plug located within the first dielectric layer and the second dielectric layer, the fourth conductive plug being electrically connected to the upper electrode layer.
[0015] Optionally, the material of the first electrical interconnect structure includes copper.
[0016] Optionally, the material of the second electrical interconnect structure includes copper.
[0017] Optionally, the material of the first dielectric layer includes silicon oxide.
[0018] Optionally, the material of the second dielectric layer includes silicon oxide.
[0019] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a capacitor region and a non-capacitor region; forming a capacitor structure on the capacitor region, the capacitor structure including a lower electrode layer, an insulating layer on the lower electrode layer, and an upper electrode layer on the insulating layer; forming a first dielectric layer on the substrate, the first dielectric layer covering the capacitor structure; forming a first electrical interconnect structure in the first dielectric layer, wherein the first electrical interconnect structure is located on the non-capacitor region.
[0020] Optionally, after forming the first electrical interconnect structure, the method further includes: forming a second dielectric layer on the first dielectric layer; forming a second electrical interconnect structure within the first dielectric layer and the second dielectric layer, wherein the second electrical interconnect structure is electrically connected to the first electrical interconnect structure and the capacitor structure, respectively.
[0021] Optionally, the method for forming the capacitor structure includes: forming a lower electrode material layer on the substrate; forming an insulating material layer on the lower electrode material layer; forming an upper electrode material layer on the insulating material layer; performing patterned etching on the upper electrode material layer, the insulating material layer, and the lower electrode material layer to form the upper electrode layer, the insulating layer, and the lower electrode layer, wherein the upper electrode layer, the insulating layer, and the lower electrode layer constitute the capacitor structure.
[0022] Optionally, the method for patterning and etching the upper electrode material layer, the insulating material layer, and the lower electrode material layer includes: etching the upper electrode material layer and a portion of the insulating material layer using a first etching process to form the upper electrode layer; depositing a first anti-reflective layer, the first anti-reflective layer covering the exposed surface of the upper electrode layer and the surface of the insulating material layer; and etching the first anti-reflective layer, the remaining portion of the insulating material layer, and the lower electrode material layer using a second etching process to form the insulating layer and the lower electrode layer.
[0023] Optionally, the lower electrode layer is a composite stack.
[0024] Optionally, the lower electrode layer includes: a first sub-electrode layer, a second sub-electrode layer located on the first sub-electrode layer, and a third sub-electrode layer located on the second sub-electrode layer.
[0025] Optionally, the first electrical interconnect structure includes: a first conductive plug, and a first conductive layer located on and electrically connected to the first conductive plug.
[0026] Optionally, the method for forming the first electrical interconnect structure includes: forming a first conductive via and a first conductive trench in the first dielectric layer using a damascus process, wherein the first conductive trench exposes the first conductive via; forming a first conductive material layer in the first conductive via, in the first conductive trench, and on the first dielectric layer; planarizing the first conductive material layer until the top surface of the first dielectric layer is exposed; forming a first conductive plug in the first conductive via and forming the first conductive layer in the first conductive trench.
[0027] Optionally, the second electrical interconnect structure includes: a second conductive plug located within the second dielectric layer, the second conductive plug being electrically connected to the first conductive layer; a third conductive plug located within the first dielectric layer and the second dielectric layer, the third conductive plug being electrically connected to the lower electrode layer; and a fourth conductive plug located within the first dielectric layer and the second dielectric layer, the fourth conductive plug being electrically connected to the upper electrode layer.
[0028] Optionally, the method for forming the second electrical interconnect structure includes: forming a second conductive via in the second dielectric layer, the second conductive via exposing the surface of the first conductive layer; forming a third conductive via in the first dielectric layer and the second dielectric layer, the third conductive via exposing the surface of the lower electrode layer; forming a fourth conductive via in the first dielectric layer and the second dielectric layer, the fourth conductive via exposing the surface of the upper electrode layer; forming a second conductive material layer in the second conductive via, the third conductive via, the fourth conductive via, and on the second dielectric layer; planarizing the second conductive material layer until the top surface of the second dielectric layer is exposed; forming a second conductive plug in the second conductive via, forming a third conductive plug in the third conductive via, and forming a fourth conductive plug in the fourth conductive via.
[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:
[0030] In the semiconductor structure of this invention, the first electrical interconnect structure and the capacitor structure are both located within the first dielectric layer. This makes the device structure density and height between the capacitor region and the non-capacitor region within the first dielectric layer tend to be consistent. Therefore, when the second dielectric layer is subsequently formed, the top surface of the second dielectric layer can be guaranteed to have good flatness. Furthermore, when the second electrical interconnect structure is subsequently formed, the amount of residual metal material on the top surface of the second dielectric layer can be reduced, thereby effectively reducing the problem of short-circuit leakage in the second electrical interconnect structure and improving the performance of the semiconductor structure. In addition, by forming the first electrical interconnect structure and the capacitor structure on the same process layer, the number of stacked layers in the semiconductor structure can be reduced, thereby reducing the parasitic capacitance generated in the semiconductor structure, reducing RC delay, and improving the performance of the semiconductor structure.
[0031] In the semiconductor structure formation method of this invention, by forming a first electrical interconnect structure and a capacitor structure within the first dielectric layer, the device structure density and height between the capacitor region and the non-capacitor region within the first dielectric layer tend to be consistent. Therefore, when the second dielectric layer is subsequently formed, the top surface of the second dielectric layer can be guaranteed to have good flatness. Furthermore, when the second electrical interconnect structure is subsequently formed, the amount of residual metal material on the top surface of the second dielectric layer can be reduced, thereby effectively reducing the problem of short-circuit leakage in the second electrical interconnect structure and improving the performance of the semiconductor structure. In addition, by forming the first electrical interconnect structure and the capacitor structure on the same process layer, the number of stacked layers in the semiconductor structure can be reduced, thereby reducing parasitic capacitance generated in the semiconductor structure, reducing RC delay, and improving the performance of the semiconductor structure.
[0032] Furthermore, the method for patterning and etching the upper electrode material layer, the insulating material layer, and the lower electrode material layer includes: etching the upper electrode material layer and a portion of the insulating material layer using a first etching process to form the upper electrode layer; depositing a first anti-reflective layer covering the exposed surfaces of the upper electrode layer and the insulating material layer; and etching the first anti-reflective layer, the remaining portion of the insulating material layer, and the lower electrode material layer using a second etching process to form the insulating layer and the lower electrode layer. In the first etching process, by retaining a portion of the insulating material layer, direct contact between the plasma and the metallic lower electrode layer is prevented, thereby reducing the risk of tip discharge between the plasma and the lower electrode layer, which could damage the entire wafer. Attached Figure Description
[0033] Figures 1-2 This is a schematic diagram of the steps involved in forming a semiconductor structure.
[0034] Figures 3-10 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation
[0035] As described in the background section, existing semiconductor structures still present numerous problems during testing. These will be explained in detail below with reference to the accompanying drawings.
[0036] Figures 1-2 This is a schematic diagram of the steps involved in forming a semiconductor structure.
[0037] Please refer to Figure 1A substrate 100 is provided, the substrate 100 including a capacitor region I and a non-capacitor region II; a first dielectric layer 101 is formed on the substrate 100; a first electrical interconnect structure 102 is formed on the first dielectric layer 101, the first electrical interconnect structure 102 being located on the non-capacitor region II; a capacitor structure 103 is formed on the first dielectric layer 101, the capacitor structure 103 being located on the capacitor region I, the capacitor structure 103 including a lower electrode layer, an insulating layer located on the lower electrode layer, and an upper electrode layer (not shown) located on the insulating layer.
[0038] Please refer to Figure 2 A second dielectric layer 104 is formed on the first dielectric layer 101, and the second dielectric layer 104 covers the capacitor structure 103; a second electrical interconnect structure 105 is formed in the second dielectric layer 104, and the second electrical interconnect structure 105 is electrically connected to the first electrical interconnect structure 102 and the capacitor structure 103 respectively.
[0039] In this embodiment, before depositing the second dielectric layer 104, the capacitor structure 103 is formed on the capacitor region I within the first dielectric layer 101, while no device structure is formed on the non-capacitor region II. There are device density and height differences between the two regions, which makes it impossible to grind the top surface of the formed second dielectric layer 104 flat through planarization, resulting in a flatness problem on the top surface of the second dielectric layer 104.
[0040] Please continue to refer to this. Figure 2 In this embodiment, the second electrical interconnect structure 105 is a plurality of conductive plugs (not shown) electrically connecting the lower electrode layer and the upper electrode layer of the first electrical interconnect structure 102 and the capacitor structure 103. During the formation of each conductive plug, due to the flatness issue on the top surface of the second dielectric layer 104, residual metal material may appear during the chemical mechanical polishing of each conductive plug, which can easily cause short circuits and leakage between the conductive plugs (e.g., ...). Figure 2 (Part A), which in turn affects the performance of the device structure.
[0041] Based on this, the present invention provides a semiconductor structure and its formation method. By forming a first electrical interconnect structure and a capacitor structure within a first dielectric layer, the device structure density and height between the capacitor region and the non-capacitor region within the first dielectric layer tend to be consistent. Therefore, when the second dielectric layer is subsequently formed, the top surface of the second dielectric layer can be guaranteed to have good flatness. Furthermore, when the second electrical interconnect structure is subsequently formed, the amount of residual metal material on the top surface of the second dielectric layer can be reduced, thereby effectively reducing the problem of short-circuit leakage in the second electrical interconnect structure and improving the performance of the semiconductor structure. In addition, by forming the first electrical interconnect structure and the capacitor structure on the same process layer, the number of stacked layers in the semiconductor structure can be reduced, thereby reducing parasitic capacitance generated in the semiconductor structure, reducing RC delay, and improving the performance of the semiconductor structure.
[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0043] Figures 3-10 This is a schematic diagram of the steps in the method for forming a semiconductor structure according to an embodiment of the present invention.
[0044] Please refer to Figure 3 A substrate 200 is provided, the substrate 200 including a capacitor region I and a non-capacitor region II.
[0045] In this embodiment, the substrate 200 includes a substrate and a device layer located on the substrate, wherein the device layer has a plurality of device structures (not shown).
[0046] In this embodiment, the substrate is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.
[0047] In this embodiment, the device structure includes one or more of the following: transistor structure, capacitor structure, resistor structure, and inductor structure.
[0048] It should be noted that in subsequent processes, a capacitor structure is formed on the capacitor region I, but no capacitor structure is formed on the non-capacitor region II.
[0049] After providing the substrate 200, the method further includes: forming a capacitor structure on the capacitor region I, the capacitor structure including a lower electrode layer, an insulating layer located on the lower electrode layer, and an upper electrode layer located on the insulating layer. Please refer to [reference needed for details]. Figures 4-5 .
[0050] Please refer to Figure 4A lower electrode material layer 201 is formed on the substrate 200; an insulating material layer 202 is formed on the lower electrode material layer 201; and an upper electrode material layer 203 is formed on the insulating material layer 202.
[0051] In this embodiment, the lower electrode layer is a composite stack. The corresponding lower electrode material layer 201 includes: a first sub-electrode material layer 2011, a second sub-electrode material layer 2012 located on the first sub-electrode material layer 2011, and a third sub-electrode material layer 2013 located on the second sub-electrode material layer 2012.
[0052] In other embodiments, the lower electrode layer may also be a single-layer structure.
[0053] In this embodiment, the first sub-electrode material layer 2011 is made of titanium nitride, the second sub-electrode material layer 2012 is made of aluminum, and the third sub-electrode material layer 2013 is made of titanium nitride.
[0054] In this embodiment, the insulating material layer 202 is made of silicon nitride.
[0055] In this embodiment, the material of the upper electrode material layer 203 is titanium nitride.
[0056] Please continue to refer to this. Figure 4 In this embodiment, the method further includes forming a second anti-reflection layer 204 on the upper electrode material layer 203. Adding the second anti-reflection layer 204 enables a clearer and more accurate exposure profile to be obtained during subsequent patterning etching to form the capacitor structure.
[0057] In this embodiment, the material of the second anti-reflective layer 204 is silicon oxynitride.
[0058] Please continue to refer to this. Figure 4 In this embodiment, before forming the lower electrode material layer 201, the method further includes forming a first etching barrier layer 205 on the substrate 200.
[0059] In this embodiment, the first etch barrier layer 205 is made of silicon nitride.
[0060] After forming the lower electrode material layer 201, the insulating material layer 202, and the upper electrode material layer 203, the process further includes: performing patterned etching on the upper electrode material layer 203, the insulating material layer 202, and the lower electrode material layer 201 to form the upper electrode layer, the insulating layer, and the lower electrode layer, which together constitute the capacitor structure. Please refer to [link to specific process details] for details. Figures 5-6 .
[0061] Please refer to Figure 5 The upper electrode material layer 203 and part of the insulating material layer 202 are etched using a first etching process to form the upper electrode layer 206.
[0062] In this embodiment, the first etching process is a dry etching process.
[0063] In the first etching process, by retaining a portion of the insulating material layer 202, the plasma in the first etching process is prevented from directly contacting the metallic lower electrode layer, thereby reducing the problem of tip discharge between the plasma and the lower electrode layer, which could cause damage to the entire wafer.
[0064] Please refer to Figure 6 A first anti-reflective layer 207 is deposited, which covers the exposed surface of the upper electrode layer 206 and the surface of the insulating material layer 202. The first anti-reflective layer 207, the remaining portion of the insulating material layer 202, and the lower electrode material layer 201 are etched using a second etching process to form the insulating layer 208 and the lower electrode layer 209.
[0065] By adding the first anti-reflective layer 207, a clearer and more accurate exposure profile can be obtained during the patterning etching process to form the capacitor structure.
[0066] In this embodiment, the material of the first anti-reflective layer 207 is silicon oxynitride.
[0067] It should be noted that, in this embodiment, the projection area of the upper electrode layer 206 toward the substrate 200 is located within the projection area of the lower electrode layer 209 toward the substrate 200. The area of the lower electrode layer 209 larger than that of the upper electrode layer 206 is used for subsequent metal wiring to avoid short circuits between the metal wiring of the lower electrode layer 209 and the upper electrode layer 206.
[0068] In this embodiment, the lower electrode layer 209 includes: a first sub-electrode layer 2091, a second sub-electrode layer 2092 located on the first sub-electrode layer 2091, and a third sub-electrode layer 2093 located on the second sub-electrode layer 2092.
[0069] In this embodiment, the second etching process is a dry etching process.
[0070] Please refer to Figure 7 A first dielectric layer 210 is formed on the substrate 200, and the first dielectric layer 210 covers the capacitor structure.
[0071] In this embodiment, the material of the first dielectric layer 210 is silicon oxide.
[0072] Please continue to refer to this. Figure 7 In this embodiment, before forming the first dielectric layer 210, the method further includes forming a second etch stop layer 215 on the surface of the exposed capacitor structure and the surface of the exposed first etch stop layer 205.
[0073] In this embodiment, the material of the second etch stop layer 215 is silicon nitride.
[0074] Please refer to Figure 8 A first electrical interconnect structure 211 is formed within the first dielectric layer 210, and the first electrical interconnect structure 211 is located on the non-capacitor region II.
[0075] In this embodiment, the first electrical interconnect structure 211 includes: a first conductive plug 2111, and a first conductive layer 2112 located on the first conductive plug 2111 and electrically connected to the first conductive plug 2111.
[0076] In this embodiment, the method for forming the first electrical interconnect structure 211 includes: forming a first conductive via and a first conductive trench (not shown) in the first dielectric layer 210 using a damascus process, wherein the first conductive trench exposes the first conductive via; forming a first conductive material layer (not shown) in the first conductive via, in the first conductive trench, and on the first dielectric layer 210; planarizing the first conductive material layer until the top surface of the first dielectric layer 210 is exposed; forming the first conductive plug 2111 in the first conductive via and forming the first conductive layer 2112 in the first conductive trench.
[0077] In this embodiment, the first electrical interconnect structure 211 is electrically connected to the device structure in the device layer. Specifically, the first conductive via penetrates the first etch stop layer 205 and the second etch stop layer 215, exposing the device structure within the device layer, and the first conductive plug 2111 is electrically connected to the device structure within the device layer.
[0078] In this embodiment, the first electrical interconnect structure 211 is made of copper.
[0079] In this embodiment, the planarization process for the first conductive material layer is a chemical mechanical polishing process.
[0080] Please refer to Figure 9 A second dielectric layer 212 is formed on the first dielectric layer 210.
[0081] In this embodiment, the material of the second dielectric layer 212 is silicon oxide.
[0082] Please continue to refer to this. Figure 9 In this embodiment, before forming the second dielectric layer 212, a third etch stop layer 213 is formed on the first dielectric layer 210.
[0083] In this embodiment, the material of the third etch stop layer 213 is silicon nitride.
[0084] Please refer to Figure 10 A second electrical interconnect structure 214 is formed in the first dielectric layer 210 and the second dielectric layer 212, and the second electrical interconnect structure 214 is electrically connected to the first electrical interconnect structure 211 and the capacitor structure, respectively.
[0085] By forming the first electrical interconnect structure 211 and the capacitor structure within the first dielectric layer 210, the device structure density and height between the capacitor region I and the non-capacitor region II within the first dielectric layer 210 tend to be consistent. Therefore, when forming the second dielectric layer 212, the top surface of the second dielectric layer 212 can be guaranteed to have good flatness. When forming the second electrical interconnect structure 214, the residual metal material on the top surface of the second dielectric layer 212 can be reduced, thereby effectively reducing the problem of short-circuit leakage in the second electrical interconnect structure 214 and improving the performance of the semiconductor structure. In addition, by forming the first electrical interconnect structure 211 and the capacitor structure on the same process layer, the number of stacked layers of the semiconductor structure can be reduced, thereby reducing the parasitic capacitance generated in the semiconductor structure, reducing RC delay, and improving the performance of the semiconductor structure.
[0086] In this embodiment, the second electrical interconnect structure 214 includes: a second conductive plug 2141 located within the second dielectric layer 212, the second conductive plug 2141 being electrically connected to the first conductive layer 2112; a third conductive plug 2142 located within the first dielectric layer 210 and the second dielectric layer 212, the third conductive plug 2142 being electrically connected to the lower electrode layer 209; and a fourth conductive plug 2143 located within the first dielectric layer 210 and the second dielectric layer 212, the fourth conductive plug 2143 being electrically connected to the upper electrode layer 206.
[0087] In this embodiment, the method for forming the second electrical interconnect structure 214 includes: forming a second conductive via (not shown) within the second dielectric layer 212, the second conductive via exposing the surface of the first conductive layer 2112; forming a third conductive via (not shown) within the first dielectric layer 210 and the second dielectric layer 212, the third conductive via exposing the surface of the lower electrode layer 209; and forming a fourth conductive via (not shown) within the first dielectric layer 210 and the second dielectric layer 212, the fourth conductive via exposing the surface of the lower electrode layer 209. The surface of the upper electrode layer 206; a second conductive material layer (not shown) is formed in the second conductive through hole, the third conductive through hole, the fourth conductive through hole and on the second dielectric layer 212; the second conductive material layer is planarized until the top surface of the second dielectric layer 212 is exposed; a second conductive plug 2141 is formed in the second conductive through hole, a third conductive plug 2142 is formed in the third conductive through hole and a fourth conductive plug 2143 is formed in the fourth conductive through hole.
[0088] In this embodiment, the material of the second electrical interconnect structure 214 is copper.
[0089] In this embodiment, the planarization process for the second conductive material layer is a chemical mechanical polishing process.
[0090] Accordingly, this invention also provides a semiconductor structure, please refer to the following embodiments. Figure 10 The system includes: a substrate 200, which includes a capacitor region I and a non-capacitor region II; a capacitor structure located on the capacitor region I, the capacitor structure including a lower electrode layer 209, an insulating layer 208 located on the lower electrode layer 209, and an upper electrode layer 206 located on the insulating layer 208; a first dielectric layer 210 located on the substrate 200, the first dielectric layer 210 covering the capacitor structure; a first electrical interconnect structure 211 located within the first dielectric layer 210, and the first electrical interconnect structure 211 located on the non-capacitor region II; and a second dielectric layer 212 located on the first dielectric layer 210.
[0091] The first electrical interconnect structure 211 and the capacitor structure are both located within the first dielectric layer 210, making the device structure density and height between the capacitor region I and the non-capacitor region II within the first dielectric layer 210 more consistent. Therefore, when the second dielectric layer 212 is subsequently formed, the top surface of the second dielectric layer 212 can be guaranteed to have good flatness. When the second electrical interconnect structure 214 is subsequently formed, the residual metal material on the top surface of the second dielectric layer 212 can be reduced, thereby effectively reducing the problem of short-circuit leakage in the second electrical interconnect structure 214 and improving the performance of the semiconductor structure. In addition, by forming the first electrical interconnect structure 211 and the capacitor structure on the same process layer, the number of stacked layers of the semiconductor structure can be reduced, thereby reducing the parasitic capacitance generated in the semiconductor structure, reducing RC delay, and improving the performance of the semiconductor structure.
[0092] In this embodiment, it further includes a second electrical interconnect structure 214 located within the first dielectric layer 210 and the second dielectric layer 212, wherein the second electrical interconnect structure 214 is electrically connected to the first electrical interconnect structure 211 and the capacitor structure, respectively.
[0093] In this embodiment, the lower electrode layer 209 is a composite stack.
[0094] In this embodiment, the lower electrode layer 209 includes: a first sub-electrode layer 2091, a second sub-electrode layer 2092 located on the first sub-electrode layer 2091, and a third sub-electrode layer 2093 located on the second sub-electrode layer 2092.
[0095] In this embodiment, the second sub-electrode layer 2092 is made of aluminum; the first sub-electrode layer 2091 and the third sub-electrode layer 2093 are made of titanium nitride.
[0096] In this embodiment, the upper electrode layer 206 is made of titanium nitride.
[0097] In this embodiment, the first electrical interconnect structure 211 includes: a first conductive plug 2111, and a first conductive layer 2112 located on the first conductive plug 2111 and electrically connected to the first conductive plug 2111.
[0098] In this embodiment, the second electrical interconnect structure 214 includes: a second conductive plug 2141 located within the second dielectric layer 212, the second conductive plug 2141 being electrically connected to the first conductive layer 2112; a third conductive plug 2142 located within the first dielectric layer 210 and the second dielectric layer 212, the third conductive plug 2142 being electrically connected to the lower electrode layer 209; and a fourth conductive plug 2143 located within the first dielectric layer 210 and the second dielectric layer 212, the fourth conductive plug 2143 being electrically connected to the upper electrode layer 206.
[0099] In this embodiment, the first electrical interconnect structure 211 is made of copper.
[0100] In this embodiment, the material of the second electrical interconnect structure 214 is copper.
[0101] In this embodiment, the material of the first dielectric layer 210 is silicon oxide.
[0102] In this embodiment, the material of the second dielectric layer 212 is silicon oxide.
[0103] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized by, Comprising: a substrate comprising a capacitor region and a non-capacitor region; a capacitor structure on the capacitor region, the capacitor structure comprising a lower plate layer, an insulating layer on the lower plate layer, and an upper plate layer on the insulating layer; a first dielectric layer on the substrate, the first dielectric layer covering the capacitor structure; a first electrical interconnect structure in the first dielectric layer and on the non-capacitor region.
2. The semiconductor structure of claim 1, wherein, Further comprising: a second dielectric layer on the first dielectric layer; a second electrical interconnect structure in the first and second dielectric layers, the second electrical interconnect structure electrically connected to the first electrical interconnect structure and the capacitor structure, respectively.
3. The semiconductor structure of claim 1, wherein, The lower plate layer is a composite stack.
4. The semiconductor structure of claim 3, wherein, The lower plate layer comprises: a first sub-plate layer, a second sub-plate layer on the first sub-plate layer, and a third sub-plate layer on the second sub-plate layer.
5. The semiconductor structure of claim 4, wherein the first and second semiconductor layers are formed of a same material. The second sub-plate layer comprises aluminum; the first and third sub-plate layers comprise titanium nitride.
6. The semiconductor structure of claim 1, wherein, The upper plate layer comprises titanium nitride.
7. The semiconductor structure of claim 2, wherein, The first electrical interconnect structure comprises: a first conductive plug, and a first conductive layer on the first conductive plug and electrically connected to the first conductive plug.
8. The semiconductor structure of claim 7, wherein, The second electrical interconnect structure comprises: a second conductive plug in the second dielectric layer, the second conductive plug electrically connected to the first conductive layer; a third conductive plug in the first and second dielectric layers, the third conductive plug electrically connected to the lower plate layer; and a fourth conductive plug in the first and second dielectric layers, the fourth conductive plug electrically connected to the upper plate layer.
9. The semiconductor structure of claim 1, wherein, The first electrical interconnect structure comprises copper.
10. The semiconductor structure of claim 2, wherein, The second electrical interconnect structure comprises copper.
11. The semiconductor structure of claim 1, wherein, The first dielectric layer comprises silicon oxide.
12. The semiconductor structure of claim 2, wherein, The second dielectric layer comprises silicon oxide.
13. A method of forming a semiconductor structure, comprising: Comprising: providing a substrate comprising a capacitor region and a non-capacitor region; forming a capacitor structure on the capacitor region, the capacitor structure comprising a lower plate layer, an insulating layer on the lower plate layer, and an upper plate layer on the insulating layer; forming a first dielectric layer on the substrate, the first dielectric layer covering the capacitor structure; forming a first electrical interconnect structure in the first dielectric layer and on the non-capacitor region.
14. The method of forming a semiconductor structure of claim 13, wherein, Further comprising, after forming the first electrical interconnect structure: forming a second dielectric layer on the first dielectric layer; and forming a second electrical interconnect structure in the first and second dielectric layers, the second electrical interconnect structure electrically connected to the first electrical interconnect structure and the capacitor structure, respectively.
15. The method of forming a semiconductor structure of claim 13, wherein The forming method of the capacitor structure comprises: forming a lower plate material layer on the substrate; forming an insulating material layer on the lower plate material layer; forming an upper plate material layer on the insulating material layer; performing a patterned etching treatment on the upper plate material layer, the insulating material layer and the lower plate material layer to form the upper plate layer, the insulating layer and the lower plate layer, and the capacitor structure is composed of the upper plate layer, the insulating layer and the lower plate layer.
16. The method of forming a semiconductor structure of claim 15, wherein, The method for performing the patterned etching treatment on the upper plate material layer, the insulating material layer and the lower plate material layer comprises: etching the upper plate material layer and part of the insulating material layer by using a first etching process to form the upper plate layer; depositing a first anti-reflection layer, the first anti-reflection layer covering the surface of the exposed upper plate layer and the surface of the insulating material layer; etching the first anti-reflection layer, the remaining part of the insulating material layer and the lower plate material layer by using a second etching process to form the insulating layer and the lower plate layer.
17. The method of forming a semiconductor structure of claim 13, wherein The lower plate layer is a composite stack.
18. The method of forming a semiconductor structure of claim 17, wherein, The lower plate layer comprises: a first sub-plate layer, a second sub-plate layer located on the first sub-plate layer, and a third sub-plate layer located on the second sub-plate layer.
19. The method of forming a semiconductor structure of claim 14, wherein, The first electrical interconnection structure comprises: a first conductive plug, and a first conductive layer located on the first conductive plug and electrically connected with the first conductive plug.
20. The method of forming a semiconductor structure of claim 19, wherein, The forming method of the first electrical interconnection structure comprises: forming a first conductive via and the first conductive trench in the first dielectric layer by using a damascene process, the first conductive trench exposing the first conductive via; forming a first conductive material layer in the first conductive via, in the first conductive trench and on the first dielectric layer; performing a planarization treatment on the first conductive material layer until the top surface of the first dielectric layer is exposed, thereby forming the first conductive plug in the first conductive via and the first conductive layer in the first conductive trench.
21. The method of forming a semiconductor structure of claim 19, wherein The second electrical interconnection structure comprises: a second conductive plug located in the second dielectric layer, the second conductive plug being electrically connected with the first conductive layer; a third conductive plug located in the first dielectric layer and the second dielectric layer, the third conductive plug being electrically connected with the lower plate layer; a fourth conductive plug located in the first dielectric layer and the second dielectric layer, the fourth conductive plug being electrically connected with the upper plate layer.
22. The method of forming a semiconductor structure of claim 21, wherein, The forming method of the second electric interconnection structure comprises: forming a second conductive via in the second dielectric layer, the second conductive via exposing a surface of the first conductive layer; forming a third conductive via in the first dielectric layer and the second dielectric layer, the third conductive via exposing a surface of the lower plate layer; forming a fourth conductive via in the first dielectric layer and the second dielectric layer, the fourth conductive via exposing a surface of the upper plate layer; forming a second conductive material layer in the second conductive via, the third conductive via, the fourth conductive via and on the second dielectric layer; performing a planarization treatment on the second conductive material layer until a top surface of the second dielectric layer is exposed, forming the second conductive plug in the second conductive via, forming the third conductive plug in the third conductive via, and forming the fourth conductive plug in the fourth conductive via.