Semiconductor device having interconnect structure with reinforcing metal alloy therein

Abstract

A semiconductor device includes a substrate and an interconnect layer on the substrate. The interconnection layer includes an interconnection structure having a first interconnection line therein, the first interconnection line including a metal alloy, the metal alloy including a single phase of ruthenium and a non-ruthenium first element, a concentration of the non-ruthenium first element in the metal alloy being in a range of greater than 0 at% to 40 at%. In the case where the first element is molybdenum, the concentration of the first element in the metal alloy may be in the range of 0.1 at% to 30 at%; however, if the first element is tungsten, the concentration of the first element in the metal alloy may be in the range of 0.1 at% to 40 at%.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2024-0085129, filed on June 28, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device having an interconnect structure with an enhanced metal alloy. Background Technology

[0003] To meet the growing demand for miniaturization, thinning, and lightweighting of electronic products, active research has been conducted on metallic elements and alloys that can be applied to thin films with a thickness of 10 nm or less. Specifically, as the size of semiconductor devices decreases, the demand for metallic materials is increasing because they typically have shorter electron mean free path (eMFP), lower resistance, and smaller surface roughness. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device including metal lines formed of a metallic material having low resistivity and generally low roughness.

[0005] According to embodiments of the present invention, a semiconductor device may include: a substrate including transistors; and an interconnect layer disposed on the substrate. The interconnect layer may include an interconnect structure comprising first interconnect lines. The first interconnect line may include ruthenium and a metal alloy, the metal alloy comprising a first element different from ruthenium. The composition ratio of the first element in the metal alloy may be greater than 0 at% and less than 40 at%, and the metal alloy may have a single phase of ruthenium.

[0006] According to embodiments of the present invention, a semiconductor device may include: a substrate including transistors; and an interconnect layer disposed on the substrate. The interconnect layer may include interconnect structures and first vias in the interconnect structures. The interconnect structures may include first interconnect lines, and the first interconnect lines may include ruthenium and a first metal alloy comprising a first element different from ruthenium. The composition ratio of the first element in the first metal alloy may be greater than 0 at% and less than 40 at%, and the first metal alloy may have a single phase of ruthenium.

[0007] According to embodiments of the present invention, a semiconductor device may include: a substrate including transistors; and an interconnect layer disposed on the substrate. The interconnect layer may include an interconnect structure comprising a plurality of first interconnect lines, each of the first interconnect lines extending in a first direction parallel to the substrate. The first interconnect lines may include interconnect lines having a pitch ranging from 1 nm to 60 nm in a second direction parallel to the substrate and perpendicular to the first direction. The first interconnect lines may include ruthenium and a metal alloy comprising a first element different from ruthenium. The composition ratio of the first element in the metal alloy may be greater than 0 at% and less than 40 at%, and the metal alloy may have a single phase of ruthenium. Attached Figure Description

[0008] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0009] Figure 2 It is along Figure 1 A sectional view taken by line A-A'.

[0010] Figures 3A to 3D This is a schematic diagram illustrating an interconnection structure according to an embodiment of the inventive concept.

[0011] Figure 4A It is a graph showing the roughness measured from metal alloys according to some embodiments of the inventive concept and pure metals according to a comparative example.

[0012] Figure 4B This is a graph showing the roughness reduction rate of a metal alloy according to some embodiments of the inventive concept relative to a pure metal according to a comparative example.

[0013] Figure 5A It is a graph showing the resistivity values ​​measured from metal alloys according to some embodiments of the inventive concept and pure metals according to a comparative example.

[0014] Figure 5B It is a graph showing the resistivity values ​​measured from pure metals and metal alloys according to some embodiments of the inventive concept, relative to the composition ratio of a first element in the metal alloy.

[0015] Figure 6 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention.

[0016] Figure 7A It is along Figure 6 A sectional view taken by line A-A'.

[0017] Figure 7B It is along Figure 6 The sectional view taken by line B-B'.

[0018] Figure 7C It is along Figure 6 A sectional view taken by line C-C'.

[0019] Figure 7D It is along Figure 6 A sectional view taken by line D-D'.

[0020] Figure 8 It is shown Figure 7A An enlarged sectional view of part "A".

[0021] Figures 9A to 9D This is a schematic diagram illustrating a method for manufacturing an interconnect structure according to an embodiment of the inventive concept.

[0022] Figure 10 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the inventive concept.

[0023] Figure 11 Is with Figure 10 The floor plan corresponding to part "P1".

[0024] Figure 12A It is along Figure 11 A sectional view taken by line A-A'.

[0025] Figure 12B It is along Figure 11 The sectional view taken by line B-B'.

[0026] Figure 12C It is along Figure 11 A sectional view taken by line C-C'.

[0027] Figure 13 It is shown Figure 12A A magnified view of part "P2".

[0028] Figures 14A to 14C This is a schematic diagram illustrating a method for manufacturing an interconnect structure according to an embodiment of the inventive concept. Detailed Implementation

[0029] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are illustrated.

[0030] Figure 1 This is a plan view illustrating a semiconductor device according to an embodiment of the concept of the present invention. Figure 2 It is along Figure 1 The sectional view taken by line A-A', and Figures 3A to 3D This is a schematic diagram illustrating an interconnection structure according to an embodiment of the inventive concept. (Refer to...) Figure 1 and Figure 2The semiconductor device 20 may include a substrate 100 containing transistors and an interconnect layer ML disposed on the substrate 100. As shown, the transistor may include a first source / drain pattern (or referred to as a "first source / drain region") SD1, a gate electrode G, and a second source / drain pattern (or referred to as a "second source / drain region") SD2. The first source / drain pattern SD1 and the second source / drain pattern SD2 may be impurity regions of a first conductivity type (e.g., n-type) or a second conductivity type (e.g., p-type). The shape of the channel is not limited to a planar transistor. Figure 1 and Figure 2 The transistor may be in the shape shown in the figure; for example, the transistor may be a fin field-effect transistor (FINFET) or a multi-bridge channel field-effect transistor (MBCFET) with a non-planar channel.

[0031] like Figure 2 As shown, the interconnect layer ML may include a first interconnect structure M1, a second interconnect structure M2, a first via VI0, a second via VI1, a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, and a fourth insulating layer IL4 disposed on the substrate 100. The first interconnect structure M1 may include multiple interconnect lines, each of which extends in a second direction D2 parallel to the substrate 100. The first interconnect structure M1 may have a linewidth L1 in the first direction D1, which is parallel to the substrate 100 and perpendicular to the second direction D2. The first interconnect structure M1 may have a thickness L2 in a third direction D3 perpendicular to the substrate 100. The first interconnect structure M1 may have a pitch P in the first direction D1.

[0032] The second interconnect structure M2 may be disposed on the substrate 100. The first interconnect structure M1 may be disposed between the second interconnect structure M2 and the substrate 100. Similar to the first interconnect structure M1, the second interconnect structure M2 may extend in the second direction D2 and may have a linewidth and pitch in the first direction D1 and a thickness in the third direction D3.

[0033] A first via VI0 may be disposed on the substrate 100 and may be positioned between the first interconnect structure M1 and the substrate 100. The first via VI0 may have a diameter L3 on the plane contacting the substrate 100. The first via VI0 may connect the first interconnect structure M1 to at least one of the gate electrode G, the first source / drain pattern SD1, and the second source / drain pattern SD2. The first via VI0 may contact one of the interconnect lines of the first interconnect structure M1. The first via VI0 may contact at least one of the gate electrode G or the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0034] The second via VI1 may be disposed on the substrate 100 and may be positioned between the first interconnect structure M1 and the second interconnect structure M2. The second via VI1 may have a diameter on a plane parallel to the substrate 100. The second via VI1 may contact one of the interconnect lines in the first interconnect structure M1. The second via VI1 may contact one of the interconnect lines in the second interconnect structure M2.

[0035] A first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, and a fourth insulating layer IL4 may be disposed on the substrate 100. The first insulating layer IL1 may cover the top surface of the substrate 100 and the side surface of the first via VI0. The second insulating layer IL2 may be disposed on the first insulating layer IL1 and may cover the top surface of the first insulating layer IL1 and the side surface of the first interconnect structure M1. The third insulating layer IL3 may be disposed on the second insulating layer IL2 and may cover the top surface of the second insulating layer IL2 and the side surface of the second via VI1. The fourth insulating layer IL4 may be disposed on the third insulating layer IL3 and may cover the top surface of the third insulating layer IL3 and the side surface of the second interconnect structure M2. Although not shown, additional interconnect structures (e.g., M3, M4, ...), additional vias (e.g., VI2, VI3, ...), and additional insulating layers (e.g., IL5, IL6, ...) may be disposed on the top surface of the fourth insulating layer IL4 and the top surface of the second interconnect structure M2.

[0036] Semiconductor device 20 may include interconnect structures with linewidths greater than 0 nm and less than 200 nm, for example, in the range of 0.1 nm to 100 nm, 1 nm to 40 nm, 3 nm to 30 nm, or 5 nm to 10 nm. In an embodiment, the linewidth L1 of the first interconnect structure M1 and / or the linewidth of the second interconnect structure M2 may be greater than 0 nm and less than 200 nm, in the range of 0.1 nm to 100 nm, 1 nm to 40 nm, 3 nm to 30 nm, 0.1 nm to 10 nm, or 5 nm to 10 nm.

[0037] Semiconductor device 20 may include interconnect structures with a thickness greater than 0 nm and less than 200 nm, for example, in the range of 0.1 nm to 100 nm, 1 nm to 40 nm, 3 nm to 30 nm, or 5 nm to 10 nm. In an embodiment, the thickness L2 of the first interconnect structure M1 and / or the thickness of the second interconnect structure M2 may be greater than 0 nm or less than 200 nm, and may be in the range of 0.1 nm to 100 nm, 1 nm to 40 nm, 3 nm to 30 nm, 0.1 nm to 10 nm, or 5 nm to 10 nm.

[0038] Semiconductor device 20 may include interconnect structures with a pitch greater than 0 nm and less than 500 nm, for example, in the range of 0.1 nm to 400 nm, 1 nm to 300 nm, 3 nm to 200 nm, 5 nm to 100 nm, 10 nm to 60 nm, or 15 nm to 30 nm. In an embodiment, the pitch P of the first interconnect structure M1 and / or the pitch of the second interconnect structure M2 may be greater than 0 nm and less than 500 nm, and may be in the range of 0.1 nm to 400 nm, 1 nm to 300 nm, 3 nm to 200 nm, 5 nm to 100 nm, 1 nm to 60 nm, 10 nm to 60 nm, or 15 nm to 30 nm.

[0039] In an embodiment, the semiconductor device 20 may further include a capacitor (not shown). The capacitor may be electrically connected to a first source / drain pattern SD1, and the first interconnect structure M1 may be electrically connected to a second source / drain pattern SD2 via a first via VI0.

[0040] Combination Figures 3A to 3D For reference Figure 1 and Figure 2 According to some embodiments of the inventive concept, the semiconductor device 20 may include one of interconnect structures 10, 11, 12, and 13. At least one of the first interconnect structure M1 and the second interconnect structure M2 may be one of interconnect structures 10, 11, 12, and 13.

[0041] Reference Figure 3A The interconnect structure 10 may include a first interconnect 1. The first interconnect 1 may include a metal alloy comprising ruthenium (Ru) and a first element different from ruthenium (Ru). In embodiments, the first element may be molybdenum (Mo) or tungsten (W). In the metal alloy, the concentration (and possibly the composition ratio) of the first element may be greater than 0 at% and less than 40 at%, and may be in the range of 0.1 at% to 12 at%, 0.1 at% to 30 at%, 0.1 at% to 40 at%, 0.5 at% to 25 at%, 1 at% to 20 at%, 3 at% to 15 at%, or 5 at% to 12 at%. The metal alloy may have a single phase of ruthenium and may not have a multiphase mixture of ruthenium and molybdenum or ruthenium and tungsten. Furthermore, the metal alloy may not have a single phase of molybdenum or tungsten.

[0042] Reference Figure 3BThe interconnect structure 11 may further include a barrier pattern 2. The barrier pattern 2 may be disposed on the first interconnect line 1. The barrier pattern 2 may include at least one of a metal, a metal nitride, and a metal silicide. For example, the barrier pattern 2 may include at least one of TiN, TiSi, TiSiN, WSi, WSiN, Ti, Ta, W, Co, and CoSi. The thickness of the barrier pattern 2 may be greater than 0 nm and equal to or less than 20 nm, or may be in the range of 0.1 nm to 15 nm, 1 nm to 10 nm, 0.1 nm to 5 nm, or 3 nm to 5 nm. The thickness of the barrier pattern 2 may be less than the thickness of the first interconnect line 1. Figure 1 and Figure 2 For reference Figure 3B The blocking pattern 2 can be placed between the first interconnect 1 and the substrate 100.

[0043] Reference Figure 3C The interconnect structure 12 may include a first interconnect line 1 and a second interconnect line 3 disposed on the first interconnect line 1. The second interconnect line 3 may include ruthenium (Ru). The composition ratio (or concentration) of ruthenium in the second interconnect line 3 may be greater than the composition ratio (or concentration) of ruthenium in the first interconnect line 1. For example, the composition ratio of ruthenium in the second interconnect line 3 may be greater than or equal to 99 at%. Figure 1 and Figure 2 For reference Figure 3C The first interconnect 1 can be placed between the second interconnect 3 and the substrate 100.

[0044] Next, refer to Figure 3D The interconnect structure 13 may include a first interconnect line 1, a barrier pattern 2, and a second interconnect line 3. The first interconnect line 1 may be placed between the second interconnect line 3 and the barrier pattern 2.

[0045] Combination Figures 3A to 3D For reference Figure 1 and Figure 2 The semiconductor device 20 may include a via disposed on one of the interconnect structures 10, 11, 12, and 13. The via may be a first via VI0 and / or a second via VI1. In an embodiment, the via disposed on one of the interconnect structures 10, 11, 12, and 13 may include a metal alloy comprising ruthenium (Ru) and a first element different from ruthenium (Ru). In an embodiment, the first element may be molybdenum (Mo) or tungsten (W). In the metal alloy, the composition ratio of the first element may be greater than 0 at% and less than 40 at%, and may be in the range of 0.1 at% to 30 at%, 0.5 at% to 25 at%, 1 at% to 20 at%, 3 at% to 15 at%, or 5 at% to 12 at%.

[0046] The metal alloy may have a ruthenium phase. The metal alloy may have a single ruthenium phase. The metal alloy may not have a multiphase structure consisting of a ruthenium phase mixed with a molybdenum phase or a ruthenium phase mixed with a tungsten phase. The metal alloy may not have a single molybdenum phase or a single tungsten phase. In an embodiment, the metal alloy in the via may be the same as the metal alloy used for the first interconnect 1 in one of the interconnect structures 10, 11, 12, and 13.

[0047] In another embodiment, the via disposed on one of the interconnect structures 10, 11, 12, and 13 may include at least one of Mo, W, and Co. The minimum diameter of the via may be greater than 0 nm and less than 200 nm, and may be in the range of 0.1 nm to 100 nm, 1 nm to 40 nm, 3 nm to 30 nm, or 5 nm to 10 nm. In an embodiment, the minimum diameter L3 of the first via VI0 and / or the minimum diameter of the second via VI1 may be greater than 0 nm or less than 200 nm, and may be in the range of 0.1 nm to 30 nm, 0.1 nm to 100 nm, 1 nm to 40 nm, 3 nm to 30 nm, or 5 nm to 10 nm.

[0048] Formation of thin metal films and measurement of roughness and resistivity An insulating layer containing SiO2 is formed on a substrate including pure silicon (Si). Thin films of metal alloys according to some embodiments of the inventive concept and thin films of pure metals according to comparative examples are formed on the insulating layer. Ruthenium-molybdenum alloys and ruthenium-tungsten alloys are used as the metal alloys. Samples are prepared by changing the composition ratio of molybdenum or tungsten and adjusting the thickness of the film, while keeping other conditions unchanged. The roughness (R0) of each film is measured by atomic force microscopy (AFM). a In addition, the resistivity (ρ) of each thin film was measured.

[0049] Figure 4A This is a graph showing the roughness measured from metal alloys according to some embodiments of the inventive concept and pure metals according to a comparative example. In detail, Figure 4A The roughness data were measured from films of 5 nm, 10 nm, and 30 nm thickness made of pure ruthenium and ruthenium-molybdenum alloys (molybdenum content of 1 at%, 3 at%, and at 5%). Furthermore, Figure 4B This is a graph showing the rate of roughness reduction of a metal alloy according to some embodiments of the inventive concept, relative to a pure metal according to a comparative example. In detail, Figure 4B The roughness reduction rate of the ruthenium-molybdenum alloy film compared to a pure ruthenium film of the same thickness is shown.

[0050] In addition, Table 1 shows the roughness values ​​measured from 30 nm thick films made of ruthenium, molybdenum, tungsten, ruthenium-molybdenum alloy (molybdenum content of 15 at%) and ruthenium-tungsten alloy (tungsten content of 21 at%).

[0051]

[0052] Table 1 Referring to Table 1, ruthenium exhibits low resistivity but high roughness, while tungsten and molybdenum, in contrast, possess low roughness but high resistivity. This suggests that incorporating tungsten or molybdenum atoms into a ruthenium-based film can result in a film with both low resistivity and low roughness, making it a suitable alloy for use in fine interconnect structures.

[0053] Reference Figure 4A and Figure 4B Even when the molybdenum content in the RuMo alloy is low (e.g., 1 at%), experiments show that the film roughness can be improved by 10% or more compared to pure ruthenium. Additionally, as... Figure 4A As shown in Table 1, the higher the molybdenum or tungsten content in the RuMo or RuW alloys, the greater the improvement in roughness. (Refer to...) Figure 4A A 30 nm thick film made of RuMo or RuW alloys with a molybdenum or tungsten content of 5 at% or higher has better roughness than a 30 nm thick film made of pure molybdenum or pure tungsten.

[0054] Figure 5A This is a graph showing the resistivity values ​​measured from metal alloys according to some embodiments of the inventive concept and pure metals according to a comparative example. In detail, Figure 5A The resistivity data were measured from films of 5 nm, 8 nm, 10 nm, and 30 nm thickness made of pure ruthenium, pure molybdenum, pure tungsten, and ruthenium-molybdenum alloys (molybdenum content of 1 at%, 3 at%, and 5 at%). (Refer to...) Figure 5A Regardless of their thickness (e.g., from 5 nm to 30 nm), RuMo alloys have lower resistivity than pure molybdenum or pure tungsten. Furthermore, RuMo alloys with 5 at% molybdenum content have slightly higher resistivity than pure ruthenium, while RuMo alloys with 1 at% or 3 at% molybdenum content have essentially the same resistivity as pure ruthenium.

[0055] Figure 5B This is a graph showing resistivity values ​​measured from pure metals and metal alloys according to some embodiments of the inventive concept, relative to the composition ratio of a first element in the metal alloy. In detail, Figure 5B The resistivity values ​​measured from a 5 nm thick film made of pure tungsten and ruthenium-molybdenum alloy (molybdenum content of 1 at%, 3 at%, and 5 at%) are shown. Figure 5B In the diagram, the x-axis represents the molybdenum content.

[0056] Reference Figure 5A and Figure 5B The molybdenum content (at%) of a 5 nm thick RuMo alloy film can be calculated. At this molybdenum content, the RuMo alloy film has a lower resistivity than a 5 nm thick pure tungsten film. For example, Figure 5A and Figure 5B As shown, when the RuMo alloy or RuW alloy film has a Mo or W content of 12 at% or less, the RuMo alloy or RuW alloy film has a better resistivity than pure molybdenum or pure tungsten.

[0057] Table 2 shows the ρ values ​​measured from samples made of pure ruthenium and ruthenium-molybdenum alloys (molybdenum content of 1 at%, 3 at%, and 5 at%). 10 / ρ 30 The resistivity ratio, where ρ 30 The resistivity, ρ, of a 30nm thick sample. 10 This is the resistivity of a 10nm thick sample.

[0058]

[0059] Table 2 Table 3 shows the ρ5 / ρ values ​​measured from samples made of pure ruthenium and ruthenium-molybdenum alloys (with molybdenum contents of 1 at%, 3 at%, and 5 at%). 10 The resistivity ratio, where ρ 10 ρ is the resistivity of a 10 nm thick sample and ρ5 is the resistivity of a 5 nm thick sample.

[0060]

[0061] Table 3 Referring to Tables 2 and 3, even when the molybdenum content in the RuMo alloy sample is low, the increase in resistivity caused by the decrease in film thickness in the RuMo alloy sample is lower than or equal to that in the pure Ru sample.

[0062] Figure 6 This is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 7A It is along Figure 6 A sectional view taken by line A-A'. Figure 7B It is along Figure 6 The sectional view taken by line B-B'. Figure 7C It is along Figure 6 A sectional view taken by line C-C'. Figure 7D It is along Figure 6 A sectional view taken along line D-D'. (Refer to...) Figure 6 and Figures 7A to 7DA single-height cell (SHC) can be disposed on the substrate 1100. Logic transistors constituting the logic circuit can be disposed on the single-height cell (SHC). The substrate 1100 can be a semiconductor substrate, formed of or including silicon, germanium, silicon-germanium, compound semiconductor materials, etc. In an embodiment, the substrate 1100 can be a silicon wafer.

[0063] The substrate 1100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in a second direction D2. In an embodiment, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0064] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR, which is formed in the upper part of the substrate 1100. The first active pattern AP1 may be disposed on a first active region AR1, and the second active pattern AP2 may be disposed on a second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertically projecting portions of the substrate 1100.

[0065] A device isolation layer ST may be disposed on the substrate 1100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover the first channel pattern CH1 and the second channel pattern CH2, which will be described below.

[0066] A first channel pattern CH1 may be disposed on a first active pattern AP1. A second channel pattern CH2 may be disposed on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first to third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in a direction perpendicular to the top surface of the substrate 1100 (e.g., third direction D3). Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of or include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first to third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon.

[0067] Multiple first source / drain patterns SD1 may be disposed on a first active pattern AP1. Multiple first recesses RS1 may be formed in the upper part of the first active pattern AP1. The first source / drain patterns SD1 may be disposed in the first recesses RS1 respectively. The first source / drain patterns SD1 may be impurity regions of a first conductivity type (e.g., n-type). A first channel pattern CH1 may be disposed between a pair of first source / drain patterns SD1. In other words, a pair of first source / drain patterns SD1 may be interconnected with each other through stacked first semiconductor patterns to third semiconductor patterns SP1, SP2 and SP3.

[0068] Multiple second source / drain patterns SD2 may be disposed on the second active pattern AP2. Multiple second recesses RS2 may be formed in the upper part of the second active pattern AP2. The second source / drain patterns SD2 may be disposed in the second recesses RS2 respectively. The second source / drain patterns SD2 may be impurity regions of a second conductivity type (e.g., p-type). A second channel pattern CH2 may be disposed between a pair of second source / drain patterns SD2. In other words, a pair of second source / drain patterns SD2 may be interconnected through stacked first semiconductor patterns to third semiconductor patterns SP1, SP2 and SP3.

[0069] The gate electrode GE may extend in a first direction D1 to intersect with the first channel pattern CH1 and the second channel pattern CH2. Each of the gate electrodes GE may be vertically (e.g., in a third direction D3) superimposed on the first channel pattern CH1 and the second channel pattern CH2. The gate electrode GE may include a first portion PO1 located between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second portion PO2 located between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 located between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0070] Reference Figure 7D The gate electrode GE may be disposed on the top surface TS, bottom surface BS, and opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The transistor according to this embodiment may be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE is configured to three-dimensionally surround the channel pattern.

[0071] A pair of gate spacers GS may be disposed on opposite side surfaces of the fourth portion PO4 of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE and in a first direction D1. The gate spacers GS may extend to opposite side surfaces of the gate overlay pattern GP. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer insulating layer 1110, which will be described below. In an embodiment, the gate spacers GS may be formed of or include at least one of SiCN, SiCON, and SiN. In an embodiment, the gate spacers GS may have a multilayer structure comprising at least two layers, each of which is made of SiCN, SiCON, or SiN.

[0072] A gate overlay pattern GP may be disposed on the gate electrode GE. The gate overlay pattern GP may extend along the gate electrode GE and in a first direction D1. The gate overlay pattern GP may be formed of or include a material having etch selectivity with respect to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. Specifically, the gate overlay pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, and SiN.

[0073] A gate insulating layer GI may be disposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI may cover the top surface TS, bottom surface BS, and opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI may cover the top surface of the device isolation layer ST beneath the gate electrode GE. The gate insulating layer GI may extend into the region between the gate electrode GE and the gate spacer GS.

[0074] Return to reference Figure 6 and Figures 7A to 7D The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a preferred work function metal, which can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be realized. For example, the first to third portions PO1, PO2, and PO3 of the gate electrode GE may be composed of the first metal pattern as a work function metal.

[0075] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include a layer composed of at least one metallic material and nitrogen (N), wherein the at least one metallic material is selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In an embodiment, the first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked work function metal layers.

[0076] The second metal pattern may include a metal with lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal material selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). In an embodiment, the fourth portion PO4 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0077] A first interlayer insulating layer 1110 may be disposed on a substrate 1100. The first interlayer insulating layer 1110 may cover a gate spacer GS and a first source / drain pattern SD1 and a second source / drain pattern SD2. The top surface of the first interlayer insulating layer 1110 may be substantially coplanar with the top surface of the gate overlay pattern GP and the top surface of the gate spacer GS.

[0078] A second interlayer insulating layer 1120 may be disposed on the first interlayer insulating layer 1110 to cover the gate overlay pattern GP. A first via insulating layer 1131 may be disposed on the second interlayer insulating layer 1120. A first interconnect insulating layer 1132 may be disposed on the first via insulating layer 1131. A second via insulating layer 1141 may be disposed on the first interconnect insulating layer 1132. A second interconnect insulating layer 1142 may be disposed on the second via insulating layer 1141. In an embodiment, the first interlayer insulating layer 1110, the second interlayer insulating layer 1120, the first via insulating layer 1131, the second via insulating layer 1141, the first interconnect insulating layer 1132, and the second interconnect insulating layer 1142 may include a silicon oxide layer.

[0079] A single-height element SHC may have a first boundary BD1 and a second boundary BD2 that are opposite to each other in a second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. A single-height element SHC may have a third boundary BD3 and a fourth boundary BD4 that are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0080] A pair of segmented structures DB, facing each other in the second direction D2, can be disposed on both sides of the single-height cell SHC. For example, the pair of segmented structures DB can be disposed on the first boundary BD1 and the second boundary BD2 of the single-height cell SHC, respectively. The segmented structures DB can extend in the first direction D1 and be parallel to the gate electrode GE. The pitch between adjacent segmented structures DB and the gate electrode GE can be equal to the first pitch.

[0081] The segmentation structure DB can be configured to penetrate the first interlayer insulation layer 1110 and the second interlayer insulation layer 1120, and can extend into the first active pattern AP1 and the second active pattern AP2. The segmentation structure DB can be configured to penetrate the upper part of each of the first active pattern AP1 and the second active pattern AP2. The segmentation structure DB can electrically separate the active region of a single-height cell SHC from the active regions of adjacent cells.

[0082] The active contact AC can be configured to penetrate the first interlayer insulation layer 1110 and the second interlayer insulation layer 1120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC can be respectively disposed on both sides of the gate electrode GE. When viewed in a plan view, the active contact AC can be a strip pattern extending in the first direction D1.

[0083] The active contact AC can be a self-aligned contact. That is, the active contact AC can be formed in a self-aligned manner using a gate cover pattern GP and a gate spacer GS. For example, the active contact AC can cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC can cover a portion of the top surface of the gate cover pattern GP.

[0084] A metal-semiconductor compound layer SC (e.g., a silicide layer) may be disposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 through the metal-semiconductor compound layer SC. In embodiments, the metal-semiconductor compound layer SC may be formed of or include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0085] Reference Figure 7B The area located on the active contact AC and adjacent to the gate contact GC0 may be filled with an upper insulating pattern UIP. The bottom surface of the upper insulating pattern UIP may be lower than the bottom surface of the gate contact GC0. In other words, due to the presence of the upper insulating pattern UIP, the top surface of the active contact AC adjacent to the gate contact GC0 may be lower than the bottom surface of the gate contact GC0.

[0086] The active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. In embodiments, the conductive pattern FM may be formed of or include at least one of a metallic material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt). The barrier pattern BM may cover the side and bottom surfaces of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of or include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may be formed of or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0087] The first metal wire M1 may be disposed in the first interconnect insulating layer 1132. The first metal wire M1 may extend in the second direction D2 and be parallel to each other.

[0088] The first via VI0 may be disposed below the first metal line M1. The first via VI0 may be disposed in the first via insulating layer 1131. The active contact AC and the first metal line M1 may be electrically connected to each other through the first via VI0. The gate contact GC0 and the first metal line M1 may be electrically connected to each other through the first via VI0. The first metal line M1 and the first via VI0 below the first metal line M1 may be formed by separate processes.

[0089] The second metal wire M2 may be disposed in the second interconnect insulating layer 1142. Each of the second metal wires M2 may be a linear pattern or a strip pattern extending in the first direction D1. In other words, the second metal wires M2 may extend in the first direction D1 and be parallel to each other.

[0090] A second via VI1 may be disposed below the second metal line M2. The second via VI1 may be disposed within the second via insulating layer 1141. The first metal line M1 and the second metal line M2 may be electrically connected to each other via VI1. As an example, the second metal line M2 and the second via VI1 may be formed together. Although not shown, multiple metal layers (e.g., M3, M4, M5, etc.) may be additionally stacked on the second interconnect insulating layer 1142. Each of the stacked metal layers may include an interconnect serving as a routing structure between cells.

[0091] Figure 8 It is shown Figure 7A An enlarged sectional view of part "A". Combined with... Figures 3A to 3D For reference Figure 6 , Figure 7A and Figure 8 The first metal line M1 and / or the second metal line M2 can be one of the interconnect structures 10, 11, 12 and 13.

[0092] The barrier pattern 2 can be configured to improve the roughness of the first metal line M1 and / or the second metal line M2. If necessary, the barrier pattern 2 can be placed between the substrate 1100 and the first interconnect line 1. The second interconnect line 3 can be configured to improve the resistivity of the first metal line M1 and / or the second metal line M2, and the first interconnect line 1 can be placed between the substrate 1100 and the second interconnect line 3.

[0093] Figures 9A to 9D This is an enlarged cross-sectional view schematically illustrating a method for manufacturing an interconnect structure according to an embodiment of the inventive concept (specifically, Figure 8 (Enlarged cross-sectional view of part "B"). The following description will refer to a manufacturing method in which the first metal wire M1 is configured to have an interconnect structure 13.

[0094] Reference Figure 9A A first via VI0 can be formed in the first via insulating layer 1131, and a barrier pattern 2 can be formed on the first via insulating layer 1131. Forming the first via VI0 in the first via insulating layer 1131 may include etching the first via insulating layer 1131 and forming the first via VI0 in the first via insulating layer 1131. The formation of the barrier pattern 2 can be performed using a physical vapor deposition (PVD) process or an atomic layer deposition (ALD) process. Depending on the desired roughness value of the interconnect structure, the formation of the barrier pattern 2 may be omitted.

[0095] Reference Figure 9B A first interconnect 1 can be formed on the first via insulating layer 1131, and a second interconnect 3 can be formed on the first via insulating layer 1131. The first interconnect 1 can cover the top surface of the barrier pattern 2. The second interconnect 3 can cover the top surface of the first interconnect 1. The formation of the first interconnect 1 and the second interconnect 3 can be performed using a physical vapor deposition (PVD) process or an atomic layer deposition (ALD) process. Depending on the desired resistivity value of the final interconnect structure, the formation of the second interconnect 3 can be omitted.

[0096] Reference Figure 9C A first metal line M1 can be formed. Forming the first metal line M1 may include etching a portion of the second interconnect 3, etching a portion of the first interconnect 1, and etching a portion of the barrier pattern 2. A dry etching process can be used to perform the partial etching of the first interconnect 1, the second interconnect 3, and the barrier pattern 2. The barrier pattern 2, the first interconnect 1, and the second interconnect 3 may have substantially the same length in the second direction D2.

[0097] Reference Figure 9D A first interconnect insulating layer 1132 may be formed on the first via insulating layer 1131. The first interconnect insulating layer 1132 may cover a portion of the top surface of the first via insulating layer 1131 and the side surface of the first metal line M1. The first interconnect insulating layer 1132 may expose the first metal line M1. An annealing process may be performed after the formation of the first interconnect insulating layer 1132.

[0098] Figure 10 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the inventive concept. (Refer to...) Figure 10 The semiconductor memory device 2000 may include cell blocks CB and peripheral blocks PB surrounding each of the cell blocks CB. Each of the cell blocks CB may include cell circuitry (e.g., a memory integrated circuit). The peripheral blocks PB may include various peripheral circuitry for operating the cell circuitry, and the peripheral circuitry may be electrically connected to the cell circuitry.

[0099] The peripheral block PB may include a sense amplifier circuit SA and a sub-word line driver circuit SWD. In an embodiment, the sense amplifier circuits SA may be arranged facing each other, with the unit block CB positioned between the sense amplifier circuits SA, and the sub-word line driver circuits SWD may be arranged facing each other, with the unit block CB positioned between the sub-word line driver circuits SWD. The peripheral block PB may also include a power driver circuit and a ground driver circuit for driving the sense amplifiers, but the inventive concept is not limited to this example.

[0100] Figure 11 This illustrates a semiconductor memory device according to an embodiment of the inventive concept and is related to... Figure 10 The floor plan corresponding to part "P1". Figure 12A It is along Figure 11 A cross-sectional view taken along line A-A' to illustrate a semiconductor memory device according to an embodiment of the inventive concept. Figure 12B It is along Figure 11 A cross-sectional view taken along line B-B' to illustrate a semiconductor memory device according to an embodiment of the inventive concept. Figure 12C It is along Figure 11 A cross-sectional view taken along line C-C' to illustrate a semiconductor memory device according to an embodiment of the inventive concept.

[0101] Reference Figure 11 , Figure 12A , Figure 12B and Figure 12C A substrate 2100 may be disposed. The substrate 2100 may be a semiconductor substrate (e.g., a silicon substrate, a germanium substrate, or a silicon-germanium substrate). A device isolation pattern 2120 may be disposed on the substrate 2100 to define an active pattern ACT. The active pattern ACT may be disposed on... Figure 10On the unit block CB. The active pattern ACT may be spaced apart from each other in a first direction D1 and a second direction D2 that are not parallel to each other (e.g., orthogonal). The first direction D1 and the second direction D2 may be parallel to the bottom surface of the substrate 2100. The active pattern ACT may be an isolated strip pattern that is spaced apart from each other and extends in a third direction D3. The third direction D3 may be parallel to the bottom surface of the substrate 2100 and may not be parallel to the first direction D1 and the second direction D2.

[0102] The active pattern ACT may have a shape that protrudes in a fourth direction D4 perpendicular to the bottom surface of the substrate 2100. For example, a device isolation pattern 2120 may be disposed in the substrate 2100, and the active pattern ACT may be a portion of the substrate 2100 surrounded by the device isolation pattern 2120. For ease of explanation, unless otherwise stated, the term "substrate 2100" may refer to the remaining portion of the substrate 2100 excluding the active pattern ACT.

[0103] Device isolation pattern 2120 may include an insulating material and may be formed of or include at least one of silicon oxide, silicon nitride, and combinations thereof. Device isolation pattern 2120 may be a single layer made of a single material or a composite layer comprising two or more materials.

[0104] Word lines WL can be configured to intersect with the active pattern ACT. As an example, word lines WL can intersect with the active pattern ACT and the device isolation pattern 2120 in a first direction D1. In an embodiment, multiple word lines WL can be provided. Word lines WL can be spaced apart from each other in a second direction D2. In an embodiment, a pair of word lines WL adjacent to each other in the second direction D2 can be configured to intersect with the active pattern ACT.

[0105] Word lines WL may be disposed in a trench region (or trench) TR that intersects the active pattern ACT and the device isolation pattern 2120. The trench region TR may extend in a first direction D1. Each word line WL may include a gate electrode GE, a gate insulating pattern (or gate insulating layer) GI, and a gate cover pattern GC1. The gate electrode GE may intersect the active pattern ACT and the device isolation pattern 2120 in the first direction D1. The gate insulating pattern GI may be disposed between the gate electrode GE and the active pattern ACT, and between the gate electrode GE and the device isolation pattern 2120. The gate cover pattern GC1 may be disposed on the gate electrode GE to cover the top surface of the gate electrode GE.

[0106] A buffer pattern 2210 may be disposed on a substrate 2100. The buffer pattern 2210 may cover the active pattern ACT, the device isolation pattern 2120, and the word line WL. In embodiments, the buffer pattern 2210 may be formed of or include at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The buffer pattern 2210 may be a monolayer made of a single material or a composite layer comprising two or more materials.

[0107] Bit line contacts DC can be disposed on each of the active patterns ACT, and in embodiments, multiple bit line contacts DC can be disposed. Bit line contacts DC can be respectively connected to the center portion 2112 of the active pattern ACT. Bit line contacts DC can be spaced apart from each other in a first direction D1 and a second direction D2. Bit line contacts DC can be positioned between each of the active patterns ACT and a corresponding bit line BL, which will be described below. Bit line contacts DC can connect a corresponding bit line BL to the center portion 2112 of a corresponding active pattern ACT.

[0108] Bit lines BL can be disposed on bit line contacts DC. Bit lines BL can extend in a second direction D2. Bit lines BL can be disposed on bit line contacts DC, which are arranged in the second direction D2 to form lines. In an embodiment, multiple bit lines BL can be disposed. Bit lines BL can be spaced apart from each other in a first direction D1. (Refer to...) Figure 13 A more detailed description of the bit line BL.

[0109] Polysilicon patterns 2310 may be disposed between bit lines BL and buffer patterns 2210, and between bit line contacts DC that are adjacent to each other in the second direction D2. In an embodiment, multiple polysilicon patterns 2310 may be disposed. In an embodiment, the polysilicon patterns 2310 may be spaced apart from each other in the first direction D1 and the second direction D2. The top surface of the polysilicon pattern 2310 may be located at substantially the same height as the top surface of the bit line contact DC, and may be coplanar with the top surface of the bit line contact DC. The polysilicon pattern 2310 may be formed of or include doped polysilicon.

[0110] The ohmic pattern 2320 may be disposed between the bit line BL and the bit line contact DC, and between the bit line BL and the polysilicon pattern 2310. The ohmic pattern 2320 may extend along the bit line BL and in the second direction D2. The ohmic pattern 2320 may be formed of or include a metal silicide.

[0111] Bit line overlay pattern 2350 may be disposed on the top surface of bit line BL. On the top surface of bit line BL, bit line overlay pattern 2350 may extend in a second direction D2. In an embodiment, multiple bit line overlay patterns 2350 may be disposed. Bit line overlay patterns 2350 may be spaced apart from each other in a first direction D1. Bit line overlay patterns 2350 may be vertically superimposed on bit line BL. Bit line overlay pattern 2350 may be composed of a single layer or multiple layers.

[0112] Bit line spacers 2360 may be disposed on the side surface of the bit line BL and the side surface of the bit line overlay pattern 2350. Bit line spacers 2360 may cover the side surfaces of the bit line BL and the bit line overlay pattern 2350. On the side surface of the bit line BL, bit line spacers 2360 may extend in a second direction D2. In an embodiment, a plurality of bit line spacers 2360 may be disposed. Bit line spacers 2360 may be spaced apart from each other in a first direction D1.

[0113] Storage node contacts BC can be disposed between adjacent bit lines BL in the bit line BL. As an example, storage node contacts BC can be disposed between adjacent bit line spacers 2360 in the bit line spacers 2360. In an embodiment, multiple storage node contacts BC can be disposed. Storage node contacts BC can be spaced apart from each other in a first direction D1 and a second direction D2. Storage node contacts BC can be spaced apart from each other in the second direction D2 by a fence pattern FN on the word line WL. Fence patterns FN can be disposed between adjacent bit lines BL in the bit line BL. In an embodiment, multiple fence patterns FN can be disposed. Fence patterns FN can be spaced apart from each other in the first direction D1 and the second direction D2. Fence patterns FN adjacent to each other in the first direction D1 can be spaced apart, with bit lines BL disposed between fence patterns FN. Fence patterns FN adjacent to each other in the second direction D2 can be spaced apart, with storage node contacts BC disposed between fence patterns FN. In an embodiment, the fence pattern FN can be formed of silicon nitride or include silicon nitride.

[0114] The storage node contact BC can fill the second recess RS2 disposed on the edge portion 2111 of the active pattern ACT. The storage node contact BC can be connected to the edge portion 2111. The storage node contact BC can be formed or comprise at least one of doped or undoped polysilicon, a metallic material, and combinations thereof.

[0115] The second barrier pattern 2410 may conformally cover the bit line spacer 2360, the fence pattern FN, and the storage node contact BC. The second barrier pattern 2410 may include a metal nitride material (e.g., titanium nitride and tantalum nitride).

[0116] A landing pad (or contact pad, locating pad, or landing mat) LP may be provided on the storage node contact BC. In an embodiment, multiple landing pads LP may be provided. The landing pads LP may be spaced apart from each other in a first direction D1 and a second direction D2. Each of the landing pads LP may be connected to a corresponding one of the storage node contacts BC. The landing pads LP may cover the top surface of the bit line overlay pattern 2350. The lower region of the landing pad LP may be vertically stacked with respect to the storage node contact BC. The upper region of the landing pad LP may be displaced from the lower region in the first direction D1. The landing pads LP may be formed of at least one of metallic materials (e.g., tungsten, titanium, and tantalum), or may include at least one of metallic materials (e.g., tungsten, titanium, and tantalum).

[0117] The fill pattern 2440 may be configured to surround the bonding pads LP. The fill pattern 2440 may be positioned between adjacent bonding pads LP. When viewed in a plan view, the fill pattern 2440 may have a mesh pattern including holes, within which the bonding pads LP are disposed. In one embodiment, the fill pattern 2440 may include at least one of silicon nitride, silicon oxide, silicon oxynitride, and combinations thereof. In another embodiment, the fill pattern 2440 may include empty spaces (i.e., air gaps) containing an air layer.

[0118] Data storage pattern DSPs can be disposed on the bonding pad LP. In an embodiment, multiple data storage pattern DSPs can be disposed. The data storage pattern DSPs can be spaced apart from each other in a first direction D1 and a second direction D2.

[0119] In one embodiment, the data storage pattern DSP may be a capacitor comprising a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor memory device may be a dynamic random access memory (DRAM) device. In another embodiment, the data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor memory device may be a magnetic random access memory (MRAM) device. In yet another embodiment, the data storage pattern DSP may be formed of or comprise a phase change material or a variable resistance material. In this case, the semiconductor memory device may be a phase change random access memory (PRAM) device or a resistive random access memory (ReRAM) device. However, the inventive concept is not limited to these examples, and the data storage pattern DSP may include various structures and / or materials suitable for storing data.

[0120] Figure 13 It is shown Figure 12A A magnified view of part "P2". Combined with... Figures 3A to 3D For reference Figure 11 , Figure 12A , Figure 12B , Figure 12C and Figure 13 The bit line BL can be interconnect structure 13. Alternatively, the bit line BL can be one of interconnect structures 10, 11, and 12.

[0121] The barrier pattern 2 can be configured to improve the roughness of the first metal line M1 and / or the second metal line M2. If necessary, the barrier pattern 2 can be placed between the substrate 2100 and the first interconnect line 1. If necessary, the second interconnect line 3 can be configured to improve the resistivity of the first metal line M1 and / or the second metal line M2, and the first interconnect line 1 can be placed between the substrate 2100 and the second interconnect line 3.

[0122] Figures 14A to 14C This is a schematic diagram illustrating a method for manufacturing an interconnect structure according to an embodiment of the inventive concept. (Refer to...) Figure 14A An ohmic pattern 2320 can be formed on the bit line contact DC, and a barrier pattern 2 can be formed on the ohmic pattern 2320. The barrier pattern 2 can be formed by a physical vapor deposition (PVD) process or an atomic layer deposition (ALD) process. Depending on the desired roughness of the final interconnect structure, the formation of the barrier pattern 2 can be omitted.

[0123] Reference Figure 14B Bit lines BL (e.g., interconnect structures 10, 11, 12, or 13) can be formed on bit line contacts DC. A first interconnect 1 can be formed on the barrier pattern 2, and a second interconnect 3 can be formed on the first interconnect 1. The first interconnect 1 can cover the top surface of the barrier pattern 2. The second interconnect 3 can cover the top surface of the first interconnect 1. The first interconnect 1 and the second interconnect 3 can be formed by physical vapor deposition (PVD) or atomic layer deposition (ALD) processes. The first interconnect 1, the barrier pattern 2, and the second interconnect 3 can form the bit line BL. Depending on the desired resistivity value of the final interconnect structure, the formation of the second interconnect 3 can be omitted.

[0124] Reference Figure 14C A bitline overlay pattern 2350 can be formed on the bitline BL.

[0125] The exemplary embodiments described herein include semiconductor devices applied to typical logic and memory (DRAM) products, but the inventive concept is not limited to these examples. For example, the semiconductor device may be a 3-stacked CMOS image sensor (CIS) chip, a vertical NAND memory device, a bonded vertical NAND memory device in which upper and lower plates, as cell regions and peripheral regions, are bonded to each other by a wafer bonding method, a 3D DRAM device, or a back-side power transmission network (BSPDN) structure in which the back-side surface of the integrated circuit layer is thinned.

[0126] In the semiconductor device according to embodiments of the inventive concept, interconnect structures and / or via structures can be formed using a metallic material that has low resistivity and low roughness even in thin regions. In this case, the reliability of the interconnect structures, via structures, and / or semiconductor device can be improved, and process failures (e.g., open-circuit problems) can be prevented in the interconnect structures and / or via structures.

[0127] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate; and an interconnect layer on the substrate, the interconnect layer comprising an interconnect structure having a first interconnect line therein, the first interconnect line comprising a metal alloy comprising a single phase of ruthenium and a first element other than ruthenium having a concentration in the metal alloy in a range of 0 at% to 40 at%.

2. The semiconductor device according to claim 1, wherein the first element is molybdenum and the concentration of the first element in the metal alloy is in a range of 0.1 at% to 30 at%.

3. The semiconductor device according to claim 1, wherein the first element is tungsten and the concentration of the first element in the metal alloy is in a range of 0.1 at% to 40 at%.

4. The semiconductor device according to claim 1, wherein the concentration of the first element in the metal alloy is in a range of 0.1 at% to 12 at%.

5. The semiconductor device according to claim 1, wherein one of a line width and a thickness of the first interconnect line is less than 200 nm.

6. The semiconductor device according to claim 1, wherein one of a line width and a thickness of the first interconnect line is in a range of 0.1 nm to 100 nm.

7. The semiconductor device according to claim 1, wherein the interconnect structure further comprises a barrier pattern between the first interconnect line and the substrate, and wherein the barrier pattern comprises at least one of a metal, a metal nitride, and a metal silicide.

8. The semiconductor device according to claim 7, wherein a thickness of the barrier pattern is in a range of 0.1 nm to 15 nm.

9. The semiconductor device according to claim 7, wherein a thickness of the barrier pattern is less than a thickness of the first interconnect line.

10. The semiconductor device of claim 1, wherein the interconnect structure further comprises a second interconnect line on the first interconnect line, wherein the second interconnect line is in contact with the first interconnect line, wherein the first interconnect line is between the substrate and the second interconnect line, wherein the second interconnect line comprises ruthenium, and wherein a concentration of ruthenium in the second interconnect line is greater than a concentration of ruthenium in the first interconnect line.

11. The semiconductor device according to claim 10, wherein the concentration of ruthenium in the second interconnect line is greater than or equal to 99 at%.

12. The semiconductor device according to claim 10, wherein a thickness of the interconnect structure is less than 200 nm.

13. The semiconductor device according to claim 10, wherein a thickness of the interconnect structure is in a range of 1 nm to 40 nm.

14. The semiconductor device according to claim 1, wherein the substrate has an area with a transistor therein, wherein the transistor comprises a gate electrode on the substrate and a source / drain region within the substrate, wherein the interconnect layer further comprises a gate contact in electrical contact with the gate electrode and an active contact in electrical contact with the source / drain region, and wherein the interconnect structure is in electrical contact with each of the gate contact and the active contact.

15. The semiconductor device according to claim 1, wherein the substrate has an area with a transistor therein, wherein the transistor comprises a first source / drain region and a second source / drain region within the substrate, wherein the semiconductor device further comprises a capacitor electrically connected to the first source / drain region, and wherein the interconnect structure is electrically connected to the second source / drain region.

16. The semiconductor device according to claim 15, wherein the transistor further comprises a bit line contact in contact with the second source / drain region and the interconnect structure, and wherein the bit line contact extends between the second source / drain region and the interconnect structure.

17. A semiconductor device comprising: a substrate comprising a transistor; and an interconnect layer disposed on the substrate; wherein the interconnect layer comprises an interconnect structure and a first via on the interconnect structure; wherein the interconnect structure comprises a first interconnect line comprising a first metal alloy comprising ruthenium and a first element other than ruthenium, wherein a composition ratio of the first element in the first metal alloy is greater than 0 at% and less than 40 at%, and wherein the first metal alloy has a single phase of ruthenium.

18. The semiconductor device according to claim 17, wherein The first via includes a second metal alloy including ruthenium and a first element different from ruthenium, wherein a composition ratio of the first element in the second metal alloy is greater than 0 at% and less than 40 at%, and wherein the second metal alloy has a single phase of ruthenium.

19. The semiconductor device according to claim 17, wherein A minimum value of a diameter of the first via is in a range of 0.1 nm to 30 nm.

20. A semiconductor device comprising: a substrate including a transistor; and an interconnect layer on the substrate; wherein the interconnect layer includes an interconnect structure including a plurality of first interconnect lines, wherein each of the plurality of first interconnect lines extends in a first direction parallel to the substrate, wherein the plurality of first interconnect lines has a pitch in a range of 0 nm to 500 nm in a second direction parallel to the substrate and perpendicular to the first direction, wherein the plurality of first interconnect lines includes a metal alloy including ruthenium and a first element different from ruthenium, wherein a composition ratio of the first element in the metal alloy is greater than 0 at% and less than 40 at%, and wherein the metal alloy has a single phase of ruthenium.

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