Semiconductor structure and alignment test method thereof, and manufacturing method of semiconductor device
By inspecting and remanufacturing the photoresist structure in the marked area, the problem of inaccurate conductive post positioning was solved, the alignment accuracy between the conductive posts and connecting wires was improved, and the electrical performance and reliability of semiconductor devices were ensured.
Patent Information
- Application Number
- CN202410852505.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-12-30
AI Technical Summary
In TSV 3D packaging technology, inaccurate positioning of conductive pillars leads to poor alignment between the conductive pillars and the metal layer, affecting chip reliability and yield.
The photoresist structure is remanufactured by detecting the alignment accuracy between the conductive pillars and the connecting wires in the marked area to ensure the alignment accuracy between the conductive pillars and the connecting wires. A mirror-symmetric opening design and optical microscope are used to detect the alignment accuracy.
This improves the alignment accuracy between the conductive posts and the connecting wires, reduces the risk of defective wafers, and ensures the electrical performance of semiconductor devices.
Smart Images
Figure CN121237778A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and its alignment testing method, and a method for manufacturing a semiconductor device. Background Technology
[0002] In the field of 3D packaging technology for integrated circuits, three-dimensional packaging based on TSV (Through Silicon Via) technology achieves high integration density and high performance in integrated circuits. TSV 3D packaging technology uses conductive pillars housed in through-holes to achieve electrical interconnections between vertically stacked chips or between wafers.
[0003] As the demand for high-bandwidth chips increases, it becomes increasingly challenging to fabricate conductive pillars with higher integration density and better performance within a limited space. Summary of the Invention
[0004] This application proposes a semiconductor structure and its alignment testing method, as well as a semiconductor device manufacturing method, to improve the electrical performance of semiconductor devices.
[0005] In some embodiments, this application provides a semiconductor structure, including:
[0006] Multiple functional areas, arranged in an array;
[0007] Multiple cutting zones, each of which is located between adjacent functional zones;
[0008] Multiple marked areas, including adjacent regions of the cut areas;
[0009] The marked area includes:
[0010] N conductive pillars are disposed in the substrate, the conductive pillars are perpendicular to the substrate, and the N conductive pillars are arranged in a preset pattern;
[0011] A first dielectric layer covers the first surface of the marked area;
[0012] A first photoresist structure is disposed on the side of the first dielectric layer away from the substrate. The first photoresist structure includes a plurality of first openings in the marking region. The marking region includes a first region and a second region. In the first region, the first openings enclose two conductive pillars. In the second region, the first openings are spaced apart from the conductive pillars.
[0013] In some embodiments, the semiconductor structure further includes:
[0014] A second dielectric layer covers the second side of the marked area;
[0015] A second photoresist structure is disposed on the side of the second dielectric layer away from the substrate. The second photoresist structure includes a plurality of second openings in the marking area. In the first region, the second openings enclose two conductive pillars. In the second region, the edges of the second openings are spaced apart from the centers of the conductive pillars in a direction parallel to the substrate.
[0016] In some embodiments, in the first region, starting from the odd-numbered conductive post, the first ends of every two adjacent conductive posts are enclosed by a first opening, and starting from the even-numbered conductive post, the second ends of every two adjacent conductive posts are enclosed by a second opening.
[0017] In some embodiments, in the second region, the second opening is mirror-symmetrical to the first opening.
[0018] In some embodiments, in the first region, a plurality of the first openings are arranged along the row direction of the functional area;
[0019] The second region includes a first sub-region and a second sub-region, which are respectively located on both sides of the first region along the row direction of the functional area; the first opening in the first sub-region is axially symmetrical with the first opening in the second sub-region, and the conductive pillar in the first sub-region is axially symmetrical with the conductive pillar in the second sub-region.
[0020] In some embodiments, the conductive pillars within the first region are axially symmetrical about the column or row direction of the functional area.
[0021] In some embodiments, this application provides a method for manufacturing a semiconductor device, including:
[0022] N first holes arranged in a predetermined pattern are formed in the marking area on the first side of the substrate, and the bottom surface of the first holes is close to the second side of the substrate; the marking area includes the adjacent area of at least two cutting areas; the cutting areas are located between adjacent functional areas arranged in an array;
[0023] A conductive post is formed within each of the first holes;
[0024] A first dielectric layer is formed to cover the marking area of the first surface;
[0025] A first photoresist structure is formed on the side of the first dielectric layer away from the substrate. The first photoresist structure includes a plurality of first openings in the marking region. The marking region includes a first region and a second region. In the first region, the first openings enclose two conductive pillars. In the second region, the first openings are spaced apart from the conductive pillars.
[0026] In some embodiments, after forming the first photoresist structure on the side of the first dielectric layer away from the substrate, the method further includes:
[0027] Using the first photoresist structure as a mask, the first dielectric layer is etched to form a plurality of first grooves;
[0028] A first connecting wire is formed in each of the first grooves, such that in the first region, starting from the odd-numbered conductive post, the first end of every two adjacent conductive posts is connected to a first connecting wire, and in the second region, the edge of the first connecting wire is spaced apart from the center of the conductive post.
[0029] In some embodiments, after forming the first photoresist structure on the side of the first dielectric layer away from the substrate, the method further includes:
[0030] The second surface of the substrate is thinned and etched so that the second end of the conductive pillar protrudes from the second surface;
[0031] An insulating structure is manufactured in the marking area that is flush with the second end of the conductive post;
[0032] A second dielectric layer is formed to cover the marking area of the second surface;
[0033] A second photoresist structure is formed on the side of the second dielectric layer away from the substrate. The second photoresist structure includes a plurality of second openings in the marking area. In the first region, the second openings enclose two conductive pillars. In the second region, the second openings are spaced apart from the conductive pillars.
[0034] In some embodiments, after forming the second photoresist structure on the side of the second dielectric layer away from the substrate, the method further includes:
[0035] Using the second photoresist structure as a mask, the second dielectric layer is etched to form multiple second grooves;
[0036] A second connecting wire is formed in each of the second grooves, such that a second connecting wire is connected to the second end of every two adjacent conductive posts starting from the even-numbered conductive post in the first region, and the edge of the second connecting wire in the second region is spaced apart from the center of the conductive post.
[0037] In some embodiments, before forming N first holes arranged in a predetermined pattern in the marking area on the first surface of the substrate, the method further includes:
[0038] A third dielectric layer is formed on the first surface of the substrate;
[0039] A groove is formed on the side of the third dielectric layer away from the substrate;
[0040] An alignment structure is formed within the groove;
[0041] N first holes arranged in a predetermined pattern are formed in the marking area on the first surface of the substrate, including:
[0042] Using the alignment structure as an alignment reference, a third photoresist structure is formed in the marking area on the first surface of the substrate. The third photoresist structure includes N third openings arranged in a preset pattern.
[0043] Using the third photoresist structure as a mask, the substrate is etched to form the first holes arranged in a preset pattern;
[0044] And, on the side of the first dielectric layer away from the substrate, a first photoresist structure is formed, including:
[0045] Using the alignment structure as an alignment reference, a first photoresist structure is formed on the side of the first dielectric layer away from the substrate.
[0046] In some embodiments, this application provides an alignment testing method for a semiconductor structure, including:
[0047] The minimum distance between the edge of the first opening of the first photoresist structure within the marking area of the first side of the substrate and the center of the conductive pillar;
[0048] Based on the minimum distance, determine the alignment accuracy between the first connecting wire at the first opening of the first photoresist structure within the functional area and the conductive post.
[0049] In some embodiments, detecting the minimum distance between the edge of the first opening of the first photoresist structure within the marking area of the first surface of the substrate and the center of the conductive pillar includes:
[0050] A photograph is taken perpendicular to the substrate from one side of the first photoresist structure to obtain a photograph containing the pattern of the first opening and the pattern of the conductive pillar;
[0051] Based on the pattern of the first opening and the pattern of the conductive pillar in the photograph, determine the minimum distance between the edge of the opening of the first photoresist structure and the center of the conductive pillar.
[0052] In some embodiments, detecting the minimum distance between the edge of the first opening of the first photoresist structure within the marking area of the first surface of the substrate and the center of the conductive pillar includes:
[0053] Using an optical microscope, the minimum distance between the edge of the opening of the first photoresist structure and the center of the conductive pillar is detected from one side of the first photoresist structure.
[0054] The beneficial technical effects of the technical solutions provided in this application include:
[0055] The semiconductor structure provided in this application includes a marking region, which can effectively ensure the alignment of each conductive pillar in the semiconductor device with the first connecting wire formed by the first photoresist structure.
[0056] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description
[0057] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:
[0058] Figure 1 This is a schematic diagram of the region division of a semiconductor structure provided in an embodiment of this application;
[0059] Figure 2 A top view of a semiconductor structure provided in an embodiment of this application;
[0060] Figure 3 This is a cross-sectional structural diagram of a semiconductor structure provided in an embodiment of this application;
[0061] Figure 4 This is a cross-sectional view of another semiconductor structure provided in an embodiment of this application.
[0062] Figure 5 A schematic cross-sectional view of a semiconductor device obtained by manufacturing a semiconductor structure through subsequent steps, as provided in an embodiment of this application.
[0063] Figure 6 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;
[0064] Figures 7 to 28 This is a schematic diagram of the intermediate structure obtained in each step of a process flow diagram of a semiconductor device manufacturing method provided in this application embodiment;
[0065] Figure 29 This is a flowchart illustrating an alignment test method for a semiconductor structure provided in an embodiment of this application.
[0066] Explanation of reference numerals in the attached figures:
[0067] 30 - Functional area; 40 - Cutting area; 50 - Marking area; 501 - First area; 502 - Second area; 502a - First sub-area; 502b - Second sub-area;
[0068] 11-Conductive pillar; 12-First dielectric layer; 121-First silicon nitride layer; 122-First oxide layer; 13-First photoresist structure; 131-First opening; 14-Substrate; 15-Second dielectric layer; 151-Fourth silicon nitride layer; 152-Fifth oxide layer; 16-Second photoresist structure; 161-Second opening;
[0069] 17-Third dielectric layer; 18-Third insulating layer; 181-Alignment structure; 19-Third photoresist structure; 191-Third opening; 20-First insulating layer; 21-Seed layer; 22-First connecting wire; 23-First insulating stack; 231-Second silicon nitride layer; 232-Second oxide layer; 24-First support layer; 25-Adhesive layer; 26-Sixth oxide layer; 27-Insulating structure; 270-Second insulating stack; 271-Third oxide layer; 272-Third silicon nitride layer; 273-Fourth oxide layer; 28-Second connecting wire;
[0070] 60 - First hole; 70 - Third groove; 80 - First groove; 90 - Second groove. Detailed Implementation
[0071] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0072] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."
[0073] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0074] In related technologies, the position of the conductive pillars formed in through-silicon vias is often inaccurate, resulting in poor alignment between the conductive pillars and the metal layer, which in turn affects the reliability and yield of the chip.
[0075] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.
[0076] This application provides a semiconductor structure, which is an intermediate structure in the process of manufacturing semiconductor devices.
[0077] The semiconductor device may be a chip or a part of a chip, and the chip may be a memory, logic chip, digital chip, etc.
[0078] The semiconductor device comprises at least two stacked silicon substrates, each silicon substrate corresponding to one chip, and different silicon substrate stacks corresponding to different chip stacks.
[0079] The silicon substrate has a memory cell array and peripheral circuits formed on it.
[0080] Each silicon substrate contains multiple vias formed on the silicon substrate, also known as silicon vias. Conductive pillars are formed in the silicon vias, which enable electrical interconnection between vertically stacked chips or between wafers.
[0081] The semiconductor structure provided in this application includes a marking region. By detecting the alignment accuracy between each conductive post in the marking region and the first photoresist structure, and when the alignment accuracy between each conductive post in the marking region and the first photoresist structure is poor, the first photoresist structure is remanufactured. This can effectively ensure the alignment accuracy between each conductive post in the marking region and the first connecting wire formed by the first photoresist structure, thereby ensuring the alignment accuracy between each conductive post in the functional area and the first connecting wire.
[0082] The semiconductor structure provided in the embodiments of this application is as follows: Figures 1 to 4 As shown.
[0083] See Figure 1 The semiconductor structure includes multiple functional regions 30, multiple dicing regions 40, and multiple marking regions 50.
[0084] Multiple functional areas are arranged in a 30-array configuration.
[0085] Multiple cutting zones 40, each located between adjacent functional zones 30.
[0086] Multiple marked areas 50 include adjacent areas of adjacent cut areas 40.
[0087] See Figure 3 The marking area 50 includes N conductive pillars 11, a first dielectric layer 12, and a first photoresist structure 13.
[0088] N conductive pillars 11 are disposed in the substrate 14, the conductive pillars 11 are perpendicular to the substrate 14, and the N conductive pillars 11 are arranged in a preset pattern.
[0089] The first dielectric layer 12 covers the first surface of the marking area 50.
[0090] The first photoresist structure 13 is disposed on the side of the first dielectric layer 12 away from the substrate 14, and the first photoresist structure 13 includes a plurality of first openings 131 in the marking area 50.
[0091] See Figure 2 The marking area 50 includes a first region 501 and a second region 502; in the first region 501, a first opening 131 encloses two conductive pillars 11, and / or, in the second region 502, the first opening 131 is spaced apart from the conductive pillars 11.
[0092] The semiconductor structure provided in this application includes a marking region 50, in which N conductive pillars 11 are arranged in a preset pattern. By detecting the alignment accuracy between each conductive pillar 11 in the marking region 50 and the first photoresist structure 13, when the alignment accuracy between each conductive pillar 11 in the marking region 50 and the first photoresist structure 13 is poor, the first photoresist structure 13 is remanufactured. This can effectively ensure the alignment accuracy between each conductive pillar 11 in the marking region 50 and the first connecting wire 22 formed by the first photoresist structure 13, thereby ensuring the alignment accuracy between each conductive pillar 11 in the functional region 30 and the first connecting wire 22, effectively ensuring the electrical performance of the finally formed semiconductor device, and reducing the risk of scrap.
[0093] Furthermore, since the first opening 131 and the conductive post 11 are spaced apart in the second region 502, after the first connecting wire 22 is formed using the first photoresist structure 13, the first connecting wire 22 and the conductive post 11 are spaced apart in the second region 502 (the first connecting wire 22 in the second region 502 does not cover or block the conductive post 11). This allows the distance between the first connecting wire 22 and the conductive post 11 in the second region 502 (for example, the minimum distance between the edge of the first connecting wire 22 and the center of the conductive post 11 in the second region 502) to be detected using an optical microscope or photography. This distance is then compared with the design distance to determine the alignment accuracy of each conductive post 11 and the first connecting wire 22 in the marking area 50, and thus evaluate the alignment accuracy of each conductive post 11 and the first connecting wire 22 in the functional area 30.
[0094] It should be noted that, Figure 2 In the diagram, the solid box represents the first opening 131 of the first photoresist structure 13, and the dashed box represents the second opening 161 of the second photoresist structure 16.
[0095] In some embodiments, the minimum distance between the edge of the first opening 131 of the first photoresist structure 13 and the edge of the conductive pillar 11 in the first region 501 of the first surface of the substrate 14 and / or the minimum distance between the edge of the first opening 131 of the first photoresist structure 13 and the center of the conductive pillar 11 in the second region 502 of the first surface of the substrate 14 can be detected; based on the minimum distance, the alignment accuracy between the first photoresist structure 13 and each conductive pillar 11 in the marking area 50 can be determined (the smaller the minimum distance, the higher the alignment accuracy).
[0096] In some embodiments, the first dielectric layer 12 includes a first silicon nitride layer 121 and a first oxide layer 122.
[0097] See Figure 4 In some embodiments, the semiconductor structure further includes a second dielectric layer 15 and a second photoresist structure 16.
[0098] The second dielectric layer 15 covers the second side of the marking area 50.
[0099] The second photoresist structure 16 is disposed on the side of the second dielectric layer 15 away from the substrate 14. The second photoresist structure 16 includes a plurality of second openings 161 in the marking area 50. In the first region 501, the second openings 161 enclose two conductive pillars 11. In the second region 502, the edges of the second openings 161 and the centers of the conductive pillars 11 are spaced apart in a direction parallel to the substrate 14.
[0100] Since the semiconductor structure includes a marking region 50, and the N conductive pillars 11 in the marking region 50 are arranged in a preset pattern, by detecting the alignment accuracy between each conductive pillar 11 in the marking region 50 and the second photoresist structure 16, when the alignment accuracy between each conductive pillar 11 in the marking region 50 and the second photoresist structure 16 is poor, the second photoresist structure 16 is remanufactured. This can effectively ensure the alignment accuracy between each conductive pillar 11 in the marking region 50 and the second connecting wire 28 formed by the second photoresist structure 16, thereby ensuring the alignment accuracy between each conductive pillar 11 in the functional region 30 and the second connecting wire 28, and effectively ensuring the electrical performance of the finally formed semiconductor device.
[0101] In some embodiments, the minimum distance between the edge of the second opening 161 of the second photoresist structure 16 and the edge of the conductive pillar 11 in the first region 501 of the second surface of the substrate 14 and / or the minimum distance between the edge of the second opening 161 of the second photoresist structure 16 and the center of the conductive pillar 11 in the second region 502 of the second surface of the substrate 14 can be detected; based on the minimum distance, the alignment accuracy between the second photoresist structure 16 and each conductive pillar 11 in the marking area 50 can be determined (the smaller the minimum distance, the higher the alignment accuracy).
[0102] In some embodiments, the second dielectric layer 15 may be a fourth silicon nitride layer 151 and a fifth oxide layer 152.
[0103] See Figures 2 to 4 In some embodiments, in the first region 501, starting from the odd-numbered conductive post 11, the first ends of every two adjacent conductive posts 11 are enclosed by a first opening 131, and starting from the even-numbered conductive post 11, the second ends of every two adjacent conductive posts 11 are enclosed by a second opening 161.
[0104] In some embodiments, a first connecting wire 22 and a second connecting wire 28 may be formed in the first dielectric layer 12, wherein the first connecting wire 22 overlaps with the orthographic projection of the first opening 131 on the first dielectric layer 12, and the second connecting wire 28 overlaps with the orthographic projection of the second opening 161 on the first dielectric layer 12.
[0105] See Figure 5 In other words, in the first region 501, starting from the first conductive post 11, a first connecting wire 22 is connected to the first end of every two adjacent conductive posts 11, and starting from the second conductive post 11, a second connecting wire 28 is connected to the second end of every two adjacent conductive posts 11.
[0106] In some embodiments, starting from the first conductive post 11, a first connecting wire 22 is connected to the first end of every two adjacent conductive posts 11; for example, the first and second conductive posts 11 are connected by a first connecting wire 22, the third and fourth conductive posts 11 are connected by another first connecting wire 22, and so on, with every two conductive posts 11 connected by a first connecting wire 22.
[0107] Starting from the second conductive post 11, a second connecting wire 28 is connected to the second end of every two adjacent conductive posts 11. In this way, the second end of the second conductive post 11 is connected to the second end of the adjacent third conductive post 11 through the second connecting wire 28, the first end of the third conductive post 11 is connected to the first end of the adjacent fourth conductive post 11 through the first connecting wire 22, and so on, with each conductive post 11 connected in series.
[0108] Since the N conductive pillars 11 in the marking area 50 are connected in series with each other through a plurality of first connecting wires 22 located on the first side of the substrate 14 and a plurality of second connecting wires 28 located on the second side of the substrate 14, the electrical connectivity of the N conductive pillars 11 in the marking area 50 can be detected, and the electrical connectivity of the conductive pillars 11 in the functional area 30 can be evaluated.
[0109] In some embodiments, in the second region 502, the second opening 161 is mirror-symmetrical to the first opening 131.
[0110] Since the second opening 161 is mirror-symmetrical to the first opening 131 in the second region 502, the first photoresist structure 13 and the second photoresist structure 16 can be formed using the same mask, thereby reducing costs.
[0111] See Figure 2 In some embodiments, in the first region 501, a plurality of first openings 131 are arranged along the row direction of the functional area 30.
[0112] See also Figure 2 The second region 502 includes a first sub-region 502a and a second sub-region 502b. The first sub-region 502a and the second sub-region 502b are respectively located on both sides of the first region 501 along the row direction of the functional area 30. The first opening 131 in the first sub-region 502a is axially symmetrical with the first opening 131 in the second sub-region 502b. The conductive pillar 11 in the first sub-region 502a is axially symmetrical with the conductive pillar 11 in the second sub-region 502b.
[0113] In some embodiments, the conductive pillars 11 in the first region 501 may be arranged in one or more rows (e.g., two rows); in each row of conductive pillars 11, the centers of each conductive pillar 11 are on the same straight line and the spacing is the same; the straight line is parallel to the row direction of the functional area 30.
[0114] In other embodiments, the conductive pillars 11 in the first region 501 may be arranged in one or more columns (e.g., two columns); in each column of conductive pillars 11, the centers of each conductive pillar 11 are on the same straight line and the spacing is the same; the straight line is parallel to the column direction of the functional area 30.
[0115] As an example, the first sub-region 502a may include four conductive pillars 11 arranged in a rectangle, and three first openings 131 respectively disposed on the three sides of the rectangle, wherein the distance between the edge of each first opening 131 and the conductive pillar 11 on the corresponding side is equal. The second sub-region 502b is similar and will not be described in detail here.
[0116] See Figure 2 In some embodiments, the conductive pillars 11 in the first region 501 are axially symmetrical about the column direction of the functional area 30.
[0117] This configuration facilitates the layout drawing of the semiconductor structure and makes it easier to detect the minimum distance between the first opening 131 and the conductive pillar 11 within the marking area 50.
[0118] In other embodiments, the conductive pillars 11 in the first region 501 are axially symmetrical about the row direction of the functional area 30.
[0119] The beneficial technical effects of the technical solutions provided in this application include:
[0120] The semiconductor structure provided in this application embodiment includes a marking region 50. By detecting the alignment accuracy between each conductive post 11 in the marking region 50 and the first photoresist structure 13, when the alignment accuracy between each conductive post 11 in the marking region 50 and the first photoresist structure 13 is poor, the first photoresist structure 13 is remanufactured. This can effectively ensure the alignment accuracy between each conductive post 11 in the marking region 50 and the first connecting wire 22 formed by the first photoresist structure 13, thereby ensuring the alignment accuracy between each conductive post 11 in the functional region 30 and the first connecting wire 22 and reducing the risk of defective wafers.
[0121] Based on the same inventive concept, embodiments of this application provide a method for manufacturing a semiconductor device, the process flow diagram of which is shown below. Figure 6 As shown, the method for manufacturing this semiconductor device includes steps S101 to S104:
[0122] S101: See also Figure 12 N first holes 60 arranged in a preset pattern are formed in the marking area 50 on the first side of the substrate 14, and the bottom surface of the first holes 60 is close to the second side of the substrate 14; the marking area 50 includes the adjacent areas of at least two cutting areas 40; the cutting areas 40 are located between adjacent functional areas 30 arranged in an array.
[0123] S102: See also Figure 14 Conductive pillars 11 are formed within each first hole 60.
[0124] S103: See also Figure 15 A first dielectric layer 12 is formed, covering the marking area 50 on the first surface.
[0125] S104: See also Figure 16 On the side of the first dielectric layer 12 away from the substrate 14, a first photoresist structure 13 is formed. The first photoresist structure 13 includes a plurality of first openings 131 in the marking region 50. The marking region 50 includes a first region 501 and a second region 502. In the first region 501, the first openings 131 enclose two conductive pillars 11, and / or, in the second region 502, the first openings 131 are spaced apart from the conductive pillars 11.
[0126] By forming N conductive pillars 11 arranged in a preset pattern in the marking area 50 on the first side of the substrate 14, and a first photoresist structure 13 containing multiple first openings 131, the alignment accuracy between each conductive pillar 11 in the marking area 50 and the first photoresist structure 13 is detected. When the alignment accuracy between each conductive pillar 11 in the marking area 50 and the first photoresist structure 13 is poor, the first photoresist structure 13 is remanufactured. This can effectively ensure the alignment accuracy between each conductive pillar 11 in the marking area 50 and the first connecting wire 22 formed by the first photoresist structure 13, thereby ensuring the alignment accuracy between each conductive pillar 11 in the functional area 30 and the first connecting wire 22 and reducing the risk of defective wafers.
[0127] In some embodiments, steps S11 to S13 are included before step S101:
[0128] S11: A third dielectric layer 17 is formed on the first surface of the substrate 14.
[0129] The material of the third dielectric layer 17 can be an oxide.
[0130] Figure 7 This is a schematic diagram of the cross-sectional structure perpendicular to the substrate 14 after the third dielectric layer 17 is formed on the first surface of the substrate 14.
[0131] S12: A third groove 70 is formed on the side of the third dielectric layer 17 away from the substrate 14.
[0132] Figure 8 This is a schematic diagram of the cross-sectional structure perpendicular to the substrate 14 after the third groove 70 is formed on the side of the third dielectric layer 17 away from the substrate 14.
[0133] Figure 9 This is a schematic diagram of the third groove 70 parallel to the substrate 14.
[0134] In some embodiments, step S12 may include: forming a photoresist structure by photolithography, and forming a third groove 70 by etching using the photoresist structure as a mask.
[0135] S13: An alignment structure 181 is formed within the third groove 70.
[0136] In some embodiments, step S13 includes forming a third insulating layer 18 on the side of the third dielectric layer 17 away from the substrate 14 and within the third groove 70, wherein the third insulating layer 18 forms an alignment structure 181 at the third groove 70. In this case, the material of the alignment structure 181 is an insulating material, such as an oxide, like silicon dioxide.
[0137] Figure 10A schematic diagram of a cross-sectional structure perpendicular to the substrate 14 is shown below, which is used to form a third insulating layer 18 on the side of the third dielectric layer 17 away from the substrate 14 and in the third groove 70. The third insulating layer 18 forms an alignment structure 181 at the third groove 70.
[0138] It is understandable that the schematic diagram of the alignment structure 181 parallel to the substrate 14 is similar to the schematic diagram of the third groove 70 parallel to the substrate 14, and can be referred to for reference. Figure 9 .
[0139] In other embodiments, step S13 includes: forming an alignment structure 181 within the third groove 70, and forming a third insulating layer 18 on the side of the third dielectric layer 17 away from the substrate 14 and on the side of the alignment structure 181 away from the substrate 14. In this case, the material of the alignment structure 181 can be metal, which allows for more accurate identification of the alignment structure 181.
[0140] The alignment structure 181 is used as a universal alignment mark to act as a bridge. The mask plates used in the subsequent manufacturing of the third photoresist structure 19 (the mask used in the development stage of the manufacturing process of the first hole 60) and the first photoresist structure 13 (the mask used in the development stage of the manufacturing process of the first connecting wire 22) are aligned with the alignment structure 181, thereby improving the manufacturing accuracy of the first hole 60 and the first connecting wire 22.
[0141] In some embodiments, step S101 includes the following sub-steps S21 to S22:
[0142] S21: Using the alignment structure 181 as the alignment reference, a third photoresist structure 19 is formed in the marking area 50 on the first side of the substrate 14. The third photoresist structure 19 includes N third openings 191 arranged in a preset pattern.
[0143] Figure 11 A schematic diagram of a cross-sectional structure perpendicular to the substrate 14 after the third photoresist structure 19 is formed in the marking area 50 on the first surface of the substrate 14 with the alignment structure 181 as the alignment reference.
[0144] S22: Using the third photoresist structure 19 as a mask, the substrate 14 is etched to form the first hole 60 arranged in a preset pattern.
[0145] Figure 12 This is a schematic diagram of a cross-sectional structure perpendicular to the substrate 14 after etching the substrate 14 with the third photoresist structure 19 as a mask to form the first hole 60 arranged in a preset pattern.
[0146] In some embodiments, before step S102, a first insulating layer 20 and a seed layer 21 are sequentially formed on the inner wall of each first hole 60.
[0147] The material of the first insulating layer 20 can be silicon dioxide.
[0148] The seed layer 21 is made of a material with good electrical conductivity, such as copper or nickel. The seed layer provides a conductive base for the subsequent electroplating process, allowing conductive material to be uniformly deposited on the inner wall of the through-silicon via.
[0149] In some embodiments, a barrier layer (not shown) may be formed conformally on the surface of the first insulating layer 20 before the seed layer 21 is formed.
[0150] The barrier layer has good conductivity and diffusion-blocking properties, which can prevent conductive materials (such as copper) from diffusing into the substrate 14. The barrier layer can be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).
[0151] Figure 13 A schematic diagram of the cross-sectional structure perpendicular to the substrate 14 after the first insulating layer 20 and the seed layer 21 are sequentially formed on the inner wall of each first hole 60.
[0152] Figure 14 A schematic diagram of a cross-sectional structure perpendicular to the substrate 14 after forming a conductive pillar 11 in each first hole 60.
[0153] In some embodiments, step S103 includes: sequentially fabricating a first silicon nitride layer 121 and a first oxide layer 122 on the first surface of the substrate 14 and the surface of the conductive pillar 11. In other words, the first dielectric layer 12 includes the first silicon nitride layer 121 and the first oxide layer 122.
[0154] Figure 15 A schematic diagram of the cross-sectional structure perpendicular to the substrate 14 after forming the first dielectric layer 12 covering the marking area 50 on the first surface.
[0155] In some embodiments, step S104 includes forming a first photoresist structure 13 on the side of the first dielectric layer 12 away from the substrate 14, using the alignment structure 181 as an alignment reference.
[0156] Figure 16 To align with the alignment structure 181 as the alignment reference, a first photoresist structure 13 is formed on the side of the first dielectric layer 12 away from the substrate 14. The first photoresist structure 13 includes a plurality of first openings 131 in the marking area 50 and is shown in the cross-sectional structure diagram perpendicular to the substrate 14.
[0157] In some embodiments, after step S104, steps S105 to S106 are further included:
[0158] S105: Using the first photoresist structure 13 as a mask, the first dielectric layer 12 is etched to form a plurality of first grooves 80.
[0159] Figure 17 This is a schematic diagram of a cross-sectional structure perpendicular to the substrate 14, formed by etching the first dielectric layer 12 using the first photoresist structure 13 as a mask to create multiple first grooves 80.
[0160] S106: A first connecting wire 22 is formed in each first groove 80 so that a first connecting wire 22 is connected to the first end of every two adjacent conductive posts 11 starting from the odd-numbered conductive posts 11 in the first region 501, and the edge of the first connecting wire 22 in the second region 502 is spaced apart from the center of the conductive post 11.
[0161] Figure 18 A schematic diagram of a cross-sectional structure perpendicular to the substrate 14 after forming a first connecting wire 22 in each first groove 80.
[0162] In some embodiments, steps S107 to S110 are included after step S106:
[0163] S107: Thinning and etching are performed on the second side of the substrate 14 so that the second end of the conductive pillar 11 protrudes from the second side.
[0164] In some embodiments, before step S107, the method further includes: fabricating a first insulating stack 23 on the side of the first connecting wire 22 away from the substrate 14; and binding a first support layer 24 to the side of the first insulating stack 23 away from the substrate 14.
[0165] The first insulating layer 23 may include a second silicon nitride layer 231 and a second oxide layer 232.
[0166] In some embodiments, the first support layer 24 may be a silicon layer.
[0167] In some embodiments, the first support layer 24 may be temporarily bonded to the side of the first insulating stack 23 away from the substrate 14 via an adhesive layer 25, which may be made of a temporary bonding material.
[0168] In some embodiments, a sixth oxide layer 26 may also be provided between the first support layer 24 and the adhesive layer 25.
[0169] Figure 19 A schematic diagram of a cross-sectional structure perpendicular to the substrate 14 after fabricating the first insulating stack 23 on the side of the first connecting wire 22 away from the substrate 14.
[0170] Figure 20 A schematic diagram of a cross-sectional structure perpendicular to the substrate 14 after the first support layer 24 is bonded to the side of the first insulating stack 23 away from the substrate 14.
[0171] In some embodiments, step S107 includes: thinning the second side of the substrate 14; etching the second side of the thinned substrate 14 so that the second end of the conductive post 11 protrudes from the second side.
[0172] Figure 21 This is a schematic diagram of the cross-sectional structure perpendicular to the substrate 14 after the second side of the substrate 14 has been thinned.
[0173] Figure 22 A schematic diagram of a cross-sectional structure in which the second end of the conductive pillar 11 protrudes from the second surface and is perpendicular to the substrate 14 after etching the second surface of the thinned substrate 14.
[0174] Since the etching options for the substrate 14 (e.g., silicon substrate 14) and the first insulating layer 20 (e.g., silicon dioxide) are relatively large, typically greater than 7, the substrate 14 is etched to a large depth during the etching process, while the first insulating layer 20 is etched to a negligible depth, thereby enabling the second end of the conductive post 11 to protrude from the second surface.
[0175] S108: An insulating structure 27 is made in the marking area 50, flush with the second end of the conductive post 11.
[0176] In some embodiments, step S108 includes: forming a second insulating stack 270 on the second surface of the substrate 14 and the second end of the conductive pillar 11; thinning the second insulating stack 270 so that the top of the conductive pillar 11 is exposed, forming an insulating structure 27 flush with the second end of the conductive pillar 11.
[0177] The second insulating layer 270 may include a third oxide layer 271, a third silicon nitride layer 272, and a fourth oxide layer 273.
[0178] In some embodiments, after thinning the second insulating layer 270 to expose the top of the conductive pillar 11 and forming an insulating structure 27 flush with the second end of the conductive pillar 11, the process may further include: using the conductive pillar 11 in the marking area 50 as a reference to align with the marking to detect the exposure of the top of the conductive pillar 11 in the functional area 30; if a preset number or a preset percentage of the tops of the conductive pillar 11 in the functional area 30 are not exposed, it indicates that there is a problem with the process (BVR process, back-side grinding process) for thinning the second insulating layer 270, and the process can be further optimized and improved in the future.
[0179] Figure 23 This is a schematic diagram of a cross-sectional structure perpendicular to the substrate 14 after a second insulating stack 270 is formed on the second surface of the substrate 14 and the second end of the conductive pillar 11.
[0180] Figure 24To thin the second insulating layer 270 so that the top of the conductive pillar 11 is exposed, an insulating structure 27 is formed flush with the second end of the conductive pillar 11. The cross-sectional structure is perpendicular to the substrate 14.
[0181] S109: Form a second dielectric layer 15 covering the marking area 50 on the second surface.
[0182] Figure 25 A schematic diagram of the cross-sectional structure perpendicular to the substrate 14 after forming the second dielectric layer 15 covering the marking area 50 on the second surface.
[0183] The second dielectric layer 15 can be a fourth silicon nitride layer 151 and a fifth oxide layer 152.
[0184] S110: A second photoresist structure 16 is formed on the side of the second dielectric layer 15 away from the substrate 14. The second photoresist structure 16 includes a plurality of second openings 161 in the marking area 50. In the first region 501, the second openings 161 surround two conductive pillars 11. In the second region 502, the second openings 161 are spaced apart from the conductive pillars 11.
[0185] Figure 26 To form a second photoresist structure 16 on the side of the second dielectric layer 15 away from the substrate 14, the second photoresist structure 16 is shown in the cross-sectional view perpendicular to the substrate 14 after the marking area 50 contains a plurality of second openings 161.
[0186] In some embodiments, steps S111 to S112 are included after step S110:
[0187] S111: Using the second photoresist structure 16 as a mask, the second dielectric layer 15 is etched to form multiple second grooves 90.
[0188] Figure 27 This is a schematic diagram of a cross-sectional structure perpendicular to the substrate 14, formed by etching the second dielectric layer 15 using the second photoresist structure 16 as a mask to create multiple second grooves 90.
[0189] S112: A second connecting wire 28 is formed in each second groove 90 so that a second connecting wire 28 is connected to the second end of every two adjacent conductive posts 11 starting from the even-numbered conductive post 11 in the first region 501, and the edge of the second connecting wire 28 in the second region 502 is spaced apart from the center of the conductive post 11.
[0190] Figure 28 A schematic diagram of a cross-sectional structure perpendicular to the substrate 14 after forming a second connecting wire 28 in each second groove 90.
[0191] The beneficial technical effects of the technical solutions provided in this application include:
[0192] In this embodiment, N conductive pillars 11 arranged in a preset pattern are formed in the marking area 50 on the first surface of the substrate 14, and a first photoresist structure 13 including multiple first openings 131 is formed. By detecting the alignment accuracy between each conductive pillar 11 in the marking area 50 and the first photoresist structure 13, when the alignment accuracy between each conductive pillar 11 in the marking area 50 and the first photoresist structure 13 is poor, the first photoresist structure 13 is remanufactured. This can effectively ensure the alignment accuracy between each conductive pillar 11 in the marking area 50 and the first connecting wire 22 formed by the first photoresist structure 13, thereby ensuring the alignment accuracy between each conductive pillar 11 in the functional area 30 and the first connecting wire 22 and reducing the risk of defective wafers.
[0193] Based on the same inventive concept, embodiments of this application provide an alignment test method for semiconductor structures.
[0194] In some embodiments, for Figure 3 The semiconductor structure shown includes N conductive pillars 11, a first dielectric layer 12, and a first photoresist structure 13 in the marked area 50.
[0195] N conductive pillars 11 are disposed in the substrate 14, the conductive pillars 11 are perpendicular to the substrate 14, and the N conductive pillars 11 are arranged in a preset pattern.
[0196] The first dielectric layer 12 covers the first surface of the marking area 50.
[0197] The first photoresist structure 13 is disposed on the side of the first dielectric layer 12 away from the substrate 14, and the first photoresist structure 13 includes a plurality of first openings 131 in the marking area 50.
[0198] See Figure 2 The marking area 50 includes a first region 501 and a second region 502; in the first region 501, a first opening 131 encloses two conductive pillars 11, and / or, in the second region 502, the first opening 131 is spaced apart from the conductive pillars 11.
[0199] The flowchart of the alignment test method for the semiconductor structure is as follows: Figure 29 As shown, the process includes the following steps S201 to S202:
[0200] S201: Detect the minimum distance between the edge of the first opening 131 of the first photoresist structure 13 and the edge of the conductive pillar 11 in the first region 501 of the first surface of the substrate 14, and / or, detect the minimum distance between the edge of the first opening 131 of the first photoresist structure 13 and the center of the conductive pillar 11 in the second region 502 of the first surface of the substrate 14.
[0201] S202: Based on the minimum distance, determine the alignment accuracy between the first connecting wire 22 and the conductive post 11 at the first opening 131 of the first photoresist structure 13 within the functional area 30.
[0202] In some embodiments, detecting the minimum distance between the edge of the first opening 131 of the first photoresist structure 13 and the center of the conductive pillar 11 within the second region 502 of the first surface of the substrate 14 may include the following sub-steps S31 to S32:
[0203] S31: Take a picture perpendicular to the substrate 14 from one side of the first photoresist structure 13 to obtain a picture containing the pattern of the first opening 131 and the pattern of the conductive pillar 11.
[0204] S32: Based on the pattern of the first opening 131 and the pattern of the conductive pillar 11 in the photograph, determine the minimum distance between the edge of the opening of the first photoresist structure 13 and the center of the conductive pillar 11.
[0205] The first dielectric layer 12 may include a first silicon nitride layer and a first oxide layer. Since oxide is transparent and silicon nitride has high transparency when it is thin, the first dielectric layer 12 has high transparency. Therefore, the pattern of the conductive pillar 11 can be captured through the first dielectric layer 12. Thus, the minimum distance between the edge of the opening of the first photoresist structure 13 and the center of the conductive pillar 11 can be determined using the pattern of the first opening 131 and the pattern of the conductive pillar 11 in the photograph.
[0206] In other embodiments, detecting the minimum distance between the edge of the first opening 131 of the first photoresist structure 13 and the center of the conductive pillar 11 within the second region 502 of the first surface of the substrate 14 may include: using an optical microscope to detect the minimum distance between the edge of the opening of the first photoresist structure 13 and the center of the conductive pillar 11 from one side of the first photoresist structure 13.
[0207] Because the first dielectric layer 12 has high transparency, the pattern of the conductive pillar 11 can be detected through the first dielectric layer 12 under an optical microscope, thereby determining the minimum distance between the edge of the opening of the first photoresist structure 13 and the center of the conductive pillar 11.
[0208] It should be noted that the minimum distance between the edge of the first opening 131 of the first photoresist structure 13 and the edge of the conductive pillar 11 in the first region 501 of the first surface of the detection substrate 14 is similar to the minimum distance between the edge of the first opening 131 of the first photoresist structure 13 and the center of the conductive pillar 11 in the second region 502 of the first surface of the detection substrate 14, and will not be elaborated here.
[0209] In other embodiments, for Figure 4 The semiconductor structure shown also includes a second dielectric layer 15 and a second photoresist structure 16.
[0210] The second dielectric layer 15 covers the second side of the marking area 50.
[0211] The second photoresist structure 16 is disposed on the side of the second dielectric layer 15 away from the substrate 14, and the second photoresist structure 16 includes a plurality of second openings 161 in the marking area 50.
[0212] See Figure 2 In the first region 501, the second opening 161 encloses two conductive pillars 11. In the second region 502, the edge of the second opening 161 and the center of the conductive pillars 11 are spaced apart in a direction parallel to the substrate 14.
[0213] Correspondingly, the alignment test method for the semiconductor structure may further include the following steps S203 to S204:
[0214] S203: Detect the minimum distance between the edge of the second opening 161 of the second photoresist structure 16 and the edge of the conductive pillar 11 within the first region 501 of the second surface of the substrate 14, and / or, detect the minimum distance between the edge of the second opening 161 of the second photoresist structure 16 and the center of the conductive pillar 11 within the second region 502 of the second surface of the substrate 14.
[0215] S204: Based on the minimum distance, determine the alignment accuracy between the second connecting wire 28 and the conductive post 11 at the second opening 161 of the second photoresist structure 16 within the functional area 30.
[0216] Understandably, the specific testing methods are similar to those described above, and will not be repeated here.
[0217] The beneficial technical effects of the technical solutions provided in this application include:
[0218] The alignment test method for semiconductor structures provided in this embodiment uses the alignment accuracy of the first connecting wire at the opening of the first photoresist structure in the marking area and the conductive post to characterize the alignment accuracy of the first connecting wire at the opening of the first photoresist structure in the functional area and the conductive post. When the alignment accuracy between each conductive post and the first photoresist structure in the marking area is poor, the first photoresist structure is remanufactured. This can effectively ensure the alignment accuracy between each conductive post in the marking area and the first connecting wire formed by the first photoresist structure, thereby guaranteeing the alignment accuracy between each conductive post and the first connecting wire in the functional area and reducing the risk of defective wafers.
[0219] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.
[0220] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0221] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0222] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0223] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0224] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.
Claims
1. A semiconductor structure, characterized by, The application relates to a substrate and a method for manufacturing the same. The substrate comprises: a plurality of functional areas arranged in an array; a plurality of cutting areas, each of which is located between adjacent functional areas; a plurality of marking areas, each of which comprises an adjacent area of the cutting areas; the marking areas comprise: N conductive columns arranged in a preset pattern in a substrate, the conductive columns being perpendicular to the substrate; a first dielectric layer covering a first surface of the marking areas; 2. The semiconductor structure of claim 1, wherein, a first photoresist structure arranged on a side of the first dielectric layer away from the substrate, the first photoresist structure comprising a plurality of first openings in the marking areas; the marking areas comprise a first region and a second region; in the first region, the first openings enclose two conductive columns, and / or in the second region, the first openings are spaced apart from the conductive columns. The application further comprises: a second dielectric layer covering a second surface of the marking areas; 3. The semiconductor structure of claim 2, wherein, a second photoresist structure arranged on a side of the second dielectric layer away from the substrate, the second photoresist structure comprising a plurality of second openings in the marking areas; in the first region, the second openings enclose two conductive columns, and in the second region, edges of the second openings are spaced apart from centers of the conductive columns in a direction parallel to the substrate.
4. The semiconductor structure of claim 2, wherein, In the first region, first ends of every two adjacent conductive columns starting from an odd-numbered conductive column are enclosed by one first opening, and second ends of every two adjacent conductive columns starting from an even-numbered conductive column are enclosed by one second opening.
5. The semiconductor structure of claim 1, wherein, In the second region, the second openings are mirror-symmetric to the first openings. In the first region, the first openings are arranged in a row direction of the functional areas.
6. The semiconductor structure of claim 5, wherein, The second region comprises a first sub-region and a second sub-region, the first sub-region and the second sub-region being arranged on two sides of the first region in the row direction of the functional areas; the first openings in the first sub-region are axially symmetric to the first openings in the second sub-region, and the conductive columns in the first sub-region are axially symmetric to the conductive columns in the second sub-region.
7. A method of manufacturing a semiconductor device, characterized by The conductive columns in the first region are axially symmetric with the column direction or the row direction of the functional areas as the axis of symmetry. The application relates to a substrate and a method for manufacturing the same. The method comprises the following steps: forming N first holes arranged in a preset pattern in a marking area on a first surface of a substrate, a bottom surface of each of the first holes being close to a second surface of the substrate; the marking area comprises an adjacent area of at least two cutting areas; the cutting areas are located between adjacent functional areas arranged in an array; forming conductive columns in each of the first holes; 8. The method of manufacturing a semiconductor device according to claim 7, wherein forming a first dielectric layer covering the marking area on the first surface; forming a first photoresist structure on a side of the first dielectric layer away from the substrate, the first photoresist structure comprising a plurality of first openings in the marking area; the marking area comprises a first region and a second region; in the first region, the first openings enclose two conductive columns, and / or in the second region, the first openings are spaced apart from the conductive columns. After the step of forming the first photoresist structure on the side of the first dielectric layer away from the substrate, the method further comprises the following steps: using the first photoresist structure as a mask to perform etching treatment on the first dielectric layer to form a plurality of first grooves. A first connecting wire is formed in each of the first grooves, so that in the first area, a first connecting wire is connected to the first end of every two adjacent conductive pillars from the first odd-numbered conductive pillar, and in the second area, the edge of the first connecting wire is spaced apart from the center of the conductive pillar.
9. The method of manufacturing a semiconductor device according to claim 7 or 8, wherein After forming the first photoresist structure on the side of the first dielectric layer away from the substrate, further comprising: The second surface of the substrate is subjected to thinning and etching treatment, so that the second end of the conductive pillar protrudes from the second surface; An insulating structure is manufactured in the mark area and flush with the second end of the conductive pillar; A second dielectric layer is formed covering the mark area of the second surface; A second photoresist structure is formed on the side of the second dielectric layer away from the substrate, and the second photoresist structure contains a plurality of second openings in the mark area; in the first area, the second opening is surrounded by two conductive pillars, and in the second area, the second opening is spaced apart from the conductive pillar.
10. The method of manufacturing a semiconductor device according to Claim 9, wherein After forming the second photoresist structure on the side of the second dielectric layer away from the substrate, further comprising: The second dielectric layer is etched with the second photoresist structure as a mask to form a plurality of second grooves; A second connecting wire is formed in each of the second grooves, so that in the first area, a second connecting wire is connected to the second end of every two adjacent conductive pillars from the first even-numbered conductive pillar, and in the second area, the edge of the second connecting wire is spaced apart from the center of the conductive pillar.
11. The method of manufacturing a semiconductor device according to Claim 7, wherein Before forming the N first holes arranged in a preset pattern in the mark area of the first surface of the substrate, further comprising: A third dielectric layer is formed on the first surface of the substrate; A groove is formed on the side of the third dielectric layer away from the substrate; An alignment structure is formed in the groove; Forming N first holes arranged in a preset pattern in the mark area of the first surface of the substrate, comprising: Taking the alignment structure as an alignment reference, a third photoresist structure is formed in the mark area of the first surface of the substrate, and the third photoresist structure includes N third openings arranged in a preset pattern; The substrate is etched with the third photoresist structure as a mask to form the first holes arranged in a preset pattern; And, forming a first photoresist structure on the side of the first dielectric layer away from the substrate, comprising: Taking the alignment structure as an alignment reference, a first photoresist structure is formed on the side of the first dielectric layer away from the substrate.
12. A method of alignment testing of a semiconductor structure as claimed in any one of claims 1-6, characterized in that Comprising: Detecting the minimum distance between the edge of the first opening of the first photoresist structure and the edge of the conductive pillar in the first area of the first surface of the substrate, and / or detecting the minimum distance between the edge of the first opening of the first photoresist structure and the center of the conductive pillar in the second area of the first surface of the substrate; According to the minimum distance, the alignment accuracy of the first connecting wire at the first opening of the first photoresist structure and the conductive pillar in the functional area is determined.
13. The method of claim 12, wherein the method further comprises: Detecting the minimum distance between the edge of the first opening of the first photoresist structure and the center of the conductive pillar in the mark area of the first surface of the substrate, comprising: taking a photo of the first photoresist structure from a side of the first photoresist structure perpendicular to the substrate, to obtain a photo containing a pattern of the first opening and a pattern of the conductive pillar; determining the minimum distance between the edge of the first opening of the first photoresist structure and the center of the conductive pillar according to the pattern of the first opening and the pattern of the conductive pillar in the photo.
14. The method of claim 12, wherein the method further comprises: detecting the minimum distance between the edge of the first opening of the first photoresist structure and the center of the conductive pillar in a mark area of a first surface of a substrate, comprising: detecting the minimum distance between the edge of the first opening of the first photoresist structure and the center of the conductive pillar from a side of the first photoresist structure by using an optical microscope.