Semiconductor structure and manufacturing method thereof
By etching the extension of the lower electrode to reduce the horizontal width and form a conductive support layer, the problem of high technical difficulty in capacitor structure manufacturing was solved, and the integrity of the capacitor structure and the capacity were improved.
Patent Information
- Application Number
- CN202410853846.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-27
- Publication Date
- 2025-12-30
AI Technical Summary
With the development of manufacturing processes, the size of capacitor holes is getting smaller and the spacing is getting smaller, which increases the difficulty of forming capacitor structures, resulting in a decrease in the integrity and capacity of capacitor structures. Furthermore, existing technologies are unable to effectively fill the dielectric layer and the top electrode.
After forming the extension of the lower electrode, its horizontal width is reduced by etching, the spacing is increased, and a conductive support layer is formed on the extension. Then, the main body is etched to expose the main body, and a dielectric layer and an upper electrode are formed on the main body to ensure the integrity and capacity of the capacitor structure.
The manufacturing process of the capacitor structure is simplified, ensuring the integrity and capacity of the capacitor structure, avoiding the problem of short circuit of the lower electrode, and improving the filling capacity and capacitance of the capacitor.
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Figure CN121237783A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof. BACKGROUND
[0002] Dynamic Random Access Memory (DRAM) is a kind of semiconductor memory widely used in computer systems. As one of the necessary structures in DRAM, the capacitor has the functions of voltage adjustment and filtering in the circuit, and is widely used in integrated circuits.
[0003] With the development of preparation process, the size of the capacitor hole is getting smaller and smaller, and the distance is also getting smaller and smaller, and the process difficulty of forming the capacitor structure also increases. SUMMARY
[0004] According to a first aspect of embodiments of the present disclosure, a manufacturing method of a semiconductor structure is provided, comprising:
[0005] forming a stack on a substrate;
[0006] forming a plurality of lower electrodes in the stack, the lower electrodes comprising a main body part in the stack and an extension part protruding from the stack;
[0007] etching the extension part so that the horizontal width of the extension part is smaller than the horizontal width of the main body part;
[0008] forming a dielectric layer and a conductive film layer on the stack in sequence, the dielectric layer and the conductive film layer covering the extension part;
[0009] etching the conductive film layer to expose the stack and form a plurality of conductive support layers;
[0010] etching the stack to expose the main body part;
[0011] forming a dielectric layer on the main body part;
[0012] forming an upper electrode on the dielectric layer.
[0013] In some embodiments, the step of forming a stack comprises:
[0014] forming a bottom support layer on the substrate;
[0015] forming a first sacrificial layer on the bottom support layer;
[0016] forming an intermediate support layer on the first sacrificial layer;
[0017] forming a second sacrificial layer on the intermediate support layer.
[0018] In some embodiments, the step of forming the lower electrode comprises:
[0019] forming a mask layer on the second sacrificial layer;
[0020] etching the stack according to the mask layer to form a capacitor hole in the stack;
[0021] forming a lower electrode in the capacitor hole;
[0022] removing part of the second sacrificial layer to make the lower electrode protrude out of the stack.
[0023] In some embodiments, the step of removing part of the second sacrificial layer comprises:
[0024] removing part of the second sacrificial layer by dry etching to form the extension;
[0025] wherein the height of the extension is substantially the same as the thickness of the intermediate support layer.
[0026] In some embodiments, the plurality of lower electrodes are formed by filling lower electrode material into the capacitor hole; the lower electrode comprises:
[0027] a plurality of first lower electrodes;
[0028] a plurality of second lower electrodes;
[0029] wherein the spacing between adjacent first lower electrodes is smaller than the spacing between adjacent second lower electrodes.
[0030] In some embodiments, the step of forming the conductive support layer comprises:
[0031] removing the conductive film layer between the extensions to expose the dielectric layer on the sidewalls of the extensions and to expose the stack;
[0032] removing the dielectric layer on the sidewalls of the extensions to expose the sidewalls of the extensions.
[0033] In some embodiments, the step of forming the conductive support layer comprises removing part of the conductive film layer between adjacent first lower electrodes to expose the second sacrificial layer between adjacent first lower electrodes.
[0034] In some embodiments, the step of forming the upper electrode comprises:
[0035] depositing an upper electrode material on the dielectric layer, the upper electrode material also being on the conductive support layer;
[0036] wherein the dielectric layer is between the upper electrode material and the conductive support layer.
[0037] In some embodiments, further comprising forming an upper plate on the conductive support layer, the upper plate in contact with the upper electrode on the conductive support layer.
[0038] In some embodiments, the upper plate further extends between adjacent ones of the body portions to contact the upper electrode between the body portions.
[0039] According to a second aspect of embodiments of the present disclosure, there is provided a semiconductor structure, comprising:
[0040] a substrate;
[0041] a plurality of lower electrodes on the substrate, the lower electrodes comprising body portions and extension portions, the extension portions having a horizontal width smaller than a horizontal width of the body portions;
[0042] an intermediate support layer on a middle region of the body portions;
[0043] a conductive support layer on the extension portions, the conductive support layer having a dielectric layer between the conductive support layer and the extension portions;
[0044] a conductive pillar on the conductive support layer.
[0045] In some embodiments, the dielectric layer is also on the body portions, and an upper electrode is further provided on the dielectric layer.
[0046] In some embodiments, the conductive support layer extends between the lower electrodes to contact the upper electrode between the lower electrodes.
[0047] In some embodiments, the conductive support layer protrudes from the upper electrode.
[0048] In some embodiments, the conductive support layer has a thickness greater than a thickness of the intermediate support layer.
[0049] In summary, the embodiment of the present disclosure proposes a semiconductor structure and a manufacturing method thereof. First, a lower electrode is formed in a stack, then an extension of the lower electrode is etched, so that the horizontal width of the extension is smaller than the horizontal width of the main body part, that is, the spacing between the extensions is increased, then a conductive support layer is formed on the extension, the lower electrode is supported by the conductive support layer, then the stack structure exposed by the conductive support layer is etched, so as to expose the main body part, and then a dielectric layer and an upper electrode are formed on the main body part, so as to form a capacitor structure. In the embodiment of the present disclosure, before the conductive support layer is formed, the extension is etched first, so that the horizontal width of the extension is reduced, and at the same time, the integrity of the main body part is ensured due to the blocking effect of the stack structure. After the main body part is exposed, the horizontal width of the extension is reduced, and the horizontal width of the extension is increased, which is beneficial to depositing the dielectric layer and the upper electrode on the main body part, so as to ensure the integrity of the capacitor, and the process is simple. BRIEF DESCRIPTION OF DRAWINGS
[0050] Figure 1 is a schematic diagram of lateral etching of the top support layer during etching according to an example embodiment;
[0051] Figure 2 is a schematic diagram of lower electrode material connection according to an example embodiment;
[0052] Figure 3 is a schematic diagram of residual first sacrificial layer according to an example embodiment;
[0053] Figure 4 is a flow chart of a manufacturing method of a semiconductor structure according to an example embodiment;
[0054] Figure 5 is a schematic diagram of forming a stack according to an example embodiment;
[0055] Figure 6 is a schematic diagram of forming a capacitor hole according to an example embodiment;
[0056] Figure 7 is a schematic diagram of Figure 6 a brief top view according to an example embodiment;
[0057] Figure 8 is another schematic diagram of forming a capacitor hole according to an example embodiment;
[0058] Figure 9 is a schematic diagram of filling upper electrode material according to an example embodiment;
[0059] Figure 10 is a schematic diagram of forming a lower electrode according to an example embodiment;
[0060] Figure 11 is shown according to an example embodiment Figure 10 is a simplified top view of
[0061] Figure 12 is another schematic view of forming a lower electrode according to an example embodiment
[0062] Figure 13 is a schematic view of etching an extension according to an example embodiment
[0063] Figure 14 is a schematic view of forming a conductive film layer according to an example embodiment
[0064] Figure 15 is an enlarged view in the dashed box of Figure 14
[0065] Figure 16 is a schematic view of forming a conductive support layer according to an example embodiment
[0066] Figure 17 is a schematic view of forming an upper electrode according to an example embodiment
[0067] Figure 18 is a schematic view of a location of a dielectric layer according to an example embodiment
[0068] Figure 19 is a schematic view of removing a surface upper electrode according to an example embodiment
[0069] Figure 20 is a schematic view of forming an upper plate according to an example embodiment
[0070] Figure 21 is a schematic view of a semiconductor structure according to an example embodiment
[0071] Figure 22 is a schematic view of a second lower electrode according to an example embodiment
[0072] Figure 23 is a schematic view of an electronic device according to an example embodiment DETAILED DESCRIPTION
[0073] The technical solutions of the present disclosure will be described in further detail below with reference to the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0074] The present disclosure will be described in more detail in the following paragraphs with reference to the accompanying drawings and embodiments. The advantages and features of the present disclosure will be more apparent from the following description and claims. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, only for the purpose of facilitating, clarifying and assisting in the description of the embodiments of the present disclosure.
[0075] It can be understood that the meanings of "on", "above" and "over" of the present disclosure should be interpreted in the broadest way, so that "on" not only means the meaning of "on" something with no intervening features or layers therebetween (i.e. directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.
[0076] In the embodiments of the present disclosure, the terms "first", "second", "third" and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.
[0077] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of a continuous structure, or the layer can be between any pair of horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.
[0078] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.
[0079] As Figure 1As shown, in some embodiments, when forming the columnar capacitor structure, a bottom support layer 102, a first sacrificial layer 103, an intermediate support layer 104, a second sacrificial layer 105, a top dielectric layer 1051, and a mask layer 106 can be sequentially formed on the substrate 101. Then, based on the mask layer 106, the top dielectric layer 1051, the second sacrificial layer 105, the intermediate support layer 104, the first sacrificial layer 103, and the bottom support layer 102 are etched sequentially, thereby forming the capacitor hole 107. In some embodiments, the material of the mask layer 106 is polysilicon, and the material of the top dielectric layer 1051 is silicon nitride. When using etching gas to remove the mask layer 106 and form the capacitor hole 107, the etching selectivity of the etching gas for polysilicon and silicon nitride is quite different. Furthermore, when the etching gas is etching downwards, the top dielectric layer 1051 will be continuously etched by the etching gas, meaning that the top dielectric layer 1051 is etched for a long time. This results in a certain amount of side etching of the top dielectric layer 1051, thereby forming a groove 1071 on the top dielectric layer 1051.
[0080] like Figures 2-3 As shown, in some embodiments, grooves 1071 are formed in some top dielectric layers 1051. In more severe cases, these top dielectric layers 1051 are consumed by etching gas, so that when the lower electrode material 108 is filled in the capacitor hole 107, the lower electrode material 108 is interconnected in the regions where these top dielectric layers 1051 are consumed. Figure 3 (As shown in the dashed box in the image), the subsequent lower electrodes are interconnected, causing the capacitor to short-circuit. Simultaneously, because these lower electrode materials 108 are interconnected, it is impossible to create holes in this portion of the lower electrode material 108. This results in the first sacrificial layer 103 located beneath these lower electrode materials 108 not being completely removed; that is, a portion of the first sacrificial layer 103 remains. Consequently, the dielectric layer and upper electrode cannot be filled in these areas, thus compromising the integrity of the capacitor structure and reducing the capacitance.
[0081] like Figure 1 As shown, in some embodiments, researchers also found that during the formation of capacitor holes 107, as the aspect ratio of the capacitor holes increases, the spacing between some capacitor holes 107 becomes smaller than the spacing between other capacitor holes 107. This is also not conducive to the subsequent filling of the dielectric layer and the top electrode, affecting the integrity of the capacitor structure.
[0082] like Figure 4 As shown, to improve the above-mentioned problems, embodiments of this disclosure propose a method for manufacturing a semiconductor structure. This method can be used to manufacture columnar capacitors, which facilitates the filling of the dielectric layer and the top electrode, and simplifies the manufacturing process of the capacitor structure. The manufacturing method includes:
[0083] S1: Forming a stack on the substrate;
[0084] S2: A plurality of lower electrodes are formed in the stack, the lower electrodes including a main body portion located in the stack and an extension portion protruding from the stack;
[0085] S3: Etch the extension portion so that the horizontal width of the extension portion is smaller than the horizontal width of the main body portion;
[0086] S4: A dielectric layer and a conductive film layer are sequentially formed on the stack, the dielectric layer and the conductive film layer covering the extension;
[0087] S5: Etch the conductive film layer to expose the stack and form multiple conductive support layers;
[0088] S6: Etch the stacked layers to expose the main body;
[0089] S7: A dielectric layer is formed on the main body, and an upper electrode is formed on the dielectric layer.
[0090] like Figure 5 As shown, in step S1, a substrate 101 is first provided, and then a bottom support layer 102, a first sacrificial layer 103, an intermediate support layer 104, and a second sacrificial layer 105 are sequentially formed on the substrate 101, that is, a stack 10 is formed on the substrate 101. The substrate 10 may include silicon, germanium, silicon-germanium, or III-V compound semiconductors (e.g., GaP, GaAs). In some embodiments, the substrate 10 may be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The substrate 101 may include word lines, bit lines, and other structures.
[0091] like Figure 5 As shown, the stack 10 can be formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In this embodiment, the bottom support layer 102 and the intermediate support layer 104 can be made of the same material, and the first sacrificial layer 103 and the second sacrificial layer 105 can be made of the same material. During subsequent etching, portions of the bottom support layer 102 and the intermediate support layer 104 are retained to support the lower electrode. The first sacrificial layer 103 and the second sacrificial layer 105 are completely removed in subsequent processes. The first sacrificial layer 103 and the second sacrificial layer 105 can be made of soft materials such as phosphorosillicate glass (PSG), boro-phospho-silicate glass (BPSG), or fluorosillicate glass (FSG); the bottom support layer 102 and the intermediate support layer 104 can be nitrides, such as silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon boronitride.
[0092] likeFigure 5 As shown in this embodiment, the first sacrificial layer 103 and the second sacrificial layer 105 have substantially the same thickness, the bottom support layer 102 and the intermediate support layer 104 have substantially the same thickness, and the thickness of the first sacrificial layer 103 is greater than the thickness of the bottom support layer 103. The larger thickness of the first sacrificial layer 103, and the subsequent removal of both the first sacrificial layer 103 and the second sacrificial layer 105, increases the capacitance. The thickness of the first sacrificial layer 103 can be 300-1000 nm, for example, 400, 500, 600, 700, 800, or 900 nm. The thickness of the bottom support layer 102 can be 10-80 nm, for example, 20, 30, 40, 50, 60, or 70 nm.
[0093] like Figure 5 As shown, after forming the stack 10, a mask layer 106 is directly formed on the stack 10, that is, the mask layer 106 is directly formed on the second sacrificial layer 105. The mask layer 106 is then patterned to expose the second sacrificial layer 105. In this embodiment, the mask layer 106 can be made of polysilicon. When etching the stack 10 based on the mask layer 106, since the material of the second sacrificial layer 105 is silicon oxide, the etching gas has a relatively low selectivity for both polysilicon and silicon oxide, thus preventing lateral etching of the silicon oxide. In this embodiment, by forming the mask layer 106 directly on the second sacrificial layer 105, that is, by not including a top dielectric layer in the stack 10, problems with subsequent lower electrode material bonding can be prevented.
[0094] like Figures 6-8 As shown, in step S2, the stack 10 is etched according to the mask layer 106, that is, the second sacrificial layer 105, the intermediate support layer 104, the first sacrificial layer 103, and the bottom support layer 102 are etched, thus forming capacitor holes 107 in the stack 10. In some embodiments, the stack 10 can be etched by dry etching, that is, a portion of the second sacrificial layer 105, a portion of the intermediate support layer 104, a portion of the first sacrificial layer 103, and a portion of the bottom support layer 102 are removed by dry etching. During etching, a large number of capacitor holes 107 are formed. Due to the large aspect ratio of the capacitor holes 107 and the increasing density of the capacitor holes 107, some capacitor holes 107 will have larger diameters and some smaller diameters during the etching process. For example, from... Figure 7 It can be seen from this that, Figure 7From left to right, the first capacitor hole 107 has a smaller diameter, while the second and third capacitor holes 107 have larger diameters. This indicates a larger gap between the first and second capacitor holes 107, and a smaller gap between the second and third capacitor holes 107. This makes it more difficult to fill the space between the second and third capacitor holes 107 with the dielectric layer and the upper electrode in subsequent processes. During the formation of the capacitor holes 107, the mask layer 106 is gradually consumed. After the capacitor holes 107 are formed, the mask layer 106 is also completely consumed. Simultaneously, because the intermediate support layer 104 is located in the middle region of the stack 10, the etching time of the intermediate support layer 104 is reduced during the formation of the capacitor holes 107. Although the intermediate support layer 104 is etched laterally, it does not cause interconnection of the lower electrode materials, nor does it completely etch away the intermediate support layer 104. This ensures that the lower electrodes are independent and do not short-circuit.
[0095] like Figures 9-10 As shown, in step S2, after forming the capacitor hole 107, the lower electrode material 108 is filled into the capacitor hole 107. In this embodiment, the lower electrode material 108 can be formed in the capacitor hole 107 by chemical vapor deposition, and the lower electrode material 108 can completely fill the capacitor hole 107. The lower electrode material 108 can be a metal nitride or a metal silicide, such as titanium nitride. Since the lower electrode material 108 completely covers the capacitor hole 107, a polishing process is performed on the lower electrode material 108 so that the lower electrode material 108 is flush with the second sacrificial layer 105, thereby forming independent lower electrodes. Simultaneously, since the second sacrificial layer 105 is not laterally etched, or in other words, the degree of lateral etching of the second sacrificial layer 105 is small, the top of the second sacrificial layer 105 will not be etched away, thus preventing interconnection of the lower electrode materials 108 and avoiding the problem of short circuits in the lower electrodes.
[0096] like Figures 10-11 As shown, in this embodiment, the lower electrode 11 can be divided into a first lower electrode 109 and a second lower electrode 110, that is, the lower electrode may include multiple first lower electrodes 109 and multiple second lower electrodes 110. The first lower electrode and the second lower electrode 110 are independent of each other, that is, separated by a second sacrificial layer 105, an intermediate support layer 104, a first sacrificial layer 103, and a bottom support layer 102. Figure 11 As can be seen, the distance d1 between the first lower electrode 109 and the second lower electrode 110 is greater than the distance d2 between the two lower electrodes 109. The distance d3 between the second lower electrode 110 and the second lower electrode 110 can be greater than the distance d1 between the two lower electrodes 109, that is, the distance between the two lower electrodes 109 is the smallest. Figure 10As can be seen, the horizontal width of the second sacrificial layer 105 between the first lower electrode 109 and the first lower electrode 109 is the smallest.
[0097] like Figure 12 As shown, in step S3, after forming the lower electrode 11 (first lower electrode 109 and second lower electrode 110), the second sacrificial layer 105 is dry-etched, thereby making the height of the second sacrificial layer 105 lower than that of the lower electrode. This embodiment uses the second lower electrode 110 as an example. After etching the second sacrificial layer 105, the second lower electrode 110 protrudes beyond the second sacrificial layer 105. That is, the second lower electrode 110 may include a main body 111 and an extension 112. The main body 111 may be located in the stack 10, and the extension 112 may protrude beyond the stack 10, i.e., the extension 112 protrudes beyond the second sacrificial layer 105. In this embodiment, the thickness of the etched second sacrificial layer 105 can be substantially the same as the thickness of the intermediate support layer 104, meaning the height of the extension 112 can be substantially the same as the thickness of the intermediate support layer 104. If the height of the extension 112 is too large, it will reduce the height of the main body 111, potentially reducing the capacitance. If the height of the extension 112 is too small, the height of the capacitor structure will increase when a conductive support layer is formed on the extension 112, increasing the risk of capacitor collapse (lower electrode collapse). Therefore, in this embodiment, the height of the extension 112 can be basically the same as the thickness of the intermediate support layer 104, which can ensure the capacitor capacity and prevent the capacitor structure from collapsing.
[0098] like Figure 13 As shown, after the second lower electrode 110 is formed, the extension 112 of the second lower electrode 109 is etched, thereby making the horizontal width of the extension 112 smaller than the horizontal width of the main body 111. Because the horizontal width of the extension 112 is small, the spacing between the extensions 112 is increased. Simultaneously, due to the blocking effect of the second sacrificial layer 105, the etching gas will not affect the main body 111, thus ensuring the integrity of the main body 111. It should be noted that the structure of the first lower electrode 109 can refer to the structure of the second lower electrode 110.
[0099] like Figures 14-15As shown, in step S4, after etching the extension 112, a dielectric layer 114 and a conductive film layer 113 can be sequentially formed on the stack 10. The dielectric layer 114 covers the surface of the extension 112 and the surface of the second sacrificial layer 105, and the conductive film layer 113 covers the dielectric layer 114. The conductive film layer 113 can fill the gaps between the extensions 112 and also covers the extensions 112. For example, the dielectric layer 114 and the conductive film layer 113 can be formed by chemical vapor deposition. The dielectric layer 114 can be a capacitor dielectric layer, which can be a high-K material, such as zirconium oxide, hafnium oxide, zirconium titanate, ruthenium oxide, antimony oxide, and aluminum oxide. The conductive film layer 113 can be a silicon-germanium layer or a tungsten metal layer. Since the dielectric layer 114 exists between the conductive film layer 113 and the extension 112, a capacitor structure is formed, increasing the capacitance.
[0100] like Figure 16 As shown, in steps S4-S5, after forming the conductive film layer 113, the conductive film layer 113 and the dielectric layer 114 are etched to expose the stack 10, which in turn exposes the second sacrificial layer 105. Simultaneously, multiple conductive support layers 115 can also be formed. When forming the conductive support layers 115, a portion of the conductive film layer 113 located between the extensions 112 is first etched to expose the dielectric layers 114 on the sidewalls of the extensions 112. Then, these dielectric layers 114 are etched to expose the sidewalls of the extensions 112. Figure 16 As can be seen, the conductive support layer 115 can be located on the extension 112. The sidewall of the conductive support layer 115 can be flush with the sidewall of the extension 112, that is, the conductive support layer 115 is not located between the extensions 112, so the spacing between the extensions 112 will not be reduced. After the second sacrificial layer 105 is exposed, the second sacrificial layer 105 and the first sacrificial layer 103 can be removed through the gap between the conductive support layers 115 using a wet removal solution, while also removing part of the intermediate support layer 104, thereby exposing the main body 111.
[0101] like Figure 16 As shown in this embodiment, since the first lower electrode 109 and the second lower electrode 110 are independent and not interconnected, the second sacrificial layer 105 can be exposed when the conductive support layer 115 is formed. Therefore, when removing the second sacrificial layer 105 and the first sacrificial layer 103 with a wet solution, it can be ensured that both the second sacrificial layer 105 and the first sacrificial layer 103 are completely removed, effectively avoiding any residual portions of these sacrificial layers.
[0102] like Figure 16As shown in this embodiment, due to the small gap between the first lower electrodes 109, the second sacrificial layer 105 located between the first lower electrodes 109 is exposed when the conductive support layer 115 is formed. Therefore, a wet chemical solution can remove the second sacrificial layer 105, the intermediate support layer 104, and the first sacrificial layer 103 between the first lower electrodes 109. Simultaneously, the intermediate support layer 104 located directly below the conductive support layer 115 is not removed, thus allowing the intermediate support layer 104 to be positioned in the middle region of the first lower electrodes 109, thereby supporting the first lower electrodes 109. Of course, the intermediate support layer 104 is also located in the middle region of the second lower electrode 110. The middle region can be the middle position between the first lower electrode 109 and the second lower electrode 110.
[0103] like Figure 14 and Figure 16 As shown, in this embodiment of the present disclosure, before forming the conductive support layer 115, the extensions 112 are first etched, that is, the horizontal width of the extensions 112 is reduced and the spacing between the extensions 112 is increased; then, a conductive film layer 113 is filled between the extensions 112, and then the conductive film layer 113 is etched to form the conductive support layer 115. The present disclosure etches the extensions 112 first, which allows the second sacrificial layer 105 to act as a barrier against the etching gas, preventing the etching gas from etching the main body 111, thereby protecting the main body 111 and preventing interface damage. Since only the extensions 112 are etched, the etching gas does not need to be replaced during the etching process, making the etching process simpler. Simultaneously, because the spacing between the extensions 112 increases when the conductive film layer 113 is etched, it is easier to etch the conductive film layer 113 between the extensions 112, ensuring that the second sacrificial layer 105 between the extensions 112 is fully exposed. Of course, in some embodiments, the extension 112 is not etched during the formation of the lower electrode. Instead, after the formation of the conductive film layer 113, a portion of the extension 112 is etched simultaneously with the etching of the conductive film layer 113, thereby increasing the spacing between the extensions 112. Although this etching method can increase the spacing between the extensions 112, before the formation of the conductive film layer 113, the small spacing of the extensions 112 may create voids in the conductive film layer 113, thus reducing the supporting effect of the conductive support layer 115. Furthermore, since the conductive film layer 113, the dielectric layer 114, and the extension 112 need to be etched simultaneously, the etching gas needs to be changed during the etching process, making the etching process relatively complex. Therefore, in this embodiment, the extension 112 is etched before the formation of the conductive film layer 113 to reduce the horizontal width of the extension 112.
[0104] like Figures 17-18As shown, in step S7, after exposing the main body 111, a dielectric layer 114 is first formed on the surface of the main body 111. The dielectric layer 114 may be located on the conductive support layer 115 and also on the intermediate support layer 104. After forming the dielectric layer 114, an upper electrode 116 is then formed on the dielectric layer 114, and the upper electrode 116 may completely cover the dielectric layer 114. Figure 18 Figure (a) shows the positional relationship between the conductive support layer 115, the dielectric layer 114, and the upper electrode 116. Figure 18 Figure (b) shows the positional relationship between the main body 110, the dielectric layer 114, and the upper electrode 116. From... Figure 18 As can be seen, the dielectric layer 114 is located between the conductive support layer 115 and the upper electrode 116. The dielectric layer 114 is located between the main body 110 and the upper electrode 116. The main body 110, the dielectric layer 114, and the upper electrode 116 can form a capacitor structure. The conductive support layer 115, the dielectric layer 114, and the upper electrode 116 can also form a capacitor structure, thereby increasing the capacitance.
[0105] like Figures 17-18As shown, in this embodiment of the present disclosure, a dielectric layer 114 is formed on the main body 111 using a chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) process. Because the extensions 112 are etched, the horizontal width of the extensions 112 decreases, and the spacing between the extensions 112 increases. Therefore, when depositing the dielectric layer 114, deposited atoms can more easily enter the area between the extensions 112, thus making it easier to form the dielectric layer 114 on the main body 111. For example, in this embodiment, because the spacing between the first lower electrodes 109 is small and the height of the first lower electrodes 109 is relatively high, the horizontal width of the extensions 112 of the first lower electrodes 109 is reduced. Deposited atoms can more easily enter the area between the extensions 112 of the first lower electrodes 109, thereby making it easier to enter the area between the main body portions 111 of the first lower electrodes 109, and thus making it easier to form the dielectric layer 114 on the first lower electrodes 109. Conversely, if the horizontal width of the extension 112 is not reduced, the dielectric layer 114 will not easily form on the first lower electrodes 109 due to the small spacing between them and their relatively high height, thus preventing the formation of a capacitor structure. After the dielectric layer 114 is formed, the spacing between the first lower electrodes 109 becomes even smaller. By reducing the horizontal width of the extension 112 on the first lower electrodes 109, the spacing between the extensions 112 is increased, making it easier for deposited atoms to enter between the first lower electrodes 109, thereby forming the upper electrode 116 on the dielectric layer 114. Of course, since the spacing between the second lower electrodes 110 is larger, the extensions 112 on the second lower electrodes 110 are also etched, making it easier to form the dielectric layer 114 and the upper electrode 116 on the second lower electrodes 110. Since the sidewall of the conductive support layer 115 is flush with the sidewall of the extension 112, there is no conductive support layer 115 between the extensions 112 of the adjacent first lower electrode 109. Therefore, the conductive support layer 115 will not occupy the area between the extensions 112 of the adjacent first lower electrode 109, which is beneficial for depositing the dielectric layer 114 and the upper electrode 116.
[0106] like Figure 18 As shown in this embodiment, the dielectric layer 114 can be made of a high-K material, such as zirconium oxide, hafnium oxide, zirconium titanium oxide, ruthenium oxide, antimony oxide, and aluminum oxide. The upper electrode 116 can be made of metal nitrides and metal silicides, such as titanium nitride and silicon titanium nitride.
[0107] like Figures 19-20As shown in this embodiment, the conductive support layer 115 is located on top of the second lower electrode 110, covering the extension 112 of the second lower electrode 110. Naturally, the conductive support layer 115 also covers the extension 112 of the first lower electrode 109. Since the conductive support layer 115 provides support for both the first lower electrode 109 and the second lower electrode 110, and because it is conductive, it can also function as a conductor, allowing interconnection with metal pillars to achieve signal transmission. Of course, in some embodiments, after forming the upper electrode 116, the dielectric layer 114 and the upper electrode 116 located on the upper surface of the conductive support layer 115 can be removed, that is, the dielectric layer 114 and the upper electrode 116 located on the sidewall of the conductive support layer 115 can be exposed. That is, the upper electrode 116 can extend from the first lower electrode 109 or the second lower electrode 110 to the conductive support layer 115, so that the conductive support layer 115 and the upper electrode 116 are coplanar. Then, an upper electrode plate 117 is formed on the conductive support layer 115, and the upper electrode plate 115 can cover the conductive support layer 116. Part of the upper electrode plate 117 can also be located in the region between adjacent conductive support layers 115 and extend between the main body portions 111, thereby interconnecting with the upper electrode 116 between the main body portions 111 and the upper electrode 116 on the conductive support layer 115, thereby increasing the contact area between the upper electrode plate 117 and the upper electrode 116, reducing the contact resistance, and also providing a supporting function. The material of the upper electrode plate 117 can be the same as that of the conductive support layer 115. The upper electrode plate 117 and the upper electrode 116 can be an integral structure, so that they can jointly support the lower electrode and also conduct electricity.
[0108] In some embodiments, the upper electrode 117 may fill only the area between the conductive support layers 115 and extend into the area between the first lower electrodes 109, providing support and allowing metal pillars to be formed directly on the conductive support layers 115. The conductive support layers 115 can support the first lower electrodes 109 and also conduct electricity. Simultaneously, this reduces the height of the capacitor structure, lowers the pressure of the upper electrode 117 on the first lower electrodes 109 and the second lower electrodes 110, and mitigates the risk of collapse of the first lower electrodes 109 and the second lower electrodes 110.
[0109] like Figure 21As shown in the embodiments of this disclosure, a semiconductor structure is also proposed. This semiconductor structure may include a substrate 101, on which a plurality of first lower electrodes 109 and a plurality of second lower electrodes 110 are disposed. These first lower electrodes 109 and second lower electrodes 110 may be collectively referred to as lower electrodes. A bottom support layer 102 is located at the bottom of the first lower electrode 109, an intermediate support layer 104 is located in the middle region of the first lower electrode 109, a first conductive support layer 115 is located at the top of the first lower electrode 109, and a second conductive support layer 117 is located on the first conductive support layer 115. The first conductive support layer 115 and the second conductive support layer 117 together form a conductive support layer 119. The bottom support layer 102 and the intermediate support layer 104 are insulating materials, such as silicon nitride. The first conductive support layer 115 is germanium-silicon, and the second conductive support layer 117 is germanium-silicon; since they are made of the same material, the interface resistance can be reduced. A dielectric layer is located between the first conductive support layer 115 and the first lower electrode 109, and a dielectric layer is located between the first conductive support layer 115 and the second lower electrode 110. Thus, the first conductive support layer 115 can support the first lower electrode 109 and the second lower electrode 110. At the same time, since there are metal pillars 118 on the second conductive support layer 117, the signal is transmitted to the first conductive support layer 115 through the metal pillars 118, and then to the capacitor structure. Therefore, the first conductive support layer 115 and the second conductive support layer 117 can also conduct electricity.
[0110] like Figures 21-22 As shown, this disclosure uses the second lower electrode 110 as an example. The second lower electrode 110 may include a main body portion 111 and an extension portion 112. The extension portion 112 is located above the main body portion 111, and in the X direction (horizontal direction), the horizontal width of the extension portion 112 is smaller than the horizontal width of the main body portion 111. Therefore, the spacing between the extension portions 112 is greater than the spacing between the main body pillars 111. At the same time, the first conductive support layer 115 may also be located on the extension portion 112, that is, the conductive support layer 115 covers the extension portion 112, and the sidewall of the first conductive support layer 115 is flush with the sidewall of the extension portion 112. In addition, an upper electrode 116 is also present on the sidewall of the first lower electrode 109, the second lower electrode 110, the extension portion 112, and the sidewall of the first conductive support layer 115. The second conductive support layer 117 covers the first conductive support layer 115, and a portion of the second conductive support layer 117 is also located between the first conductive support layers 115 and between the extensions 112, extending further into the main body portion 111. This allows it to contact the upper electrode 116 on the first conductive support layer 115, the extensions 112, and the main body portion 111, thereby increasing the contact area and reducing the contact resistance. Simultaneously, since the second conductive support layer 117 extends into the main body portion 111, it can provide support for the first lower electrode 109 and the second lower electrode 110.
[0111] like Figures 21-22 As shown in this embodiment, since the height of the extension 112 is substantially the same as the thickness of the intermediate support layer 104, the main body 110 can be guaranteed to have an appropriate height, ensuring the capacitor capacity; it can also reduce the overall height of the capacitor structure, reducing the risk of the lower electrode collapsing. In this embodiment, the conductive support layer 119 covers the extension 112, therefore the thickness of the conductive support layer 119 is greater than the thickness of the intermediate support layer 104. Thus, by increasing the thickness of the conductive support layer 119, both the support effect can be increased and the resistance of the conductive support layer 119 can be reduced.
[0112] like Figure 21 As shown, a dielectric layer 114 (reference) also exists between the upper electrode 116 and the first lower electrode 109. Figure 18 Between the first conductive support layer 115 and the extension 112, there is also a dielectric layer 114 (see reference). Figure 18 The upper electrode 116, the first lower electrode 109, and the dielectric layer 114 can together form a capacitor structure, and the first conductive support layer 115, the extension 112, and the dielectric layer 114 can also together form a capacitor structure, thereby increasing the capacitance.
[0113] It should be noted that, Figure 21 The manufacturing method of the semiconductor structure can be referred to the above description.
[0114] like Figure 23 As shown, this disclosure also proposes an electronic device 100, which may include a semiconductor structure 100, which may refer to... Figure 21 The structure of the semiconductor structure 100 can be manufactured using the method described above. The electronic device 100 may include one or more of the following: for example, a smartphone, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, personal digital assistant (PDA), portable multimedia player (PMP), MPEG-1 audio layer 3 (MP3) player, mobile medical device, camera, home appliance, medical device, Internet of Things (IoT) device, and wearable device. Wearable devices may be accessory type, fabric or clothing type, body-attached type, or implantable circuit type. Accessory-type wearable devices may be, for example, watches, rings, bracelets, anklets, necklaces, glasses, contact lenses, or head-mounted devices (HMDs).
[0115] In summary, the present disclosure provides a semiconductor structure and its manufacturing method. After forming a second sacrificial layer on a substrate, a mask layer is directly formed on the second sacrificial layer. That is, after forming a stack excluding the top support layer (silicon nitride), the etching gas will not laterally etch the second sacrificial layer during the etching of the stack, thereby ensuring that the lower electrode will not connect. As a result, the first and second sacrificial layers can be completely cleaned away in subsequent processes, avoiding the presence of residual first sacrificial layer, which is beneficial for the formation of capacitors.
[0116] Secondly, due to the large aspect ratio and high density of the capacitor holes, the diameter of some holes increases, leading to a larger diameter of the first lower electrode and a smaller spacing between them. Therefore, by reducing the horizontal width of the extensions and increasing the spacing between them, making the spacing between the extensions greater than the spacing between the main bodies, it becomes easier for deposited atoms to enter between the main bodies. This facilitates the formation of the dielectric layer and the upper electrode, ensuring the formation of the capacitor structure and simplifying the manufacturing process.
[0117] Secondly, since the conductive support layer is located on the extension, it can support the lower electrode. Simultaneously, the conductive support layer can also be used for the upper electrode plate, i.e., for power transmission. Because there is a dielectric layer between the conductive support layer and the extension, a capacitor structure can be formed, increasing the capacitance.
[0118] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A method of manufacturing a semiconductor structure, characterized by, Comprising: forming a stack on a substrate; forming a plurality of lower electrodes in the stack, the lower electrodes comprising a main body portion in the stack and an extension portion protruding from the stack; etching the extension portion so that the horizontal width of the extension portion is less than the horizontal width of the main body portion; forming a dielectric layer and a conductive film layer on the stack in sequence, the dielectric layer and the conductive film layer covering the extension portion; etching the conductive film layer to expose the stack and form a plurality of conductive support layers; etching the stack to expose the main body portion; forming a dielectric layer on the main body portion; forming an upper electrode on the dielectric layer.
2. The production method according to claim 1, characterized by The step of forming a stack comprises: forming a bottom support layer on the substrate; forming a first sacrificial layer on the bottom support layer; forming an intermediate support layer on the first sacrificial layer; forming a second sacrificial layer on the intermediate support layer.
3. The production method according to claim 2, characterized by The step of forming the lower electrodes comprises: forming a mask layer on the second sacrificial layer; etching the stack according to the mask layer to form a plurality of capacitor holes in the stack; forming a lower electrode in the capacitor hole; removing part of the second sacrificial layer so that the lower electrode protrudes from the stack.
4. The production method according to claim 3, characterized by The step of removing part of the second sacrificial layer comprises: removing part of the second sacrificial layer by dry etching to form the extension portion; wherein the height of the extension portion is substantially the same as the thickness of the intermediate support layer.
5. The production method according to claim 3, wherein The plurality of lower electrodes are formed by filling the capacitor hole with a lower electrode material; the lower electrodes comprise: a plurality of first lower electrodes; a plurality of second lower electrodes; wherein the spacing between adjacent first lower electrodes is less than the spacing between adjacent second lower electrodes.
6. The production method according to any one of claims 1 to 5, characterized by, The step of forming the conductive support layers comprises: removing the conductive film layer between the extension portions to expose the dielectric layer on the sidewall of the extension portion and expose the stack; removing the dielectric layer on the sidewall of the extension portion to expose the sidewall of the extension portion.
7. The production method according to claim 6, wherein The step of forming the conductive support layers comprises: removing part of the conductive film layer between adjacent first lower electrodes to expose the second sacrificial layer between adjacent first lower electrodes.
8. The production method according to claim 1, wherein The step of forming the upper electrode comprises: depositing an upper electrode material on the dielectric layer, the upper electrode material also being on the conductive support layer; wherein the upper electrode material and the conductive support layer are separated by the dielectric layer.
9. The production method according to any one of claims 1 to 5, characterized by, Further comprising forming an upper plate on the conductive support layer, the upper plate being in contact with the upper electrode on the conductive support layer.
10. The method of claim 9, wherein the method further comprises: The upper plate also extends between adjacent main body portions to be in contact with the upper electrode between the main body portions.
11. A semiconductor structure formed using the method of any of claims 1-10. Comprising: a substrate; a plurality of lower electrodes on the substrate, the lower electrodes comprising a main body portion and an extension portion, the horizontal width of the extension portion being less than the horizontal width of the main body portion; an intermediate support layer on the middle region of the main body portion; a conductive support layer on the extension portion, the conductive support layer and the extension portion being separated by a dielectric layer; a conductive pillar on the conductive support layer.
12. The semiconductor structure of claim 11, wherein, The medium layer is also located on the main body part, and an upper electrode is also arranged on the medium layer.
13. The semiconductor structure of claim 11, wherein, The conductive support layer extends to between the lower electrodes and is in contact with the upper electrode located between the lower electrodes.
14. The semiconductor structure of claim 11, wherein, The conductive support layer protrudes from the upper electrode.
15. The semiconductor structure of claim 11, wherein, The thickness of the conductive support layer is greater than the thickness of the intermediate support layer.