Capacitor structure and forming method thereof

Abstract

The invention discloses a capacitor structure and a forming method thereof, and the capacitor structure comprises a substrate which comprises a capacitor region; a plurality of first grooves located in the capacitor region; and a plurality of second grooves located in the capacitor region, wherein the first grooves and the second grooves are arranged in a crossed manner. A plurality of first grooves and a plurality of second grooves, which are different in arrangement direction and extension direction, are arranged in a crossed manner, so that a first conductive plug and a second conductive plug can guide current to the first grooves extending in the second direction and the second grooves extending in the first direction at the same time, and therefore, a current path can be shortened; therefore, the equivalent series resistance of the capacitor structure is reduced. The plurality of first polar plate wiring regions can be inserted in the capacitor structure in a discrete manner, so that large-area overall laying is avoided, the area of a forming region of the first groove and the second groove is increased, and the capacitance density of the capacitor structure is increased. In addition, stress generated by the capacitor structures which are arranged in a crossed mode is uniform, and the problem of wafer warping caused by uneven stress can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a capacitor structure and a method for forming the same. Background Technology

[0002] In the development of very large-scale integrated circuits (VLSI), as operating frequencies and circuit power continuously increase while operating voltages and noise margins decrease, higher-density capacitors are needed to reduce noise ripple and ensure power integrity. Compared to traditional ceramic capacitors, deep trench capacitors (DTCs) offer better integration characteristics and higher capacitance density, making them more beneficial for improving system power integrity. Therefore, integrating DTCs into silicon interposers is an inevitable trend. Simultaneously, due to the increasing demands for high-frequency performance in integrated circuits, the equivalent series resistance (ESR) of DTCs needs to be significantly lower to meet the high bandwidth requirements of integrated circuits.

[0003] However, existing deep trench capacitors still have many problems. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a capacitor structure and a method for forming the same, which improves capacitance density and reduces equivalent series resistance.

[0005] To address the aforementioned problems, the present invention provides a capacitor structure, comprising: a substrate, the substrate including a capacitor region, the capacitor region including a plurality of first electrode connection regions and a plurality of second electrode connection regions; a plurality of first trenches arranged parallel to each other along a first direction within the capacitor region, the first trenches extending along a second direction, and a portion of the first trenches avoiding the first electrode connection regions; a plurality of second trenches arranged parallel to each other along the second direction within the capacitor region, the second trenches extending along the first direction, and a portion of the second trenches avoiding the first electrode connection regions; the plurality of first trenches and the plurality of second trenches being arranged intersectingly, and the region enclosed by the plurality of first trenches and the plurality of second trenches intersectingly. The domain comprises several second electrode plate interconnection areas; at least one first electrode plate layer, at least one insulating layer, and at least one second electrode plate layer are formed on the substrate; wherein the first electrode plate layer and the second electrode plate layer are stacked alternately, and the insulating layer is located between adjacent first electrode plate layers and second electrode plate layers; the first electrode plate layer, the second electrode plate layer, and the insulating layer also fill the first trench and the second trench; several first conductive plugs are located on each first electrode plate interconnection area, and the first conductive plugs are electrically connected to the at least one first electrode plate layer; second conductive plugs are located on each second electrode plate interconnection area, and the second conductive plugs are electrically connected to the at least one second electrode plate layer.

[0006] Optionally, the plurality of first electrode plate connection regions include: a central electrode plate connection region and a plurality of edge electrode plate connection regions, wherein the plurality of edge electrode plate connection regions are evenly distributed around the periphery of the central electrode plate connection region.

[0007] Optionally, the first direction is perpendicular to the second direction.

[0008] Optionally, the first direction is not perpendicular to the second direction.

[0009] Optionally, the number of layers in the first electrode layer is the same as the number of layers in the second electrode layer.

[0010] Optionally, the number of layers in the first electrode layer is different from the number of layers in the second electrode layer.

[0011] Optionally, the width of the first trench is 0.1 micrometer to 20 micrometers; the length of the first trench is 0.5 micrometer to 20 micrometers; the depth of the first trench is 3 micrometers to 30 micrometers; and the spacing between adjacent first trenches along the first direction is 0.1 micrometer to 5 micrometers.

[0012] Optionally, the width of the second trench is 0.1 micrometer to 20 micrometers; the length of the second trench is 0.5 micrometer to 20 micrometers; the depth of the second trench is 3 micrometers to 30 micrometers; and the spacing between adjacent second trenches along the second direction is 0.1 micrometer to 5 micrometers.

[0013] Accordingly, the present invention also provides a method for forming a capacitor structure, comprising: providing a substrate, the substrate including a capacitor region; selecting a plurality of first electrode connection regions on the capacitor region; forming a plurality of first trenches arranged parallel to each other along a first direction within the capacitor region, the first trenches extending along a second direction, and a portion of the first trenches avoiding the first electrode connection regions; forming a plurality of second trenches arranged parallel to each other along the second direction within the capacitor region, the second trenches extending along the first direction, a portion of the second trenches avoiding the first electrode connection regions, the plurality of first trenches and the plurality of second trenches being arranged intersectingly, and the plurality of first trenches and the plurality of second trenches intersecting and enclosing each other. The region is a plurality of second electrode plate interconnection areas; at least one first electrode plate layer, at least one insulating layer, and at least one second electrode plate layer are formed on the substrate; wherein the first electrode plate layer and the second electrode plate layer are stacked alternately, and the insulating layer is located between adjacent first electrode plate layers and second electrode plate layers; the first electrode plate layer, the second electrode plate layer, and the insulating layer also fill the first trench and the second trench; a plurality of first conductive plugs are formed on each of the first electrode plate interconnection areas, and the first conductive plugs are electrically connected to the at least one first electrode plate layer; a second conductive plug is formed on each of the second electrode plate interconnection areas, and the second conductive plugs are electrically connected to the at least one second electrode plate layer.

[0014] Optionally, the plurality of first electrode plate connection regions include: a central electrode plate connection region and a plurality of edge electrode plate connection regions, wherein the plurality of edge electrode plate connection regions are evenly distributed around the periphery of the central electrode plate connection region.

[0015] Optionally, the first direction is perpendicular to the second direction.

[0016] Optionally, the first direction is not perpendicular to the second direction.

[0017] Optionally, the number of layers in the first electrode layer is the same as the number of layers in the second electrode layer.

[0018] Optionally, the number of layers in the first electrode layer is different from the number of layers in the second electrode layer.

[0019] Optionally, the width of the first trench is 0.1 micrometer to 20 micrometers; the length of the first trench is 0.5 micrometer to 20 micrometers; the depth of the first trench is 3 micrometers to 30 micrometers; and the spacing between adjacent first trenches along the first direction is 0.1 micrometer to 5 micrometers.

[0020] Optionally, the width of the second trench is 0.1 micrometer to 20 micrometers; the length of the second trench is 0.5 micrometer to 20 micrometers; the depth of the second trench is 3 micrometers to 30 micrometers; and the spacing between adjacent second trenches along the second direction is 0.1 micrometer to 5 micrometers.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the capacitor structure of this invention, by arranging several first trenches and several second trenches with different arrangement and extension directions in a cross-shaped manner, both the first conductive plug and the second conductive plug can simultaneously guide current into the first trench extending along the second direction and the second trench extending along the first direction, thereby shortening the current path and reducing the equivalent series resistance of the capacitor structure. Since the first conductive plug can simultaneously guide current into the first trench extending along the second direction and the second trench extending along the first direction, several first electrode connection areas can be discretely interspersed, avoiding large-area integral laying, thus increasing the area of ​​the first trench and the second trench formation region, thereby increasing the capacitance density of the capacitor structure. Furthermore, the stress generated by the cross-shaped capacitor structure is uniform, which can effectively reduce wafer warpage caused by uneven stress.

[0023] Furthermore, the plurality of first electrode plate connection regions include: a central electrode plate connection region and a plurality of edge electrode plate connection regions, wherein the plurality of edge electrode plate connection regions are evenly distributed around the periphery of the central electrode plate connection region. By evenly distributing each of the first electrode plate connection regions at various positions of the capacitor structure, the amount of reduction in current path in each region of the capacitor structure can be balanced, thereby ensuring an increase in the overall amount of reduction in current path of the capacitor structure, and further reducing the equivalent series resistance of the capacitor structure.

[0024] In the capacitor structure formation method of this invention, a plurality of first trenches and a plurality of second trenches with different arrangement and extension directions are arranged in a cross pattern. This allows both the first conductive plug and the second conductive plug to simultaneously guide current into the first trench extending along the second direction and the second trench extending along the first direction, thereby shortening the current path and reducing the equivalent series resistance of the capacitor structure. Since the first conductive plug can simultaneously guide current into the first trench extending along the second direction and the second trench extending along the first direction, a plurality of first electrode connection areas can be discretely interspersed, avoiding large-area integral laying. This increases the area of ​​the formation region of the first trench and the second trench, thereby increasing the capacitance density of the capacitor structure. Furthermore, the stress generated by the cross-arranged capacitor structure is uniform, effectively reducing wafer warpage caused by uneven stress.

[0025] Furthermore, the plurality of first electrode plate connection regions include: a central electrode plate connection region and a plurality of edge electrode plate connection regions, wherein the plurality of edge electrode plate connection regions are evenly distributed around the periphery of the central electrode plate connection region. By evenly distributing each of the first electrode plate connection regions at various positions of the capacitor structure, the amount of reduction in current path in each region of the capacitor structure can be balanced, thereby ensuring an increase in the overall amount of reduction in current path of the capacitor structure, and further reducing the equivalent series resistance of the capacitor structure. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the arrangement of one group of trenches in a capacitor structure;

[0027] Figure 2 This is a schematic diagram of the arrangement of the four sets of capacitor trenches in the capacitor structure.

[0028] Figure 3 This is a schematic diagram of a capacitor structure.

[0029] Figure 4 This is a schematic diagram of another capacitor structure;

[0030] Figure 5 This is a top view of the capacitor structure in this embodiment of the invention, omitting the first electrode layer, the insulating layer, and the second electrode layer;

[0031] Figure 6 This is a schematic diagram of the structure of the first electrode layer, the insulating layer, and the second electrode layer in a single trench of the capacitor structure in an embodiment of the present invention;

[0032] Figure 7 This is a schematic diagram of the distribution structure of the first and second trenches of the capacitor structure in another embodiment of the present invention;

[0033] Figure 8 This is a schematic diagram of the structure of the first electrode layer, the insulating layer, and the second electrode layer in a single trench of the capacitor structure in another embodiment of the present invention;

[0034] Figure 9 This is a schematic diagram of the structure of the first electrode layer, the insulating layer, and the second electrode layer in a single trench of the capacitor structure in another embodiment of the present invention. Detailed Implementation

[0035] As described in the background section, existing deep trench capacitors still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic diagram of the arrangement of one group of trenches in a capacitor structure; Figure 2 This is a schematic diagram of the arrangement of the four sets of capacitor trenches in the capacitor structure. Figure 3 This is a schematic diagram of a capacitor structure. Figure 4 This is a schematic diagram of another type of capacitor structure.

[0037] For deep trench capacitors, the current mainstream technology typically involves rectangular trenches 100 arranged in the same direction (e.g., Figure 1 As shown), when fabricating this type of deep trench capacitor on a wafer, it is often necessary to arrange four identical capacitor trench groups along the X and Y directions (e.g., Figure 2 (as shown), to reduce wafer warping caused by trench stress.

[0038] However, this arrangement of deep trench capacitors presents a trade-off between low equivalent series resistance and high capacitance density: since the arrangement of the capacitor trench group includes both X and Y directions, the arrangement of the conductive plugs 101 (Contact) connecting the metal leads also needs to ensure that current flows in both the X and Y directions simultaneously. Figure 3 The direction of the current arrows shown follows the direction of each trench, which will not cause the current path to be too long; otherwise, the current path will be too long. Figure 4 The direction of the current arrow shown is perpendicular to the direction of some trench extensions, which can cause the current path to be too long, resulting in an excessively high equivalent series resistance and thus a reduction in circuit bandwidth. However, Figure 3 In order to reduce the current path, the deep trench capacitor shown needs to have more conductive plugs 101, which requires a larger area for the distribution of conductive plugs 101, thereby reducing the capacitance density of the deep trench capacitor.

[0039] Based on this, the present invention provides a capacitor structure and its formation method. By arranging a plurality of first trenches and a plurality of second trenches with different arrangement and extension directions in a cross-shaped manner, both the first conductive plug and the second conductive plug can simultaneously guide current into the first trench extending along the second direction and the second trench extending along the first direction, thereby shortening the current path and reducing the equivalent series resistance of the capacitor structure. Since the first conductive plug can simultaneously guide current into the first trench extending along the second direction and the second trench extending along the first direction, the plurality of first electrode connection areas can be discretely interspersed, avoiding large-area integral laying, thereby increasing the area of ​​the formation region of the first trench and the second trench, thereby increasing the capacitance density of the capacitor structure. In addition, the stress generated by the cross-shaped arrangement of the capacitor structure is uniform, which can effectively reduce the wafer warpage problem caused by uneven stress.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figure 5 This is a top view of the capacitor structure in this embodiment of the invention, omitting the first electrode layer, the insulating layer, and the second electrode layer; Figure 6 This is a schematic diagram of the structure of the first electrode layer, the insulating layer, and the second electrode layer in a single trench of the capacitor structure in an embodiment of the present invention; Figure 7 This is a schematic diagram of the distribution structure of the first and second trenches of the capacitor structure in another embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of the first electrode layer, the insulating layer, and the second electrode layer in a single trench of the capacitor structure in another embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of the first electrode layer, the insulating layer, and the second electrode layer in a single trench of the capacitor structure in another embodiment of the present invention.

[0042] Please refer to Figure 5 and Figure 6A capacitor structure includes: a substrate 200, the substrate 200 including a capacitor region 201, the capacitor region 201 including a plurality of first electrode connection regions 202 and a plurality of second electrode connection regions 203; a plurality of first trenches 204 arranged parallel to each other along a first direction X within the capacitor region 201, the first trenches 204 extending along a second direction Y, and a portion of the first trenches 204 avoiding the first electrode connection regions 202; a plurality of second trenches 205 arranged parallel to each other along the second direction Y within the capacitor region 201, the second trenches 205 extending along the first direction X, a portion of the second trenches 205 avoiding the first electrode connection regions 202, the plurality of first trenches 204 and the plurality of second trenches 205 being arranged intersectingly, and the area enclosed by the intersection of the plurality of first trenches 204 and the plurality of second trenches 205 being a plurality of second electrode connection regions 202. The electrode connection area 203 includes at least one first electrode layer 206, at least one insulating layer 207, and at least one second electrode layer 208 located on the substrate 200; wherein the first electrode layer 206 and the second electrode layer 208 are alternately stacked, and the insulating layer 207 is located between adjacent first electrode layers 206 and second electrode layers 208; the first electrode layer 206, the second electrode layer 208, and the insulating layer 207 also fill the first trench 204 and the second trench 205; a plurality of first conductive plugs 209 are located on each of the first electrode connection areas 202, and the first conductive plugs 209 are electrically connected to the at least one first electrode layer 206; and second conductive plugs 210 are located on each of the second electrode connection areas 203, and the second conductive plugs 210 are electrically connected to the at least one second electrode layer 208.

[0043] By arranging a plurality of first trenches 204 and a plurality of second trenches 205 with different arrangement and extension directions in a cross pattern, the first conductive plug 209 and the second conductive plug 210 can simultaneously guide current (e.g., to the first trench 204 extending along the second direction Y and the second trench 205 extending along the first direction X) to the first trench 204 extending along the second direction Y and the second trench 205 extending along the first direction X. Figure 5 (As indicated by the arrows in the diagram), this shortens the current path, thereby reducing the equivalent series resistance of the capacitor structure. Since the first conductive plug 209 can simultaneously guide current to both the first trench 204 extending along the second direction Y and the second trench 205 extending along the first direction X, several first electrode connection areas 202 can be discretely interspersed within them, avoiding large-area integral laying. This increases the area of ​​the formation regions of the first trench 204 and the second trench 205, thereby increasing the capacitance density of the capacitor structure. Furthermore, the uniform stress generated by the cross-arranged capacitor structure effectively reduces wafer warpage caused by uneven stress.

[0044] Please continue to refer to this. Figure 6 In this embodiment, a first electrode layer 206, a second electrode layer 208, and an insulating layer 207 are used as an example. The first electrode layer 206, located at the bottom layer, is formed on the bottom surface and sidewalls of the first trench 204 and the second trench 205. The subsequently formed first electrode layer 206, insulating layer 207, and second electrode layer 208 are stacked and filled in the first trench 204 and the second trench 205 based on the morphology of the bottom first electrode layer 206.

[0045] Please continue to refer to this. Figure 5 In this embodiment, the plurality of first electrode plate connection regions 202 include: a central electrode plate connection region and a plurality of edge electrode plate connection regions, wherein the plurality of edge electrode plate connection regions are evenly distributed around the periphery of the central electrode plate connection region. By evenly distributing each of the first electrode plate connection regions 202 at various positions of the capacitor structure, the amount of reduction in current path in each region of the capacitor structure can be balanced, thereby ensuring an increase in the overall reduction in current path of the capacitor structure, and further reducing the equivalent series resistance of the capacitor structure.

[0046] Please continue to refer to this. Figure 5 In this embodiment, five first electrode plate connection areas 202 are taken as an example.

[0047] Please continue to refer to this. Figure 3 and Figure 5 Assume that the width of each groove is 'a', and the distance between two adjacent grooves is 'a'. Figure 3 The trench shown has a length dimension of 9a, and the area occupied by the conductive plugs arranged along the X and Y directions has a width dimension of 2a.

[0048] Under the above conditions, the regulations are as follows Figure 3 and Figure 5 The individual capacitor structure units have equal areas (21a*21a), equal trench depths, and the same materials and thicknesses for the electrode layer and insulating layer 207. Therefore, to compare the capacitance density of the two capacitor structures, it is only necessary to compare the total perimeter of all trenches.

[0049] Figure 3 In the capacitor structure shown, the trench length is 9a, so the total perimeter of the trench in this structure is (a+9a)*2*5*4=400a; Figure 5 In the capacitor structure shown, the trench length is 21a, so the total perimeter of the trench in this structure is 21a*4+4a*80+12a*5=464a.

[0050] Figure 5The capacitance density of the capacitor structure shown is compared to Figure 3 The capacitance density of the capacitor structure shown is increased by 16%. If the aspect ratio of the trench in the example is larger, then for the same area of ​​a single capacitor unit, Figure 5 The capacitor structure shown has a higher rate of increase in capacitance density.

[0051] In this embodiment, the width of the first trench 204 is 0.1 micrometers to 20 micrometers; the length of the first trench 204 is 0.5 micrometers to 20 micrometers; the depth of the first trench 204 is 3 micrometers to 30 micrometers; and the spacing between adjacent first trenches 204 along the first direction X is 0.1 micrometers to 5 micrometers.

[0052] In this embodiment, the width of the second trench 205 is 0.1 micrometers to 20 micrometers; the length of the second trench 205 is 0.5 micrometers to 20 micrometers; the depth of the second trench 205 is 3 micrometers to 30 micrometers; and the spacing between adjacent second trenches 205 along the second direction Y is 0.1 micrometers to 5 micrometers.

[0053] Please continue to refer to this. Figure 5 In this embodiment, the first direction X is perpendicular to the second direction Y.

[0054] Please refer to Figure 7 In other embodiments, the first direction X and the second direction Y may not be perpendicular.

[0055] In this embodiment, the number of layers of the first electrode layer 206 is the same as the number of layers of the second electrode layer 208.

[0056] Please refer to Figure 8 In other embodiments, the number of layers of the first electrode layer 206, the second electrode layer 208, and the insulating layer 207 may be greater than one.

[0057] In one specific embodiment, the first electrode layer 206, the second electrode layer 208, and the insulating layer 207 each have two layers. The two layers of the first electrode layer 206 are electrically connected by the first conductive plug 209, and the two layers of the second electrode layer 208 are electrically connected by the second conductive plug 210. This forms a parallel structure of three capacitors, and the parallel connection between the capacitors can further increase the capacitance density.

[0058] Please refer to Figure 9 In other embodiments, the number of layers of the first electrode layer 206 may be different from the number of layers of the second electrode layer 208.

[0059] In one specific embodiment, the first electrode layer 206 and the insulating layer 207 each have two layers, and the second electrode layer 208 has one layer. The two layers of the first electrode layer 206 are electrically connected by the first conductive plug 209, and the one layer of the second electrode layer 208 is electrically connected by the second conductive plug 210.

[0060] Accordingly, the present invention also provides a method for forming a capacitor structure; please refer to the following: Figure 5 and Figure 6 The method includes: providing a substrate 200, the substrate 200 including a capacitor region 201; selecting a plurality of first electrode connection regions 202 on the capacitor region 201; forming a plurality of first trenches 204 arranged parallel to a first direction X in the capacitor region 201, the first trenches 204 extending along a second direction Y, and a portion of the first trenches 204 avoiding the first electrode connection regions 202; forming a plurality of second trenches 205 arranged parallel to the second direction Y in the capacitor region 201, the second trenches 205 extending along the first direction X, a portion of the second trenches 205 avoiding the first electrode connection regions 202, the plurality of first trenches 204 and the plurality of second trenches 205 being arranged intersectingly, and the area enclosed by the plurality of first trenches 204 and the plurality of second trenches 205 being a plurality of second electrode connection regions 203; At least one first electrode layer 206, at least one insulating layer 207, and at least one second electrode layer 208 are formed on the substrate 200; wherein the first electrode layer 206 and the second electrode layer 208 are stacked alternately, and the insulating layer 207 is located between adjacent first electrode layers 206 and second electrode layers 208; the first electrode layer 206, the second electrode layer 208, and the insulating layer 207 also fill the first trench 204 and the second trench 205; a plurality of first conductive plugs 209 are formed on each of the first electrode connection areas 202, and the first conductive plugs 209 are electrically connected to the at least one first electrode layer 206; and second conductive plugs 210 are formed on each of the second electrode connection areas 203, and the second conductive plugs 210 are electrically connected to the at least one second electrode layer 208.

[0061] By arranging several first trenches 204 and several second trenches 205 with different arrangement and extension directions in a cross pattern, both the first conductive plug 209 and the second conductive plug 210 can simultaneously guide current to the first trench 204 extending along the second direction Y and the second trench 205 extending along the first direction X, thereby shortening the current path and reducing the equivalent series resistance of the capacitor structure. Since the first conductive plug 209 can simultaneously guide current to the first trench 204 extending along the second direction Y and the second trench 205 extending along the first direction X, several first electrode connection areas 202 can be discretely interspersed, avoiding large-area integral laying, thereby increasing the area of ​​the formation region of the first trench 204 and the second trench 205, thus increasing the capacitance density of the capacitor structure. Furthermore, the cross-arranged capacitor structure generates uniform stress, effectively reducing wafer warpage caused by uneven stress.

[0062] In this embodiment, the plurality of first electrode plate connection regions 202 include: a central electrode plate connection region and a plurality of edge electrode plate connection regions, wherein the plurality of edge electrode plate connection regions are evenly distributed around the periphery of the central electrode plate connection region. By evenly distributing each of the first electrode plate connection regions 202 at various positions of the capacitor structure, the amount of reduction in current path in various regions of the capacitor structure can be balanced, thereby ensuring an increase in the overall amount of reduction in current path of the capacitor structure, and further reducing the equivalent series resistance of the capacitor structure.

[0063] Please continue to refer to this. Figure 5 In this embodiment, the first direction X is perpendicular to the second direction Y.

[0064] Please continue to refer to this. Figure 7 In other embodiments, the first direction X and the second direction Y may not be perpendicular.

[0065] Please continue to refer to this. Figure 6 and Figure 8 In this embodiment, the number of layers of the first electrode layer 206 is the same as the number of layers of the second electrode layer 208.

[0066] Please continue to refer to this. Figure 9 In other embodiments, the number of layers of the first electrode layer 206 may be different from the number of layers of the second electrode layer 208.

[0067] In this embodiment, the width of the first trench 204 is 0.1 micrometers to 20 micrometers; the length of the first trench 204 is 0.5 micrometers to 20 micrometers; the depth of the first trench 204 is 3 micrometers to 30 micrometers; and the spacing between adjacent first trenches 204 along the first direction X is 0.1 micrometers to 5 micrometers.

[0068] In this embodiment, the width of the second trench 205 is 0.1 micrometers to 20 micrometers; the length of the second trench 205 is 0.5 micrometers to 20 micrometers; the depth of the second trench 205 is 3 micrometers to 30 micrometers; and the spacing between adjacent second trenches 205 along the second direction Y is 0.1 micrometers to 5 micrometers.

[0069] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A capacitive structure, characterized by, The application relates to a capacitor, comprising: a substrate, wherein the substrate comprises a capacitor region, and the capacitor region comprises a plurality of first-plate connecting regions and a plurality of second-plate connecting regions; a plurality of first grooves arranged in parallel along a first direction in the capacitor region, wherein the first grooves extend along a second direction, and part of the first grooves avoid the first-plate connecting regions; a plurality of second grooves arranged in parallel along the second direction in the capacitor region, wherein the second grooves extend along the first direction, and part of the second grooves avoid the first-plate connecting regions, the first grooves and the second grooves are arranged in cross, and the region surrounded by the first grooves and the second grooves is the second-plate connecting region; at least one first-plate layer, at least one insulating layer and at least one second-plate layer on the substrate, wherein the first-plate layer and the second-plate layer are alternately stacked, and the insulating layer is arranged between the adjacent first-plate layer and second-plate layer; the first-plate layer, the second-plate layer and the insulating layer also fill into the first grooves and the second grooves; a plurality of first conductive plugs on each first-plate connecting region, wherein the first conductive plugs are electrically connected with the at least one first-plate layer; a plurality of second conductive plugs on each second-plate connecting region, wherein the second conductive plugs are electrically connected with the at least one second-plate layer.

2. The capacitor structure of claim 1, wherein, The plurality of first-plate connecting regions comprises a central-plate connecting region and a plurality of edge-plate connecting regions, and the plurality of edge-plate connecting regions are uniformly distributed on the periphery of the central-plate connecting region.

3. The capacitor structure of claim 1, wherein, The first direction is perpendicular to the second direction.

4. The capacitor structure of claim 1, wherein, The first direction is not perpendicular to the second direction.

5. The capacitor structure of claim 1, wherein, The number of layers of the first-plate layer is the same as that of the second-plate layer.

6. The capacitor structure of claim 1, wherein, The number of layers of the first-plate layer is not the same as that of the second-plate layer.

7. The capacitor structure of claim 1, wherein, The width of the first grooves is 0.1-20 microns, the length of the first grooves is 0.5-20 microns, the depth of the first grooves is 3-30 microns, and the distance between the adjacent first grooves along the first direction is 0.1-5 microns.

8. The capacitor structure of claim 1, wherein, The width of the second grooves is 0.1-20 microns, the length of the second grooves is 0.5-20 microns, the depth of the second grooves is 3-30 microns, and the distance between the adjacent second grooves along the second direction is 0.1-5 microns.

9. A method of forming a capacitor structure, comprising: The application also relates to a capacitor manufacturing method, comprising the following steps: providing a substrate, wherein the substrate comprises a capacitor region; selecting a plurality of first-plate connecting regions on the capacitor region; forming a plurality of first grooves arranged in parallel along a first direction in the capacitor region, wherein the first grooves extend along a second direction, and part of the first grooves avoid the first-plate connecting regions; A plurality of second grooves are formed in the capacitor region, the second grooves are parallel to the second direction, the second grooves extend along the first direction, and some of the second grooves avoid the first plate connection regions, the first grooves and the second grooves are arranged in a cross manner, and the regions enclosed by the first grooves and the second grooves are the second plate connection regions; At least one first plate layer, at least one insulating layer, and at least one second plate layer are formed on the substrate, wherein The first plate layer and the second plate layer are alternately stacked, and the insulating layer is between the adjacent first plate layer and the second plate layer; The first plate layer, the second plate layer, and the insulating layer also fill the first grooves and the second grooves; A plurality of first conductive plugs are formed on each first plate connection region, and the first conductive plugs are electrically connected to the at least one first plate layer; A second conductive plug is formed on each second plate connection region, and the second conductive plug is electrically connected to the at least one second plate layer.

10. The method for forming the capacitor structure as described in claim 9, characterized in that, The first plate connection regions include a center plate connection region and a plurality of edge plate connection regions, and the edge plate connection regions are uniformly distributed on the periphery of the center plate connection region.

11. The method for forming the capacitor structure as described in claim 9, characterized in that, The first direction is perpendicular to the second direction.

12. The method for forming the capacitor structure as described in claim 9, characterized in that, The first direction is not perpendicular to the second direction.

13. The method for forming the capacitor structure as described in claim 9, characterized in that, The number of layers of the first plate layer is the same as the number of layers of the second plate layer.

14. The method for forming the capacitor structure as described in claim 9, characterized in that, The number of layers of the first plate layer is not the same as the number of layers of the second plate layer.

15. The method for forming the capacitor structure as described in claim 9, characterized in that, The width of the first groove is 0.1-20 microns, the length of the first groove is 0.5-20 microns, the depth of the first groove is 3-30 microns, and the distance between adjacent first grooves along the first direction is 0.1-5 microns.

16. The method for forming the capacitor structure as described in claim 9, characterized in that, The width of the second groove is 0.1-20 microns, the length of the second groove is 0.5-20 microns, the depth of the second groove is 3-30 microns, and the distance between adjacent second grooves along the second direction is 0.1-5 microns.

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