Boost converter and its transient response circuit, control method

Abstract

The application discloses a boost converter and a transient response circuit and a control method thereof, relates to the technical field of switching power supplies, and comprises a voltage detection circuit and a control circuit. The application comprises the voltage detection circuit and the control circuit. The voltage detection circuit can monitor abnormal drop or overshoot of an output voltage in real time and immediately generates a level signal. The control circuit responds to the signal, modulates a reference voltage, and provides a "lead" or "lag" correction amount for a feedback control circuit, thereby effectively compressing system response delay and accelerating an output voltage recovery process. The application improves transient response speed and accelerates the recovery process of the system without changing the original bandwidth and phase margin of the main loop, and solves the contradiction between stability and fast transient response of the traditional boost converter caused by the right half plane zero point limitation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of switching power supply, and particularly to a boost converter and a transient response circuit and a control method thereof. BACKGROUND

[0002] The boost converter faces inherent contradiction in ensuring system stability and control performance due to its inherent right-half-plane zero (RHPZ). The existence of RHPZ makes the achievable bandwidth usually less than one fifth to one tenth of the RHPZ frequency, limiting the rapid response capability of the system. SUMMARY

[0003] The main purpose of the present application is to provide a boost converter and a transient response circuit and a control method thereof, aiming at solving the technical problem that the conventional boost converter cannot improve the load transient response characteristic by increasing the loop bandwidth due to the limitation of the right-half-plane zero.

[0004] To achieve the above-mentioned purpose, the present application provides a transient response circuit of a boost converter, the boost converter comprising a feedback control circuit, the feedback control circuit being configured to adjust an output voltage of the boost converter according to a comparison result of the output voltage of the boost converter and a reference voltage, the transient response circuit comprising:

[0005] a voltage detection circuit, an input end of which is electrically connected to an output end of the boost converter, and configured to generate a corresponding level signal when detecting that the output voltage of the boost converter is lower than a first threshold value or higher than a second threshold value;

[0006] a control circuit, an input end of which is electrically connected to an output end of the voltage detection circuit, and an output end of which is electrically connected to a reference input end of the feedback control circuit, and configured to modulate a reference voltage input to the feedback control circuit in response to the level signal output by the voltage detection circuit, so as to reduce the time for the feedback control circuit to adjust the output voltage.

[0007] In an embodiment, the voltage detection circuit comprises:

[0008] a first comparator having a non-inverting input end and an inverting input end, the non-inverting input end of the first comparator being connected to the first threshold value, and the inverting input end of the first comparator being connected to the output voltage, and configured to output a first detection signal when detecting that the output voltage is lower than the first threshold value;

[0009] a second comparator having a non-inverting input end and an inverting input end, the non-inverting input end of the second comparator being connected to the output voltage, and the inverting input end of the second comparator being connected to the second threshold value, and configured to output a second detection signal when detecting that the output voltage is higher than the second threshold value;

[0010] a first trigger circuit, having an input end electrically connected with the first comparator and the second comparator, and an output end electrically connected with the control end of the control circuit, for receiving and generating a corresponding level signal according to the first detection signal or the second detection signal.

[0011] In an embodiment, the control circuit comprises:

[0012] a step signal generating circuit, having a control end electrically connected with the output end of the voltage detecting circuit, for generating a corresponding step signal in response to the level signal output by the voltage detecting circuit.

[0013] a coupling circuit, having one end electrically connected with the output end of the step signal generating circuit, and another end electrically connected with the reference input end of the feedback control circuit, for coupling the step signal output by the step signal generating circuit to the reference voltage input to the feedback control circuit.

[0014] In an embodiment, the step signal generating circuit comprises:

[0015] a mirror current source, having a reference current end and a mirror output end, the reference current end being connected to ground through the current source, and the mirror output end being connected to ground through a first resistor; the current of the mirror output end being the same as that of the reference current end;

[0016] a first switch tube, having an input end electrically connected with the reference current end, an output end electrically connected with the current source, and a control end electrically connected with the output end of the voltage detecting circuit, for turning on or off the connection between the reference current end and the current source in response to the level signal output by the voltage detecting circuit.

[0017] wherein the mirror output end is electrically connected with the coupling circuit, when the first switch tube is turned on, the mirror current source works and generates a first step signal on the first resistor, which is coupled to the reference input end of the feedback control circuit through the coupling circuit; when the first switch tube is turned off, the mirror current source stops working, and the first resistor discharges to generate a second step signal, which is coupled to the reference input end of the feedback control circuit through the coupling circuit.

[0018] In an embodiment, the coupling circuit comprises:

[0019] a first capacitor, connected in series between the output end of the step signal generating circuit and the reference input end of the feedback control circuit, for coupling the step signal output by the step signal generating circuit to the reference input end of the feedback control circuit.

[0020] a second capacitor, having one end electrically connected with the reference input end of the feedback control circuit, and another end connected to ground.

[0021] a second resistor, one end of which is electrically connected to the reference input end of the feedback control circuit, and the other end of which is electrically connected to the original reference voltage;

[0022] The second capacitor and the second resistor form an RC filter network for restoring the voltage at the reference input end of the feedback control circuit to the original reference voltage.

[0023] In an embodiment, the voltage boost converter further comprises a clock signal, and the transient response circuit further comprises:

[0024] a shielding circuit, an input end of which is electrically connected to the output end of the voltage detection circuit and the clock signal, and an output end of which is electrically connected to the controlled end of the voltage detection circuit, for inhibiting the voltage detection circuit from generating a level signal again within a preset clock signal in response to the level signal output by the voltage detection circuit.

[0025] In an embodiment, the voltage detection circuit further comprises a first logic gate circuit, and the shielding circuit comprises:

[0026] a pulse generation circuit, an input end of which is electrically connected to the output end of the voltage detection circuit, for receiving the level signal output by the voltage detection circuit and generating a pulse signal;

[0027] a timing circuit, an input end of which is electrically connected to the clock signal, and an output end of which is electrically connected to the controlled end of the logic gate circuit, the timing circuit being configured to receive the clock signal to perform timing, and output an inhibition signal to the first logic gate circuit during the timing to block the voltage detection circuit from generating the level signal logic gate circuit, and output an enabling signal to the logic gate circuit after the timing ends to allow the voltage detection circuit to generate the level signal;

[0028] wherein the timing circuit has a reset end, the reset end being electrically connected to the output end of the pulse generation circuit, and the timing circuit being further configured to restart the timing when the pulse signal output by the pulse generation circuit is received.

[0029] In an embodiment, the pulse generation circuit comprises:

[0030] a first one-shot circuit, an input end of which is electrically connected to the output end of the voltage detection circuit, for outputting a first pulse signal when the level signal output by the voltage detection circuit is detected;

[0031] a second one-shot circuit, an input end of which is electrically connected to the output end of the voltage detection circuit through an inverter, for outputting a second pulse signal when the level signal output by the voltage detection circuit is detected;

[0032] A second logic gate circuit has a first input end and a second input end, the first input end is electrically connected with the output end of the first one-shot circuit, the second input end is electrically connected with the output end of the second one-shot circuit, and an output end is electrically connected with the reset end of the timing circuit, for outputting the first pulse signal and the second pulse signal to the timing circuit.

[0033] In addition, to achieve the above object, the application further provides a boost converter, comprising a transient response circuit of a boost converter as described above, and

[0034] The feedback control circuit is used for adjusting the output voltage of the boost converter according to the comparison result of the output voltage of the boost converter and the reference voltage.

[0035] In addition, to achieve the above object, the application further provides a control method, which is realized based on a boost converter as described above, comprising:

[0036] Monitoring the output voltage of the boost converter;

[0037] When it is monitored that the output voltage is lower than a first threshold value or higher than a second threshold value, a corresponding level signal is generated;

[0038] In response to the level signal output by the voltage detection circuit, the reference voltage input to the feedback control circuit is modulated, so as to reduce the time for the feedback control circuit to adjust the output voltage.

[0039] The one or more technical solutions provided by the application have at least the following technical effects:

[0040] The application comprises a voltage detection circuit and a control circuit, the voltage detection circuit can monitor abnormal drop or overshoot of the output voltage in real time and immediately generate a level signal. The control circuit responds to the signal, modulates the reference voltage, and provides a "leading" or "lagging" correction amount for the feedback control circuit, so as to effectively compress the system response delay and speed up the output voltage recovery process. Without changing the original bandwidth and phase margin of the main loop, the application improves the transient response speed, speeds up the recovery process of the system, solves the contradiction between stability and fast transient response of the traditional boost converter due to the limitation of the right half plane zero point, and solves the contradiction between stability and fast transient response of the traditional boost converter due to the limitation of the right half plane zero point. In addition, the transient response circuit as an additional module does not need to be complexly modified to the original feedback control loop, simplifies the design and debugging process while improving the performance, reduces the development cost, and effectively avoids the additional stability risk that may be introduced by directly modifying the main loop. BRIEF DESCRIPTION OF DRAWINGS

[0041] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the application and, together with the specification, serve to explain the principles of the application.

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0043] Figure 1 The constituent framework diagram provided for the first embodiment of the transient response circuit of the present application;

[0044] Figure 2 The circuit diagram provided for the second embodiment of the transient response circuit of the present application;

[0045] Figure 3 The constituent framework diagram provided for the third embodiment of the transient response circuit of the present application;

[0046] Figure 4 The circuit diagram provided for the fourth embodiment of the transient response circuit of the present application;

[0047] Figure 5 The single pulse circuit diagram provided for an embodiment of the present application;

[0048] Figure 6 The simulation waveform diagram of the transient response circuit of the present application;

[0049] Figure 7 The flow step diagram of an embodiment of the transient control method of the present application.

[0050] Explanation of the reference numerals: power switch circuit 01, feedback control circuit 02, transient response circuit 03, voltage detection circuit 31, control circuit 32, shielding circuit 33.

[0051] The purpose realization, functional features and advantages of the present application will be further explained with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0052] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application, and are not used to limit the present application.

[0053] In order to better understand the technical solutions of the present application, the following will be described in detail in combination with the drawings of the specification and the specific embodiments.

[0054] The present application provides a transient response circuit of a boost converter, the boost converter comprising a feedback control circuit 02, the feedback control circuit 02 being configured to adjust an output voltage of the boost converter according to a comparison result of the output voltage of the boost converter and a reference voltage, as shown in Figure 1 and Figure 2 The transient response circuit 03 comprises:

[0055] The voltage detection circuit 31 is electrically connected to the output end of the boost converter, and is configured to generate a corresponding level signal when detecting that the output voltage of the boost converter is lower than a first threshold or higher than a second threshold; the control circuit 32 is electrically connected to the output end of the voltage detection circuit 31, and is electrically connected to the reference input end of the feedback control circuit 02, and is configured to modulate the reference voltage input to the feedback control circuit 02 in response to the level signal output by the voltage detection circuit 31, so as to reduce the time for the feedback control circuit 02 to adjust the output voltage.

[0056] More specifically, the boost converter is widely used in many fields such as battery-powered devices, liquid crystal display backlight driving, portable electronic products, etc. as a basic DC-DC power conversion topology. Its function is to boost a lower input voltage to a stable higher output voltage. An ideal boost converter should be able to quickly adjust the duty cycle of the power switch tube through its internal closed-loop feedback control system when the load changes, so as to minimize the fluctuation of the output voltage and quickly recover to the rated value. In order to achieve this goal, one of the most direct and effective methods is to increase the bandwidth of the control loop. Higher loop bandwidth means that the control system can respond to load changes at a faster speed, thereby effectively suppressing the fluctuation of the output voltage.

[0057] However, the boost converter has an inherent control problem in the continuous conduction mode, the right half plane zero (RHPZ). The RHPZ is a special zero point in the transfer function of the boost converter, whose gain increases with increasing frequency, but the phase decreases with increasing frequency. In the continuous conduction mode (CCM), the energy transfer of the boost converter mainly occurs in the switch-off stage, and when the output voltage changes, the duty cycle adjustment needs to wait for multiple cycles to stabilize the inductor current, resulting in a delay in the output transient response, and the RHPZ reflects this hysteresis characteristic of energy transfer. The phase characteristic of the RHPZ is opposite to that of the ordinary zero point, making the system stability analysis and compensation design more complex. The presence of the RHPZ makes the achievable bandwidth usually less than one-fifth to one-tenth of the RHPZ frequency. For example, if the RHPZ frequency is 100 kHz, the actual bandwidth may only be about 20 kHz, limiting the fast response capability of the system. At the same time, the RHPZ cannot be completely canceled by conventional pole-zero compensation, and special compensation strategies need to be adopted, such as introducing high-frequency poles or adjusting the parameters of the compensator, to suppress the gain of the RHPZ at high frequencies, and ensure the stability of the system.

[0058] Due to the existence of the right half plane zero, the loop bandwidth of the boost converter is limited, and the load transient response characteristics cannot be improved by increasing the loop bandwidth, thereby limiting the performance of the boost converter in high-performance and dynamic load application scenarios. Therefore, in the existing boost converter architecture, stability and fast dynamic response become a pair of contradictions that are difficult to reconcile. In view of the above problems, the application provides a transient response circuit of a boost converter, which aims to solve the technical problem that the traditional boost converter cannot improve the load transient response characteristics by increasing the loop bandwidth due to the limitation of the right half plane zero.

[0059] Among them, the general boost converter includes a feedback control circuit 02, which continuously monitors the state of the output voltage, compares it with a reference voltage, and calculates a correction instruction according to the comparison result, and finally adjusts the on and off timing of the power switch to dynamically maintain the stability of the output voltage. In the feedback control circuit 02, it includes a feedback network, a reference voltage source, an error amplifier and a pulse width modulator. The error amplifier compares the output voltage of the boost converter with the reference voltage and amplifies the difference between the two to generate an error signal. The pulse width modulator generates a pulse signal with a corresponding duty cycle according to the signal output by the error amplifier to drive the power switch tube. When the output voltage is low, increase the on-duty of the switch tube to input more energy; when the output voltage is high, reduce the duty cycle.

[0060] The transient response circuit 03 of the application is built on the above-mentioned boost converter, which monitors the rapid change of the output voltage and actively intervenes in the adjustment of the reference voltage, thereby shortening the recovery time of the system and improving the overall stability. Among them, the transient response circuit 03 includes a voltage detection circuit 31 and a control circuit 32. The voltage detection circuit 31 continuously monitors the output voltage of the boost converter to determine whether it deviates from the normal steady state range, which is bounded by the first threshold and the second threshold. The first threshold usually corresponds to the minimum value of the output voltage allowed, that is, the undershoot threshold; the second threshold usually corresponds to the maximum value of the output voltage allowed, that is, the overshoot threshold.

[0061] Specifically, the input of the voltage detection circuit 31 is directly connected to the output of the boost converter, sampling the output voltage in real time. In normal working condition, when the output voltage is stable within the steady state range defined by the first threshold and the second threshold, the voltage detection circuit 31 is in a silent state and does not output any level signal. When the output voltage drops below the first threshold due to sudden load increase, or rises above the second threshold due to sudden load decrease, the voltage detection circuit 31 will quickly act. It usually contains a comparator structure inside, which can quickly compare the real-time output voltage with the two fixed thresholds. Once an out-of-limit condition is detected, the circuit will immediately generate a corresponding level signal. This signal indicates that the converter enters a transient process and needs external intervention to speed up the recovery.

[0062] The input of the control circuit 32 is connected to the output of the voltage detection circuit 31. When receiving a level signal indicating that the output voltage is too low, the control circuit 32 will quickly act, and its output will temporarily modulate the reference voltage input to the feedback control circuit 02. Specifically, the control circuit 32 will temporarily and slightly lower the value of the reference voltage. This operation is equivalent to "deceiving" the error amplifier of the feedback control circuit 02, making it believe that the current output voltage is "high enough", so as to prompt the error amplifier to output an instruction to immediately increase the peak value or duty cycle of the inductor current, to charge the output capacitor faster and quickly raise the output voltage.

[0063] Conversely, when detecting that the output voltage is too high, the control circuit 32 will temporarily raise the reference voltage, making the main loop mistakenly believe that the output voltage is "too low", and then quickly reduce the energy input to suppress the voltage overshoot. This intelligent and dynamic modulation of the reference voltage provides a powerful feedforward correction signal for the originally bandwidth-limited main loop, speeding up its response speed.

[0064] The present application includes the voltage detection circuit 31 and the control circuit 32. The voltage detection circuit 31 can monitor abnormal drop or overshoot of the output voltage in real time and immediately generate a level signal. The control circuit 32 responds to this signal by modulating the reference voltage to provide a "lead" or "lag" correction for the feedback control circuit 02, thereby effectively compressing the system response delay and speeding up the output voltage recovery process. Without changing the original bandwidth and phase margin of the main loop, the present application improves the transient response speed, speeds up the recovery process of the system, and solves the contradiction between stability and fast transient response of the traditional boost converter due to the right half plane zero point limitation. In addition, the transient response circuit 03 as an additional module does not need to modify the original feedback control loop, which simplifies the design and debugging process, reduces the development cost, and effectively avoids the additional stability risk that may be introduced by directly modifying the main loop.

[0065] In an embodiment, as shown in FIG. 1, the voltage detection circuit 31 comprises: Figure 2

[0066] a first comparator having a non-inverting input and an inverting input, the non-inverting input of the first comparator being connected to a first threshold, and the inverting input being connected to the output voltage, for outputting a first detection signal when detecting that the output voltage is lower than the first threshold; and a second comparator having a non-inverting input and an inverting input, the non-inverting input of the second comparator being connected to the output voltage, and the inverting input being connected to a second threshold, for outputting a second detection signal when detecting that the output voltage is higher than the second threshold.

[0067] a first flip-flop circuit having an input electrically connected to the first comparator and the second comparator, and an output electrically connected to a control terminal of the control circuit 32, for receiving and generating a corresponding level signal according to the first detection signal or the second detection signal.

[0068] In the embodiment, the voltage detection circuit 31 adopts a classical window comparator structure composed of two comparators and a flip-flop circuit, aiming to accurately and reliably capture abnormal falling and rising events of the output voltage. The first comparator is responsible for monitoring whether the output voltage is lower than a preset minimum allowed value. The core of the first comparator is an analog voltage comparator, which has a non-inverting input and an inverting input. The non-inverting input of the first comparator is applied with a fixed first threshold voltage (VREFL), which is set slightly lower than the normal rated output voltage, representing the allowed undershoot boundary. The inverting input is directly or through a voltage dividing network connected to the output voltage (VOUT) of the boost converter for real-time monitoring. In normal circumstances, when VOUT is higher than VREFL, the inverting input voltage is higher than the non-inverting input, and the first comparator outputs a low level. Once the load suddenly increases, causing VOUT to rapidly drop and fall below VREFL, the inverting input voltage of the first comparator decreases accordingly, making the non-inverting input voltage relatively higher, and its output state immediately flips, generating an effective first detection signal, usually a high level.

[0069] The second comparator is symmetrical to the first comparator in structure, but its responsibility is to monitor whether the output voltage exceeds a preset maximum allowed value. The inverting input of the second comparator is applied with a fixed second threshold voltage (VREFH), which is set slightly higher than the normal rated output voltage, representing the allowed overshoot boundary. The non-inverting input is connected to the monitored VOUT. In normal circumstances, VOUT is lower than VREFH, and the second comparator outputs a low level. When the load suddenly decreases, causing VOUT to rapidly rise and exceed VREFH, the non-inverting input voltage of the second comparator exceeds the inverting input, and its output state immediately flips, generating an effective second detection signal.

[0070] ​The first trigger circuit receives the detection signals from the two preceding comparators. The circuit can be composed of basic logic gates, or can contain simple timing logic or monostable trigger to achieve necessary de-bouncing, pulse shaping or latching functions.

[0071] In particular, the first trigger circuit in this embodiment is an RS flip-flop. An RS flip-flop generally has two input terminals, a set terminal and a reset terminal, and two complementary output terminals. In this embodiment, the set terminal of the RS flip-flop is connected to the output of the first comparator, for receiving the first detection signal; the reset terminal is connected to the output of the second comparator, for receiving the second detection signal. Meanwhile, one of the output terminals is used as the output terminal of the first trigger circuit, which outputs a high level when the first detection signal is received, and outputs a low level when the second detection signal is received.

[0072] During the transient response process, the output voltage can oscillate around the threshold value, causing the output of the comparator to produce multiple glitches or rapid flips. Without latching function, these glitches can be mistaken as multiple independent transient events, causing the control circuit 32 to act incorrectly. Once set or reset, the RS flip-flop will maintain the state unchanged until the opposite instruction is received, thus ensuring that only one stable and clean level signal is generated for a complete transient event, improving the reliability of the system.

[0073] In an embodiment, the control circuit 32 comprises:

[0074] a step signal generating circuit, having a controlled terminal electrically connected to the output terminal of the voltage detection circuit 31, for generating a corresponding step signal in response to the level signal output by the voltage detection circuit 31; and a coupling circuit, having one end electrically connected to the output terminal of the step signal generating circuit, and the other end electrically connected to the reference input terminal of the feedback control circuit 02, for coupling the step signal output by the step signal generating circuit to the reference voltage input to the feedback control circuit 02.

[0075] In this embodiment, the control circuit 32 comprises a step signal generating circuit and a coupling circuit. The step signal generating circuit is the "signal generator" of the control circuit 32, which converts the level signal output by the voltage detection circuit 31 into a transient step signal. The voltage detection circuit 31 only outputs a high / low level jump, while the step signal generating circuit needs to generate a step voltage signal with specific polarity, specific amplitude and specific duration based on it. The controlled terminal of the circuit is electrically connected to the output terminal of the voltage detection circuit 31, and when receiving the level signal indicating "output voltage is too low", the circuit will be activated to generate a positive step signal, for example a rapid voltage jump. Conversely, when receiving the level signal "output voltage is too high", the circuit will generate a negative step signal, aiming to pull down the reference voltage.

[0076] One end of the coupling circuit is connected to the output end of the step signal generating circuit, and the other end is connected to the reference voltage input end of the feedback control circuit 02. The step signal is superimposed on the original reference voltage to achieve the modulation of the entire loop target. At the same time, when the system is in a steady state without a level signal, the coupling circuit should present a high impedance or an effective isolation state, so that the step signal generating circuit is completely isolated from the reference voltage source, avoiding any load effect or noise interference, thereby ensuring the absolute accuracy and stability of the reference voltage in the steady state.

[0077] The coupling circuit can use capacitive coupling. Specifically, when a step signal, such as a negative voltage step, passes through the coupling circuit, it will cause the reference voltage actually input to the error amplifier to have a transient, same direction drop. This modulated reference voltage will immediately "deceive" the error amplifier, making it believe that the current output voltage is relatively high, thereby prompting the error amplifier to output instructions to immediately reduce energy delivery of the power stage and quickly suppress voltage overshoot. Conversely, once the step signal is maintained at a fixed DC level, the capacitor will gradually charge, and its coupling effect will weaken, thereby ensuring that the modulated reference voltage is temporary, and the final reference voltage will slowly recover to the original value.

[0078] In an embodiment, as shown in FIG. 1, the step signal generating circuit includes: Figure 2

[0079] A mirror current source has a reference current end and a mirror output end. The reference current end is connected to the ground through a current source, and the mirror output end is connected to the ground through a first resistor. The current of the mirror output end is the same as that of the reference current end. A first switch tube has an input end electrically connected to the reference current end, an output end electrically connected to the current source, and a controlled end electrically connected to the output end of the voltage detection circuit 31, for responding to the trigger output by the voltage detection circuit 31 to turn on or off the connection between the reference current end and the current source.

[0080] The mirror output end is electrically connected to the coupling circuit. When the first switch tube is turned on, the mirror current source works and generates a first step signal on the first resistor, which is coupled to the reference input end of the feedback control circuit 02 through the coupling circuit. When the first switch tube is turned off, the mirror current source stops working, and the first resistor discharges to generate a second step signal, which is coupled to the reference input end of the feedback control circuit 02 through the coupling circuit.

[0081] ​It can be understood that the embodiment utilizes a controlled mirror current source and a resistor to generate two step signals of opposite polarities by a single control signal. The working principle is as follows: when the system is in a steady state, the voltage detection circuit 31 has no level signal output, and the first switch tube is in a default steady state, which can be on or off, depending on the design convention. The key lies in the dynamic process of the circuit response to the level signal. Assuming that the default state of the first switch tube is off, when the load suddenly increases, causing the output voltage to drop, the voltage detection circuit 31 sends a high-level level signal, which drives the first switch tube from off to on.

[0082] A complete loop is established for the reference current path of the mirror current source. The current source starts to drive a constant current through the reference current terminal. According to the "copying" characteristics of the current mirror, an identical current immediately appears at the mirror output terminal. This current flows through the first resistor, and an instantaneous jump from zero voltage to a fixed positive voltage is generated on the first resistor. This positive voltage jump is the first step signal. It is superimposed on the reference voltage through the coupling circuit, temporarily raising the reference voltage. This is equivalent to setting a higher output voltage target for the feedback loop, thereby prompting the loop to quickly respond and increase the on-time of the power switch to supply energy to the output terminal at the maximum speed, effectively raising the falling output voltage.

[0083] Conversely, when the load suddenly decreases, causing the output voltage to surge, the voltage detection circuit 31 sends a low-level level signal, which controls the first switch tube to change from on to off, cutting off the reference current of the mirror current source. The reference current is immediately zero, and the mirror output current also immediately disappears. At this time, the voltage maintained on the first resistor loses current support, and the charge stored therein will quickly discharge through parasitic capacitance or a small current path designed intentionally, and the voltage across the resistor will quickly drop from a positive voltage value to zero volts. This negative jump from positive voltage to zero voltage is the second step signal. The negative step is superimposed on the reference voltage through the coupling circuit, which is equivalent to temporarily lowering the reference target of the output voltage. This will make the feedback loop mistakenly believe that the current output voltage is too high, thereby reducing or even closing the on-time of the power switch, slowing down energy delivery, and quickly pulling the overshooting voltage back to normal level.

[0084] The embodiment only uses one set of elements (current mirror, one switch, and one resistor) to handle two transient scenarios. The amplitude of the step signal is accurately set by the current value of the current source and the resistance value of the first resistor, ensuring the controllability of the intervention strength. At the same time, the step signal is a temporary signal, and once the transient process is over, the circuit will automatically return to the waiting state, without affecting the long-term steady-state accuracy of the system.

[0085] In an embodiment, the coupling circuit comprises:

[0086] The first capacitor is connected in series between the output of the step signal generating circuit and the reference input of the feedback control circuit 02, and is used to couple the step signal output by the step signal generating circuit to the reference input of the feedback control circuit 02; the second capacitor has one end electrically connected to the reference input of the feedback control circuit 02 and the other end grounded; the second resistor has one end electrically connected to the reference input of the feedback control circuit 02 and the other end electrically connected to the original reference voltage; the second capacitor and the second resistor form an RC filter network, which is used to restore the voltage at the reference input of the feedback control circuit 02 to the original reference voltage.

[0087] It can be understood that the first capacitor is connected in series between the output of the step signal generating circuit and the reference input of the feedback control circuit 02, and realizes AC coupling, and the first capacitor only allows the passage of varying signals and blocks DC components. In the steady state, when the step signal generating circuit does not output, the first capacitor blocks any influence of the DC level on the rear-end reference voltage node due to its DC blocking characteristic. It ensures that the transient response circuit 03 and the main feedback loop are highly isolated when the system is working normally, and the accuracy of the original reference voltage will not be disturbed, which is the key to ensuring the steady-state performance of the converter. When a transient event occurs, the step signal generating circuit outputs a fast voltage step, and this sudden change can be regarded as a high-frequency AC signal by the first capacitor. The capacitor allows the jump to be transmitted to the other side almost without attenuation, thereby instantaneously modulating the voltage at the reference input of the feedback control circuit 02.

[0088] The second capacitor and the second resistor form an RC filter network connected in parallel to the reference input, which realizes automatic recovery of the reference voltage and suppresses spike interference. One end of the second resistor is connected to the modulated reference input, and the other end is connected to the original, stable reference voltage source. When the transient step signal coupled by the first capacitor causes the voltage at the reference input to deviate, the original reference voltage source will continuously inject or extract current to the node through the second resistor, trying to pull the voltage back to the original value. The greater the resistance of the resistor, the slower the recovery process; the smaller the resistance, the faster the recovery, but it may weaken the effect of transient intervention.

[0089] The second capacitor is connected in parallel to the second resistor to the ground, which plays a role in filtering and maintaining the integrity of the voltage. First, the second capacitor and the second resistor together form a low-pass filter, which presents a low impedance to the DC or low-frequency signals from the original reference voltage source, ensuring the stability of the steady-state voltage; but for the fast transient signal injected by the step signal generating circuit, it presents a higher impedance, so that the step voltage can effectively act on the reference input without being instantaneously pulled down by the original reference voltage source. Second, the second capacitor provides a path for charge discharge. When a negative step signal is injected, the voltage at the reference input is pulled down, and the second capacitor can assist the pull-down process through discharging; conversely, when it needs to be restored, it is charged through the second resistor.

[0090] When a step signal arrives, the first capacitor acts as a channel to couple the fast voltage jump in. The presence of the second capacitor ensures that the jump effectively changes the instantaneous potential of the reference input. Then the RC network comes into play: the original reference voltage source slowly charges the second capacitor through the second resistor, driving the voltage of the reference input to smoothly return to the original set value in an exponential law. The time constant of this recovery process, determined by the product of the second resistor and the second capacitor, is designed to be much slower than the response speed of the feedback loop, thus ensuring that the transient auxiliary action has enough time to take effect, but also ensuring that it quietly exits after the transient ends, returning the system to steady-state control.

[0091] In an embodiment, as shown in Figure 3 the boost converter further comprises a clock signal, and the transient response circuit 03 further comprises:

[0092] a shielding circuit 33, having an input electrically connected to the output of the voltage detection circuit 31 and the clock signal, and an output electrically connected to a controlled terminal of the voltage detection circuit 31, for inhibiting the voltage detection circuit 31 from generating a new level signal within a preset clock signal in response to the level signal output by the voltage detection circuit 31.

[0093] In this embodiment, the transient response circuit 03 further comprises a shielding circuit 33. After the voltage detection circuit 31 outputs a level signal to start the transient response mechanism, the shielding circuit 33 will immediately intervene to temporarily "shield" or "inhibit" the voltage detection circuit 31 from outputting a new level signal within a preset time window. This ensures that the system will not be mistakenly triggered for a second or third time due to normal fluctuations in the output voltage or ripples caused by the correction action itself before completing a complete correction action and stabilizing.

[0094] The input of the shielding circuit 33 is electrically connected to the output of the voltage detection circuit 31 and the clock signal of the system, and the output is electrically connected to a controlled terminal of the voltage detection circuit 31. It can be understood that the shielding circuit 33 can monitor the triggering state of the voltage detector and accurately control the length of the shielding time using the clock signal, and ultimately realize the shielding function by controlling the working state of the voltage detection circuit 31. Effectively prevent the output voltage oscillation caused by the loop adjustment after the step signal injection from being mistaken as a new transient event.

[0095] In an embodiment, as shown in Figure 4 the voltage detection circuit 31 further comprises a first logic gate circuit, and the shielding circuit 33 comprises:

[0096] The pulse generating circuit is electrically connected with the output end of the voltage detecting circuit 31, and is used to receive the level signal output by the voltage detecting circuit 31 and generate a pulse signal; the timing circuit is electrically connected with the clock signal at the input end and is electrically connected with the controlled end of the logic gate circuit at the output end, and is used to perform timing when receiving the clock signal and output a disable signal to the first logic gate circuit during the timing to block the logic gate circuit from generating the level signal by the voltage detecting circuit 31, and is also used to output an enable signal to the logic gate circuit after the timing is completed to allow the voltage detecting circuit 31 to generate the level signal; wherein the timing circuit has a reset end, the reset end is electrically connected with the output end of the pulse generating circuit, and the timing circuit is also used to restart the timing when receiving the pulse signal output by the pulse generating circuit.

[0097] In the embodiment, the voltage detecting circuit 31 further comprises the first logic gate circuit, and the shielding circuit 33 comprises the pulse generating circuit and the timing circuit. It is intended to ensure that after any transient event is detected, the system enters a controlled "quiet period", during which any fluctuation of the output voltage is ignored, so as to avoid repeated triggering or system oscillation.

[0098] Specifically, the first logic gate circuit is two AND gates, which are respectively arranged between the two comparators and the first trigger circuit. One input end of the first logic gate circuit receives the detection signal from the comparator, and the other input end is used as the controlled end and receives the enable or disable instruction from the shielding circuit 33. When the comparator outputs a high-level signal and the shielding circuit 33 outputs a high-level, the logic gate outputs a high-level to the first trigger circuit. When the shielding circuit 33 outputs a low-level, the logic gate outputs a low-level to the first trigger circuit, so as to realize the direct control of the output ability of the voltage detecting circuit 31.

[0099] The input end of the pulse generating circuit is connected with the output end of the voltage detecting circuit 31, and converts the level signal output by the voltage detecting circuit 31 into a short pulse signal. This is usually realized by a monostable trigger circuit. Once the voltage detecting circuit 31 outputs the level signal, no matter how long the duration is, the pulse generating circuit will be triggered immediately and generate a very short standardized pulse as the reset / enable signal of the timing circuit.

[0100] The timing circuit is a resettable timer, which receives the system clock signal at its input to provide a precise time reference. Its output is connected to the control input of the first logic gate, to output the "disable" or "enable" signal. In addition, it has a vital reset input, which is connected to the output of the pulse generator. When the reset input of the timing circuit receives a pulse signal from the pulse generator, it is immediately reset and starts counting again. During the counting period, the output of the timing circuit remains "disable", which is sent to the control input of the first logic gate to close the gate and thus achieve the shielding.

[0101] The timer measures time by counting clock cycles. This preset count determines the duration of the shielding window. The time must be longer than the time required for the feedback loop to respond to a step signal and stabilize the output. If the voltage detection circuit 31 generates a level signal again due to output fluctuations within the current shielding window, the pulse generator will generate another pulse to the reset input of the timing circuit. This will cause the timer to reset and start a new counting cycle from the beginning. This means that as long as the output voltage continues to fluctuate and trigger the detection circuit before it stabilizes, the shielding period will be continuously extended, thus eliminating the possibility of any secondary triggering before the system is fully stable. Only when the output voltage is truly stable and no longer triggers the detection circuit, the timer can successfully complete the entire counting period and then output the "enable" signal to reopen the first logic gate, and the system can return to the normal monitoring state.

[0102] Specifically, the timer of the present embodiment is a hexadecimal counter and a register. The hexadecimal counter counts the incoming clock signal. Every time a clock cycle arrives, the value of the counter increases by one. Since it is hexadecimal, this means that it will overflow every 16 clock cycles. It also has a reset input, which, when active, will immediately clear the counter to zero and start counting from the beginning, regardless of the current value.

[0103] The register is used to hold a preset value, which represents the number of clock cycles required for the desired shielding time. For example, if the clock frequency is 1 MHz and the required shielding time is 100 microseconds, the register will be preset to the value 100. The output value of the register serves as a constant "target value" or "threshold value", which is continuously compared with the current count value of the hexadecimal counter. When the pulse generator sends a pulse signal, the pulse acts on the reset input of the hexadecimal timer. The counter is immediately cleared to zero and starts counting from its initial state (0) again. The counter starts from 0 and increases with every clock cycle: 0, 1, 2, 3... In a digital comparator, the real-time count value of the counter is continuously compared with the preset value in the register.

[0104] The output of the comparator will remain as the "disable" signal until the value of the counter is less than the preset value of the register. This signal is sent to the first logic gate, which masks the voltage detection circuit 31. When the value of the counter is equal to the preset value of the register, the output state of the comparator is flipped to the "enable" signal, i.e. the high level signal. This signal unblocks the first logic gate, and the voltage detection circuit 31 resumes normal operation. At this time, the comparator state has changed, which has no effect on the masking function until the next reset signal arrives.

[0105] In one embodiment, as shown in Figure 4 and Figure 5 The pulse generation circuit comprises:

[0106] A first one-shot circuit, the input end of which is electrically connected to the output end of the voltage detection circuit 31, for outputting a first pulse signal when detecting the level signal output by the voltage detection circuit 31; a second one-shot circuit, the input end of which is electrically connected to the output end of the voltage detection circuit 31 through an inverter, for outputting a second pulse signal when detecting the level signal output by the voltage detection circuit 31; and a second logic gate circuit, having a first input end and a second input end, the first input end being electrically connected to the output end of the first one-shot circuit, the second input end being electrically connected to the output end of the second one-shot circuit, and the output end being electrically connected to the reset end of the timing circuit, for outputting the first pulse signal and the second pulse signal to the timing circuit.

[0107] It can be understood that the pulse generation circuit aims to create a detection mechanism that is sensitive to the change of the input level signal, whether it is the rising edge or the falling edge, and can generate a pulse output to reset the timing circuit in the back stage. It achieves this goal by parallelly connecting two paths that process different edges, and synthesizing through a logic gate. The circuit mainly consists of a first one-shot circuit, a second one-shot circuit, an inverter, and a second logic gate circuit.

[0108] The input end of the first one-shot circuit is directly connected to the output end of the voltage detection circuit 31, to detect the effective jump edge of the level signal. Assuming that the voltage detection circuit 31 outputs a jump from low level to high level as the level signal when it needs to act. When the voltage detection circuit 31 outputs the level signal, i.e. the level rises, the first one-shot circuit will be triggered immediately. Its internal mechanism is usually based on a monostable trigger that ignores the subsequent high level state of the input signal, and generates a first pulse signal.

[0109] The second one-shot circuit is a parallel detection path. An inverter is connected in series between the output of the voltage detection circuit 31 and the input of the second one-shot circuit. The polarity of the level signal is reversed, and the second one-shot circuit is configured to detect a valid transition edge of its input signal. When the first trigger circuit outputs a transition from high to low as the level signal, the falling edge is inverted by the inverter and becomes a rising edge, which is sent to the input of the second one-shot circuit. The second one-shot circuit is triggered and generates a second pulse signal.

[0110] The second logic gate circuit has two inputs connected to the outputs of the first and second one-shot circuits, respectively, and an output connected to the reset terminal of the timing circuit. The function of the second logic gate is "NOR" logic. As long as either of its two inputs has a high level pulse, its output will immediately become low level. When the rising edge, the first one-shot circuit generates the first pulse, the second logic gate outputs a low level pulse. When the falling edge, the second one-shot circuit generates the second pulse, the second logic gate also outputs a low level pulse. This signal is output as a reset signal to the reset terminal of the timing circuit, and the timing circuit is asynchronously reset to 0 and re-timed.

[0111] In addition, the application also proposes a boost converter, as shown in Figure 1 The boost converter further includes a power switch circuit 01 for boosting the input voltage. The output of the power switch circuit 01 is the output of the boost converter. The transient response circuit 03 includes a voltage detection circuit 31, an input terminal of which is electrically connected to the output terminal of the boost converter, for generating a corresponding level signal when detecting that the output voltage of the boost converter is lower than a first threshold or higher than a second threshold; a control circuit 32, an input terminal of which is electrically connected to the output terminal of the voltage detection circuit 31, and an output terminal of which is electrically connected to the reference input terminal of the feedback control circuit 02, for modulating the reference voltage input to the feedback control circuit 02 in response to the level signal output by the voltage detection circuit 31, so as to reduce the time for the feedback control circuit 02 to adjust the output voltage.

[0112] The transient response circuit 03 of the application comprises a voltage detection circuit 31 and a control circuit 32. The voltage detection circuit 31 can monitor abnormal drop or overshoot of the output voltage in real time and immediately generate a level signal. The control circuit 32 responds to the signal and provides a “lead” or “lag” correction to the feedback control circuit 02 by modulating the reference voltage, thereby effectively compressing the system response delay and accelerating the output voltage recovery process. The application improves the transient response speed and accelerates the recovery process of the system without changing the original bandwidth and phase margin of the main loop, solves the contradiction between stability and fast transient response of the traditional boost converter due to the limitation of the right half plane zero point. In addition, the transient response circuit 03 as an additional module does not need to modify the original feedback control loop, simplifies the design and debugging process, reduces the development cost, and effectively avoids the additional stability risk that may be introduced by directly modifying the main loop.

[0113] In addition, the application also proposes a control method, which is realized based on the boost converter as described above, as shown in Figure 6 and Figure 7 , comprising:

[0114] S100: monitoring the output voltage of the boost converter;

[0115] S200: generating a corresponding level signal when the monitored output voltage is lower than a first threshold or higher than a second threshold;

[0116] S300: modulating the reference voltage input to the feedback control circuit in response to the level signal output by the voltage detection circuit to reduce the time for the feedback control circuit to adjust the output voltage.

[0117] It can be understood that the specific steps of the embodiment are as follows:

[0118] In step S100, the first comparator and the second comparator are respectively used to detect whether the output voltage VOUT overshoots or undershoots to generate a level signal EN_TRAN, and then adjust the reference input signal of the operational amplifier, thereby optimizing the transient response optimization characteristics.

[0119] In step S200, when the load jumps from light load to heavy load, the VOUT voltage starts to drop, and when it drops to the first threshold VREFL, the first comparator output signal VOUT_L becomes high level, and the output voltage EN_TRAN of the RS flip-flop becomes high level. In step S300, when the high level output by the RS flip-flop is received, the first switch tube N1 MOS tube is turned on, the current source I0 is mirrored to the first resistor R0 through the current mirror P1, P2, thereby generating a step voltage of 0 to I0*R0 on R0, and the step voltage is coupled on the second capacitor C2 on the basis of the VREF reference voltage through the first capacitor C1. V, and then the voltage on the second capacitor C2 decreases slowly through the second resistor R3 to equal VREF. Since the input reference voltage of the operational amplifier is coupled to be high for a period of time when the load jumps from heavy to light, the error signal at both inputs of the operational amplifier becomes larger, so that the COMP voltage can be adjusted to be high quickly, the duty cycle is made to be large quickly, the switching converter can supply energy to the load more quickly, and the output voltage drop is suppressed, so that the transient response performance of the loop is improved.

[0120] Similarly, when the load jumps from heavy to light, the VOUT voltage begins to rise, and when it rises to the second threshold VREFH, the second comparator output signal VOUT_H becomes high, the output voltage EN_TRAN of the RS flip-flop becomes low, the first switch N1 MOS tube is closed, the current flowing through the current mirror P2 becomes 0, and the voltage on the first resistor R0 decreases from the initial I0*R0 to 0 through R0, thereby generating a second step signal that changes from high to low. The step voltage is coupled to the second capacitor C2 through the first capacitor C1 to generate a second voltage that decreases from VREF on the basis of the reference voltage VREF. V, and then the voltage on the second capacitor C2 decreases slowly through the second resistor R3 to equal VREF. Since the input reference voltage of the operational amplifier is coupled to be high for a period of time when the load jumps from heavy to light, the error signal at both inputs of the operational amplifier becomes larger, so that the COMP voltage can be adjusted to be high quickly, the duty cycle is made to be large quickly, the switching converter can supply energy to the load more quickly, and the output voltage drop is suppressed, so that the transient response performance of the loop is improved.

[0121] Meanwhile, since the output voltage may fluctuate repeatedly during the transient response adjustment process, the transient response optimization circuit is repeatedly triggered, which may cause the system to be unstable. A shielding circuit 33 is added, which prevents the transient response optimization circuit from being triggered again within a period of time after the transient response optimization circuit is triggered.

[0122] When EN_TRAN changes from low to high or from high to low, the two one-pulse circuits ONEPULSE CIRCUIT generate a pulse signal, respectively, so that the counter of the timing circuit and the D flip-flop of the register are all reset to zero, and the output signal BLANK of the register becomes low, thereby preventing VOUT_L and VOUT_H from being input to the RS flip-flop. The transient response optimization circuit maintains the original state unchanged. Only when the counter counts to a certain time and the BLANK signal is flipped high, VOUT_L and VOUT_H are allowed to be input to the RS flip-flop, and the transient response optimization circuit is allowed to be triggered again according to the circuit state.

[0123] The above merely describes some embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structural transformation, direct / indirect application in other related technical fields, or the like, which is made based on the technical concept of the present application and the content of the specification and drawings, is included in the patent protection scope of the present application.

Claims

1. A transient response circuit for a boost converter, the boost converter including a feedback control circuit, the feedback control circuit being used to adjust the output voltage of the boost converter based on a comparison result between the output voltage of the boost converter and a reference voltage, characterized in that, The transient response circuit includes: The voltage detection circuit, with its input terminal electrically connected to the output terminal of the boost converter, is used to generate a corresponding level signal when the output voltage of the boost converter is detected to be lower than a first threshold or higher than a second threshold. The control circuit has its input terminal electrically connected to the output terminal of the voltage detection circuit and its output terminal electrically connected to the reference input terminal of the feedback control circuit. It is used to respond to the level signal output by the voltage detection circuit and modulate the reference voltage input to the feedback control circuit to reduce the time for the feedback control circuit to adjust the output voltage. The control circuit includes: A step signal generating circuit, with its controlled terminal electrically connected to the output terminal of the voltage detection circuit, is used to generate a corresponding step signal in response to the level signal output by the voltage detection circuit. A coupling circuit, one end of which is electrically connected to the output terminal of the step signal generating circuit, and the other end of which is electrically connected to the reference input terminal of the feedback control circuit, is used to couple the step signal output by the step signal generating circuit to the reference voltage input to the feedback control circuit. The step signal generation circuit includes: A current mirror source has a reference current terminal and a mirror output terminal. The reference current terminal is grounded after passing through the current source, and the mirror output terminal is grounded after passing through a first resistor. The current at the mirror output terminal is the same as that at the reference current terminal. The first switching transistor has its input terminal electrically connected to the reference current terminal, its output terminal electrically connected to the current source, and its controlled terminal electrically connected to the output terminal of the voltage detection circuit. It is used to turn on or off the connection between the reference current terminal and the current source in response to the level signal output by the voltage detection circuit. The mirror output terminal is electrically connected to one end of the coupling circuit. When the first switch is turned on, the mirror current source operates and generates a first step signal on the first resistor, which is coupled to the reference input terminal of the feedback control circuit through the coupling circuit. When the first switch is turned off, the mirror current source stops operating, and the first resistor discharges to generate a second step signal, which is coupled to the reference input terminal of the feedback control circuit through the coupling circuit. The coupling circuit includes: The first capacitor is connected in series between the output terminal of the step signal generation circuit and the reference input terminal of the feedback control circuit, and is used to couple the step signal output by the step signal generation circuit to the reference input terminal of the feedback control circuit. The second capacitor has one end electrically connected to the reference input terminal of the feedback control circuit, and the other end grounded. The second resistor has one end electrically connected to the reference input terminal of the feedback control circuit and the other end electrically connected to the original reference voltage. The second capacitor and the second resistor form an RC filter network, which is used to restore the voltage at the reference input terminal of the feedback control circuit to the original reference voltage.

2. The transient response circuit of the boost converter as described in claim 1, characterized in that, The voltage detection circuit includes: A first comparator has a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal of the first comparator is connected to the first threshold, and the inverting input terminal is connected to the output voltage. It is used to output a first detection signal when the output voltage is detected to be lower than the first threshold. The second comparator has a non-inverting input terminal and an inverting input terminal. The non-inverting input terminal of the second comparator is connected to the output voltage, and the inverting input terminal is connected to the second threshold. It is used to output a second detection signal when the output voltage is detected to be higher than the second threshold. The first trigger circuit has its input terminals electrically connected to the first comparator and the second comparator, respectively, and its output terminal electrically connected to the input terminal of the control circuit. It is used to receive and generate a corresponding level signal based on the first detection signal or the second detection signal.

3. The transient response circuit of the boost converter as described in claim 1 or 2, characterized in that, The boost converter also includes a clock signal, and the transient response circuit also includes: The shielding circuit has its input terminal electrically connected to the output terminal of the voltage detection circuit and the clock signal, respectively, and its output terminal electrically connected to the controlled terminal of the voltage detection circuit. It is used to respond to the level signal output by the voltage detection circuit and prevent the voltage detection circuit from generating a level signal again within a preset clock signal.

4. The transient response circuit of the boost converter as described in claim 3, characterized in that, The voltage detection circuit further includes a first logic gate circuit, and the shielding circuit includes: A pulse generation circuit, with its input terminal electrically connected to the output terminal of the voltage detection circuit, is used to receive the level signal output by the voltage detection circuit and generate a pulse signal. The timing circuit has its input terminal electrically connected to the clock signal and its output terminal electrically connected to the controlled terminal of the first logic gate circuit. The timing circuit is used to receive the clock signal for timing and output an inhibit signal to the first logic gate circuit during the timing period to block the voltage detection circuit from generating a level signal. It is also used to output an start signal to the first logic gate circuit after the timing ends to allow the voltage detection circuit to generate a level signal. The timing circuit has a reset terminal, which is electrically connected to the output terminal of the pulse generation circuit. The timing circuit is also used to restart the timing when it receives the pulse signal output by the pulse generation circuit.

5. The transient response circuit of the boost converter as described in claim 4, characterized in that, The pulse generation circuit includes: The first single-pulse circuit has its input terminal electrically connected to the output terminal of the voltage detection circuit, and is used to output a first pulse signal when the voltage detection circuit outputs a level signal. The second single-pulse circuit has its input terminal connected to the output terminal of the voltage detection circuit via an inverter, and is used to output a second pulse signal when the voltage detection circuit outputs a level signal. The second logic gate circuit has a first input terminal and a second input terminal. The first input terminal is electrically connected to the output terminal of the first single-pulse circuit, the second input terminal is electrically connected to the output terminal of the second single-pulse circuit, and the output terminal is electrically connected to the reset terminal of the timing circuit. It is used to output the first pulse signal and the second pulse signal to the timing circuit.

6. A boost converter, characterized in that, Including the transient response circuit of the boost converter as described in any one of claims 1 to 5, and The feedback control circuit is used to adjust the output voltage of the boost converter based on the comparison result between the output voltage of the boost converter and the reference voltage.

7. A control method, implemented based on the boost converter as described in claim 6, characterized in that, include: Monitor the output voltage of the boost converter; When the output voltage is detected to be lower than the first threshold or higher than the second threshold, a corresponding level signal is generated; In response to the level signal output by the voltage detection circuit, the reference voltage input to the feedback control circuit is modulated to reduce the time it takes for the feedback control circuit to adjust the output voltage.

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