Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes: a first light emitting element; a second light emitting element spaced apart from the first light emitting element in a plan view; a first pixel driving circuit portion including a driving transistor electrically connected to the first light emitting element, in which the driving transistor in the first pixel driving circuit portion at least partially overlaps the first light emitting element in a plan view; and a second pixel driving circuit portion including a driving transistor electrically connected to the second light emitting element, in which the driving transistor in the second pixel driving circuit portion at least partially overlaps the first light emitting element in a plan view.

Description

Technical Field

[0001] This disclosure relates to display devices and electronic devices including said display devices. More specifically, this disclosure relates to display devices that provide visual information and electronic devices including said display devices. Background Technology

[0002] Display devices are devices that display images to provide visual information to users. Among display devices, organic light-emitting diode (OLED) displays have recently attracted attention.

[0003] The organic light-emitting diode (OLED) display device may include a light-emitting element and a pixel driving circuit portion electrically connected to the light-emitting element. Since the light-emitting element emits light in all directions, the light emitted from the light-emitting element may reach the transistors included in the pixel driving circuit portion. Summary of the Invention

[0004] Embodiments of this disclosure provide a display device with improved quality.

[0005] Embodiments of this disclosure provide an electronic device including the display device.

[0006] A display device according to one or more embodiments includes: a first light-emitting element; a second light-emitting element spaced apart from the first light-emitting element in a plan view; a first pixel driving circuit portion including a driving transistor electrically connected to the first light-emitting element, wherein the driving transistor in the first pixel driving circuit portion at least partially overlaps with the first light-emitting element in a plan view; and a second pixel driving circuit portion including a driving transistor electrically connected to the second light-emitting element, wherein the driving transistor in the second pixel driving circuit portion at least partially overlaps with the second light-emitting element in a plan view.

[0007] In one or more embodiments, the driving transistor in the first pixel driving circuit portion may be configured to provide driving current to the first light-emitting element.

[0008] In one or more embodiments, the driving transistor in the second pixel driving circuit portion may be configured to provide driving current to the second light-emitting element.

[0009] In one or more embodiments, the display device may further include: a voltage line electrically connected to each of the first pixel driving circuit portion and the second pixel driving circuit portion.

[0010] In one or more embodiments, the driving transistor in the first pixel driving circuit portion may be located on one side of the voltage line.

[0011] In one or more embodiments, the driving transistor in the second pixel driving circuit portion may be located on the other side of the voltage line.

[0012] In one or more embodiments, each of the first pixel driving circuit portion and the second pixel driving circuit portion may further include a capacitor.

[0013] In one or more embodiments, the capacitor in the first pixel driving circuit portion may be located on one side of the voltage line.

[0014] In one or more embodiments, the capacitor in the second pixel driving circuit portion may be located on the other side of the voltage line.

[0015] In one or more embodiments, the voltage line may be configured to apply an electrical voltage to each of the first pixel driving circuit portion and the second pixel driving circuit portion.

[0016] In one or more embodiments, each of the first pixel driving circuit portion and the second pixel driving circuit portion may further include a first switching transistor.

[0017] In one or more embodiments, the first switching transistor in the first pixel driving circuit portion may be located on one side of the voltage line.

[0018] In one or more embodiments, the first switching transistor in the second pixel driving circuit portion may be located on the other side of the voltage line.

[0019] In one or more embodiments, each of the first pixel driving circuit portion and the second pixel driving circuit portion may further include a second switching transistor.

[0020] In one or more embodiments, each of the second switching transistor in the first pixel driving circuit portion and the second switching transistor in the second pixel driving circuit portion may be located on one side of the voltage line or on the other side of the voltage line.

[0021] In one or more embodiments, the display device may further include: a third light-emitting element, spaced apart from each of the first light-emitting element and the second light-emitting element in a plan view; and a third pixel driving circuit portion, including a driving transistor electrically connected to the third light-emitting element.

[0022] In one or more embodiments, the driving transistor in the third pixel driving circuit portion may at least partially overlap with the third light-emitting element in a planar view.

[0023] In one or more embodiments, the first light-emitting element, the second light-emitting element, and the third light-emitting element may be configured to emit light having different wavelengths from each other.

[0024] In one or more embodiments, the display device may further include: a voltage line electrically connected to each of the first pixel driving circuit portion, the second pixel driving circuit portion, and the third pixel driving circuit portion.

[0025] In one or more embodiments, each of the driving transistors in the first pixel driving circuit portion and the third pixel driving circuit portion may be located on one side of the voltage line.

[0026] In one or more embodiments, the driving transistor in the second pixel driving circuit portion may be located on the other side of the voltage line.

[0027] In one or more embodiments, each of the first pixel driving circuit portion, the second pixel driving circuit portion, and the third pixel driving circuit portion may further include a capacitor.

[0028] In one or more embodiments, each of the capacitors in the first pixel driving circuit portion and the third pixel driving circuit portion may be located on one side of the voltage line.

[0029] In one or more embodiments, the capacitor in the second pixel driving circuit portion may be located on the other side of the voltage line.

[0030] A display device according to one or more embodiments of the present disclosure includes: a first light-emitting element; a second light-emitting element, spaced apart from the first light-emitting element in a plan view; a voltage line; a first pixel driving circuit portion including a driving transistor located on one side of the voltage line, wherein the first pixel driving circuit portion is electrically connected to each of the first light-emitting element and the voltage line; and a second pixel driving circuit portion including a driving transistor located on the other side of the voltage line, wherein the second pixel driving circuit portion is electrically connected to each of the second light-emitting element and the voltage line.

[0031] In one or more embodiments, the driving transistor in the first pixel driving circuit portion may at least partially overlap with the first light-emitting element in a planar view.

[0032] In one or more embodiments, the driving transistor in the second pixel driving circuit portion may at least partially overlap with the second light-emitting element in a planar view.

[0033] In one or more embodiments, the voltage line may be configured to apply an electrical voltage to each of the first pixel driving circuit portion and the second pixel driving circuit portion.

[0034] In one or more embodiments, each of the first pixel driving circuit portion and the second pixel driving circuit portion may further include a capacitor.

[0035] In one or more embodiments, the capacitor in the first pixel driving circuit portion may be located on one side of the voltage line.

[0036] In one or more embodiments, the capacitor in the second pixel driving circuit portion may be located on the other side of the voltage line.

[0037] In one or more embodiments, the display device may further include: a third light-emitting element, spaced apart from each of the first light-emitting element and the second light-emitting element in a plan view; and a third pixel driving circuit portion electrically connected to each of the third light-emitting element and the voltage line.

[0038] In one or more embodiments, the third pixel driving circuit portion may include a driving transistor located on one side of the voltage line or on the other side of the voltage line.

[0039] An electronic device according to one or more embodiments of the present disclosure includes: a first light-emitting element; a second light-emitting element spaced apart from the first light-emitting element in a plan view; a first pixel driving circuit portion including a driving transistor electrically connected to the first light-emitting element, wherein the driving transistor in the first pixel driving circuit portion at least partially overlaps with the first light-emitting element in a plan view; a second pixel driving circuit portion including a driving transistor electrically connected to the second light-emitting element, wherein the driving transistor in the second pixel driving circuit portion at least partially overlaps with the second light-emitting element in a plan view; and a memory configured to store data information.

[0040] A display device according to one or more embodiments of the present disclosure may include: a first light-emitting element; a second light-emitting element, spaced apart from the first light-emitting element in a plan view; a first pixel driving circuit portion including a driving transistor electrically connected to the first light-emitting element; and a second pixel driving circuit portion including a driving transistor electrically connected to the second light-emitting element. The driving transistor in the first pixel driving circuit portion at least partially overlaps with the first light-emitting element in a plan view. The driving transistor in the second pixel driving circuit portion at least partially overlaps with the second light-emitting element in a plan view.

[0041] Therefore, light emitted from the first light-emitting element can be prevented from reaching the driving transistor in the second pixel driving circuit section. Furthermore, light emitted from the second light-emitting element can be prevented from reaching the driving transistor in the first pixel driving circuit section. Therefore, degradation of the driving transistor in the first pixel driving circuit section and the driving transistor in the second pixel driving circuit section can be prevented. Attached Figure Description

[0042] The illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0043] Figure 1 This is a schematic diagram illustrating a display device according to one or more embodiments.

[0044] Figure 2 It is shown Figure 1 A block diagram of the display device.

[0045] Figure 3 This is a schematic diagram showing the equivalent circuit of a pixel.

[0046] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 This illustrates one or more embodiments. Figure 1 The layout diagram of pixels included in the display device.

[0047] Figure 14 It is along Figure 13 The line I-I' intercepted Figure 13 A cross-sectional view of the display device.

[0048] Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This illustrates one or more embodiments. Figure 1 The layout diagram of pixels included in the display device.

[0049] Figure 25 This is a block diagram illustrating an electronic device according to one or more embodiments.

[0050] Figure 26This is a schematic diagram of an electronic device according to one or more embodiments. Detailed Implementation

[0051] In the following description, the display device according to an embodiment will be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0052] The aspects and features of embodiments of this disclosure, as well as methods for implementing these aspects and features, can be more readily understood through the detailed description of the embodiments and the accompanying drawings. Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are not essential for a full understanding of the aspects and features of this disclosure by those skilled in the art are not described.

[0053] In the accompanying drawings, the relative dimensions of elements, layers, and areas may be exaggerated for clarity. Additionally, the use of crosshairs and / or shading in the drawings is generally intended to clarify the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate a preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, or any other features, properties, characteristics, etc.

[0054] Various embodiments are described herein with reference to cross-sectional views that serve as schematic diagrams of examples and / or intermediate structures. Thus, variations in the illustrated shape can be anticipated, for example, due to manufacturing techniques and / or tolerances. Furthermore, the specific structural or functional descriptions disclosed herein are illustrative only for the purpose of describing embodiments according to this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shape of the shown area, but will include deviations in shape caused, for example, by manufacturing processes.

[0055] For example, an injection zone shown as rectangular may have rounded or curved features and / or a gradient of injection concentration at its edges, rather than a binary variation from the injection zone to the non-injection zone. Similarly, a buried zone formed by injection may result in some injection in the zone between the buried zone and the surface through which the injection occurs. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the zones of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in a variety of different ways, all of which do not depart from the spirit and / or scope of this disclosure.

[0056] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that various embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and arrangements are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0057] For ease of explanation, spatial relative terms such as “below,” “under,” “below,” “below,” “above,” and / or “above” may be used herein to describe the relationship of one element or feature to another element (or feature) or feature (or feature) as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device is flipped in the drawings, an element described as “below,” “below,” or “below” other elements or features will subsequently be oriented “above” other elements or features. Thus, the example terms “below,” “below,” or “below” can include both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly. Similarly, when a first component is described as being arranged “above” a second component, this means that the first component is arranged above or below the second component, and not limited to the upper side of the second component based on the direction of gravity.

[0058] Furthermore, in this specification, the phrase "in a plane" or "in a plan view" refers to the target portion viewed from the top, and the phrase "in a cross section" refers to the cross section formed by vertically cutting the target portion viewed from the side.

[0059] It will be understood that when an element, layer, area, or component is referred to as "formed on," "on," "connected to," or "coupled to" another element, layer, area, or component, the element, layer, area, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, area, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, area, or component, such that one or more intermediary elements, intermediary layers, intermediary areas, or intermediary components may exist. For example, when a layer, area, or component is referred to as "electrically connected" or "electrically coupled" to another layer, area, or component, the layer, area, or component may be directly electrically connected or directly electrically coupled to the other layer, area, or component, or an intermediary layer, intermediary area, or intermediary component may exist. However, "direct connection / direct coupling" refers to a component being directly connected or directly coupled to another component without an intermediary component. Similarly, other expressions describing relationships between components, such as "between," "immediately adjacent to," or "adjacent to" and "directly adjacent to," can be interpreted similarly. Furthermore, it will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or there may be one or more intermediary elements or layers.

[0060] For the purposes of this disclosure, expressions such as “at least one of…”, “one of…”, or “selected from…” modify the entire column of elements but not individual elements within that column when preceding / following a list of elements. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of only X, only Y, only Z, two or more of X, Y, and Z (such as XYZ, XY, XZ, and YZ) or any variations thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B. Furthermore, in describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure”.

[0061] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, first component, first area, first layer, or first part described below may be designated as a second element, second component, second area, second layer, or second part.

[0062] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction DR1, the second direction DR2, and / or the third direction DR3.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It should also be understood that, when used in this specification, the terms “comprises,” “have,” and “includes” indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0064] As used herein, the terms “substantially,” “approximately,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to explain the inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), “approximately” or “approximately” as used herein includes stated values ​​and indicates a range of acceptable deviations from a particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0065] When one or more embodiments can be implemented differently, a particular process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0066] Furthermore, any numerical range disclosed and / or described herein is intended to include all subranges with the same numerical precision contained within the described range. For example, the range “1.0 to 10.0” is intended to include all subranges between the described minimum value of 1.0 and the described maximum value of 10.0 (and includes both the minimum value of 1.0 and the maximum value of 10.0), such as having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described herein is intended to include all higher numerical limits contained therein. Therefore, the applicant reserves the right to amend this specification (including the claims) to expressly describe any subranges contained within the range expressly described herein.

[0067] Electronic or electrical devices and / or any other related devices or components according to one or more embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed in an integrated circuit (IC) chip or a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, a tape-on-a-carrier package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0068] Furthermore, the various components of these devices can be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented in the computing device using standard memory devices such as random access memory (RAM). The computer program instructions can also be stored on other non-transitory computer-readable media, such as read-only optical disc storage (CD-ROM) and / or flash memory drives. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0069] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent, for example, with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense.

[0070] It will be appreciated by those skilled in the art that, in view of the whole of this disclosure, unless otherwise stated or implied, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with one another, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0071] Figure 1 This is a schematic diagram illustrating a display device according to one or more embodiments.

[0072] Reference Figure 1 The display device DD according to one or more embodiments can be an electricalally activated device. For example, the display device DD can be a small display device for small electronic devices (such as smartphones, mobile phones, smartwatches, game consoles, and / or cameras). However, this disclosure is not limited thereto, and the display device DD can be a medium to large display device for medium to large electronic devices (such as personal computers (PCs) (e.g., laptops, tablets), televisions, computer monitors, vehicle monitors, and / or external billboards).

[0073] The upper surface of the display device DD can be defined as the display surface IS. The display surface IS can be a surface parallel to a plane formed on a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The image generated by the display device DD can be provided to the user through the display surface IS.

[0074] The display device DD may include a display area DA and a non-display area NDA. For example, a display surface IS may include a display area DA and a non-display area NDA. The display area DA may be an area in which an image is displayed. For example, the display area DA may be an area that generates light or modulates the transmittance of light provided from an external light source to display an image. The non-display area NDA may be around at least a portion of the display area DA along its edge or periphery (e.g., it may surround at least a portion of the display area DA). In one or more embodiments, the non-display area NDA may be an area in which no image is displayed. However, this disclosure is not limited thereto, and an image may be displayed in a portion of the non-display area NDA. The non-display area NDA may include a plurality of drivers. Reference may be made later. Figure 2 Describes multiple drivers.

[0075] Multiple pixels can be located within a display area DA. For example, a first pixel PX1, a second pixel PX2, and a third pixel PX3 can be located within the display area DA. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can emit light. In one or more embodiments, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can emit light with different wavelengths from each other. For example, the first pixel PX1 can emit green light, the second pixel PX2 can emit red light, and the third pixel PX3 can emit blue light, but this disclosure is not limited thereto. The first pixel PX1, the second pixel PX2, and the third pixel PX3 can be spaced apart from each other in a planar view (e.g., spaced apart). The multiple pixels can be located collectively within the display area DA. Therefore, the display area DA can display an image.

[0076] The display device DD may include a housing HZ and a window WM. The housing HZ and the window WM may be coupled to form the appearance of the display device DD. The housing HZ may protect the components included in the display device DD from external impacts. The housing HZ may include a material with relatively high rigidity. For example, the housing HZ may include glass, plastic, and / or metal. These materials may be used alone or in combination with each other. The window WM may be coupled to the housing HZ. For example, the window WM may be ultra-thin glass and / or polyimide film, but this disclosure is not limited thereto.

[0077] In one or more embodiments, a first direction DR1 and a second direction DR2 intersecting the first direction DR1 may be defined. For example, the second direction DR2 may be substantially perpendicular to the first direction DR1. However, this disclosure is not limited thereto, and the second direction DR2 may form an acute or obtuse angle with the first direction DR1. Additionally, a third direction DR3 intersecting the plane formed by the first direction DR1 and the second direction DR2 may be defined. For example, the third direction DR3 may be substantially perpendicular to the plane formed by the first direction DR1 and the second direction DR2. However, this disclosure is not limited thereto, and the third direction DR3 may form an acute or obtuse angle with the plane formed by the first direction DR1 and the second direction DR2.

[0078] Figure 2 It is shown Figure 1 A block diagram of the display device.

[0079] Reference Figure 2 The display device DD may include a drive controller 100, a scan driver 200, a gamma reference voltage generator 300, a data driver 400, and a voltage generator 500. As described above, the non-display area (e.g., Figure 1 The non-display area (NDA) may include multiple drivers, and the multiple drivers may include a drive controller 100, a scan driver 200, a gamma reference voltage generator 300, a data driver 400, and a voltage generator 500.

[0080] The drive controller 100 can receive input image data IMG and input control signal CONT from an external device. In one or more embodiments, the input image data IMG may include red image data, green image data, and blue image data. In one or more embodiments, the input image data IMG may include white image data. In one or more embodiments, the input image data IMG may include magenta image data, yellow image data, and / or cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0081] The drive controller 100 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT. For example, the drive controller 100 can generate the first control signal CONT1 based on the input control signal CONT and output the first control signal CONT1 to the scan driver 200. The first control signal CONT1 may include a vertical start signal and a gate clock signal. Additionally, the drive controller 100 can generate the second control signal CONT2 based on the input control signal CONT and output the second control signal CONT2 to the gamma reference voltage generator 300. Furthermore, the drive controller 100 can generate the third control signal CONT3 based on the input control signal CONT and output the third control signal CONT3 to the data driver 400. The third control signal CONT3 may include a horizontal start signal and a load signal. Finally, the drive controller 100 can generate the fourth control signal CONT4 based on the input control signal CONT and output the fourth control signal CONT4 to the voltage generator 500. In addition, the drive controller 100 can generate a data signal DATA based on the input image data IMG and output the data signal DATA to the data driver 400.

[0082] The scan driver 200 can output signals to the signal lines in response to the first control signal CONT1. For example, the scan driver 200 can output signals to the scan signal lines SCL1 to SCLn and the sensing signal lines SSL1 to SSLn in response to the first control signal CONT1. Here, n is a positive integer. For example, the scan driver 200 can output scan signals to the scan signal lines SCL1 to SCLn (e.g., Figure 3 The scan signal SC), and output the sensing signal to the sensing signal lines SSL1 to SSLn (e.g., Figure 3 The sensing signal SS).

[0083] The gamma reference voltage generator 300 can generate a gamma reference voltage VGREF in response to the second control signal CONT2. The gamma reference voltage generator 300 can provide the gamma reference voltage VGREF to the data driver 400. For example, the gamma reference voltage VGREF can have a value corresponding to the data signal DATA.

[0084] The data driver 400 can receive inputs of a third control signal CONT3 and a data signal DATA from the drive controller 100. Additionally, the data driver 400 can receive inputs of a gamma reference voltage VGREF from the gamma reference voltage generator 300. The data driver 400 can use the gamma reference voltage VGREF to convert the data signal DATA into an analog data voltage (e.g., ...). Figure 3 The data voltage (DT). The data driver 400 can output the data voltage to data lines DL1 to DLm. Here, m is a positive integer.

[0085] Voltage generator 500 can generate a first power voltage ELVDD, a second power voltage ELVSS, and an initialization voltage VINT in response to a fourth control signal CONT4. Voltage generator 500 can output the first power voltage ELVDD, the second power voltage ELVSS, and the initialization voltage VINT to the display area DA.

[0086] Figure 2 Examples of the positions of multiple drivers can be shown. For example, scan driver 200 may be spaced apart from display area DA in a direction opposite to the first direction DR1 (e.g., spaced apart), gamma reference voltage generator 300 and data driver 400 may be spaced apart from display area DA in a direction opposite to the second direction DR2 (e.g., spaced apart), and voltage generator 500 may be spaced apart from display area DA in the second direction DR2 (e.g., spaced apart). However, this disclosure is not limited thereto, and the positions of the multiple drivers may be varied according to embodiments.

[0087] The display area DA can be electrically connected to scan signal lines SCL1 to SCLn, sensing signal lines SSL1 to SSLn, and data lines DL1 to DLm. The first pixel PX1 can be connected to the corresponding scan signal line among the scan signal lines SCL1 to SCLn, the corresponding sensing signal line among the sensing signal lines SSL1 to SSLn, and the corresponding data line among the data lines DL1 to DLm. Additionally, the second pixel PX2 can be connected to the corresponding scan signal line among the scan signal lines SCL1 to SCLn, the corresponding sensing signal line among the sensing signal lines SSL1 to SSLn, and the corresponding data line among the data lines DL1 to DLm. Furthermore, the third pixel PX3 can be connected to the corresponding scan signal line among the scan signal lines SCL1 to SCLn, the corresponding sensing signal line among the sensing signal lines SSL1 to SSLn, and the corresponding data line among the data lines DL1 to DLm.

[0088] In one or more embodiments, scan signal lines SCL1 to SCLn may extend in a first direction DR1 and be arranged along a second direction DR2. Additionally, sensing signal lines SSL1 to SSLn may extend in the first direction DR1 and be arranged along the second direction DR2. Furthermore, data lines DL1 to DLm may extend in the second direction DR2 and be arranged along the first direction DR1. However, this disclosure is not limited thereto, and the extension and arrangement directions of the scan signal lines SCL1 to SCLn, the sensing signal lines SSL1 to SSLn, and the data lines DL1 to DLm may vary depending on the embodiment.

[0089] Figure 3 This is a schematic diagram showing the equivalent circuit of a pixel.

[0090] Specifically, Figure 3 It is shown Figure 2 The circuit diagram of the first pixel PX1, the second pixel PX2, and the third pixel PX3 included in the display device DD. For example, Figure 2 Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 in the image can have Figure 3 The circuit diagram shown is shown.

[0091] Reference Figure 3 A pixel PX may include a light-emitting element LED and a pixel driving circuit section PXC electrically connected to the light-emitting element LED. The pixel driving circuit section PXC may include a first transistor T1, a second transistor T2, a third transistor T3, and a capacitor CST.

[0092] In one or more embodiments, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be an n-type transistor. The active pattern of the n-type transistor may include an oxide semiconductor material. However, this disclosure is not limited thereto, and the active pattern of the n-type transistor may include a silicon semiconductor material.

[0093] In one or more embodiments, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be a p-type transistor. In one or more embodiments, some of the first transistor T1, the second transistor T2, and the third transistor T3 may be n-type transistors, and the others may be p-type transistors. The active pattern of the p-type transistor may include silicon semiconductor material.

[0094] The pixel driving circuit section PXC can be electrically connected to the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, the scan signal line SCL, the sensing signal line SSL, and the data line DL.

[0095] A first voltage line VL1 can apply a first power voltage ELVDD to the pixel driving circuit section PXC. A second voltage line VL2 can apply a second power voltage ELVSS to the pixel driving circuit section PXC. In one or more embodiments, the voltage level of the first power voltage ELVDD can be higher than the voltage level of the second power voltage ELVSS. A third voltage line VL3 can apply an initialization voltage VINT to the pixel driving circuit section PXC. A scan signal line SCL can apply a scan signal SC to the pixel driving circuit section PXC. A sensing signal line SSL can apply a sensing signal SS to the pixel driving circuit section PXC.

[0096] The first transistor T1 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the first transistor T1 may be connected to a first node N1. The first terminal of the first transistor T1 may be connected to a first voltage line VL1. The second terminal of the first transistor T1 may be connected to a fifth node N5. The first transistor T1 may provide a drive current ID to a light-emitting element LED. For example, the first transistor T1 may be referred to as a drive transistor.

[0097] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor T2 may be connected to the scan signal line SCL. The first terminal of the second transistor T2 may be connected to the second node N2. The second terminal of the second transistor T2 may be connected to the first node N1.

[0098] The gate terminal of the second transistor T2 can receive the scan signal SC via the scan signal line SCL. The second transistor T2 can be turned on or off in response to the scan signal SC. For example, when the second transistor T2 is an n-type transistor, it can be turned off when the scan signal SC has a negative voltage level and turned on when the scan signal SC has a positive voltage level. Conversely, when the second transistor T2 is a p-type transistor, it can be turned off when the scan signal SC has a positive voltage level and turned on when the scan signal SC has a negative voltage level. The first terminal of the second transistor T2 can receive the data voltage DT via the data line DL. For example, the first terminal of the second transistor T2 can receive the data voltage DT via the second node N2. The second terminal of the second transistor T2 can supply the data voltage DT to the first node N1 during the period when the second transistor T2 is on. Therefore, the second transistor T2 can drive the first transistor T1. For example, the second transistor T2 can be referred to as the first switching transistor.

[0099] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor T3 can be connected to the sensing signal line SSL. The first terminal of the third transistor T3 can be connected to the third node N3. The second terminal of the third transistor T3 can be connected to the fourth node N4.

[0100] The gate terminal of the third transistor T3 can receive the sensing signal SS via the sensing signal line SSL. The third transistor T3 can be turned on or off in response to the sensing signal SS. For example, when the third transistor T3 is an n-type transistor, it can be turned off when the sensing signal SS has a negative voltage level and turned on when the sensing signal SS has a positive voltage level. Conversely, when the third transistor T3 is a p-type transistor, it can be turned off when the sensing signal SS has a positive voltage level and turned on when the sensing signal SS has a negative voltage level. The third transistor T3 can receive the initialization voltage VINT via the third voltage line VL3. For example, the third transistor T3 can receive the initialization voltage VINT via the third node N3. During the period when the third transistor T3 is on, it can provide the initialization voltage VINT to the fifth node N5. Therefore, the third transistor T3 can initialize the first electrode of the light-emitting element LED. For example, the third transistor T3 can be referred to as the second switching transistor.

[0101] The capacitor CST may include a first terminal and a second terminal. The first terminal of the capacitor CST may be connected to a first node N1. The second terminal of the capacitor CST may be connected to a fourth node N4. The charge corresponding to the difference between the voltage at the gate terminal of the first transistor T1 and the voltage at the second terminal of the first transistor T1 may be stored in the capacitor CST.

[0102] The light-emitting element (LED) may include a first terminal and a second terminal. The first terminal of the LED may be connected to the fifth node N5. The second terminal of the LED may be connected to the second voltage line VL2. For example, the first terminal of the LED may be an anode terminal, and the second terminal of the LED may be a cathode terminal.

[0103] like Figure 3 As shown, the pixel driving circuit section PXC may include three transistors and one capacitor. However, this disclosure is not limited thereto, and the number of transistors and capacitors included in the pixel driving circuit section PXC may vary depending on the embodiment.

[0104] Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 This illustrates one or more embodiments. Figure 1 The layout diagram of pixels included in the display device.

[0105] Specifically, Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 It can be shown Figure 2 The arrangement of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0106] Reference Figure 4 Display devices (e.g., Figure 2 The display device (DD) may include a lower metal layer (BML). The lower metal layer (BML) may include a first lower metal pattern 1010, a second lower metal pattern 1020, a third lower metal pattern 1030, a fourth lower metal pattern 1040, a fifth lower metal pattern 1050, a sixth lower metal pattern 1060, a seventh lower metal pattern 1070, an eighth lower metal pattern 1080, a ninth lower metal pattern 1090, a tenth lower metal pattern 1100, an eleventh lower metal pattern 1110, a twelfth lower metal pattern 1120, and a thirteenth lower metal pattern 1130.

[0107] The first metal pattern 1010, the second metal pattern 1020, the third metal pattern 1030, the fourth metal pattern 1040, the fifth metal pattern 1050, the sixth metal pattern 1060, the seventh metal pattern 1070, the eighth metal pattern 1080, the ninth metal pattern 1090, the tenth metal pattern 1100, the eleventh metal pattern 1110, the twelfth metal pattern 1120, and the thirteenth metal pattern 1130 can be separated from each other in the planar diagram (e.g., spaced apart).

[0108] The first lower metal pattern 1010 may be spaced apart from the second lower metal pattern 1020 in a direction opposite to the first direction DR1. The first lower metal pattern 1010 may extend in the second direction DR2. In an embodiment, Figure 3 The second electrical voltage ELVSS can be applied to the first lower metal pattern 1010. For example, the first lower metal pattern 1010 can be... Figure 3 At least a portion of the second voltage line VL2.

[0109] The second lower metal pattern 1020 may be spaced apart (e.g., spaced apart) from the third lower metal pattern 1030, the fourth lower metal pattern 1040, and the fifth lower metal pattern 1050 in a direction opposite to the first direction DR1. The second lower metal pattern 1020 may extend in the second direction DR2. In one or more embodiments, Figure 3 The data voltage DT can be applied to the second lower metal pattern 1020. For example, the red data voltage can be applied to the second lower metal pattern 1020, but this disclosure is not limited thereto. For example, the second lower metal pattern 1020 can be... Figure 3 At least a portion of the data cable DL.

[0110] The third lower metal pattern 1030 may be separated from the fourth lower metal pattern 1040 in a direction opposite to the second direction DR2 (e.g., spaced apart). Additionally, the third lower metal pattern 1030 may be separated from the sixth lower metal pattern 1060 in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0111] The fourth lower metal pattern 1040 may be separated from the fifth lower metal pattern 1050 in a direction opposite to the second direction DR2 (e.g., spaced apart). In addition, the fourth lower metal pattern 1040 may be separated from the sixth lower metal pattern 1060 in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0112] The fifth lower metal pattern 1050 may be separated from the sixth lower metal pattern 1060 in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0113] The sixth lower metal pattern 1060 may be spaced apart from the seventh lower metal pattern 1070 in a direction opposite to the first direction DR1 (e.g., spaced apart). The sixth lower metal pattern 1060 may extend in the second direction DR2. In one or more embodiments, Figure 3 The initialization voltage VINT can be applied to the sixth lower metal pattern 1060. For example, the sixth lower metal pattern 1060 can be... Figure 3 At least a portion of the third voltage line VL3.

[0114] The seventh lower metal pattern 1070 may be spaced apart (e.g., spaced apart) from the eighth lower metal pattern 1080, the ninth lower metal pattern 1090, the tenth lower metal pattern 1100, and the eleventh lower metal pattern 1110 in a direction opposite to the first direction DR1. The seventh lower metal pattern 1070 may extend in the second direction DR2. In one or more embodiments, Figure 3 The first electrical voltage ELVDD can be applied to the seventh lower metal pattern 1070. For example, the seventh lower metal pattern 1070 can be... Figure 3At least a portion of the first voltage line VL1. For example, the seventh lower metal pattern 1070 can be referred to as a voltage line.

[0115] The eighth lower metal pattern 1080 may be separated from the twelfth lower metal pattern 1120 in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the eighth lower metal pattern 1080 may be separated from the ninth lower metal pattern 1090 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0116] The ninth lower metal pattern 1090 may be separated from the twelfth lower metal pattern 1120 in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the ninth lower metal pattern 1090 may be separated from the tenth lower metal pattern 1100 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0117] The tenth lower metal pattern 1100 may be separated from the twelfth lower metal pattern 1120 in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the tenth lower metal pattern 1100 may be separated from the eleventh lower metal pattern 1110 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0118] The eleventh lower metal pattern 1110 may be separated from the twelfth lower metal pattern 1120 in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0119] The twelfth lower metal pattern 1120 may be spaced apart from the thirteenth lower metal pattern 1130 in a direction opposite to the first direction DR1 (e.g., spaced apart). The twelfth lower metal pattern 1120 may extend in the second direction DR2. In one or more embodiments, Figure 3 The data voltage DT can be applied to the twelfth lower metal pattern 1120. For example, the green data voltage can be applied to the twelfth lower metal pattern 1120, but this disclosure is not limited thereto. For example, the twelfth lower metal pattern 1120 can be... Figure 3 At least a portion of the data cable DL.

[0120] The thirteenth lower metal pattern 1130 can extend in the second direction DR2. In one or more embodiments, Figure 3 The data voltage DT can be applied to the thirteenth lower metal pattern 1130. For example, the blue data voltage can be applied to the thirteenth lower metal pattern 1130, but this disclosure is not limited thereto. For example, the thirteenth lower metal pattern 1130 can be... Figure 3 At least a portion of the data cable DL.

[0121] For example, the lower metal layer (BML) may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals may include silver (“Ag”), molybdenum (“Mo”), aluminum (“Al”), tungsten (“W”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), and / or scandium (“Sc”). These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide. These materials may be used alone or in combination with each other. Additionally, examples of metal nitrides may include aluminum nitride (“AlN”). x ), Tungsten nitride ("WN") x ") and / or chromium nitride ("CrN") x These materials can be used individually or in combination with each other.

[0122] Reference Figure 5 The active layer ACT can be located in the lower metal layer (e.g., Figure 4 The active layer ACT may include a first active pattern 2010, a second active pattern 2020, a third active pattern 2030, a fourth active pattern 2040, a fifth active pattern 2050, a sixth active pattern 2060, a seventh active pattern 2070, an eighth active pattern 2080, a ninth active pattern 2090, and a tenth active pattern 2100.

[0123] The first active pattern 2010, the second active pattern 2020, the third active pattern 2030, the fourth active pattern 2040, the fifth active pattern 2050, the sixth active pattern 2060, the seventh active pattern 2070, the eighth active pattern 2080, the ninth active pattern 2090 and the tenth active pattern 2100 can be separated from each other in the planar diagram (e.g., spaced apart).

[0124] The first active pattern 2010 may include a first region A1, a first channel region CH1, and a second region A2. The first region A1 and the second region A2 may be spaced apart from each other in a plan view (e.g., separated). For example, the first region A1 and the second region A2 may be spaced apart from each other (e.g., separated), and the first channel region CH1 is located between the first region A1 and the second region A2. For example, the first channel region CH1 may be located between the first region A1 and the second region A2. The first region A1 and the second region A2 may have higher conductivity than the first channel region CH1.

[0125] The second active pattern 2020 may include a third region A3, a second channel region CH2, and a fourth region A4. The third region A3 and the fourth region A4 may be spaced apart from each other in a plan view (e.g., separated). For example, the third region A3 and the fourth region A4 may be spaced apart from each other (e.g., separated), and the second channel region CH2 is located between the third region A3 and the fourth region A4. For example, the second channel region CH2 may be located between the third region A3 and the fourth region A4. The third region A3 and the fourth region A4 may have higher conductivity than the second channel region CH2.

[0126] In one or more embodiments, the third active pattern 2030 may include a single region. For example, the third active pattern 2030 may include a single region having a substantially constant conductivity across the third active pattern 2030, but this disclosure is not limited thereto.

[0127] The fourth active pattern 2040 may include a fifth region A5, a third channel region CH3, and a sixth region A6. The fifth region A5 and the sixth region A6 may be spaced apart from each other in a planar view (e.g., separated). For example, the fifth region A5 and the sixth region A6 may be spaced apart from each other (e.g., separated), and the third channel region CH3 may be located between the fifth region A5 and the sixth region A6. For example, the third channel region CH3 may be located between the fifth region A5 and the sixth region A6. The fifth region A5 and the sixth region A6 may have higher conductivity than the third channel region CH3.

[0128] The fifth active pattern 2050 may include a seventh region A7, a fourth channel region CH4, and an eighth region A8. The seventh region A7 and the eighth region A8 may be spaced apart from each other in a planar view (e.g., separated). For example, the seventh region A7 and the eighth region A8 may be spaced apart from each other, and the fourth channel region CH4 may be located between the seventh region A7 and the eighth region A8. For example, the fourth channel region CH4 may be located between the seventh region A7 and the eighth region A8. The seventh region A7 and the eighth region A8 may have higher conductivity than the fourth channel region CH4.

[0129] The sixth active pattern 2060 may include a ninth region A9, a fifth channel region CH5, and a tenth region A10. The ninth region A9 and the tenth region A10 may be spaced apart from each other in a planar view (e.g., separated). For example, the ninth region A9 and the tenth region A10 may be spaced apart from each other, and the fifth channel region CH5 may be located between the ninth region A9 and the tenth region A10. For example, the fifth channel region CH5 may be located between the ninth region A9 and the tenth region A10. The ninth region A9 and the tenth region A10 may have higher conductivity than the fifth channel region CH5.

[0130] The seventh active pattern 2070 may include an eleventh region A11, a sixth channel region CH6, and a twelfth region A12. The eleventh region A11 and the twelfth region A12 may be spaced apart from each other in a planar view (e.g., separated). For example, the eleventh region A11 and the twelfth region A12 may be spaced apart from each other (e.g., separated), and the sixth channel region CH6 is located between the eleventh region A11 and the twelfth region A12. For example, the sixth channel region CH6 may be located between the eleventh region A11 and the twelfth region A12. The eleventh region A11 and the twelfth region A12 may have higher conductivity than the sixth channel region CH6.

[0131] The eighth active pattern 2080 may include a thirteenth region A13, a seventh channel region CH7, and a fourteenth region A14. The thirteenth region A13 and the fourteenth region A14 may be spaced apart from each other in a plan view (e.g., spaced apart). For example, the thirteenth region A13 and the fourteenth region A14 may be spaced apart from each other (e.g., spaced apart), and the seventh channel region CH7 is located between the thirteenth region A13 and the fourteenth region A14. For example, the seventh channel region CH7 may be located between the thirteenth region A13 and the fourteenth region A14. The thirteenth region A13 and the fourteenth region A14 may have higher conductivity than the seventh channel region CH7.

[0132] The ninth active pattern 2090 may include a fifteenth region A15, an eighth channel region CH8, and a sixteenth region A16. The fifteenth region A15 and the sixteenth region A16 may be spaced apart from each other in a planar view (e.g., spaced apart). For example, the fifteenth region A15 and the sixteenth region A16 may be spaced apart from each other (e.g., spaced apart), and the eighth channel region CH8 may be located between the fifteenth region A15 and the sixteenth region A16. For example, the eighth channel region CH8 may be located between the fifteenth region A15 and the sixteenth region A16. The fifteenth region A15 and the sixteenth region A16 may have higher conductivity than the eighth channel region CH8.

[0133] The tenth active pattern 2100 may include a seventeenth region A17, a ninth channel region CH9, and an eighteenth region A18. The seventeenth region A17 and the eighteenth region A18 may be spaced apart from each other in a planar view (e.g., spaced apart). For example, the seventeenth region A17 and the eighteenth region A18 may be spaced apart from each other (e.g., spaced apart), and the ninth channel region CH9 is located between the seventeenth region A17 and the eighteenth region A18. For example, the ninth channel region CH9 may be located between the seventeenth region A17 and the eighteenth region A18. The seventeenth region A17 and the eighteenth region A18 may have higher conductivity than the ninth channel region CH9.

[0134] For example, the active layer ACT may include inorganic semiconductors (e.g., amorphous silicon, polycrystalline silicon, metal oxide semiconductors) and / or organic semiconductors. These materials may be used alone or in combination with each other. The active layer ACT may include a source region, a drain region, and a channel region located between the source region and the drain region. The metal oxide semiconductor may include binary compounds (“AB”) comprising indium (“In”), zinc (“Zn”), gallium (“Ga”), tin (“Sn”), titanium (“Ti”), aluminum (“Al”), hafnium (“Hf”), zirconium (“Zr”), and / or magnesium (“Mg”). x ), ternary compounds ("AB") x C y ") and / or quaternary compounds ("AB") x C y D z These materials can be used alone or in combination with each other. For example, metal oxide semiconductors can include zinc oxide ("ZnO"). x Gallium oxide (GaO) x "), Tin oxide ("SnO") x Indium oxide (InO) x Indium gallium oxide (“IGO”), indium zinc oxide (“IZO”), indium tin oxide (“ITO”), indium zinc tin oxide (“IZTO”) and / or indium gallium zinc oxide (“IGZO”). These materials can be used alone or in combination with each other.

[0135] Reference Figure 4 , Figure 5 and Figure 6 The capacitor CSTA may include a portion of the ninth lower metal pattern 1090 and a portion of the fifth active pattern 2050. For example, the capacitor CSTA may include a portion of the seventh region A7 and the portion of the ninth lower metal pattern 1090. The portion of the seventh region A7 and the portion of the ninth lower metal pattern 1090 may overlap each other in a planar view. The capacitor CSTA may be... Figure 8 The capacitor included in the first pixel driving circuit section PXCa.

[0136] The capacitor CSTb may include a portion of a fourth lower metal pattern 1040 and a portion of a third active pattern 2030. The portions of the fourth lower metal pattern 1040 and the third active pattern 2030 may overlap each other in a planar view. The capacitor CSTb may be... Figure 8 The capacitor included in the second pixel driving circuit section PXCb.

[0137] The capacitor CSTc may include a portion of the tenth lower metal pattern 1100 and a portion of the ninth active pattern 2090. For example, the capacitor CSTc may include a portion of the fifteenth region A15 and the portion of the tenth lower metal pattern 1100. The portion of the fifteenth region A15 and the portion of the tenth lower metal pattern 1100 may overlap each other in a planar view. The capacitor CSTc may be... Figure 8 The capacitor included in the third pixel driving circuit section PXCc.

[0138] Reference Figure 7 The metal layer MTL can be located in the active layer (e.g., Figure 5 On the active layer (ACT). The metal layer MTL may include a first metal pattern 3010, a second metal pattern 3020, a third metal pattern 3030, a fourth metal pattern 3040, a fifth metal pattern 3050, a sixth metal pattern 3060, a seventh metal pattern 3070, an eighth metal pattern 3080, a ninth metal pattern 3090, a tenth metal pattern 3100, an eleventh metal pattern 3110, a twelfth metal pattern 3120, a thirteenth metal pattern 3130, a fourteenth metal pattern 3140, a fifteenth metal pattern 3150, a sixteenth metal pattern 3160, a seventeenth metal pattern 3170, an eighteenth metal pattern 3180, a nineteenth metal pattern 3190, and a twentieth metal pattern 3200.

[0139] The first metal pattern 3010, the second metal pattern 3020, the third metal pattern 3030, the fourth metal pattern 3040, the fifth metal pattern 3050, the sixth metal pattern 3060, the seventh metal pattern 3070, the eighth metal pattern 3080, the ninth metal pattern 3090, the tenth metal pattern 3100, the eleventh metal pattern 3110, the twelfth metal pattern 3120, the thirteenth metal pattern 3130, the fourteenth metal pattern 3140, the fifteenth metal pattern 3150, the sixteenth metal pattern 3160, the seventeenth metal pattern 3170, the eighteenth metal pattern 3180, the nineteenth metal pattern 3190, and the twentieth metal pattern 3200 may be separated from each other in the planar view (e.g., spaced apart).

[0140] In one or more embodiments, the first metal pattern 3010 may include a first portion 3011, a second portion 3012, and a third portion 3013. The first portion 3011 may extend in a first direction DR1. Each of the second portion 3012 and the third portion 3013 may be a portion extending from the first portion 3011. For example, each of the second portion 3012 and the third portion 3013 may be a portion extending from the first portion 3011 in a second direction DR2. In one or more embodiments, Figure 3The sensing signal SS can be applied to the first metal pattern 3010. For example, the first metal pattern 3010 can be... Figure 3 At least a portion of the sensing signal line SSL.

[0141] The second metal pattern 3020 may be located between the first portion 3011 and the first portion 3181 of the eighteenth metal pattern 3180, which will be described later. Additionally, the second metal pattern 3020 may be spaced apart (e.g., spaced apart) from the third metal pattern 3030, the eighth metal pattern 3080, and the seventeenth metal pattern 3170 in a direction opposite to the first direction DR1. The second metal pattern 3020 may extend in the second direction DR2.

[0142] The third metal pattern 3030 may be spaced apart from the first portion 3011 in the second direction DR2 (e.g., spaced apart). Additionally, the third metal pattern 3030 may be spaced apart from the fourth metal pattern 3040 in a direction opposite to the first direction DR1 (e.g., spaced apart). Furthermore, the third metal pattern 3030 may be spaced apart from the eighth metal pattern 3080 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0143] The fourth metal pattern 3040 may be located between the second portion 3012 and the third portion 3013 in the plan view. In addition, the fourth metal pattern 3040 may be spaced apart from the first portion 3011 in the second direction DR2 (e.g., spaced apart).

[0144] The fifth metal pattern 3050 may be spaced apart from the first portion 3011 in the second direction DR2 (e.g., spaced apart). Additionally, the fifth metal pattern 3050 may be spaced apart from the third portion 3013 in the first direction DR1 (e.g., spaced apart). Furthermore, the fifth metal pattern 3050 may be spaced apart from the sixth metal pattern 3060 in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0145] The sixth metal pattern 3060 may be spaced apart from the first portion 3011 in the second direction DR2 (e.g., spaced apart). Additionally, the sixth metal pattern 3060 may be spaced apart from the eleventh metal pattern 3110 in a direction opposite to the second direction DR2 (e.g., spaced apart). Furthermore, the sixth metal pattern 3060 may be spaced apart from the seventh metal pattern 3070 in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0146] The seventh metal pattern 3070 may be spaced apart from the first portion 3011 in the second direction DR2 (e.g., spaced apart). In addition, the seventh metal pattern 3070 may be spaced apart from the eleventh metal pattern 3110 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0147] The eighth metal pattern 3080 may be spaced apart from the ninth metal pattern 3090 in a direction opposite to the first direction DR1 (e.g., spaced apart). For example, in a plan view, the eighth metal pattern 3080 may be located between the second metal pattern 3020 and the ninth metal pattern 3090.

[0148] The ninth metal pattern 3090 may be spaced apart from the tenth metal pattern 3100 in a direction opposite to the first direction DR1 (e.g., spaced apart). For example, in a plan view, the ninth metal pattern 3090 may be located between the eighth metal pattern 3080 and the tenth metal pattern 3100.

[0149] The tenth metal pattern 3100 may be separated from the thirteenth metal pattern 3130 in a direction opposite to the first direction DR1 (e.g., spaced apart). For example, in a plan view, the tenth metal pattern 3100 may be located between the ninth metal pattern 3090 and the thirteenth metal pattern 3130.

[0150] The eleventh metal pattern 3110 may be separated from the fifteenth metal pattern 3150 and the sixteenth metal pattern 3160 in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the eleventh metal pattern 3110 may be separated from the thirteenth metal pattern 3130 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0151] The twelfth metal pattern 3120 may be separated from the first portion 3181 of the eighteenth metal pattern 3180 in a direction opposite to the second direction DR2 (e.g., spaced apart). In addition, the twelfth metal pattern 3120 may be separated from the second portion 3182 of the eighteenth metal pattern 3180, which will be described later, in the first direction DR1 (e.g., spaced apart).

[0152] The thirteenth metal pattern 3130 may be separated from the fourteenth metal pattern 3140 in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the thirteenth metal pattern 3130 may be separated from the first portion 3181 of the eighteenth metal pattern 3180 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0153] The fourteenth metal pattern 3140 may be separated from the third portion 3183 of the eighteenth metal pattern 3180, which will be described later, in a direction opposite to the first direction DR1 (e.g., spaced apart). Additionally, the fourteenth metal pattern 3140 may be separated from the first portion 3181 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0154] The fifteenth metal pattern 3150 may be separated from the third portion 3183 of the eighteenth metal pattern 3180 in the first direction DR1 (e.g., spaced apart). In addition, the fifteenth metal pattern 3150 may be separated from the sixteenth metal pattern 3160 in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0155] The sixteenth metal pattern 3160 can be positioned adjacent to the third part 3183 of the eighteenth metal pattern 3180.

[0156] The seventeenth metal pattern 3170 may be separated from the second portion 3182 of the eighteenth metal pattern 3180 in a direction opposite to the first direction DR1 (e.g., spaced apart). For example, in a plan view, the seventeenth metal pattern 3170 may be located between the second metal pattern 3020 and the second portion 3182 of the eighteenth metal pattern 3180.

[0157] In one or more embodiments, the eighteenth metal pattern 3180 may include a first portion 3181, a second portion 3182, and a third portion 3183. The first portion 3181 may extend in a first direction DR1. Each of the second portion 3182 and the third portion 3183 may be a portion extending from the first portion 3181. For example, each of the second portion 3182 and the third portion 3183 may be a portion extending from the first portion 3181 in a direction opposite to the second direction DR2. In one or more embodiments, Figure 3 The scanning signal SC can be applied to the eighteenth metal pattern 3180. For example, the eighteenth metal pattern 3180 can be... Figure 3 At least a portion of the scan signal line SCL.

[0158] The nineteenth metal pattern 3190 may be separated from the eighteenth metal pattern 3180 in the second direction DR2 (e.g., spaced apart). The nineteenth metal pattern 3190 may extend in the first direction DR1.

[0159] The twentieth metal pattern 3200 may be spaced apart from the first metal pattern 3010 in a direction opposite to the second direction DR2 (e.g., spaced apart). For example, the twentieth metal pattern 3200 may be spaced apart from the first portion 3011 of the first metal pattern 3010 in a direction opposite to the second direction DR2 (e.g., spaced apart). The twentieth metal pattern 3200 may extend in the first direction DR1.

[0160] For example, the metal layer MTL can include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals can include silver (“Ag”), molybdenum (“Mo”), aluminum (“Al”), tungsten (“W”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), and / or scandium (“Sc”). These materials can be used alone or in combination with each other. Examples of conductive metal oxides can include indium tin oxide and / or indium zinc oxide. These materials can be used alone or in combination with each other. Additionally, examples of metal nitrides can include aluminum nitride (“AlN”). x ), Tungsten nitride ("WN") x ") and / or chromium nitride ("CrN") x These materials can be used individually or in combination with each other.

[0161] Reference Figure 6 , Figure 7 and Figure 8 A portion of the metal layer MTL can be connected to a portion of the underlying metal layer BML via contact holes. Additionally, a portion of the metal layer MTL can be connected to a portion of the active layer ACT via contact holes. For example... Figure 8 As shown, the contact hole is represented by an "X" in a box.

[0162] In one or more embodiments, the display device (e.g., Figure 2 The display device (DD) may include a first pixel driving circuit portion PXCa, a second pixel driving circuit portion PXCb, and a third pixel driving circuit portion PXCc. For example, the first pixel driving circuit portion PXCa includes... Figure 2 In the first pixel PX1, the second pixel driving circuit portion PXCb is included Figure 2 The second pixel PX2, and the third pixel driving circuit portion PXCc may be included in Figure 2 In the third pixel PX3, however, this disclosure is not limited thereto. Furthermore, each of the first pixel driving circuit portion PXCa, the second pixel driving circuit portion PXCb, and the third pixel driving circuit portion PXCc can be connected to... Figure 3 The pixel driving circuit portion of the PXC has a substantially the same structure, but this disclosure is not limited thereto.

[0163] The first pixel driving circuit section PXCa may include a first transistor T1a, a second transistor T2a, a third transistor T3a, and a capacitor CSTA. The first transistor T1a may correspond to... Figure 3 The first transistor T1 and the second transistor T2a can correspond to Figure 3 The second transistor T2 and the third transistor T3a can correspond to Figure 3 The third transistor T3, and the capacitor CSTA can correspond to Figure 3 The capacitor CST.

[0164] The second pixel driving circuit section PXCb may include a first transistor T1b, a second transistor T2b, a third transistor T3b, and a capacitor CSTb. The first transistor T1b may correspond to... Figure 3 The first transistor T1 and the second transistor T2b can correspond to Figure 3 The second transistor T2 and the third transistor T3b can correspond to Figure 3 The third transistor T3, and the capacitor CSTb can correspond to Figure 3 The capacitor CST.

[0165] The third pixel driving circuit section PXCc may include a first transistor T1c, a second transistor T2c, a third transistor T3c, and a capacitor CSTc. The first transistor T1c may correspond to... Figure 3 The first transistor T1 and the second transistor T2c can correspond to Figure 3 The second transistor T2 and the third transistor T3c can correspond to Figure 3 The third transistor T3, and the capacitor CSTc can correspond to Figure 3 The capacitor CST.

[0166] The first transistor T1a may include a portion of the fourth active pattern 2040 (i.e., a portion of the fifth region A5, a portion of the sixth region A6, and the third channel region CH3) and a portion of the sixth metal pattern 3060 that overlaps with the third channel region CH3 in a planar view. For example, the portion of the sixth metal pattern 3060 that overlaps with the third channel region CH3 in a planar view may be referred to as the gate electrode of the first transistor T1a.

[0167] The second transistor T2a may include a portion of the fifth active pattern 2050 (i.e., a portion of the seventh region A7, a portion of the eighth region A8, and the fourth channel region CH4) and a portion of the third portion 3183 of the eighteenth metal pattern 3180 that overlaps with the fourth channel region CH4 in a planar view. For example, the portion of the third portion 3183 of the eighteenth metal pattern 3180 that overlaps with the fourth channel region CH4 in a planar view may be referred to as the gate electrode of the second transistor T2a.

[0168] The third transistor T3a may include a portion of the second active pattern 2020 (i.e., a portion of the third region A3, a portion of the fourth region A4, and the second channel region CH2) and a portion of the third portion 3013 of the first metal pattern 3010 that overlaps with the second channel region CH2 in a plan view. For example, the portion of the third portion 3013 of the first metal pattern 3010 that overlaps with the second channel region CH2 in a plan view may be referred to as the gate electrode of the third transistor T3a.

[0169] The first transistor T1b may include a portion of the seventh active pattern 2070 (i.e., a portion of the eleventh region A11, a portion of the twelfth region A12, and the sixth channel region CH6) and a portion of the ninth metal pattern 3090 that overlaps with the sixth channel region CH6 in a planar view. For example, the portion of the ninth metal pattern 3090 that overlaps with the sixth channel region CH6 in a planar view may be referred to as the gate electrode of the first transistor T1b.

[0170] The second transistor T2b may include a portion of the tenth active pattern 2100 (i.e., a portion of the seventeenth region A17, a portion of the eighteenth region A18, and the ninth channel region CH9) and a portion of the second portion 3182 of the eighteenth metal pattern 3180 that overlaps with the ninth channel region CH9 in a planar view. For example, the portion of the second portion 3182 of the eighteenth metal pattern 3180 that overlaps with the ninth channel region CH9 in a planar view may be referred to as the gate electrode of the second transistor T2b.

[0171] The third transistor T3b may include a portion of the first active pattern 2010 (i.e., a portion of the first region A1, a portion of the second region A2, and the first channel region CH1) and a portion of the second portion 3012 of the first metal pattern 3010 that overlaps with the first channel region CH1 in a plan view. For example, the portion of the second portion 3012 of the first metal pattern 3010 that overlaps with the first channel region CH1 in a plan view may be referred to as the gate electrode of the third transistor T3b.

[0172] The first transistor T1c may include a portion of the eighth active pattern 2080 (i.e., a portion of the thirteenth region A13, a portion of the fourteenth region A14, and the seventh channel region CH7) and a portion of the thirteenth metal pattern 3130 that overlaps with the seventh channel region CH7 in a planar view. For example, the portion of the thirteenth metal pattern 3130 that overlaps with the seventh channel region CH7 in a planar view may be referred to as the gate electrode of the first transistor T1c.

[0173] The second transistor T2c may include a portion of the ninth active pattern 2090 (i.e., a portion of the fifteenth region A15, a portion of the sixteenth region A16, and the eighth channel region CH8) and a portion of the third portion 3183 of the eighteenth metal pattern 3180 that overlaps with the eighth channel region CH8 in a planar view. For example, the portion of the third portion 3183 of the eighteenth metal pattern 3180 that overlaps with the eighth channel region CH8 in a planar view may be referred to as the gate electrode of the second transistor T2c.

[0174] The third transistor T3c may include a portion of the sixth active pattern 2060 (i.e., a portion of the ninth region A9, a portion of the tenth region A10, and the fifth channel region CH5) and a portion of the third portion 3013 of the first metal pattern 3010 that overlaps with the fifth channel region CH5 in a planar view. For example, the portion of the third portion 3013 of the first metal pattern 3010 that overlaps with the fifth channel region CH5 in a planar view may be referred to as the gate electrode of the third transistor T3c.

[0175] Also refer to Figure 4 In one or more embodiments, the first transistor T1a may be located on one side of the seventh lower metal pattern 1070. For example, the first transistor T1a may be spaced apart from the seventh lower metal pattern 1070 in the first direction DR1 (e.g., spaced apart). Additionally, the first transistor T1b may be located on the other side of the seventh lower metal pattern 1070. For example, the first transistor T1b may be spaced apart from the seventh lower metal pattern 1070 in a direction opposite to the first direction DR1 (e.g., spaced apart). Furthermore, the first transistor T1c may be located on one side of the seventh lower metal pattern 1070. For example, the first transistor T1c may be spaced apart from the seventh lower metal pattern 1070 in the first direction DR1 (e.g., spaced apart). As described above, Figure 3 The first electrical voltage ELVDD can be applied to the seventh lower metal pattern 1070, and the seventh lower metal pattern 1070 can be referred to as the voltage line. Each of the first transistors T1a and T1c can be located on one side of the voltage line, and the first transistor T1b can be located on the other side of the voltage line.

[0176] In one or more embodiments, the second transistor T2a may be located on one side of the seventh lower metal pattern 1070. For example, the second transistor T2a may be spaced apart from the seventh lower metal pattern 1070 in the first direction DR1. Additionally, the second transistor T2b may be located on the other side of the seventh lower metal pattern 1070. For example, the second transistor T2b may be spaced apart from the seventh lower metal pattern 1070 in a direction opposite to the first direction DR1. Furthermore, the second transistor T2c may be located on one side of the seventh lower metal pattern 1070. For example, the second transistor T2c may be spaced apart from the seventh lower metal pattern 1070 in the first direction DR1. Each of the second transistor T2a and the second transistor T2c may be located on one side of the voltage line, and the second transistor T2b may be located on the other side of the voltage line.

[0177] In one or more embodiments, the third transistor T3a may be located on the other side of the seventh lower metal pattern 1070. For example, the third transistor T3a may be spaced apart from the seventh lower metal pattern 1070 in a direction opposite to the first direction DR1. Additionally, the third transistor T3b may be located on the other side of the seventh lower metal pattern 1070. For example, the third transistor T3b may be spaced apart from the seventh lower metal pattern 1070 in a direction opposite to the first direction DR1. Additionally, the third transistor T3c may be located on the other side of the seventh lower metal pattern 1070. For example, the third transistor T3c may be spaced apart from the seventh lower metal pattern 1070 in a direction opposite to the first direction DR1. Each of the third transistors T3a, T3b, and T3c may be located on the other side of the voltage line.

[0178] In one or more embodiments, capacitor CSTA may be located on one side of the seventh lower metal pattern 1070. For example, capacitor CSTA may be spaced apart from the seventh lower metal pattern 1070 in the first direction DR1. Additionally, capacitor CSTb may be located on the other side of the seventh lower metal pattern 1070. For example, capacitor CSTb may be spaced apart from the seventh lower metal pattern 1070 in a direction opposite to the first direction DR1. Additionally, capacitor CSTc may be located on one side of the seventh lower metal pattern 1070. For example, capacitor CSTc may be spaced apart from the seventh lower metal pattern 1070 in the first direction DR1. Each of capacitors CSTA and CSTc may be located on one side of the voltage line, and capacitor CSTb may be located on the other side of the voltage line.

[0179] Reference Figure 8 , Figure 9 and Figure 10The lower electrode layer E1 may be located on the metal layer MTL. The lower electrode layer E1 may include a first lower electrode pattern E1a, a second lower electrode pattern E1b, a third lower electrode pattern E1c, and a fourth lower electrode pattern E1d. The first lower electrode pattern E1a, the second lower electrode pattern E1b, the third lower electrode pattern E1c, and the fourth lower electrode pattern E1d may be spaced apart from each other in a planar view (e.g., spaced apart). For example, the lower electrode layer E1 may have a stacked structure including ITO / Ag / ITO, but this disclosure is not limited thereto. A portion of the lower electrode layer E1 may be connected to a portion of the metal layer MTL via contact holes. Figure 10 As shown, the contact hole is represented by an "X" in a box.

[0180] Reference Figure 11 and Figure 12 The pixel defining layer (PDL) may be located on the lower electrode layer E1. For example, the pixel defining layer (PDL) may cover the lower electrode layer E1. In one or more embodiments, the pixel defining layer (PDL) may define a first opening OP1, a second opening OP2, a third opening OP3, and a fourth opening OP4. The first opening OP1 may expose at least a portion of the upper surface of the first lower electrode pattern E1a. Additionally, the second opening OP2 may expose at least a portion of the upper surface of the second lower electrode pattern E1b. Additionally, the third opening OP3 may expose at least a portion of the upper surface of the third lower electrode pattern E1c. Additionally, the fourth opening OP4 may expose at least a portion of the upper surface of the fourth lower electrode pattern E1d. The first opening OP1, the second opening OP2, the third opening OP3, and the fourth opening OP4 may be spaced apart from each other in a planar view (e.g., spaced apart).

[0181] For example, the pixel defining layer (PDL) may include inorganic and / or organic materials. In one or more embodiments, the pixel defining layer (PDL) may include organic materials, such as epoxy resins and / or silicone resins. These materials may be used alone or in combination with each other. In one or more embodiments, the pixel defining layer (PDL) may also include a light-blocking material comprising black pigments and / or black dyes.

[0182] Reference Figure 12 and Figure 13 The upper electrode layer E2 may be located on the pixel-defining layer PDL and the lower electrode layer E1. In one or more embodiments, the upper electrode layer E2 may extend across the entire display area (e.g., Figure 2 The display area DA) is positioned. For example, the portion of the upper electrode layer E2 located in the first opening OP1 can be referred to as the first upper electrode pattern (e.g., Figure 14The first upper electrode pattern E2a), the portion of the upper electrode layer E2 located in the second opening OP2 can be called the second upper electrode pattern, the portion of the upper electrode layer E2 located in the third opening OP3 can be called the third upper electrode pattern, and the portion of the upper electrode layer E2 located in the fourth opening OP4 can be called the fourth upper electrode pattern.

[0183] For example, the upper electrode layer E2 may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals may include silver (“Ag”), molybdenum (“Mo”), aluminum (“Al”), tungsten (“W”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), and / or scandium (“Sc”). These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide. These materials may be used alone or in combination with each other. Additionally, examples of metal nitrides may include aluminum nitride (“AlN”). x ), Tungsten nitride ("WN") x ") and / or chromium nitride ("CrN") x These materials can be used individually or in combination with each other.

[0184] The first light-emitting element LEDa can be located in the first opening OP1. The first light-emitting element LEDa can be included in... Figure 2 In the first pixel PX1. For example. Figure 2 The first pixel PX1 may include a first light-emitting element LEDa and a first pixel driving circuit portion electrically connected to the first light-emitting element LEDa (e.g., Figure 8 The first pixel driving circuit part PXCa).

[0185] The first light-emitting element LEDa may include a first lower electrode pattern E1a and a first intermediate layer (e.g., ...). Figure 14 The first intermediate layer (EMLa) and the first upper electrode pattern. The first intermediate layer may be located between the first lower electrode pattern (E1a) and the first upper electrode pattern. The first lower electrode pattern (E1a) may be the anode of the first light-emitting element (LEDa), and the first upper electrode pattern may be the cathode of the first light-emitting element (LEDa).

[0186] The second light-emitting element LEDb can be located in the second opening OP2. The second light-emitting element LEDb can be included in... Figure 2 In the second pixel PX2. For example. Figure 2 The second pixel PX2 may include a second light-emitting element LEDb and a second pixel driving circuit portion electrically connected to the second light-emitting element LEDb (e.g., Figure 8 The second pixel driving circuit part PXCb).

[0187] The second light-emitting element LEDb may include a second lower electrode pattern E1b, a second intermediate layer, and a second upper electrode pattern. The second intermediate layer may be located between the second lower electrode pattern E1b and the second upper electrode pattern. The second lower electrode pattern E1b may be the anode of the second light-emitting element LEDb, and the second upper electrode pattern may be the cathode of the second light-emitting element LEDb.

[0188] The third light-emitting element LEDc can be located in the third opening OP3. The third light-emitting element LEDc can be included in... Figure 2 In the third pixel PX3. For example, Figure 2 The third pixel PX3 may include a third light-emitting element LEDc and a third pixel driving circuit portion electrically connected to the third light-emitting element LEDc (e.g., Figure 8 The third pixel driving circuit part PXCc).

[0189] The third light-emitting element LEDc may include a third lower electrode pattern E1c, a third intermediate layer, and a third upper electrode pattern. The third intermediate layer may be located between the third lower electrode pattern E1c and the third upper electrode pattern. The third lower electrode pattern E1c may be the anode of the third light-emitting element LEDc, and the third upper electrode pattern may be the cathode of the third light-emitting element LEDc.

[0190] Each of the first intermediate layer, the second intermediate layer, and the third intermediate layer may include a first functional layer, a light-emitting layer located on the first functional layer, and a second functional layer located on the light-emitting layer. For example, the first functional layer may include a hole injection layer and / or a hole transport layer, and the second functional layer may include an electron transport layer and / or an electron injection layer. The first intermediate layer may be as follows: Figure 14 As shown in the image.

[0191] In one or more embodiments, the first light-emitting element LEDa, the second light-emitting element LEDb, and the third light-emitting element LEDc can emit light having different wavelengths from each other. For example, the first light-emitting element LEDa can emit green light, the second light-emitting element LEDb can emit red light, and the third light-emitting element LEDc can emit blue light, but this disclosure is not limited thereto. In one or more embodiments, the first light-emitting element LEDa, the second light-emitting element LEDb, and the third light-emitting element LEDc can be spaced apart from each other in a plan view (e.g., spaced apart).

[0192] The contact portion LDP can be located within the fourth opening OP4. The contact portion LDP can be the part where the fourth lower electrode pattern E1d and the fourth upper electrode pattern contact each other through the fourth opening OP4. The fourth lower electrode pattern E1d can be connected to... Figure 4 The first metal pattern is 1010. Figure 3 The second power voltage ELVSS can be applied to Figure 4 The first lower metal pattern 1010. For example, in the fourth opening OP4, the fourth upper electrode pattern can be connected to the fourth lower electrode pattern E1d. Figure 4 The first lower metal pattern 1010. Therefore, the IR drop phenomenon of the upper electrode layer E2 can be prevented.

[0193] Also refer to Figure 8 and Figure 13 Each of the first light-emitting element LEDa, the second light-emitting element LEDb, and the third light-emitting element LEDc can emit light in all directions. For example, light emitted from the first light-emitting element LEDa may reach the second pixel driving circuit portion PXCb and the third pixel driving circuit portion PXCc. Similarly, light emitted from the second light-emitting element LEDb may reach the first pixel driving circuit portion PXCa and the third pixel driving circuit portion PXCc. Furthermore, light emitted from the third light-emitting element LEDc may reach both the first pixel driving circuit portion PXCa and the second pixel driving circuit portion PXCb.

[0194] In one or more embodiments, the first transistor T1a may at least partially overlap with the first light-emitting element LEDa in a planar view. Additionally, the first transistor T1b may at least partially overlap with the second light-emitting element LEDb in a planar view. Furthermore, the first transistor T1c may at least partially overlap with the third light-emitting element LEDc in a planar view. Therefore, a sufficient spacing distance in a planar view between the first transistor T1a and the second light-emitting element LEDb can be ensured. Additionally, a sufficient spacing distance in a planar view between the first transistor T1a and the third light-emitting element LEDc can be ensured. Therefore, light emitted from each of the second light-emitting element LEDb and the third light-emitting element LEDc can be prevented from reaching the first transistor T1a. Alternatively, only a small portion of the light emitted from each of the second light-emitting element LEDb and the third light-emitting element LEDc can reach the first transistor T1a. Therefore, degradation of the first transistor T1a can be prevented or reduced.

[0195] Furthermore, sufficient spacing between the first transistor T1b and the first light-emitting element LEDa in the plan view can be ensured. Additionally, sufficient spacing between the first transistor T1b and the third light-emitting element LEDc in the plan view can be ensured. Therefore, light emitted from each of the first light-emitting element LEDa and the third light-emitting element LEDc can be prevented from reaching the first transistor T1b. Alternatively, only a small fraction of the light emitted from each of the first light-emitting element LEDa and the third light-emitting element LEDc can reach the first transistor T1b. Therefore, degradation of the first transistor T1b can be prevented or reduced.

[0196] Furthermore, sufficient spacing between the first transistor T1c and the first light-emitting element LEDa in the plan view can be ensured. Additionally, sufficient spacing between the first transistor T1c and the second light-emitting element LEDb in the plan view can be ensured. Therefore, light emitted from each of the first light-emitting elements LEDa and LEDb can be prevented from reaching the first transistor T1c. Alternatively, only a small fraction of the light emitted from each of the first light-emitting elements LEDa and LEDb can reach the first transistor T1c. Therefore, degradation of the first transistor T1c can be prevented or reduced.

[0197] For example, the first transistor T1a can be unaffected by light emitted from the light-emitting element adjacent to the first transistor T1a. Similarly, the first transistor T1b can be unaffected by light emitted from the light-emitting element adjacent to the first transistor T1b. Furthermore, the first transistor T1c can be unaffected by light emitted from the light-emitting element adjacent to the first transistor T1c.

[0198] Furthermore, as described above, each of the first transistors T1a and T1c can be located on one side of the voltage line, and the first transistor T1b can be located on the other side of the voltage line. Therefore, sufficient spacing between the first transistor T1a and the second light-emitting element LEDb in the planar view can be ensured. Additionally, sufficient spacing between the first transistor T1b and the first light-emitting element LEDa in the planar view can be ensured. Furthermore, sufficient spacing between the first transistor T1b and the third light-emitting element LEDc in the planar view can be ensured. Additionally, sufficient spacing between the first transistor T1c and the second light-emitting element LEDb in the planar view can be ensured. Therefore, degradation of each of the first transistors T1a, T1b, and T1c can be prevented or reduced.

[0199] Furthermore, as described above, each of the second transistors T2a and T2c can be located on one side of the voltage line, and the second transistor T2b can be located on the other side of the voltage line. Therefore, a sufficient spacing distance in the planar view between the second transistor T2a and the second light-emitting element LEDb can be ensured. Therefore, light emitted from the second light-emitting element LEDb can be prevented from reaching the second transistor T2a. Therefore, degradation of the second transistor T2a can be prevented or reduced. Additionally, a sufficient spacing distance in the planar view between the second transistor T2b and the first light-emitting element LEDa can be ensured. Additionally, a sufficient spacing distance in the planar view between the second transistor T2b and the third light-emitting element LEDc can be ensured. Therefore, light emitted from the first light-emitting element LEDa and the third light-emitting element LEDc can be prevented from reaching the second transistor T2b. Therefore, degradation of the second transistor T2b can be prevented. Additionally, a sufficient spacing distance in the planar view between the second transistor T2c and the second light-emitting element LEDb can be ensured. Therefore, light emitted from the second light-emitting element LEDb can be prevented from reaching the second transistor T2c. Therefore, degradation of the second transistor T2c can be prevented or reduced.

[0200] Figure 14 It is along Figure 13 The line I-I' intercepted Figure 13 A cross-sectional view of the display device.

[0201] Reference Figure 14 The substrate SUB can be a display device (e.g., Figure 1 The substrate of the display device (DD) can be formed from a transparent resin substrate. Examples of transparent resin substrates include polyimide substrates. In this case, the polyimide substrate may include a first organic layer, a first barrier layer, and / or a second organic layer, etc. Alternatively, the substrate SUB may include a quartz substrate (e.g., a synthetic quartz substrate, a fluorine-doped quartz substrate), a calcium fluoride substrate, a soda-lime glass substrate, and / or an alkali-free glass substrate, etc. These materials may be used alone or in combination with each other.

[0202] The seventh lower metal pattern 1070 and the ninth lower metal pattern 1090 may be located on the substrate SUB. Additionally, a first insulating layer IL1 may be located on the substrate SUB. The first insulating layer IL1 may cover the seventh lower metal pattern 1070 and the ninth lower metal pattern 1090. For example, the first insulating layer IL1 may comprise an inorganic material, such as silicon oxide ("SiO2"). x ), silicon nitride ("SiN") x ), silicon carbide ("SiC") x ), silicon oxynitride ("SiO2") x N y ") and / or silicon dioxide ("SiO2") x Cy These materials can be used individually or in combination with each other.

[0203] The fourth active pattern 2040 and the second active pattern 2020 may be located on the first insulating layer IL1. Additionally, the second insulating layer IL2 may be located on the first insulating layer IL1. The second insulating layer IL2 may cover the fourth active pattern 2040 and the second active pattern 2020. For example, the second insulating layer IL2 may comprise an inorganic material, such as silicon oxide ("SiO2"). x ), silicon nitride ("SiN") x ), silicon carbide ("SiC") x ), silicon oxynitride ("SiO2") x N y ") and / or silicon dioxide ("SiO2") x C y These materials can be used individually or in combination with each other.

[0204] The fifth metal pattern 3050, the sixth metal pattern 3060, and the seventh metal pattern 3070 may be located on the second insulating layer IL2. The fifth metal pattern 3050 can be connected to the fourth active pattern 2040 through a contact hole penetrating (or defined by) the second insulating layer IL2. Similarly, the seventh metal pattern 3070 can be connected to the fourth active pattern 2040 through a contact hole penetrating (or defined by) the second insulating layer IL2. Furthermore, the seventh metal pattern 3070 can be connected to the ninth lower metal pattern 1090 through contact holes penetrating (or defined by) the first insulating layer IL1 and the second insulating layer IL2. Additionally, the seventh metal pattern 3070 can be connected to the second active pattern 2020 through a contact hole penetrating (or defined by) the second insulating layer IL2. A third insulating layer IL3 may be located on the second insulating layer IL2. The third insulating layer IL3 may cover the fifth metal pattern 3050, the sixth metal pattern 3060, and the seventh metal pattern 3070. In one or more embodiments, the third insulating layer IL3 may comprise an organic material. For example, the third insulating layer IL3 may comprise organic materials such as phenolic resins, acrylic resins, polyimide resins, polyamide resins, siloxane resins, and / or epoxy resins. These materials may be used alone or in combination with each other. In one or more embodiments, the third insulating layer IL3 may also comprise inorganic materials such as silicon oxide ("SiO2"). x ), silicon nitride ("SiN") x ), silicon carbide ("SiC") x ), silicon oxynitride ("SiO2") x N y ") and / or silicon dioxide ("SiO2")x C y These materials can be used individually or in combination with each other.

[0205] The first light-emitting element LEDa can be located on the third insulating layer IL3. For example, the first lower electrode pattern E1a can be located on the third insulating layer IL3, the first intermediate layer EMLa can be located on the first lower electrode pattern E1a, and the first upper electrode pattern E2a can be located on the first intermediate layer EMLa. Additionally, the pixel defining layer PDL can be located on the third insulating layer IL3, overlapping the first lower electrode pattern E1a. As described above, the pixel defining layer PDL can define a first opening OP1 that exposes a portion of the upper surface of the first lower electrode pattern E1a. The first intermediate layer EMLa and the first upper electrode pattern E2a can be located within the first opening OP1.

[0206] The encapsulation layer TFE can be located on the first upper electrode pattern E2a. For example, the encapsulation layer TFE can be located on the upper electrode layer (e.g., Figure 13 The upper electrode layer (E2) is applied. The TFE encapsulation layer prevents impurities and / or moisture from penetrating into the first light-emitting element LEDa and the second light-emitting element (e.g., ...). Figure 13 The second light-emitting element (LEDb) and the third light-emitting element (e.g., Figure 13 In the third light-emitting element (LEDc), for example, the encapsulation layer TFE may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the inorganic encapsulation layer and the organic encapsulation layer may be stacked alternately. The inorganic encapsulation layer may include inorganic materials, such as silicon oxide ("SiO2"). x ), silicon nitride ("SiN") x ), silicon carbide ("SiC") x ), silicon oxynitride ("SiO2") x N y ") and / or silicon dioxide ("SiO2") x C y These materials can be used alone or in combination with each other. Organic encapsulation layers may include cured polymers such as polyacrylates.

[0207] Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This illustrates one or more embodiments. Figure 1 The layout diagram of pixels included in the display device.

[0208] Specifically, Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 It can be shown Figure 2 The arrangement of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0209] Reference Figure 15 Display devices (e.g., Figure 2 The display device (DD) may include a lower metal layer BML'. The lower metal layer BML' may include a first lower metal pattern 1010', a second lower metal pattern 1020', a third lower metal pattern 1030', a fourth lower metal pattern 1040', a fifth lower metal pattern 1050', a sixth lower metal pattern 1060', a seventh lower metal pattern 1070', an eighth lower metal pattern 1080', a ninth lower metal pattern 1090', a tenth lower metal pattern 1100', an eleventh lower metal pattern 1110', a twelfth lower metal pattern 1120', and a thirteenth lower metal pattern 1130'.

[0210] The first metal pattern 1010', the second metal pattern 1020', the third metal pattern 1030', the fourth metal pattern 1040', the fifth metal pattern 1050', the sixth metal pattern 1060', the seventh metal pattern 1070', the eighth metal pattern 1080', the ninth metal pattern 1090', the tenth metal pattern 1100', the eleventh metal pattern 1110', the twelfth metal pattern 1120', and the thirteenth metal pattern 1130' can be spaced apart from each other in the planar diagram (e.g., spaced apart).

[0211] The first lower metal pattern 1010' may be spaced apart from the second lower metal pattern 1020' in a direction opposite to the first direction DR1 (e.g., spaced apart). The first lower metal pattern 1010' may extend in the second direction DR2. In one or more embodiments, Figure 3 The second electrical voltage ELVSS can be applied to the first lower metal pattern 1010'. For example, the first lower metal pattern 1010' can be... Figure 3 At least a portion of the second voltage line VL2.

[0212] The second lower metal pattern 1020' may be spaced apart (e.g., spaced apart) from the third lower metal pattern 1030', the fourth lower metal pattern 1040', and the fifth lower metal pattern 1050' in a direction opposite to the first direction DR1. The second lower metal pattern 1020' may extend in the second direction DR2. In one or more embodiments, Figure 3 The initialization voltage VINT can be applied to the second lower metal pattern 1020'. For example, the second lower metal pattern 1020' can be... Figure 3 At least a portion of the third voltage line VL3.

[0213] The third lower metal pattern 1030' may be separated from the fourth lower metal pattern 1040' in a direction opposite to the second direction DR2 (e.g., spaced apart). In addition, the third lower metal pattern 1030' may be separated from the sixth lower metal pattern 1060' in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0214] The fourth lower metal pattern 1040' may be separated from the fifth lower metal pattern 1050' in a direction opposite to the second direction DR2 (e.g., spaced apart). In addition, the fourth lower metal pattern 1040' may be separated from the sixth lower metal pattern 1060' in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0215] The fifth lower metal pattern 1050' may be separated from the sixth lower metal pattern 1060' in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0216] The sixth lower metal pattern 1060' may be spaced apart from the seventh lower metal pattern 1070' in a direction opposite to the first direction DR1 (e.g., spaced apart). The sixth lower metal pattern 1060' may extend in the second direction DR2. In one or more embodiments, Figure 3 The data voltage DT can be applied to the sixth lower metal pattern 1060'. For example, the red data voltage can be applied to the sixth lower metal pattern 1060', but this disclosure is not limited thereto. For example, the sixth lower metal pattern 1060' can be... Figure 3 At least a portion of the data cable DL.

[0217] The seventh lower metal pattern 1070' may be spaced apart (e.g., spaced apart) from the eighth lower metal pattern 1080', the ninth lower metal pattern 1090', the tenth lower metal pattern 1100', and the eleventh lower metal pattern 1110' in a direction opposite to the first direction DR1. The seventh lower metal pattern 1070' may extend in the second direction DR2. In one or more embodiments, Figure 3The first electrical voltage ELVDD can be applied to the seventh lower metal pattern 1070'. For example, the seventh lower metal pattern 1070' can be... Figure 3 At least a portion of the first voltage line VL1. For example, the seventh lower metal pattern 1070' can be referred to as a voltage line.

[0218] The eighth lower metal pattern 1080' may be separated from the twelfth lower metal pattern 1120' in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the eighth lower metal pattern 1080' may be separated from the ninth lower metal pattern 1090' in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0219] The ninth lower metal pattern 1090' may be separated from the twelfth lower metal pattern 1120' in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the ninth lower metal pattern 1090' may be separated from the tenth lower metal pattern 1100' in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0220] The tenth lower metal pattern 1100' may be separated from the twelfth lower metal pattern 1120' in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the tenth lower metal pattern 1100' may be separated from the eleventh lower metal pattern 1110' in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0221] The eleventh lower metal pattern 1110' may be separated from the twelfth lower metal pattern 1120' in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0222] The twelfth lower metal pattern 1120' may be spaced apart from the thirteenth lower metal pattern 1130' in a direction opposite to the first direction DR1 (e.g., spaced apart). The twelfth lower metal pattern 1120' may extend in the second direction DR2. In one or more embodiments, Figure 3 The data voltage DT can be applied to the twelfth lower metal pattern 1120'. For example, the blue data voltage can be applied to the twelfth lower metal pattern 1120', but this disclosure is not limited thereto. For example, the twelfth lower metal pattern 1120' can be... Figure 3 At least a portion of the data cable DL.

[0223] The thirteenth lower metal pattern 1130' can extend in the second direction DR2. In one or more embodiments, Figure 3 The data voltage DT can be applied to the thirteenth lower metal pattern 1130'. For example, the green data voltage can be applied to the thirteenth lower metal pattern 1130', but this disclosure is not limited thereto. For example, the thirteenth lower metal pattern 1130' can be... Figure 3 At least a portion of the data line DL in the middle.

[0224] For example, the lower metal layer BML' may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals may include silver (“Ag”), molybdenum (“Mo”), aluminum (“Al”), tungsten (“W”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), and / or scandium (“Sc”). These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide. These materials may be used alone or in combination with each other. Additionally, examples of metal nitrides may include aluminum nitride (“AlN”). x ), Tungsten nitride ("WN") x ") and / or chromium nitride ("CrN") x These materials can be used individually or in combination with each other.

[0225] Reference Figure 16 The active layer ACT' can be located in the lower metal layer (e.g., Figure 15 The active layer ACT' may include a first active pattern 2010', a second active pattern 2020', a third active pattern 2030', a fourth active pattern 2040', a fifth active pattern 2050', a sixth active pattern 2060', a seventh active pattern 2070', an eighth active pattern 2080', a ninth active pattern 2090', and a tenth active pattern 2100'.

[0226] The first active pattern 2010', the second active pattern 2020', the third active pattern 2030', the fourth active pattern 2040', the fifth active pattern 2050', the sixth active pattern 2060', the seventh active pattern 2070', the eighth active pattern 2080', the ninth active pattern 2090', and the tenth active pattern 2100' can be separated from each other in the planar diagram (e.g., spaced apart).

[0227] The first active pattern 2010' may include a first region A1', a first channel region CH1', and a second region A2'. The first region A1' and the second region A2' may be spaced apart from each other in a planar view (e.g., separated). For example, the first region A1' and the second region A2' may be spaced apart from each other (e.g., separated), and the first channel region CH1' is located between the first region A1' and the second region A2'. For example, the first channel region CH1' may be located between the first region A1' and the second region A2'. The first region A1' and the second region A2' may have higher conductivity than the first channel region CH1'.

[0228] The second active pattern 2020' may include a third region A3', a second channel region CH2', and a fourth region A4'. The third region A3' and the fourth region A4' may be spaced apart from each other in a planar view (e.g., separated). For example, the third region A3' and the fourth region A4' may be spaced apart from each other (e.g., separated), and the second channel region CH2' is located between the third region A3' and the fourth region A4'. For example, the second channel region CH2' may be located between the third region A3' and the fourth region A4'. The third region A3' and the fourth region A4' may have higher conductivity than the second channel region CH2'.

[0229] In one or more embodiments, the third active pattern 2030' may include a fifth region A5', a sixth region A6', and a third channel region CH3'. The fifth region A5' and the sixth region A6' may be spaced apart from each other in a plan view (e.g., spaced apart). For example, the fifth region A5' and the sixth region A6' may be spaced apart from each other (e.g., spaced apart), and the third channel region CH3' may be located between the fifth region A5' and the sixth region A6'. For example, the third channel region CH3' may be located between the fifth region A5' and the sixth region A6'. The fifth region A5' and the sixth region A6' may have higher conductivity than the third channel region CH3'.

[0230] The fourth active pattern 2040' may include a single region. For example, the fourth active pattern 2040' may include a single region having a substantially constant conductivity across the fourth active pattern 2040', but this disclosure is not limited thereto.

[0231] The fifth active pattern 2050' may include a seventh region A7', a fourth channel region CH4', and an eighth region A8'. The seventh region A7' and the eighth region A8' may be spaced apart from each other in a planar view (e.g., separated). For example, the seventh region A7' and the eighth region A8' may be spaced apart from each other (e.g., separated), and the fourth channel region CH4' may be located between the seventh region A7' and the eighth region A8'. For example, the fourth channel region CH4' may be located between the seventh region A7' and the eighth region A8'. The seventh region A7' and the eighth region A8' may have higher conductivity than the fourth channel region CH4'.

[0232] The sixth active pattern 2060' may include a ninth region A9', a fifth channel region CH5', and a tenth region A10'. The ninth region A9' and the tenth region A10' may be spaced apart from each other in a planar view (e.g., separated). For example, the ninth region A9' and the tenth region A10' may be spaced apart from each other (e.g., separated), and the fifth channel region CH5' may be located between the ninth region A9' and the tenth region A10'. For example, the fifth channel region CH5' may be located between the ninth region A9' and the tenth region A10'. The ninth region A9' and the tenth region A10' may have higher conductivity than the fifth channel region CH5'.

[0233] The seventh active pattern 2070' may include an eleventh region A11', a sixth channel region CH6', and a twelfth region A12'. The eleventh region A11' and the twelfth region A12' may be spaced apart from each other in a planar view (e.g., separated). For example, the eleventh region A11' and the twelfth region A12' may be spaced apart from each other (e.g., separated), and the sixth channel region CH6' is located between the eleventh region A11' and the twelfth region A12'. For example, the sixth channel region CH6' may be located between the eleventh region A11' and the twelfth region A12'. The eleventh region A11' and the twelfth region A12' may have higher conductivity than the sixth channel region CH6'.

[0234] The eighth active pattern 2080' may include a thirteenth region A13', a seventh channel region CH7', and a fourteenth region A14'. The thirteenth region A13' and the fourteenth region A14' may be spaced apart from each other in a planar view (e.g., separated). For example, the thirteenth region A13' and the fourteenth region A14' may be spaced apart from each other (e.g., separated), and the seventh channel region CH7' is located between the thirteenth region A13' and the fourteenth region A14'. For example, the seventh channel region CH7' may be located between the thirteenth region A13' and the fourteenth region A14'. The thirteenth region A13' and the fourteenth region A14' may have higher conductivity than the seventh channel region CH7'.

[0235] The ninth active pattern 2090' may include a fifteenth region A15', an eighth channel region CH8', and a sixteenth region A16'. The fifteenth region A15' and the sixteenth region A16' may be spaced apart from each other in a planar view (e.g., spaced apart). For example, the fifteenth region A15' and the sixteenth region A16' may be spaced apart from each other (e.g., spaced apart), and the eighth channel region CH8' may be located between the fifteenth region A15' and the sixteenth region A16'. For example, the eighth channel region CH8' may be located between the fifteenth region A15' and the sixteenth region A16'. The fifteenth region A15' and the sixteenth region A16' may have higher conductivity than the eighth channel region CH8'.

[0236] The tenth active pattern 2100' may include a seventeenth region A17', a ninth channel region CH9', and an eighteenth region A18'. The seventeenth region A17' and the eighteenth region A18' may be spaced apart from each other in a planar view (e.g., spaced apart). For example, the seventeenth region A17' and the eighteenth region A18' may be spaced apart from each other (e.g., spaced apart), and the ninth channel region CH9' is located between the seventeenth region A17' and the eighteenth region A18'. For example, the ninth channel region CH9' may be located between the seventeenth region A17' and the eighteenth region A18'. The seventeenth region A17' and the eighteenth region A18' may have higher conductivity than the ninth channel region CH9'.

[0237] For example, the active layer ACT' may include inorganic semiconductors (e.g., amorphous silicon, polycrystalline silicon, metal oxide semiconductors) and / or organic semiconductors. These materials may be used alone or in combination with each other. The active layer ACT may include a source region, a drain region, and a channel region located between the source region and the drain region. The metal oxide semiconductor may include binary compounds ("AB") comprising indium ("In"), zinc ("Zn"), gallium ("Ga"), tin ("Sn"), titanium ("Ti"), aluminum ("Al"), hafnium ("Hf"), zirconium ("Zr"), and / or magnesium ("Mg"), etc. x ), ternary compounds ("AB") x C y ") and / or quaternary compounds ("AB") x C y D z These materials can be used alone or in combination with each other. For example, metal oxide semiconductors can include zinc oxide ("ZnO"). x Gallium oxide (GaO) x "), Tin oxide ("SnO") x Indium oxide (InO) xIndium gallium oxide (“IGO”), indium zinc oxide (“IZO”), indium tin oxide (“ITO”), indium zinc tin oxide (“IZTO”) and / or indium gallium zinc oxide (“IGZO”). These materials can be used alone or in combination with each other.

[0238] Reference Figure 15 , Figure 16 and Figure 17 The capacitor CSTA' may include a portion of the ninth lower metal pattern 1090' and a portion of the fifth active pattern 2050'. For example, the capacitor CSTA' may include a portion of the seventh region A7' and the portion of the ninth lower metal pattern 1090'. The portion of the seventh region A7' and the portion of the ninth lower metal pattern 1090' may overlap each other in a planar view. The capacitor CSTA' may be Figure 19 The capacitor included in the first pixel driving circuit section PXCa'.

[0239] The capacitor CSTb' may include a portion of a fourth lower metal pattern 1040' and a portion of a fourth active pattern 2040'. The portions of the fourth lower metal pattern 1040' and the fourth active pattern 2040' may overlap each other in a planar view. The capacitor CSTb' may be... Figure 19 The capacitor included in the second pixel driving circuit section PXCb'.

[0240] Capacitor CSTc' may include a portion of the tenth lower metal pattern 1100' and a portion of the seventh active pattern 2070'. For example, capacitor CSTc' may include a portion of the twelfth region A12' of the seventh active pattern 2070' and the portion of the tenth lower metal pattern 1100'. The portion of the twelfth region A12' and the portion of the tenth lower metal pattern 1100' may overlap each other in a planar view. Capacitor CSTc' may be Figure 19 The capacitor included in the third pixel driving circuit section PXCc'.

[0241] Reference Figure 18 The metal layer MTL' can be located in the active layer (e.g., Figure 16On the active layer ACT'). The metal layer MTL' may include the first metal pattern 3010', the second metal pattern 3020', the third metal pattern 3030', the fourth metal pattern 3040', the fifth metal pattern 3050', the sixth metal pattern 3060', the seventh metal pattern 3070', the eighth metal pattern 3080', the ninth metal pattern 3090', the tenth metal pattern 3100', the eleventh metal pattern 3110', the twelfth metal pattern 3120', the thirteenth metal pattern 3130', the fourteenth metal pattern 3140', the fifteenth metal pattern 3150', the sixteenth metal pattern 3160', the seventeenth metal pattern 3170', and the eighteenth metal pattern 3180'.

[0242] The first metal pattern 3010', the second metal pattern 3020', the third metal pattern 3030', the fourth metal pattern 3040', the fifth metal pattern 3050', the sixth metal pattern 3060', the seventh metal pattern 3070', the eighth metal pattern 3080', the ninth metal pattern 3090', the tenth metal pattern 3100', the eleventh metal pattern 3110', the twelfth metal pattern 3120', the thirteenth metal pattern 3130', the fourteenth metal pattern 3140', the fifteenth metal pattern 3150', the sixteenth metal pattern 3160', the seventeenth metal pattern 3170', and the eighteenth metal pattern 3180' may be spaced apart from each other in the planar diagram (e.g., spaced apart).

[0243] In one or more embodiments, the first metal pattern 3010' may include a first portion 3011' and a second portion 3012'. The first portion 3011' may extend in a first direction DR1. The second portion 3012' may be a portion extending from the first portion 3011'. For example, the second portion 3012' may be a portion extending from the first portion 3011' in a second direction DR2. In one or more embodiments, Figure 3 The sensing signal SS can be applied to the first metal pattern 3010'. For example, the first metal pattern 3010' can be... Figure 3 At least a portion of the sensing signal line SSL.

[0244] The second metal pattern 3020' may be located between the first portion 3011' of the first metal pattern 3010' and the first portion 3161' of the sixteenth metal pattern 3160', which will be described later. Additionally, the second metal pattern 3020' may be spaced apart from the third metal pattern 3030' in a direction opposite to the first direction DR1 (e.g., spaced apart). The second metal pattern 3020' may extend in the second direction DR2.

[0245] The third metal pattern 3030' may be spaced apart (e.g., separated) from the first portion 3011' of the first metal pattern 3010' in the second direction DR2. Additionally, the third metal pattern 3030' may be spaced apart (e.g., separated) from the second portion 3012' of the first metal pattern 3010' in a direction opposite to the first direction DR1. Furthermore, the third metal pattern 3030' may be spaced apart (e.g., separated) from the first portion 3161' of the sixteenth metal pattern 3160' in a direction opposite to the second direction DR2. The third metal pattern 3030' may extend in the second direction DR2.

[0246] The fourth metal pattern 3040' may be spaced apart from the first portion 3011' of the first metal pattern 3010' in the second direction DR2 (e.g., spaced apart). Additionally, the fourth metal pattern 3040' may be spaced apart from the second portion 3012' of the first metal pattern 3010' in the first direction DR1 (e.g., spaced apart). Furthermore, the fourth metal pattern 3040' may be spaced apart from the fifth metal pattern 3050' in the opposite direction of the first direction DR1 (e.g., spaced apart).

[0247] The fifth metal pattern 3050' may be spaced apart (e.g., separated) from the first portion 3011' of the first metal pattern 3010' in the second direction DR2. Additionally, the fifth metal pattern 3050' may be spaced apart (e.g., separated) from the first portion 3161' of the sixteenth metal pattern 3160' in a direction opposite to the second direction DR2. Furthermore, the fifth metal pattern 3050' may be spaced apart (e.g., separated) from the sixth metal pattern 3060' and the twelfth metal pattern 3120' in a direction opposite to the first direction DR1. The fifth metal pattern 3050' may extend in the second direction DR2.

[0248] The sixth metal pattern 3060' may be separated from the twelfth metal pattern 3120' in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0249] The seventh metal pattern 3070' may be separated from the first portion 3011' of the first metal pattern 3010' in the second direction DR2 (e.g., spaced apart).

[0250] The eighth metal pattern 3080' may be separated from the second portion 3012' of the first metal pattern 3010' in the first direction DR1 (e.g., spaced apart). In addition, the eighth metal pattern 3080' may be separated from the ninth metal pattern 3090' in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0251] The ninth metal pattern 3090' may be spaced apart from the fifth metal pattern 3050' in a direction opposite to the first direction DR1 (e.g., spaced apart). Additionally, the ninth metal pattern 3090' may be spaced apart from the tenth metal pattern 3100' in a direction opposite to the second direction DR2 (e.g., spaced apart). Furthermore, the ninth metal pattern 3090' may be spaced apart from the fourth metal pattern 3040' in the second direction DR2 (e.g., spaced apart).

[0252] The tenth metal pattern 3100' may be separated from the eleventh metal pattern 3110' in a direction opposite to the first direction DR1 (e.g., spaced apart). In addition, the tenth metal pattern 3100' may be separated from the first portion 3161' of the sixteenth metal pattern 3160' in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0253] The eleventh metal pattern 3110' may be separated from the first portion 3161' of the sixteenth metal pattern 3160' in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0254] The twelfth metal pattern 3120' may be separated from the sixth metal pattern 3060' in the second direction DR2 (e.g., spaced apart).

[0255] The thirteenth metal pattern 3130' may be separated from the first portion 3161' of the sixteenth metal pattern 3160' in a direction opposite to the second direction DR2 (e.g., spaced apart). Additionally, the thirteenth metal pattern 3130' may be separated from the second portion 3162' of the sixteenth metal pattern 3160', which will be described later, in a direction opposite to the first direction DR1 (e.g., spaced apart).

[0256] The fourteenth metal pattern 3140' may be separated from the second portion 3162' of the sixteenth metal pattern 3160' in the first direction DR1 (e.g., spaced apart). In addition, the fourteenth metal pattern 3140' may be separated from the fifteenth metal pattern 3150' in a direction opposite to the second direction DR2 (e.g., spaced apart).

[0257] The fifteenth metal pattern 3150' can be positioned adjacent to the second part 3162' of the sixteenth metal pattern 3160'.

[0258] In one or more embodiments, the sixteenth metal pattern 3160' may include a first portion 3161' and a second portion 3162'. The first portion 3161' may extend in a first direction DR1. The second portion 3162' may extend from the first portion 3161'. For example, the second portion 3162' may be a portion extending from the first portion 3161' in a direction opposite to the second direction DR2. In one or more embodiments, Figure 3 The scanning signal SC can be applied to the sixteenth metal pattern 3160'. For example, the sixteenth metal pattern 3160' can be... Figure 3 At least a portion of the scan signal line SCL.

[0259] The seventeenth metal pattern 3170' may be separated from the sixteenth metal pattern 3160' in the second direction DR2 (e.g., spaced apart). The seventeenth metal pattern 3170' may extend in the first direction DR1.

[0260] The eighteenth metal pattern 3180' may be spaced apart from the first metal pattern 3010' in a direction opposite to the second direction DR2 (e.g., spaced apart). For example, the eighteenth metal pattern 3180' may be spaced apart from the first portion 3011' of the first metal pattern 3010' in a direction opposite to the second direction DR2 (e.g., spaced apart). The eighteenth metal pattern 3180' may extend in the first direction DR1.

[0261] For example, the metal layer MTL' can include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals can include silver (“Ag”), molybdenum (“Mo”), aluminum (“Al”), tungsten (“W”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), and / or scandium (“Sc”). These materials can be used alone or in combination with each other. Examples of conductive metal oxides can include indium tin oxide and / or indium zinc oxide. These materials can be used alone or in combination with each other. Additionally, examples of metal nitrides can include aluminum nitride (“AlN”). x ), Tungsten nitride ("WN") x ") and / or chromium nitride ("CrN") x These materials can be used individually or in combination with each other.

[0262] Reference Figure 17 , Figure 18 and Figure 19 A portion of the metal layer MTL' can be connected to a portion of the lower metal layer BML' via contact holes. Additionally, a portion of the metal layer MTL' can be connected to a portion of the active layer ACT' via contact holes. For example... Figure 19As shown, the contact hole is represented by an "X" in a box.

[0263] In one or more embodiments, the display device (e.g., Figure 2 The display device (DD) may include a first pixel driving circuit portion PXCa', a second pixel driving circuit portion PXCb', and a third pixel driving circuit portion PXCc'. For example, the first pixel driving circuit portion PXCa' includes... Figure 2 In the first pixel PX1, the second pixel driving circuit portion PXCb' is included Figure 2 The second pixel PX2, and the third pixel driving circuit portion PXCc' may be included in Figure 2 In the third pixel PX3, however, this disclosure is not limited thereto. Furthermore, each of the first pixel driving circuit portion PXCa', the second pixel driving circuit portion PXCb', and the third pixel driving circuit portion PXCc' can be connected to... Figure 3 The pixel driving circuit portion of the PXC has a substantially the same structure, but this disclosure is not limited thereto.

[0264] The first pixel driving circuit section PXCa' may include a first transistor T1a', a second transistor T2a', a third transistor T3a', and a capacitor CSTA'. The first transistor T1a' may correspond to... Figure 3 The first transistor T1 and the second transistor T2a' can correspond to Figure 3 The second transistor T2 and the third transistor T3a' can correspond to Figure 3 The third transistor T3, and the capacitor CSTA' can correspond to Figure 3 The capacitor CST.

[0265] The second pixel driving circuit section PXCb' may include a first transistor T1b', a second transistor T2b', a third transistor T3b', and a capacitor CSTb'. The first transistor T1b' may correspond to... Figure 3 The first transistor T1 and the second transistor T2b' can correspond to Figure 3 The second transistor T2 and the third transistor T3b' can correspond to Figure 3 The third transistor T3, and the capacitor CSTb' can correspond to Figure 3 The capacitor CST.

[0266] The third pixel driving circuit section PXCc' may include a first transistor T1c', a second transistor T2c', a third transistor T3c', and a capacitor CSTc'. The first transistor T1c' may correspond to... Figure 3 The first transistor T1 and the second transistor T2c' can correspond to Figure 3The second transistor T2 and the third transistor T3c' can correspond to Figure 3 The third transistor T3, and the capacitor CSTc' can correspond to Figure 3 The capacitor CST.

[0267] The first transistor T1a' may include a portion of the third active pattern 2030' (i.e., a portion of the fifth region A5', a portion of the sixth region A6', and the third channel region CH3') and a portion of the sixth metal pattern 3060' that overlaps with the third channel region CH3' in a planar view. For example, the portion of the sixth metal pattern 3060' that overlaps with the third channel region CH3' in a planar view may be referred to as the gate electrode of the first transistor T1a'.

[0268] The second transistor T2a' may include a portion of the fifth active pattern 2050' (i.e., a portion of the seventh region A7', a portion of the eighth region A8', and the fourth channel region CH4') and the portion of the second portion 3162' of the sixth metal pattern 3060' that overlaps with the fourth channel region CH4' in a planar view. For example, the portion of the second portion 3162' of the sixth metal pattern 3060' that overlaps with the fourth channel region CH4' in a planar view may be referred to as the gate electrode of the second transistor T2a'.

[0269] The third transistor T3a' may include a portion of the first active pattern 2010' (i.e., a portion of the first region A1', a portion of the second region A2', and the first channel region CH1') and a portion of the second portion 3012' of the first metal pattern 3010 that overlaps with the first channel region CH1' in a planar view. For example, the portion of the second portion 3012' of the first metal pattern 3010 that overlaps with the first channel region CH1' in a planar view may be referred to as the gate electrode of the third transistor T3a'.

[0270] The first transistor T1b' may include a portion of the sixth active pattern 2060' (i.e., a portion of the ninth region A9', a portion of the tenth region A10', and the fifth channel region CH5') and a portion of the ninth metal pattern 3090' that overlaps with the fifth channel region CH5' in a planar view. For example, the portion of the ninth metal pattern 3090' that overlaps with the fifth channel region CH5' in a planar view may be referred to as the gate electrode of the first transistor T1b'.

[0271] The second transistor T2b' may include a portion of the eighth active pattern 2080' (i.e., a portion of the thirteenth region A13', a portion of the fourteenth region A14', and the seventh channel region CH7') and a portion of the tenth metal pattern 3100' that overlaps with the seventh channel region CH7' in the plan view. For example, the portion of the tenth metal pattern 3100' that overlaps with the seventh channel region CH7' in the plan view may be referred to as the gate electrode of the second transistor T2b'.

[0272] The third transistor T3b' may include a portion of the second active pattern 2020' (i.e., a portion of the third region A3', a portion of the fourth region A4', and the second channel region CH2') and a portion of the second portion 3012' of the first metal pattern 3010 that overlaps with the second channel region CH2' in a plan view. For example, the portion of the second portion 3012' that overlaps with the second channel region CH2' in a plan view may be referred to as the gate electrode of the third transistor T3b'.

[0273] The first transistor T1c' may include a portion of the ninth active pattern 2090' (i.e., a portion of the fifteenth region A15', a portion of the sixteenth region A16', and the eighth channel region CH8') and a portion of the twelfth metal pattern 3120' that overlaps with the eighth channel region CH8' in a planar view. For example, the portion of the twelfth metal pattern 3120' that overlaps with the eighth channel region CH8' in a planar view may be referred to as the gate electrode of the first transistor T1c'.

[0274] The second transistor T2c' may include a portion of the seventh active pattern 2070' (i.e., a portion of the eleventh region A11', a portion of the twelfth region A12', and the sixth channel region CH6') and the portion of the second part 3162' of the sixteenth metal pattern 3160' that overlaps with the sixth channel region CH6' in a planar view. For example, the portion of the second part 3162' that overlaps with the sixth channel region CH6' in a planar view may be referred to as the gate electrode of the second transistor T2c'.

[0275] The third transistor T3c' may include a portion of the tenth active pattern 2100' (i.e., a portion of the seventeenth region A17', a portion of the eighteenth region A18', and the ninth channel region CH9') and the portion of the second portion 3012' that overlaps with the ninth channel region CH9' in the plan view. For example, the portion of the second portion 3012' of the first metal pattern 3010 that overlaps with the ninth channel region CH9' in the plan view may be referred to as the gate electrode of the third transistor T3c'.

[0276] Also refer to Figure 15In one or more embodiments, the first transistor T1a' may be located on one side of the seventh lower metal pattern 1070'. For example, the first transistor T1a' may be spaced apart from the seventh lower metal pattern 1070' in the first direction DR1 (e.g., spaced apart). Additionally, the first transistor T1b' may be located on the other side of the seventh lower metal pattern 1070'. For example, the first transistor T1b' may be spaced apart from the seventh lower metal pattern 1070' in a direction opposite to the first direction DR1 (e.g., spaced apart). Furthermore, the first transistor T1c' may be located on one side of the seventh lower metal pattern 1070'. For example, the first transistor T1c' may be spaced apart from the seventh lower metal pattern 1070' in the first direction DR1 (e.g., spaced apart). As described above, Figure 3 The first electrical voltage ELVDD can be applied to the seventh lower metal pattern 1070', and the seventh lower metal pattern 1070' can be referred to as the voltage line. Each of the first transistors T1a' and T1c' can be located on one side of the voltage line, and the first transistor T1b' can be located on the other side of the voltage line.

[0277] In one or more embodiments, the second transistor T2a' may be located on one side of the seventh lower metal pattern 1070'. For example, the second transistor T2a' may be spaced apart from the seventh lower metal pattern 1070' in the first direction DR1. Additionally, the second transistor T2b' may be located on the other side of the seventh lower metal pattern 1070'. For example, the second transistor T2b' may be spaced apart from the seventh lower metal pattern 1070' in a direction opposite to the first direction DR1. Furthermore, the second transistor T2c' may be located on one side of the seventh lower metal pattern 1070'. For example, the second transistor T2c' may be spaced apart from the seventh lower metal pattern 1070' in the first direction DR1. Each of the second transistor T2a' and the second transistor T2c' may be located on one side of the voltage line, and the second transistor T2b' may be located on the other side of the voltage line.

[0278] In one or more embodiments, the third transistor T3a' may be located on the other side of the seventh lower metal pattern 1070'. For example, the third transistor T3a' may be spaced apart from the seventh lower metal pattern 1070' in a direction opposite to the first direction DR1. Additionally, the third transistor T3b' may be located on the other side of the seventh lower metal pattern 1070'. For example, the third transistor T3b' may be spaced apart from the seventh lower metal pattern 1070' in a direction opposite to the first direction DR1. Additionally, the third transistor T3c' may be located on the other side of the seventh lower metal pattern 1070'. For example, the third transistor T3c' may be spaced apart from the seventh lower metal pattern 1070' in a direction opposite to the first direction DR1. Each of the third transistors T3a', T3b', and T3c' may be located on the other side of the voltage line.

[0279] In one or more embodiments, capacitor CSTA' may be located on one side of the seventh lower metal pattern 1070'. For example, capacitor CSTA' may be spaced apart from the seventh lower metal pattern 1070' in the first direction DR1 (e.g., spaced apart). Additionally, capacitor CSTb' may be located on the other side of the seventh lower metal pattern 1070'. For example, capacitor CSTb' may be spaced apart from the seventh lower metal pattern 1070' in a direction opposite to the first direction DR1 (e.g., spaced apart). Additionally, capacitor CSTc' may be located on one side of the seventh lower metal pattern 1070'. For example, capacitor CSTc' may be spaced apart from the seventh lower metal pattern 1070' in the first direction DR1 (e.g., spaced apart). Each of capacitors CSTA' and CSTc' may be located on one side of the voltage line, and capacitor CSTb' may be located on the other side of the voltage line.

[0280] Reference Figure 19 , Figure 20 and Figure 21 The lower electrode layer E1' may be located on the metal layer MTL'. The lower electrode layer E1' may include a first lower electrode pattern E1a', a second lower electrode pattern E1b', a third lower electrode pattern E1c', and a fourth lower electrode pattern E1d'. The first lower electrode pattern E1a', the second lower electrode pattern E1b', the third lower electrode pattern E1c', and the fourth lower electrode pattern E1d' may be spaced apart from each other in a planar view (e.g., spaced apart). For example, the lower electrode layer E1' may have a stacked structure including ITO / Ag / ITO, but this disclosure is not limited thereto. A portion of the lower electrode layer E1' may be connected to a portion of the metal layer MTL' via contact holes. Figure 21 As shown, the contact hole is represented by an "X" in a box.

[0281] Reference Figure 22and Figure 23 The pixel defining layer PDL' may be located on the lower electrode layer E1'. For example, the pixel defining layer PDL' may cover the lower electrode layer E1'. In one or more embodiments, the pixel defining layer PDL' may define a first opening OP1', a second opening OP2', a third opening OP3', and a fourth opening OP4'. The first opening OP1' may expose at least a portion of the upper surface of the first lower electrode pattern E1a'. Additionally, the second opening OP2' may expose at least a portion of the upper surface of the second lower electrode pattern E1b'. Additionally, the third opening OP3' may expose at least a portion of the upper surface of the third lower electrode pattern E1c'. Additionally, the fourth opening OP4' may expose at least a portion of the upper surface of the fourth lower electrode pattern E1d'. The first opening OP1', the second opening OP2', the third opening OP3', and the fourth opening OP4' may be spaced apart from each other in a planar view (e.g., spaced apart).

[0282] For example, the pixel defining layer PDL' may include inorganic and / or organic materials. In one or more embodiments, the pixel defining layer PDL' may include organic materials, such as epoxy resins and / or silicone resins. These materials may be used alone or in combination with each other. In one or more embodiments, the pixel defining layer PDL' may also include a light-blocking material comprising black pigments and / or black dyes.

[0283] Reference Figure 23 and Figure 24 The upper electrode layer E2' may be located on the pixel-defining layer PDL' and the lower electrode layer E1'. In one or more embodiments, the upper electrode layer E2' may extend across the entire display area (e.g., Figure 2 The display area (DA) is positioned. For example, the portion of the upper electrode layer E2' located in the first opening OP1' can be referred to as the first upper electrode pattern, the portion of the upper electrode layer E2' located in the second opening OP2' can be referred to as the second upper electrode pattern, the portion of the upper electrode layer E2' located in the third opening OP3' can be referred to as the third upper electrode pattern, and the portion of the upper electrode layer E2' located in the fourth opening OP4' can be referred to as the fourth upper electrode pattern.

[0284] For example, the upper electrode layer E2' may include metals, alloys, metal nitrides, conductive metal oxides, and / or transparent conductive materials. Examples of metals may include silver (“Ag”), molybdenum (“Mo”), aluminum (“Al”), tungsten (“W”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), titanium (“Ti”), tantalum (“Ta”), platinum (“Pt”), and / or scandium (“Sc”). These materials may be used alone or in combination with each other. Examples of conductive metal oxides may include indium tin oxide and / or indium zinc oxide. These materials may be used alone or in combination with each other. Additionally, examples of metal nitrides may include aluminum nitride (“AlN”). x ), Tungsten nitride ("WN") x ") and / or chromium nitride ("CrN") x These materials can be used individually or in combination with each other.

[0285] The first light-emitting element LEDa' can be located in the first opening OP1'. The first light-emitting element LEDa' can be included in... Figure 2 In the first pixel PX1. For example. Figure 2 The first pixel PX1 may include a first light-emitting element LEDa' and a first pixel driving circuit portion electrically connected to the first light-emitting element LEDa' (e.g., Figure 19 The first pixel driving circuit part PXCa').

[0286] The first light-emitting element LEDa' may include a first lower electrode pattern E1a', a first intermediate layer, and a first upper electrode pattern. The first intermediate layer may be located between the first lower electrode pattern E1a' and the first upper electrode pattern. The first lower electrode pattern E1a' may be the anode of the first light-emitting element LEDa', and the first upper electrode pattern may be the cathode of the first light-emitting element LEDa'.

[0287] The second light-emitting element LEDb' can be located in the second opening OP2'. The second light-emitting element LEDb' can be included in... Figure 2 In the second pixel PX2. For example. Figure 2 The second pixel PX2 may include a second light-emitting element LEDb' and a second pixel driving circuit portion electrically connected to the second light-emitting element LEDb' (e.g., Figure 19 The second pixel driving circuit part PXCb').

[0288] The second light-emitting element LEDb' may include a second lower electrode pattern E1b', a second intermediate layer, and a second upper electrode pattern. The second intermediate layer may be located between the second lower electrode pattern E1b' and the second upper electrode pattern. The second lower electrode pattern E1b' may be the anode of the second light-emitting element LEDb', and the second upper electrode pattern may be the cathode of the second light-emitting element LEDb'.

[0289] The third light-emitting element LEDc' can be located in the third opening OP3'. The third light-emitting element LEDc' can be included in... Figure 2 In the third pixel PX3. For example, Figure 2 The third pixel PX3 may include a third light-emitting element LEDc' and a third pixel driving circuit portion electrically connected to the third light-emitting element LEDc' (e.g., Figure 19 The third pixel driving circuit part PXCc').

[0290] The third light-emitting element LEDc' may include a third lower electrode pattern E1c', a third intermediate layer, and a third upper electrode pattern. The third intermediate layer may be located between the third lower electrode pattern E1c' and the third upper electrode pattern. The third lower electrode pattern E1c' may be the anode of the third light-emitting element LEDc', and the third upper electrode pattern may be the cathode of the third light-emitting element LEDc'.

[0291] In one or more embodiments, each of the first intermediate layer, the second intermediate layer, and the third intermediate layer may include a first functional layer, a light-emitting layer located on the first functional layer, and a second functional layer located on the light-emitting layer. For example, the first functional layer may include a hole injection layer and / or a hole transport layer, and the second functional layer may include an electron transport layer and / or an electron injection layer. The first intermediate layer, the second intermediate layer, and the third intermediate layer may not be shown in the diagram. Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 middle.

[0292] In one or more embodiments, the first light-emitting element LEDa', the second light-emitting element LEDb', and the third light-emitting element LEDc' can emit light having different wavelengths from each other. For example, the first light-emitting element LEDa' can emit green light, the second light-emitting element LEDb' can emit red light, and the third light-emitting element LEDc' can emit blue light, but this disclosure is not limited thereto. In one or more embodiments, the first light-emitting element LEDa', the second light-emitting element LEDb', and the third light-emitting element LEDc' can be spaced apart from each other in a plan view (e.g., spaced apart).

[0293] The contact portion LDP' can be located within the fourth opening OP4'. The contact portion LDP' can be the part where the fourth lower electrode pattern E1d' and the fourth upper electrode pattern contact each other through the fourth opening OP4'. The fourth lower electrode pattern E1d' can be connected to a contact hole. Figure 15 The first metal pattern is 1010'. Figure 3 The second power voltage ELVSS can be applied to Figure 15 The first lower metal pattern 1010'. For example, in the fourth opening OP4', the fourth upper electrode pattern can be connected to the fourth lower electrode pattern E1d'. Figure 15 The first lower metal pattern 1010' is used. Therefore, the IR drop phenomenon of the upper electrode layer E2' can be prevented.

[0294] Also refer to Figure 19 and Figure 24 Each of the first light-emitting element LEDa', the second light-emitting element LEDb', and the third light-emitting element LEDc' can emit light in all directions. For example, light emitted from the first light-emitting element LEDa' may reach the second pixel driving circuit portion PXCb' and the third pixel driving circuit portion PXCc'. Similarly, light emitted from the second light-emitting element LEDb' may reach the first pixel driving circuit portion PXCa' and the third pixel driving circuit portion PXCc'. Furthermore, light emitted from the third light-emitting element LEDc' may reach the first pixel driving circuit portion PXCa' and the second pixel driving circuit portion PXCb'.

[0295] In one or more embodiments, the first transistor T1a' may at least partially overlap with the first light-emitting element LEDa' in a planar view. Additionally, the first transistor T1b' may at least partially overlap with the second light-emitting element LEDb' in a planar view. Furthermore, the first transistor T1c' may at least partially overlap with the third light-emitting element LEDc' in a planar view. Therefore, a sufficient spacing distance in a planar view between the first transistor T1a' and the second light-emitting element LEDb' can be ensured. Additionally, a sufficient spacing distance in a planar view between the first transistor T1a' and the third light-emitting element LEDc' can be ensured. Therefore, light emitted from each of the second light-emitting element LEDb' and the third light-emitting element LEDc' can be prevented from reaching the first transistor T1a'. Alternatively, only a small fraction of the light emitted from each of the second light-emitting element LEDb' and the third light-emitting element LEDc' can reach the first transistor T1a'. Therefore, degradation of the first transistor T1a' can be prevented or reduced.

[0296] Furthermore, sufficient spacing between the first transistor T1b' and the first light-emitting element LEDa' in the plan view can be ensured. Additionally, sufficient spacing between the first transistor T1b' and the third light-emitting element LEDc' in the plan view can be ensured. Therefore, light emitted from each of the first light-emitting element LEDa' and the third light-emitting element LEDc' can be prevented from reaching the first transistor T1b'. Alternatively, only a small fraction of the light emitted from each of the first light-emitting element LEDa' and the third light-emitting element LEDc' can reach the first transistor T1b'. Therefore, degradation of the first transistor T1b' can be prevented or reduced.

[0297] Furthermore, sufficient spacing between the first transistor T1c' and the first light-emitting element LEDa' in the plan view can be ensured. Additionally, sufficient spacing between the first transistor T1c' and the second light-emitting element LEDb' in the plan view can be ensured. Therefore, light emitted from each of the first light-emitting elements LEDa' and LEDb' can be prevented from reaching the first transistor T1c'. Alternatively, only a small fraction of the light emitted from each of the first light-emitting elements LEDa' and LEDb' can reach the first transistor T1c'. Therefore, degradation of the first transistor T1c' can be prevented or reduced.

[0298] For example, the first transistor T1a' may be unaffected by light emitted from the light-emitting element adjacent to the first transistor T1a'. Similarly, the first transistor T1b' may be unaffected by light emitted from the light-emitting element adjacent to the first transistor T1b'. Furthermore, the first transistor T1c' may be unaffected by light emitted from the light-emitting element adjacent to the first transistor T1c'.

[0299] Furthermore, as described above, each of the first transistors T1a' and T1c' can be located on one side of the voltage line, and the first transistor T1b' can be located on the other side of the voltage line. Therefore, sufficient spacing between the first transistor T1a' and the second light-emitting element LEDb' in the planar view can be ensured. Additionally, sufficient spacing between the first transistor T1b' and the first light-emitting element LEDa' in the planar view can be ensured. Furthermore, sufficient spacing between the first transistor T1b' and the third light-emitting element LEDc' in the planar view can be ensured. Additionally, sufficient spacing between the first transistor T1c' and the second light-emitting element LEDb' in the planar view can be ensured. Therefore, degradation of each of the first transistors T1a', T1b', and T1c' can be prevented or reduced.

[0300] Furthermore, as described above, each of the second transistor T2a' and the second transistor T2c' can be located on one side of the voltage line, and the second transistor T2b' can be located on the other side of the voltage line. Therefore, the spacing between the second transistor T2a' and the second light-emitting element LEDb' in the planar view can be ensured. Therefore, light emitted from the second light-emitting element LEDb' can be prevented from reaching the second transistor T2a'. Therefore, degradation of the second transistor T2a' can be prevented or reduced. Additionally, the spacing between the second transistor T2b' and the first light-emitting element LEDa' in the planar view can be ensured. Additionally, the spacing between the second transistor T2b' and the third light-emitting element LEDc' in the planar view can be ensured. Therefore, light emitted from the first light-emitting element LEDa' and the third light-emitting element LEDc' can be prevented from reaching the second transistor T2b'. Therefore, degradation of the second transistor T2b' can be prevented or reduced. Additionally, the spacing between the second transistor T2c' and the second light-emitting element LEDb' in the planar view can be ensured. Therefore, light emitted from the second light-emitting element LEDb' can be prevented from reaching the second transistor T2c'. Therefore, the degradation of the second transistor T2c' can be prevented or reduced.

[0301] A display device according to one or more embodiments (e.g., Figure 1 The display device (DD) can be applied to various electronic devices. An electronic device according to one or more embodiments may include the aforementioned display device, and may also include modules or devices with other additional functions in addition to the display device.

[0302] Figure 25 This is a block diagram illustrating an electronic device according to one or more embodiments.

[0303] Reference Figure 25The electronic device 10 according to one or more embodiments may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0304] Processor 12 may include a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and / or a controller.

[0305] The data required for the operation of the processor 12 or the display module 11 can be stored in the memory 15. When the processor 12 executes the application stored in the memory 15, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0306] The power module 14 may include a power module such as a power adapter and / or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0307] At least one of the components of the electronic device 10 described above may be included in the display device according to the above embodiments. Additionally, some of the individual modules that are functionally included in a single module may be included in the display device, and other modules may be provided separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as another device in the electronic device 10 besides the display device.

[0308] Figure 26 This is a schematic diagram of an electronic device according to one or more embodiments.

[0309] Reference Figure 26 The various electronic devices to which the display device according to one or more embodiments is applied may include not only electronic devices for image display (such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, televisions 10_1d and / or desktop monitors 10_1e, etc.), but also wearable electronic devices (such as smart glasses 10_2a, head-mounted displays 10_2b and / or smartwatches 10_2c, etc.) that include display modules, as well as vehicle electronic devices 10_3 (such as vehicle dashboards, central instrument panels, central information displays (“CID”) located on the instrument panel, and / or rearview mirror displays, etc.).

[0310] The foregoing is illustrative of the embodiments and should not be construed as limiting the embodiments. Although several embodiments have been described, those skilled in the art will readily appreciate that many modifications can be made to the embodiments without substantially departing from the novel teachings and scope of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims and their equivalents. It will therefore be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the embodiments and other embodiments are intended to be included within the scope of the appended claims and their equivalents.

Claims

1. A display device, wherein, The display device includes: a first light emitting element; a second light emitting element spaced apart from the first light emitting element in a plan view; a first pixel drive circuit portion including a drive transistor electrically connected to the first light emitting element, wherein the drive transistor in the first pixel drive circuit portion at least partially overlaps the first light emitting element in a plan view; and a second pixel drive circuit portion including a drive transistor electrically connected to the second light emitting element, wherein the drive transistor in the second pixel drive circuit portion at least partially overlaps the second light emitting element in a plan view.

2. The display device according to claim 1, wherein: the drive transistor in the first pixel drive circuit portion is configured to supply a drive current to the first light emitting element; and the drive transistor in the second pixel drive circuit portion is configured to supply a drive current to the second light emitting element.

3. The display device according to claim 1, wherein The display device further includes: a voltage line electrically connected to each of the first pixel drive circuit portion and the second pixel drive circuit portion.

4. The display device according to claim 3, wherein the drive transistor in the first pixel drive circuit portion is located on one side of the voltage line, and wherein the drive transistor in the second pixel drive circuit portion is located on the other side of the voltage line.

5. The display device according to claim 3, wherein each of the first pixel drive circuit portion and the second pixel drive circuit portion further includes a capacitor, wherein the capacitor in the first pixel drive circuit portion is located on one side of the voltage line, and wherein the capacitor in the second pixel drive circuit portion is located on the other side of the voltage line.

6. The display device according to claim 3, wherein the voltage line is configured to apply a power voltage to each of the first pixel drive circuit portion and the second pixel drive circuit portion.

7. The display device according to claim 3, wherein each of the first pixel drive circuit portion and the second pixel drive circuit portion further includes a first switching transistor, wherein the first switching transistor in the first pixel drive circuit portion is located on one side of the voltage line, and wherein the first switching transistor in the second pixel drive circuit portion is located on the other side of the voltage line.

8. The display device of claim 7, wherein, each of the first pixel drive circuit portion and the second pixel drive circuit portion further includes a second switching transistor, and wherein each of the second switching transistor in the first pixel drive circuit portion and the second switching transistor in the second pixel drive circuit portion is located on the one side of the voltage line or the other side of the voltage line.

9. The display device according to claim 1, wherein The display device further includes: a third light emitting element spaced apart from each of the first light emitting element and the second light emitting element in a plan view; and a third pixel drive circuit portion including a drive transistor electrically connected to the third light emitting element, wherein the drive transistor in the third pixel drive circuit portion at least partially overlaps the third light emitting element in a plan view.

10. The display device of claim 9, wherein, the first light emitting element, the second light emitting element, and the third light emitting element are configured to emit light having wavelengths different from each other.

11. The display device of claim 9, wherein, The display device further includes: a voltage line electrically connected to each of the first pixel drive circuit portion, the second pixel drive circuit portion, and the third pixel drive circuit portion.

12. The display device of claim 11, wherein, Each of the drive transistor in the first pixel drive circuit portion and the drive transistor in the third pixel drive circuit portion is located on one side of the voltage line, and wherein the drive transistor in the second pixel drive circuit portion is located on the other side of the voltage line.

13. The display device of claim 11, wherein, Each of the first pixel drive circuit portion, the second pixel drive circuit portion, and the third pixel drive circuit portion further includes a capacitor, wherein each of the capacitor in the first pixel drive circuit portion and the capacitor in the third pixel drive circuit portion is located on one side of the voltage line, and wherein the capacitor in the second pixel drive circuit portion is located on the other side of the voltage line.

14. A display device, wherein, The display device includes: a first light emitting element; a second light emitting element spaced apart from the first light emitting element in a plan view; a voltage line; a first pixel drive circuit portion including a drive transistor located on one side of the voltage line, wherein the first pixel drive circuit portion is electrically connected to each of the first light emitting element and the voltage line; and a second pixel drive circuit portion including a drive transistor located on the other side of the voltage line, wherein the second pixel drive circuit portion is electrically connected to each of the second light emitting element and the voltage line.

15. The display device of claim 14, wherein, The drive transistor in the first pixel drive circuit portion at least partially overlaps the first light emitting element in a plan view, and wherein the drive transistor in the second pixel drive circuit portion at least partially overlaps the second light emitting element in a plan view.

16. The display device of claim 14, wherein, The voltage line is configured to apply a power voltage to each of the first pixel drive circuit portion and the second pixel drive circuit portion.

17. The display device of claim 14, wherein, Each of the first pixel drive circuit portion and the second pixel drive circuit portion further includes a capacitor, wherein the capacitor in the first pixel drive circuit portion is located on the one side of the voltage line, and wherein the capacitor in the second pixel drive circuit portion is located on the other side of the voltage line.

18. The display device of claim 14, wherein, The display device further includes: a third light emitting element spaced apart from each of the first light emitting element and the second light emitting element in a plan view; and a third pixel drive circuit portion electrically connected to each of the third light emitting element and the voltage line.

19. The display device of claim 18, wherein, The third pixel drive circuit portion includes a drive transistor located on the one side of the voltage line or the other side of the voltage line.

20. An electronic device, wherein, The electronic device includes: a first light emitting element; a second light emitting element spaced apart from the first light emitting element in a plan view; a first pixel drive circuit portion including a drive transistor electrically connected to the first light emitting element, wherein the drive transistor in the first pixel drive circuit portion at least partially overlaps the first light emitting element in a plan view; and a second pixel drive circuit portion including a drive transistor electrically connected to the second light emitting element, wherein the drive transistor in the second pixel drive circuit portion at least partially overlaps the second light emitting element in a plan view. a second pixel drive circuit portion including a drive transistor electrically connected to the second light emitting element, wherein the drive transistor in the second pixel drive circuit portion at least partially overlaps the second light emitting element in a plan view; and a memory configured to store data information.

Images