Autonomous imaging system on chip

Abstract

An ultrasound imaging system integrated on a chip for autonomous scanning, comprising: an on-chip input memory configured to store scan sequence instructions and parameters; an on-chip processor configured to read scan sequence instructions and parameters input into the memory; and an on-chip beamformer configured to be programmed and timed by the processor according to scan sequence instructions and parameters. In some examples, scan sequence instructions and parameters are stored in a non-volatile input memory programmed at a plant. In other examples, scan sequence instructions and parameters are received from an external user device. The scan parameters are optimized or minimized to accommodate limited input memory capacity. In some examples, the scan sequence instructions and parameters include programmable nested loops, and each of the programmable nested loops corresponds to a transmit and / or receive event in the scan sequence.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 459,905, filed April 17, 2023, entitled "Autonomous Imaging System-on-Chip," which relates to U.S. Patent Application No. 17 / 569,805, filed January 6, 2022, entitled "Full-Array Digital 3D Ultrasonic Imaging System with Integrated Matrix Array Transducers." Each application is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to systems, devices and methods for ultrasound imaging, and more particularly, to imaging systems-on-chips (iSoCs) for autonomously performing scanning and imaging without requiring real-time control by an external processor. Background Technology

[0003] Ultrasound imaging is an imaging method that uses sound waves to produce images of the structures inside a patient's body. Because ultrasound images are captured in real time, they can also show the movement of internal organs and the flow of blood through blood vessels. These images can provide valuable information for diagnosis and guiding the treatment of various diseases and conditions.

[0004] Wide field-of-view 3D imaging with large steering angles typically requires two-dimensional (2D) (matrix) array transducers with high element density in both azimuth and elevation. On the other hand, high resolution and high sensitivity usually require wide apertures. Therefore, good 3D transducers typically require very high transducer element counts, ranging from several thousand to tens of thousands of elements. High element counts present a major implementation challenge for imaging systems, particularly for receive beamforming, forcing the element count to remain low and / or limiting receive beamforming to multi-step beamforming, where only the first step involves a microwave beamformer, closely proximate to or integrated with the array, and the second step involves a macro beamformer, located on a remote processor. Microwave beamformers typically perform intra-array beamforming and are often single-beam analog beamformers that generally lack dynamic focusing capabilities. Macro beamformers perform inter-array beamforming and are often digital beamformers with dynamic focusing and multi-beam (parallel beam) capabilities. Step-by-step processing can create connectivity issues via flexible / cable systems and limit signal and control data bandwidth.

[0005] General-purpose processors and field-programmable gate arrays (FPGAs) consume far more power than wearable products can handle. Summary of the Invention

[0006] For autonomous operation, the imaging on-chip system requires a low-power, full-featured central controller, which is integrated into an application-specific integrated circuit (ASIC). This, in turn, necessitates a streamlined ultrasound-specific architecture and a streamlined input parameter set for the central controller to reduce on-chip storage requirements.

[0007] In some approaches, the matrix array transducer is integrated with transmit and receive beamformers packaged in an application-specific integrated circuit (iSoC) with a digital acquisition channel for each transducer element. This helps reduce the cost, size, weight, and power consumption of ultrasound imaging systems, while increasing functionality (e.g., real-time 3D) and improving performance. An on-ASIC delay and weight (apodization) computer is also provided, which uses several parameters for each beam to generate the delay and apodization of transmit and receive beamforming on-chip. This eliminates the need to pre-compute and store the delay and apodization profiles, which could potentially require large amounts of memory, especially for matrix array transducers used for 3D imaging.

[0008] To support a wide range of clinical applications, ultrasound imaging systems can perform imaging in various modes with diverse features (e.g., B-mode, color Doppler, spectral Doppler, M-mode, elastography, etc.), various scan geometries (sector, vector, trapezoidal, linear, adjustable-direction linear, conical, rectangular prism, etc.), and various numbers of dimensions (1D, 2D, 3D, 4D). To support this rich set of capabilities, imaging systems employ software-controlled general-purpose processors (Central Processing Unit (CPU), Graphics Processing Unit (GPU)) or Field-Programmable Gate Arrays (FPGAs) that run complex mode-specific and feature-specific scan sequence algorithms and state machines for data acquisition and update parameters of the transmit and receive beamformers and other signal processing blocks at each pulse-echo event. Integrating an on-chip central controller for imaging devices has always been a challenging task. Furthermore, the complexity introduced by the large number of parameters required for each imaging mode remains unresolved for on-chip controllers.

[0009] This disclosure describes a method and system for an imaging system-on-a-chip (iSoC) capable of autonomous scanning and imaging without requiring real-time control from an external processor. This enables the development of low-cost, low-power, small, and lightweight imaging products that can be worn by patients for diagnosis, monitoring, or treatment.

[0010] In some examples, this paper discloses methods and systems that enable an imaging on-chip system to autonomously scan and image in any mode with any characteristics, in any scan geometry, and in any dimension without real-time control by an external processor.

[0011] In a preferred embodiment, the imaging on-chip system has an on-ASIC input memory that stores a set of instructions for the scan sequence and timing and imaging parameters for each event in the scan sequence. The scan instructions and parameters that collectively define the scan sequence are referred to as the scan design. In this preferred embodiment, the imaging on-chip system also has a dedicated ultrasound central controller that can generate the scan sequence based on the instructions in the input memory and execute each transmit and receive event in the scan sequence using the desired timing and imaging parameters also captured in the input memory. In a preferred embodiment, the scan design consists of programmable nested loops in the spatial and temporal dimensions of the transmit and receive events, where each event or event loop is preceded by imaging and timing parameters to be updated at that point in the scan sequence. In a preferred embodiment, the imaging parameters are streamlined to minimize the on-ASIC storage requirements of the scan design.

[0012] In some aspects, an on-chip ultrasound imaging system for autonomous scanning includes an on-chip processor configured to read scan sequence instructions and parameters. In some examples, the ultrasound imaging system also includes on-chip input memory for storing the scan sequence instructions and parameters. In some examples, the ultrasound imaging system includes an on-chip beamformer configured to be programmed and timed by the processor according to the scan sequence instructions and parameters. In some examples, scan sequence instructions and parameters are received from an external user equipment. The scan parameters are optimized or minimized to accommodate limited input memory capacity. In some examples, the scan sequence instructions and parameters include programmable nested loops, and each of the programmable nested loops corresponds to a transmit and / or receive event in the scan sequence.

[0013] Scans performed autonomously by the on-chip central controller consist of a periodically repeating sequence of events. In some examples, the scan sequence may include individual events, time loops of events, and spatial loops of events in x and y, wherein each event and the event loop from the innermost event loop, the x loop, and the y loop to the outermost scan loop are timed.

[0014] For example, when a user sends a command to the on-chip central controller (CPU) to begin a scan, such as from an external processor, the CPU autonomously executes the scan sequence instructions and parameters, collectively referred to as the scan design, stored in its internal input memory, without any further intervention from the user. The user can pause, resume, or stop the scan. The scan design includes the scan sequence instructions and parameters for each transmit and / or receive event, as well as an event loop comprising the scan sequence. The scan design also defines the timing, inter-event, and / or inter-loop periods for full-frame / plane 2D imaging, two planes for dual-plane imaging, and full-volume 3D imaging. The scan design can serve as the framework for the autonomous scanning process. The CPU drives the execution of the scan design. Multiple scan designs, each tailored for different imaging modalities, features, or clinical applications, can be stored in the input memory and selected by the user as needed.

[0015] In contrast to scanning processes in some other approaches (such as those running on power-hungry CPUs, GPUs, FPGAs, or software utilizing a combination of pattern-specific and scan geometry-specific programs), the subject matter techniques disclosed herein provide a pattern / feature and scan geometry-agnostic scan design / framework to flexibly adapt all possible scan requirements to autonomous scans executed by ASICs.

[0016] Additional features and advantages of the present subject matter will be set forth in the following description, and will be apparent in part from the description, or may be learned by practice of the present subject matter. The advantages of the present subject matter will be realized and obtained through the structures particularly pointed out in the written description, its embodiments, and the accompanying drawings.

[0017] The systems, methods, and apparatus disclosed herein are innovative in several ways, but no single aspect is solely responsible for the desired properties disclosed herein.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the technical subject matter.

[0019] Note that the various embodiments described above can be combined with any other embodiments described herein. The features and advantages described in the specification are not all inclusive, and in particular, many additional features and advantages will be apparent to those skilled in the art upon consideration of the drawings, specification, and claims. Furthermore, it should be noted that the language used in the specification has been chosen primarily for readability and instruction purposes and may not have been chosen to depict or limit the subject matter of the invention. Attached Figure Description

[0020] Various features of illustrative embodiments of the present invention are described below with reference to the accompanying drawings. The illustrated embodiments are intended to show, and not limit, the invention. The drawings include the following: Figure 1 An exemplary architecture of components of an Autonomous Imaging System-on-Chip (AiSoC) according to some embodiments is shown. Figure 2 An exemplary schematic diagram of an ultrasound system using a transducer assembly and a remote processor having a user interface and a display, according to some embodiments, is shown. The transducer assembly includes a 2D transducer array and an ASIC mounted on a PCB with additional circuitry. Figure 3 A schematic diagram of a digital 3D single-stage full array beamformer with ASIC is shown according to some embodiments. Figure 4 A schematic diagram of a digital 3D two-stage full array beamformer with ASIC is shown according to some embodiments. Figure 5 A graph showing the geometry of an ultrasonic beam generated by an ultrasonic transducer array according to some embodiments is shown. Figure 6 A flowchart of a 3D dynamic delay and weighted computer is shown according to some embodiments. Figure 7 A graph showing the geometry of an ultrasonic beam generated by an ultrasonic transducer array according to some embodiments is shown. Figure 8A and Figure 8B An exemplary rectangular beam grid for a sampling prism is shown according to some embodiments. Figure 9 An exemplary scanning design according to some embodiments is shown.

[0021] Reference will now be made to embodiments, examples of which are illustrated in the accompanying drawings. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without requiring some of these specific details. Detailed Implementation

[0022] It should be understood that various configurations of the subject matter will become apparent to those skilled in the art based on this disclosure, wherein the various configurations of the subject matter are shown and described by way of illustration. As will be appreciated, the subject matter can have other different configurations, and certain details thereof can be modified in various other respects, all without departing from the scope of the subject matter. Therefore, the summary, drawings, and detailed description are to be considered illustrative rather than restrictive.

[0023] The detailed description set forth below is intended as a description of various configurations of the subject matter, and not as representing only the configurations in which the subject matter can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description. The detailed description includes specific details to provide a thorough understanding of the subject matter. However, it will be apparent to those skilled in the art that the subject matter can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring the concepts of the subject matter. For ease of understanding, the same components are labeled with the same element reference numerals.

[0024] Figure 1 An exemplary architecture of components of an Autonomous Imaging System-on-Chip (AiSoC) 1022 according to some embodiments is shown. This disclosure focuses on Figure 1 The central controller and input memory are shown.

[0025] refer to Figure 1 The input memory 1002 can store multiple scan designs selectable by the user. The memory 1002 can be a read-only memory (ROM or EEPROM), which is programmable only at the factory using pre-designed scan sequences. Alternatively, the memory 1002 can be a random access memory (RAM, SRAM, DDRSRAM) for storing field-upgradable scan sequences.

[0026] Autonomous scanning is performed by the ASIC's central controller 1004. The central controller 1004 reads the scan design from the input memory 1002, executes the scan sequence instructions, and simultaneously distributes imaging parameters to the appropriate components in a synchronous manner based on timing parameters also in the scan design. The central controller 1004 is agnostic to the scan geometry, mode, and features. The central controller 1004 executes the scan design faithfully without any use case knowledge.

[0027] The components of the AiSoC controlled by the central controller 1004 may include a beamformer 1006, a detector 1008, an output memory 1010, and a transceiver 1012. The beamformer 1006 may have an on-chip delay and weighting (apodization) computer 1014, a transmit beamformer 1016, and a receive beamformer 1018. The transmit beamformer 1016 and the receive beamformer 1018 drive and receive from an array of transducer elements 1020. Preferably, the AiSoC 1022 is integrated with the transducer array for efficient and low-cost coupling to the transducer elements 1020. The transducer 1020 may be a 1-D, 1.25-D, 1.5-D, or 2-D array. The transducer 1020 may be a microelectromechanical sensor (MEMS), such as a piezoelectric or capacitive microelectromechanical ultrasonic transducer (pMUT or cMUT).

[0028] Detector 1008 may include a complex demodulator that down-converts to baseband, followed by a decimator, an envelope detector and logarithmic compressor for B-mode detection, a clutter filter, an autocorrelator for color Doppler modes, and a flow parameter detector. Output memory 1010 provides a buffer for the processed output of the beamformer so that the output can be transmitted to external processor 1024 for further processing (e.g., volume rendering) and display. Transceiver 1012 may be wired, such as USB, or wireless, such as Bluetooth or Wi-Fi.

[0029] Ultrasonic imaging system

[0030] Figure 2 Exemplary embodiments of the ultrasound imaging system disclosed herein, according to some embodiments, are shown. The imaging system may include an application-specific integrated circuit (ASIC) (100) preferably integrated with transducer 200. The transducer may be a one-dimensional or two-dimensional array of pMUT (piezoelectric micromechanical ultrasonic transducer), cMUT (capacitive micromechanical ultrasonic transducer), or bulk PZT elements. The ASIC and transducer array are typically mounted on one or more printed circuit boards (PCBs) (300). The PCB may have additional circuitry, such as (optional) microprocessors, power supplies (batteries, regulators), clocks, memory, and input / output devices.

[0031] An ASIC, a transducer array, and a PCB constitute a transducer assembly (400). The area of ​​the transducer assembly can be matched with the area of ​​the transducer array to maintain a small coverage area. The transducer assembly can be packaged in a surface mount or in a wearable or handheld housing.

[0032] The transducer assembly can communicate with a remote processor (500) via input / output devices. The remote processor may include a user interface, a display, and memory. The processor may be a mobile device, such as a smartphone, smartwatch, tablet, or laptop, or it may be a desktop computer. The processor can perform image processing, perform planar and volume rendering, and connect to networks and databases such as electronic health records. Communication between the transducer assembly and the remote processor can be wired or wireless, using standard communication protocols.

[0033] In one example, the microprocessor on the transducer assembly can initialize the ASIC with a small set of parameters (e.g., imaging frequency and transmit and receive f-numbers), and can then provide transmit and receive beam parameters (beam origin, angle, depth of focus) for each pulse echo (transmit-receive) event in the scan sequence. A delay and weighting computer on the ASIC can calculate the transmit and receive beamforming parameters (delay and weighting) for each beam defined by the transmit and receive beam parameters. The ASIC can emit directional and focused transmit pulses, receive echoes from the tissue at each transducer element, and form the receive beam using the delay and weighting calculated by the ASIC. The ASIC's output is typically a fully formed beam using the full aperture.

[0034] In an alternative example, the microprocessor on the transducer assembly is optional and can assist the ASIC in communicating with a remote processor for field upgrades of the ASIC input memory or by transmitting the formed beam and collected information to the remote processor for further processing, analysis, or display. A central controller on the ASIC (e.g., 1004) executes the scan design defined by the scan sequence instruction set and imaging system parameters stored in the ASIC's input memory, periodically forming frames or volumes of images without real-time control from an external processor. An on-ASIC delay and weighting computer can calculate the static transmit and dynamic receive beamforming parameters (delay and weighting) for each beam, defined by the transmit and receive beamforming parameters in the scan design. The ASIC can emit directional and focused transmit pulses, receive echoes from the tissue at each transducer element, and form the receive beam using the delay and weighting calculated by the ASIC. The ASIC's output typically uses a fully formed beam with full aperture.

[0035] The following sections describe the transducer assembly, transmitter and receiver, geometry for deriving the 3D delay equation, and methods and apparatus for performing delay and weighted calculations using the 3D delay equation.

[0036] Transducer assembly

[0037] Figure 3 Details of a transducer assembly (400) and an ASIC (100) within the transducer assembly, according to some embodiments, are shown.

[0038] In one example, the ASIC receives input (101) from a microprocessor on a PCB (300). The input may include initialization parameters such as transmit center frequency and bandwidth, transmit and receive f-numbers, and receive center frequency and bandwidth. The ASIC may also receive transmit beam parameters and receive beam parameters, as well as triggers for each pulse echo event. The transmitter may create a transmit pulse (110), apply element coordinate-dependent delay (111a) and weighting (111b) to the pulse, and drive a pulse generator (112) for each acoustic element based on the transmit pulse and transmit beam parameters, utilizing the delayed and weighted pulse.

[0039] In an alternative example, the microprocessor on the PCB (300) is optional, and this optional microprocessor on the PCB (300) can assist the ASIC in communicating with a remote processor for field upgrades of the ASIC input memory, or in transmitting the formed beam and collected information to the remote processor for further processing, analysis, or display. A central controller on the ASIC (e.g., 1004) executes the scan design defined by the scan sequence instruction set and imaging system parameters stored in the ASIC's input memory, thereby periodically forming frames or volumes of images without real-time control from an external processor. An on-ASIC delay and weighting computer can calculate the static transmit beamforming parameters and dynamic receive beamforming parameters (delay and weighting) for each beam, defined by the transmit and receive beamforming parameters in the scan design. The ASIC can emit directional and focused transmit pulses, receive echoes from tissue at each transducer element, and form the receive beam using the delay and weighting calculated by the ASIC. The ASIC's output is typically a fully formed beam using the full aperture.

[0040] The receiving path of each acoustic element may include a transmit / receive switch (121), an analog front-end (122) for low-noise preamplification, time gain compensation, and anti-aliasing, an analog-to-digital converter (ADC) (123), an element memory (124), and a beamformer (125) that can apply time-varying (dynamic) delays and weights to the stored element data. The transmit beamformer (delay and weighting), pulse generator, receive switch, analog front-end, ADC, memory, and receive beamformer (delay and weighting) circuitry may constitute an electronic component (120). Each acoustic element may have one electronic component.

[0041] The outputs of the electronic components can be summed across the entire array (140) to complete full-array beamforming. The beam thus formed can then be filtered by a receive filter (150) for data compression, which may include demodulation to baseband by a complex time-varying multiplier followed by a low-pass baseband filter (BBF). The delay, weighting, array, and receive filter circuitry can be replicated to form multiple beams with different delay and / or weighting parameters in parallel (160) using the same component data stored in memory. The delay and weighting of the transmit and receive beamforming (for all parallel beams) can be created by a 3D dynamic delay and weighting computer (170) on the ASIC. The output of the ASIC (102) can be complex (in-phase and quadrature-phase) samples of the parallel beams. The transducer assembly stores the output beams and sends them to a remote processor (500) for further processing, rendering, and display.

[0042] Figure 3 The receiving beamforming can also be implemented in multiple stages. Figure 4 A schematic diagram of a digital 3D two-stage full array beamformer with an ASIC, according to some embodiments, is shown. The multi-stage implementation allows for flexible reduction in the size of both the component memory and the parallel beam circuitry. Instead of summing the outputs of all electronic components, the outputs of a subset (subarray) of electronic components (130) can be summed (131) and stored in a second subarray memory set (132). The first stage beamforming in each subarray can also be referred to as microwave beamforming. The second stage applies delay and weighting (133) to the subarray beamformer outputs, and the array sum (140) can complete the full array beamforming. Only the second-stage circuitry (macro beamformer) can be replicated for parallel beam operation. The subarray size can be... 1 component, of which and It can be 2 electronic components, 3 electronic components, 4 electronic components, 5 electronic components, etc.

[0043] transmitter

[0044] A K-bit deep, L-bit long shift register with a programmable clock can be used as an arbitrary programmable pulse generator (110).

[0045] The depth K of the shift register can be determined by the number of pulse generator states. Typically, a K-bit deep shift register can support up to 2^360 bits. K A pulse generator has several states. Therefore, for a 2-state (unipolar) pulse generator, K will be 1; for a 3-state (bipolar) and 4-state pulse generator, K will be 2, and so on.

[0046] The length L of the shift register can be determined by the maximum pulse length specification and the transmitter clock frequency. In a preferred embodiment, the shift register length L is set to 256 bits. This will support long pulses of up to 16 cycles in the transmit clock cycle (which is 16 times the transmit center frequency). Pulses longer than 16 cycles can still be supported by reducing the transmitter clock frequency (trading for delayed quantization steps).

[0047] The simplest type of pulse can be a unipolar pulse, where the active node of the transducer element is switched between ground and positive (or negative) voltage rails via two complementary switches. These switches can be controlled by a single one-bitstream, a set of 1s for the +V segment, followed by a set of 0s for GND, with this pattern of 1s and 0s repeated multiple times as needed. Each bit can represent the duration of a transmitter clock cycle. Therefore, if the transmitter clock cycle is... Then in The bit stream of the two-cycle pulse will be 11111111000000001111111100000000. The duration of each +V and GND segment can be fixed or independently programmable, for example, for linear (or nonlinear) frequency modulation or some other coded stimulus. This bit pattern can be pre-generated during initialization and loaded into the pulse generator shift register in the ASIC, and flow out when a pulse indicating the start of transmission is received. In some embodiments, the start and / or end of the pulse can be marked by a very short code (e.g., 010), such as 11111111000000001111111100000000 010 This triggers other transmit and / or receive circuitry to turn on or off. Using this embedded code may require a decoder (matched filter) of the same length. In some embodiments, instead of waiting for all components to complete their pulse transmission, each component's transmit / receive switch can be turned on to receive mode as soon as its own pulse transmission is complete. This can help clear some near-field artifacts by temporarily dispersing leaked transmit and receive enable / disable signals and eliminate dead zones caused by lost receive sampling.

[0048] Next, we come to the more complex 3-state bipolar pulse, where the active node of the transducer element is switched between a positive voltage rail, ground, and a negative voltage rail via three complementary switches. This type of pulse can be implemented using a 2-bit deep pulse stream, where, for example, 00 represents ground, 10 represents +V, and 01 represents -V. An 11-state can be used to mark the start and / or end of the pulse.

[0049] A special case of a 3-state bipolar pulse is that the transducer is grounded only before the pulse begins and after the pulse ends, and switches between +V and -V states during the pulse. Compared to all 2-state pulses with a ground segment within the pulse and those 3-state pulses, this type of pulse provides the best second harmonic suppression. It can also be the simplest (lowest cost) architecture in terms of power supply. This special case of a bipolar pulse can be implemented using a single bitstream as described above, where 1 is mapped to +V and 0 is mapped to -V. The embedded code snippet described above can be used to indicate the start of the ground state at the end of the pulse. Upon receiving this code, the transducer element is grounded until the start of the next pulse indicated by the stream of 1s. Pulse inversion capability can be added along with additional programmable bits shared by all elements that invert the mapping of 1 and 0 values ​​to -V and +V at the pulse generator.

[0050] Under the action of the pulse marking the start of the pulse echo event, a pulse shared by all elements can be generated, which typically repeats at a regular pulse repetition interval (PRI). The pulse can then be delayed (111a) by element-specific delays for the elements of the array (and in some embodiments, for each element). The delayed pulse can then be weighted by element-specific weighting for apodization. Here, a simple binary on / off weighting is shown. In a preferred embodiment, the delay and weighting of the transmit beamformer are generated by a delay and weighting computer (170) on the ASIC before the transmit event begins.

[0051] The output of the apodization can drive the pulse generator (112) after digital-to-analog conversion.

[0052] In some embodiments, for architectural simplicity, the pulse generator and delay operation share the same transmitter clock. Furthermore, for efficiency purposes, the transmitter clock frequency... It can be used as the center frequency for transmission. The function changes accordingly and can be set to equal 16. To achieve the desired delay quantization step size ,in .

[0053] In some embodiments, the order of the pulse generator, delay, and binary weighting can be changed. For example, to accommodate various architectural trade-offs, the binary weighting can be moved before the delay operation, or the delay operation can be moved before the pulse generator, etc.

[0054] receiver

[0055] A typical receiver pairs from various components The echo is dynamically adjusted with varying gain, delay, and weighting (apodization), where (i, j) are the column and row indices of the elements in the matrix array. The beamformer can then sum the amplified, delayed, and weighted element signals to generate a beam. ,in The origin of the beam Coordinates (for planar arrays, (where r is zero), and r is the depth. It represents the beam angle in the zx and zy planes. For digital beamformers, analog signals can be converted into digital signals by an ADC before the delay stage and after the LPF.

[0056] Gain It can have multiple programmable components, including the static low-noise amplifier gain G. LNA and dynamic time-varying gain (Also known as time gain compensation) to compensate for tissue attenuation. The final gain stage can be an optional programmable gain amplifier.

[0057] A low-pass filter (LPF) with a preferred programmable cutoff frequency provides anti-aliasing and improves the signal-to-noise ratio (SNR). Multiple poles of the LPF can be distributed across the various gain stages.

[0058] Dynamic delay It can vary over time to track the depth of the echo source as the transmitted beam propagates deeper into the tissue. The input to the delay stage is a function of time, while its output is a function of depth (range). Depth is the time distortion caused by the time-varying delay.

[0059] Dynamic toe cutting or weighted The effective aperture size can be increased with depth to maintain resolution, and the contribution of edge elements (i.e., apodization) can be gradually reduced to decrease beam sidelobes. For matrix arrays, the effective aperture shape can also have apodization effects. In some embodiments, apodization weighting is depth-dependent, but it is binary, with 0 for off and 1 for on, thus eliminating the need for multiplication for each element and each depth. Semicircular apodization is achieved by turning on elements around the beam origin within an ever-growing circle or ellipse. The growth rate of the circle and ellipse can be controlled by a programmable f-number. This is due to the application of [f-number] before delay operation. Therefore, the gain can be distributed over time as a function of the element-dependent delay. This can produce an additional apodization effect on depths where the gain changes rapidly.

[0060] Given beam parameters and Component coordinates ADC sampling rate Speed ​​of sound In the case of f-numbers, dynamic delay and weighted calculations can be performed by a computer. In many existing technology systems, these calculations are performed entirely or partially on a remote processor.

[0061] The element summation stage can sum time-aligned (and therefore coherent) and weighted element signals.

[0062] Multiple beams with independent origins and angles can be generated in parallel using a set of replicas at delay, weighted summation, and element summation levels. Alternatively, if the element data is stored for the entire depth of interest, multiple beams can be formed serially using a single beamformer circuit system, taking into account the time between transmission events, thus compromising frame rate.

[0063] Array and beam geometry

[0064] Figure 5 A graph showing the geometry of an ultrasonic beam generated by an ultrasonic transducer array according to some embodiments is shown.

[0065] Figure 5 This describes the situation on the xy-plane centered at Cartesian coordinates (0,0,0) (or on a non-planar curved xyz-plane). Figure 5 (not shown in the image) A 2D array of elements (201). The x, y, and z coordinates of the (i, j)th element The elements of the 2D array can be on a square or rectangular grid, a rotated square, a rhombus (parallelogram), a hexagon, a ring, or any arbitrary grid. The physical aperture can be square, rectangular, circular, or elliptical, or any shape.

[0066] In 3D, a beam can be defined by three parameters: the focus depth *r* of the static transmit focus, or the focus depth set of the dynamic receive focus, and the (nominal) beam origin. It is its x, y and z coordinates. The vector and the angle It is also the angle between its zx plane and zy plane. The vector. Note that bold letters are used here to indicate vectors such as... and The vector. The sample along the receiving beam. The coordinates at depth (or range) r are .for The agreement is to make and The points from the +z axis to the +x and +y axes are positive, respectively. Beam origin. Also the depth zero point It also eliminates beam truncation caused by physical aperture. The nominal center of the effective aperture. All samples of the receiving beam lie on such a line whose projections are angles on the zx and zy planes, respectively. and Place.

[0067] 2D imaging in the azimuth (i.e., xz) plane is a special case, in which... and For all beams, it is zero. 2D imaging in the orthogonal elevation (yz) plane corresponds to... and All zeros. A special case of 2D imaging is when the array is a 1-D array, for example, .

[0068] The geometry defined here can support independent combinations of scan geometries for both azimuth and elevation. For example, to define sector geometry for both azimuth and elevation, and For all beams, the value will be set to 0. For linear scans, such as at the elevation angle, All beams are set to zero, while the values ​​are changed from the first row to the last row. For vector formats, such as at elevation angles, It will change from a negative angle to a positive angle, and simultaneously change from the first row to the last row. .

[0069] The geometry here can also be applied to multi-stage beamforming, where the first-stage subarray beamformer (microbeamformer) is... Each element group performs beamforming, and the second stage The beamformer (macro beamformer) completes beamforming from the output of the subarray beamformer, whereby... and .

[0070] In some examples, alternative coordinate systems such as spherical coordinates exist to define the beam in 3D. The framework used here is based on the beam origin. Angles in spherical coordinates centered and beam angle The relationship between them is:

[0071] The analysis and derivation here can be applied to any alternative beam definition with minor modifications.

[0072] 3D Delay Equation

[0073] It is now possible to derive the beam-side parameters for a specific element (i, j). Distance of depth r .

[0074] Beam Sample Cartesian coordinates yes:

[0075] Wherein, the unit vector along the beam yes:

[0076] And the x, y, z coordinates of the beam are:

[0077] Then, and The distance between them is given by the following formula:

[0078] The square root of the sum of the squares of three terms can be written as the square root of the sum of the squares of two terms, as follows:

[0079] Delay in μs Distance in mm Bidirectional sound velocity in mm / μs .

[0080] Or at ADC sampling rate The number of samples (in MHz) is the unit.

[0081] 3D dynamic time-lapse and weighted computing

[0082] The above delay formula is suitable for an efficient implementation using CORDIC (Coordinate Rotation Digital Computer), which is an efficient method for calculating the square root of the square of two numbers. Figure 6 A block diagram and steps of a dynamic 3D delay and weighting computer (170) using two cascaded CORDIC operations (176) according to some embodiments are shown.

[0083] The inputs to a delay and weighted computer may include the origin of the beam, the unit vector and (one or more) focal depths, the coordinates of the elements, the ADC sampling rate, the speed of sound, and the f-number.

[0084] The beam unit vector Cartesian coordinates (171) can be multiplied by the depth (172) and added to the beam origin coordinates (173) to create beam sample Cartesian coordinates (174) for a specific depth r. The x, y, and z coordinates of the element can be subtracted from the corresponding x, y, and z coordinates of the beam sample (175) to create the inputs for the CORDIC operation. The output of the first CORDIC and the x-component of the beam sample constitute the input of the second CORDIC. The output of the second CORDIC provides the element (i, j) and the beam sample. The distance between the two CORDIC stages is scaled by the gain of the two CORDIC stages (CORDIC is not a unity-gain operation). In a preferred embodiment, CORDIC gain compensation can be performed by a distance-delay conversion multiplier at the output of a delay computer (178).

[0085] In some embodiments, the cascaded CORDICs are each rotated at eight angles. This number of rotations is sufficient to minimize the maximum distance error. Inside, among which At the imaging center frequency The period is . Each angular rotation can be achieved using 2 shifts and 2 additions. For eight angular rotations, each CORDIC stage has a gain of approximately 1.65, and two CORDIC stages together have a total gain of approximately 2.71.

[0086] In some examples, high-precision distance (delay) calculations based on CORDIC may be necessary only for sparse sets of depth, elements, and beams. Linear interpolation between the CORDIC-calculated distance values ​​(177) is sufficient to keep delay errors within specifications. In some embodiments, a coarse distance grid is spaced out. ,in At the imaging center frequency The wavelength at that location. A linear distance interpolator provides the midpoint distance value between coarse distance grid points. In some embodiments, CORDIC-based delay calculations are performed on a subset of beams (e.g., the edge beams of a multi-beam group), and the linear distance interpolator provides the distance value between the beams. In some embodiments, the coarse element grid is spaced 4 elements apart in both azimuth and elevation. Again, the linear distance interpolator can interpolate the distance value between elements. Since linear interpolation only requires addition and bit shifts for upsampling to powers of 2, they can be very efficient.

[0087] The final stage of the delay engine (178) compensates for the non-unity gain of the CORDIC stage and uses the ADC sampling rate and sound velocity as inputs to measure distances in mm. Delay converted to ADC sampling rate Performing distance-delay conversion at the very output allows for easy optimization of the volume sound velocity as a function of clinical applications and the ADC sampling rate as a function of the imaging center frequency. Alternatively, in some embodiments, the CORDIC input parameters may be pre-compensated (pre-scaled) by the central controller for the CORDIC gain and distance-delay conversion factor to eliminate delay and multiplication within the weighted computer.

[0088] The order of linear operations is interchangeable. For example, distance-delay conversion can be performed at any point in the delayed computer signal path, or interpolation can be reordered depending on the specific considerations of the implementation.

[0089] In some embodiments, the weighting is binary, meaning that elements are either on or off at any given time / depth. A delay computer can provide input to the weighting computer. In some examples, the distance between any element and the beam origin can be calculated by the delay computer by setting r to zero. This distance is scaled by a scalar as a function of the f-number (aperture growth rate), which can be compared to the distance output of the delay computer during the reception event to enable each element (179) to open at the correct time (depth). Using this method, the aperture can be grown into a circle around the beam origin. Alternatively, the growth rate and aperture limit can be programmed independently for x and y (e.g., for rectangular or elliptical aperture growth).

[0090] Data Acquisition

[0091] Data acquisition for all imaging modes and features can be generalized through a unified concept of sampling in the spatial, temporal, and parametric domains. This concept allows for the definition of scan designs for any imaging mode or feature (B-mode, color Doppler, spectral Doppler, M-mode, elastography, pulse inversion, composite, etc.) in any scan geometry (sector, trapezoidal, or linear, conical, rectangular prism, etc.) and any number of dimensions (1D, 2D, 3D, 4D), as nested scan loops of events in the spatial and temporal domains, while simultaneously varying a small set of parameters between events. Events can be pulse-echo (transmit and receive), pulse-only, or echo-only events.

[0092] For example, a planar or 2D image can be formed by sampling the xz or yz plane through sequential electronic scanning of the transmitted beam along the x-axis or y-axis. Conversely, a volumetric or 3D image can be formed by raster scanning of the transmitted beam along both the x-axis and y-axis, thus sampling the entire xyz space. Typically, the x-axis or azimuth is the fast scan axis, while the y-axis or elevation is the slow scan axis. In some applications, the fast and slow axes can be rotated relative to the x-axis and y-axis, respectively.

[0093] A receive beamformer uses the echoes received in response to each transmit event to form multiple receive beams in parallel. The parallel receive beams can be distributed along the x and / or y axes, typically centered on the transmit beam axis (line of sight).

[0094] The transmit and receive sampling grids in x and y can be uniformly spaced along the beam angle, uniformly spaced along the sine of the beam angle (closer towards the z-axis), or uniformly spaced at the beam origin. Alternatively, spatial sampling can be on a nonlinear grid, such as a hexagon, spiral, etc.

[0095] Real-time 2D or real-time 3D (e.g., 4D) images are formed by repeating the volumetric or planar scans described above at regular time intervals.

[0096] Patterns used to detect motion or flow, such as color Doppler, spectral Doppler, and M-mode, require temporal sampling, in which the object is sampled at regular time intervals at each line of sight (spatial location).

[0097] Modes used to improve detail resolution, contrast resolution, or penetration, such as synthetic aperture, pulse inversion second harmonic, frequency compounding, spatial compounding, and sequential focus, require parameter domain sampling. In these modes, the object is sampled multiple times as parameters such as aperture, phase, frequency, insonification angle, or focus change. Parameter changes can be event-based, frame-based, or volume-based alternating.

[0098] In a preferred embodiment, the concepts of sampling in the spatial, temporal, and parameter domains generate a pattern-agnostic and feature-agnostic architecture and language for the central controller.

[0099] Array and beam geometry

[0100] Figure 7 A graph showing the geometry of an ultrasonic beam generated by an ultrasonic transducer array according to some embodiments is shown.

[0101] Figure 7A 2D array is shown, where Cartesian coordinates are centered on the array's center, with the x-axis being the array's major axis (or azimuth) and the y-axis being the array's minor axis (or elevation). Assume the object / organization is z≥0. Whether transmitting or receiving, the beam axis is determined by a pair of vectors. Defined as follows: one vector for the angle and one vector for the origin. Beam angle vector. It can be determined by the angle between the z-axis and the projection of the beam onto the xz and yz planes. To define. The beam origin vector of the beam. The x and y coordinates of the points on the 2D array surface can be determined by the beam passing through them. To define it. For a planar transducer array, the z-coordinate of the beam origin is zero.

[0102] The 3D space is sampled along the receiver beam set (grid) at regular depth intervals, with each receiver beam having a unique angle and / or origin. Receiver beam Spatial sampling points The depth r is defined as the beam origin and the spatial sampling point. The distance between them (see the thick arrow).

[0103] Scan geometry

[0104] Imaging systems can be programmed to scan a single line, a plane (e.g., the xz plane), two planes (e.g., the xz and yz planes), multiple planes, or volumes. Based on the beam grid used for spatial sampling, the 2D scanning geometry can be sector, vector, trapezoidal, linear, adjustable-direction linear, etc., and the 3D scanning geometry can be pyramidal, conical, frustum, truncated cone, cuboid, tilted cuboid, etc. For example, if all beams originate from the center of the array, the scanning geometry is sectoral, pyramidal, or conical. If the beam origin is distributed over at least a portion of the aperture, and all beam angles are zero, it is a linear scanning geometry or a cuboid. If the beam origin is distributed over the aperture, and all beam angles are the same and not zero, it is an adjustable-direction linear or tilted cuboid. If the beam origin is distributed over the aperture, and the beam angles monotonically change in the x and y directions, it is a trapezoidal scanning geometry, frustum, or truncated cone. There are also hybrid scan geometries, for example, a 3D scan geometry can be a trapezoid in one of the horizontal axes and linear along the orthogonal axes.

[0105] Figure 8A and Figure 8B An exemplary rectangular beam grid for a sampling prism is shown according to some embodiments. Here, a 33×19 beam grid is used. The total of 627 transmit beams are uniformly distributed in angle and origin domains in an independently programmable angle and origin domain, which are off-center to indicate programmability of arbitrary volume.

[0106] In this example, the transmit beam angle and Start at one corner of a rectangular grid And with beam spacing and The parameters, along with the number of transmitted beams in x and y (33 and 19 in this example, respectively), define the angular span of the 3D FOV. The larger square represents the limit of the array's deflectability (maximum angular domain), which is a function of the imaging center frequency, the array element spacing, and the effective element width.

[0107] Figure 8A A smaller rectangular grid 802 for the angles of the parallel receive beam groups is also shown, where the receive beams will be formed in parallel by the receive beamformer in response to each transmit beam. Here, there are a total of 21 parallel receive beams on a 7×3 beam grid. Centered on the angle of each transmitted beam. For simplicity, only the parallel receive beam angle grid is shown for one of the transmitted beams. In this example, the parallel receive beam angle... and Relative to (each) transmit beam angle, starting from And with beam spacing and Increase evenly.

[0108] Figure 8B An example of the same beam origin grid with 33×19 transmit beams and 7×3 parallel receive beams is also shown. The transmit beam origin and the parallel receive beam origin are spaced apart in x and y by beam spacing. and The beams are evenly spaced. The domain of the origin of the transmitting beam is defined by one corner of a rectangular grid. The domain of the parallel receive beams relative to each transmit beam is defined by the number of transmit beams in x and y (33 and 19 in this example, respectively). The number of parallel receiving beams in x and y (7 and 3 in this example, respectively) defines the beam origin. The larger rectangle 804 shows the maximum domain of the beam origin. Its size is equal to that of the acoustic array.

[0109] In some examples, the receive beam angle / origin may or may not coincide with either the transmit beam angle / origin. The angle / origin grid may also be non-uniformly distributed. The receive beam angle and origin may also be defined in absolute terms, rather than relative to the transmit beam angle / origin. All angle parameters here are in degrees, and all origin parameters are in millimeters.

[0110] In some examples, a wide range of scan geometries, as described earlier, can be defined by folding the 2D angle and / or origin meshes into 1D meshes or single points, and / or moving them around in the angle or origin domains. For example, for sector, pyramid, or conical scan geometries, all beam origins are folded to a single point (x, y) = (0, 0) at the center of the array. For linear or cuboid scan geometries, all beam angles are folded to a single point. .

[0111] Scanning Design

[0112] Figure 9 Exemplary scanning designs according to some embodiments are shown. References Figure 9 The scan design 900 is a serialized set of scan sequence instructions distributed with timing and imaging parameters, which are updated between instructions that can be read and interpreted by a central controller. The scan sequence instructions are parameter update, scan loop, y loop, x loop, event loop, and event. Of these, only parameter update and event are fundamental, as all scan designs can be constructed independently from sequences of these two instructions. However, this flattened scan design would consume too much memory and would be difficult to read, understand, and debug. Four loop instructions simplify and shorten the scan design while providing complete flexibility.

[0113] In some embodiments, each scan design instruction may correspond to a given central controller state.

[0114] A scan design can begin with a parameter update instruction to initialize some or all registers before the outermost loop (scan loop) begins. The scan design can use additional parameter update instructions before other instructions such as the y-loop, x-loop, event loop, or event loop. The central controller reads this instruction to enter the parameter update state. In this state, the central controller extracts the parameters listed between the parameter update instruction and the next instruction in the scan design and updates the values ​​of the individual registers in the ASIC. The scan design can update a single parameter, multiple parameters, or all parameters in this state. Once the register updates are complete, the central controller reads the next instruction in the scan design.

[0115] A scan cycle is the outermost loop in a scan sequence. For 2D and 3D imaging, a scan is a 2D frame or a 3D volume, respectively. Scans can include single-mode or mixed-mode scans, such as B-mode and color Doppler. The central controller enters the scan cycle state upon reading the scan cycle instruction and either begins scanning or waits until it receives an external start scan signal before starting scanning. The central controller repeats scans (frames, volumes) indefinitely at a rate determined by the scan cycle repetition interval (the reciprocal of the frame rate or volume rate), or a finite number of times determined by the scan count, or until an external end scan signal. The scan cycle repetition interval and scan count are input parameters that need to be updated before the scan cycle instruction. The start scan and end scan signals are initiated by an external processor, for example, upon user request. The external processor can also pause and resume the scan cycle using pause and resume scan signals.

[0116] The y-cycle and x-cycle are typically the slower (outer) and faster (inner) cycles that control the raster scan of the lateral field of view. The parameters for these cycles include the transmit scan geometry and the cycle repetition interval. More specifically, the y-cycle parameters are: , , , , The loop repeats at intervals of y and x, and the loop parameter is: , The x-cycle repeat interval. In some examples, for a 2D image of the azimuth plane (xz plane), the y-cycle parameter will set the angle and origin of a single y-plane as well as the repeat interval, while the x-cycle repeats at a given inter-beam interval. The beam is sent by scanning from the starting angle and origin at multiples of the x and y loops. The order of the x and y loops can be switched so that the y loop becomes the faster (inner) loop.

[0117] Before the inner loop, the parallel beam mesh parameters also need to be updated. The parallel beam mesh parameters include... , , , , , , , , .

[0118] The event loop is reserved for temporal sampling of objects for motion / flow detection. The event loop initiates a recurring set of events without any parameter updates between events. Two event loop parameters need to be updated before any event loop: the event count and the event loop repetition interval. In some cases, the event loop can alternate with its spatial loop (x-loop or y-loop), for example, for block-alternating color Doppler with long event repetition intervals.

[0119] The central controller enters its event execution state when it reads event commands during the scanning design. Prior to the event, event parameters, transmit beamformer parameters, and receive beamformer parameters need to be set using parameter update commands and parameter values. Event parameters can include the event type (e.g., pulse-echo, pulse only, echo only) and the event duration. Transmit beamformer parameters can include transmit f-number, focus depth, and transmit pulse parameters. Receive beamformer parameters can include receive analog front-end parameters, receive f-number, demodulation frequency, baseband filter parameters, etc.

[0120] In some scanning designs, certain states can be repeated multiple times. For example, within an x-loop, there can be two events, one for shallow transmit focus and one for deeper transmit focus. For frame interleaved mixed mode, within a y-loop, there can be two x-loops sequentially, one for B mode and one for stream mode (see examples below). In some other scanning designs, some of these states may not be used. For example, in a B-mode-only scanning design, there may be no event loop.

[0121] Even if the beamformer parameters are reprogrammed before each common x and common y event, a typical mixed-mode scan design can use less than 1k bits.

[0122] Below is an example of a hybrid-mode scan design. The central controller instructions (text with a colored background) define the scan sequence based on nested loops of events in space (x and y) and time, with parameters to be updated scattered before each loop or event.

[0123] In this example, there are two common y-scans, one for mode B and one for flow. For the first common y-scan (mode B), there are two common x-events, one for shallow focus and one for deep focus. In this example, after initializing all parameters, all x-cycle parameters and parallel beam grid parameters are updated before each common y-event, and all Tx and Rx beamformer parameters are updated before each common x-event. However, note that in many cases, only a subset of these parameters will need to be updated between the common y and common x-events. Therefore, the scan design can be shorter than the example shown in this paper.

[0124] Description of the subject technology of the clause

[0125] For convenience, various examples of aspects of this disclosure are described as numbered clauses (1, 2, 3, etc.). These clauses are provided as examples and do not limit the technical scope of this subject matter. The figures and reference numerals are provided as examples only and for illustrative purposes, and the clauses are not limited by those reference numerals.

[0126] Clause 1. An on-chip imaging system for autonomous scanning, comprising: an on-chip input memory configured to store scan sequence instructions and parameters; an on-chip processor configured to read the scan sequence instructions and parameters from the input memory; and an on-chip beamformer configured to be programmed and timed by the processor according to the scan sequence instructions and parameters.

[0127] Clause 2. The imaging system according to Clause 1, wherein the imaging system is coupled to an ultrasonic transducer.

[0128] Clause 3. The imaging system according to any one of the preceding clauses, wherein the chip is an application-specific integrated circuit (ASIC).

[0129] Clause 4. The imaging system according to any one of the preceding clauses, wherein the processor is configured to autonomously perform a scan, wherein the scan comprises a periodically repeating sequence of events.

[0130] Clause 5. The imaging system according to Clause 4, wherein the event sequence comprises individual events, time loops of events, and spatial loops of events in x and y, wherein each event and each event loop from the innermost event loop, the x loop, and the y loop to the outermost scan loop are timed.

[0131] Clause 6. The imaging system according to any one of Clauses 2 to 5, wherein the imaging system and the ultrasonic transducer are encapsulated within the same ultrasonic probe.

[0132] Clause 7. The imaging system according to any one of Clauses 2 to 6, wherein the imaging system and the ultrasonic transducer are integrated.

[0133] Clause 8. The imaging system according to any one of the preceding clauses, wherein the autonomous scanning includes beamforming processed by the beamformer.

[0134] Clause 9. The imaging system according to any one of the preceding clauses, wherein the processor is a dedicated ultrasound central controller.

[0135] Clause 10. The imaging system according to Clause 9, wherein the dedicated ultrasound central controller is configured to generate a scan sequence based on the scan sequence instructions and parameters.

[0136] Clause 11. The imaging system according to Clause 9, wherein the dedicated ultrasound central controller is configured to execute each event of the transducer in the scan sequence based on the scan sequence instructions and parameters.

[0137] Clause 12. The imaging system according to Clause 11, wherein the event is a transmit and receive event, a transmit-only event, or a receive-only event.

[0138] Clause 13. The imaging system according to any one of the preceding clauses, wherein the scan sequence instructions and parameters are provided by an external process outside the chip.

[0139] Clause 14. The imaging system according to any one of the preceding clauses, wherein the scan sequence instructions and parameters include timing for each event in the scan sequence.

[0140] Clause 15. The imaging system according to any one of the preceding clauses, wherein the scan sequence instructions and parameters include imaging parameters for each event in the scan sequence.

[0141] Clause 16. The imaging system according to any one of the preceding clauses, wherein the scan sequence instructions and parameters are included in multiple scan designs.

[0142] Clause 17. The imaging system according to Clause 16, wherein each of the plurality of scan designs is customized for different imaging modes, features or clinical applications that can be selected by the user.

[0143] Clause 18. The imaging system according to any one of the preceding clauses, wherein the scan sequence instructions and parameters include programmable nested loops.

[0144] Clause 19. The imaging system according to Clause 18, wherein each of the programmable nested loops corresponds to a transmit and / or receive event in the scan sequence.

[0145] Clause 20. The imaging system according to Clause 19, wherein the imaging and timing parameters to be updated at that point in the scan sequence are prior to the transmission and / or reception event.

[0146] Clause 21. The imaging system according to Clause 20, wherein the imaging parameters and timing parameters to be updated are provided from an external user equipment.

[0147] Clause 22. The imaging system according to Clause 20, wherein the imaging parameters are optimized based on the input memory.

[0148] Clause 23. The imaging system according to any one of Clauses 2 to 22, wherein the scanning sequence instructions and parameters include the spatial and temporal dimensions of the transducer's transmit and / or receive events.

[0149] Clause 24. The imaging system according to any one of the preceding clauses, wherein the scan sequence instructions and parameters are used in mode B.

[0150] Clause 25. The imaging system according to any one of the preceding clauses, wherein the scan sequence instructions and parameters are used for mixed modes.

[0151] Clause 26. The imaging system according to any one of the preceding clauses, wherein the scan sequence instructions and parameters include scan geometry.

[0152] Clause 27. The imaging system according to Clause 26, wherein the scanning geometry is used for planar imaging, dual-plane imaging, or multi-plane imaging.

[0153] Clause 28. The imaging system according to Clause 26, wherein the scanning geometry is sector, vector, trapezoidal, linear, or linear with adjustable direction.

[0154] Clause 29. The imaging system according to Clause 26, wherein the scanning geometry is used for 3D imaging or real-time 3D imaging.

[0155] Clause 30. The imaging system according to Clause 26, wherein the scanning geometry is a pyramid, cone, frustum, truncated cone, cuboid, or tilted cuboid.

[0156] Clause 31. The imaging system according to any one of the preceding clauses, wherein the scanning sequence instructions and parameters include instructions for sampling in the spatial domain, the temporal domain, and the parameter domain.

[0157] Clause 32. The imaging system according to any one of the preceding clauses further includes a detector coupled to the processor and the beamformer.

[0158] Clause 33. The imaging system according to Clause 32 further includes an output memory coupled to the detector and the processor.

[0159] Clause 34. The imaging system according to Clause 33 further includes a transceiver coupled to the output memory, the input memory, the processor, and the beamformer.

[0160] Clause 35. The imaging system according to Clause 34, wherein the transceiver is coupled to an external computing device.

[0161] Clause 36. The imaging system according to any one of Clauses 2 to 35, wherein the number of transducers is between 500 and 5000.

[0162] Clause 37. The imaging system according to any one of Clauses 2 to 36, wherein the number of transducers is between 100 and 9000.

[0163] Clause 38. An imaging system according to any one of Clauses 2 to 37, wherein the number of transducers is 2k, where k is a non-negative integer.

[0164] Clause 39. The imaging system according to any one of the preceding clauses, wherein the processor is configured to execute a scan design including the scan sequence instructions and parameters without any knowledge of the usage of the scan.

[0165] Clause 40. An integrated imaging system for autonomous scanning, comprising: an on-chip input memory configured to store scan design data; and an on-chip controller configured to read the scan design data from the input memory and to program and time beamforming of the transducer based on the scan design data.

[0166] Clause 41. An on-chip ultrasound imaging system, comprising: an on-chip controller configured to receive scan design data and program and time beamforming based on the scan design data.

[0167] Clause 42. The imaging system according to Clause 41 further includes an on-chip input memory configured to store the scan design data.

[0168] Clause 43. The imaging system according to any one of Clauses 40 to 42, wherein the scan design data includes scan sequence instructions and parameters.

[0169] Clause 44. The imaging system according to Clause 43 further includes an on-chip beamformer configured to be programmed and timed by the controller to perform beamforming according to the scan sequence instructions and parameters.

[0170] Clause 45. The imaging system according to any one of Clauses 40 to 44, wherein the imaging system is coupled to an ultrasonic transducer.

[0171] Clause 46. The imaging system according to any one of Clauses 40 to 45, wherein the on-chip ultrasound imaging system is an application-specific integrated circuit (ASIC).

[0172] Clause 47. The imaging system according to Clause 45, wherein the imaging system and the ultrasonic transducer are encapsulated within the same ultrasonic probe.

[0173] Clause 48 The imaging system described in Clause 45, wherein the imaging system and the ultrasonic transducer are integrated.

[0174] Clause 49. The imaging system according to any one of Clauses 40 to 48, wherein the beamforming is included in an autonomous scanning process.

[0175] Clause 50. The imaging system according to any one of Clauses 40 to 49, wherein the controller is a dedicated central controller for ultrasound.

[0176] Clause 51. The imaging system according to Clause 50, wherein the dedicated ultrasound central controller is configured to generate a scan sequence based on the scan design data.

[0177] Clause 52. The imaging system according to Clause 50, wherein the dedicated ultrasound central controller is configured to execute each event of the transducer in the scan sequence based on the scan design data.

[0178] Clause 53. The imaging system according to Clause 52, wherein the event is a transmit and receive event, a transmit-only event, or a receive-only event.

[0179] Clause 54. An imaging system according to any one of Clauses 40 to 53, wherein the scan design data is provided by an external process outside the chip.

[0180] Clause 55. An imaging system according to any one of Clauses 40 to 54, wherein the scan design data includes timing for each event in the scan sequence.

[0181] Clause 56. An imaging system according to any one of Clauses 40 to 55, wherein the scan design data includes imaging parameters for each event in the scan sequence.

[0182] Clause 57. An imaging system according to any one of Clauses 40 to 56, wherein the scan design data includes programmable nested loops.

[0183] Clause 58. The imaging system according to Clause 57, wherein each of the programmable nested loops corresponds to a transmit and / or receive event in the scan sequence.

[0184] Clause 59. The imaging system according to Clause 58, wherein the imaging and timing parameters to be updated at that point in the scan sequence are prior to the transmission and / or reception event.

[0185] Clause 60. The imaging system pursuant to Clause 59, wherein the imaging parameters and timing parameters to be updated are provided from an external user equipment.

[0186] Clause 61. The imaging system according to Clause 59, wherein the imaging parameters are optimized based on an input memory integrated within the on-chip ultrasound imaging system.

[0187] Clause 62. An imaging system according to any one of Clauses 40 to 60, wherein the scanning design data includes the spatial and temporal dimensions of the transducer's transmission and / or reception events.

[0188] Clause 63. The imaging system according to any one of Clauses 40 to 62, wherein the scan design data is used in mode B.

[0189] Clause 64. The imaging system according to any one of Clauses 40 to 63, wherein the scan design data is used for mixed modes.

[0190] Clause 65. The imaging system according to any one of Clauses 40 to 64, wherein the scan design data includes scan geometry.

[0191] Clause 66. The imaging system according to Clause 65, wherein the scanning geometry is used for planar imaging, dual-planar imaging, or multi-planar imaging.

[0192] Clause 67. The imaging system according to Clause 65, wherein the scanning geometry is sector, vector, trapezoidal, linear, or linear with adjustable direction.

[0193] Clause 68. The imaging system according to Clause 65, wherein the scanning geometry is used for 3D imaging or real-time 3D imaging.

[0194] Clause 69. The imaging system according to Clause 65, wherein the scanning geometry is a pyramid, cone, frustum, truncated cone, cuboid, or tilted cuboid.

[0195] Clause 70. An imaging system according to any one of Clauses 40 to 69, wherein the scan design data includes instructions for sampling in the spatial domain, the temporal domain, and the parametric domain.

[0196] Clause 71. The imaging system according to any one of Clauses 40 to 70 further includes a detector coupled to the controller and the beamformer.

[0197] Clause 72. The imaging system according to Clause 71 further includes an output memory coupled to the detector and the controller.

[0198] Clause 73. The imaging system according to Clause 72 further includes a transceiver coupled to the output memory, the input memory, the controller, and the beamformer, wherein the input memory is configured to store the scan design data.

[0199] Clause 74. The imaging system according to Clause 73, wherein the transceiver is coupled to an external computing device.

[0200] Clause 75. The imaging system according to any one of Clauses 40 to 74, wherein the number of transducers is between 500 and 5000.

[0201] Clause 76. The imaging system according to any one of Clauses 40 to 75, wherein the number of transducers is between 100 and 9000.

[0202] Clause 77. An imaging system according to any one of Clauses 40 to 76, wherein the number of transducers is 2k, where k is a non-negative integer.

[0203] Clause 78. An imaging system according to any one of Clauses 40 to 77, wherein the controller is configured to perform a scan design based on the scan design data without any knowledge of the usage of the scan.

[0204] Clause 79. A method for autonomous scanning, comprising: at an imaging system integrated on an application-specific integrated circuit (ASIC) chip including an input memory and a processor: storing scan sequence instructions and parameters in the input memory; having the processor read the scan sequence instructions and parameters from the input memory; and having the processor program and time beamforming according to the scan sequence instructions and parameters.

[0205] Clause 80. The method according to Clause 79, wherein the imaging system is coupled to an ultrasonic transducer.

[0206] Clause 81. The method according to Clause 80, wherein the imaging system and the ultrasonic transducer are encapsulated within the same ultrasonic probe.

[0207] Clause 82. The method according to Clause 80, wherein the imaging system and the ultrasonic transducer are integrated.

[0208] Clause 83. The method according to any one of Clauses 79 to 82, wherein the autonomous scanning includes beamforming processed by a beamformer.

[0209] Clause 84. The method according to any one of Clauses 79 to 83, wherein the processor is a dedicated central controller for ultrasound.

[0210] Clause 85. The method according to Clause 84 further includes generating a scan sequence based on the scan sequence instructions and parameters.

[0211] Clause 86. The method according to Clause 84 further includes performing each event of the transducer in the scan sequence based on the scan sequence instructions and parameters.

[0212] Clause 87. The method described in accordance with Clause 86, wherein the event is a send and receive event, a send event only, or a receive event only.

[0213] Clause 88. The method according to any one of Clauses 79 to 87, wherein the scan sequence instructions and parameters are provided by an external process outside the chip.

[0214] Clause 89. The method according to any one of Clauses 79 to 88, wherein the scan sequence instructions and parameters include timing for each event in the scan sequence.

[0215] Clause 90. The method according to any one of Clauses 79 to 89, wherein the scan sequence instructions and parameters include imaging parameters for each event in the scan sequence.

[0216] Clause 91. The method according to any one of Clauses 79 to 90, wherein the scan sequence instructions and parameters include programmable nested loops.

[0217] Clause 92. The method according to Clause 91, wherein each of the programmable nested loops corresponds to a transmit event and / or receive event in the scan sequence.

[0218] Clause 93. The method according to Clause 92, wherein the imaging and timing parameters to be updated at that point in the scan sequence precede the transmission and / or reception event.

[0219] Clause 94. The method according to Clause 93, wherein the imaging and timing parameters to be updated are provided from an external user equipment.

[0220] Clause 95. The method according to Clause 93, wherein the imaging parameters are optimized based on the input memory.

[0221] Clause 96. The method according to any one of Clauses 80 to 95, wherein the scan sequence instructions and parameters include the spatial and temporal dimensions of the transducer's transmit and / or receive events.

[0222] Clause 97. The method according to any one of Clauses 79 to 96, wherein the scan sequence instructions and parameters are used in mode B.

[0223] Clause 98. The method according to any one of Clauses 79 to 97, wherein the scan sequence instructions and parameters are used in a mixed mode.

[0224] Clause 99. The method according to any one of Clauses 79 to 98, wherein the scan sequence instructions and parameters include scan geometry.

[0225] Clause 100. The method according to Clause 99, wherein the scanning geometry is used for planar imaging, dual-plane imaging, or multi-plane imaging.

[0226] Clause 101. The method according to Clause 99, wherein the scanning geometry is sectoral, vector, trapezoidal, linear, or linear with adjustable direction.

[0227] Clause 102. The method according to Clause 99, wherein the scanning geometry is used for 3D imaging or real-time 3D imaging.

[0228] Clause 103. The method according to Clause 99, wherein the scanning geometry is a pyramid, cone, frustum, truncated cone, cuboid, or inclined cuboid.

[0229] Clause 104. The method according to any one of Clauses 79 to 103, wherein the scan sequence instructions and parameters include instructions for sampling in the spatial domain, the temporal domain, and the parameter domain.

[0230] Clause 105. The method according to any one of Clauses 79 to 104, wherein the imaging system further includes a detector and a beamformer, wherein the detector is coupled to the processor and the beamformer.

[0231] Clause 106. The method according to Clause 105, wherein the imaging system further includes an output memory coupled to the detector and the processor.

[0232] Clause 107. The method according to Clause 106, wherein the imaging system further includes a transceiver coupled to the output memory, the input memory, the processor and the beamformer.

[0233] Clause 108. The method according to Clause 107, wherein the transceiver is coupled to an external computing device.

[0234] Clause 109. The method according to any one of Clauses 80 to 108, wherein the number of transducers is between 100 and 9000.

[0235] Clause 110. The method according to any one of Clauses 80 to 109, wherein the number of transducers is between 500 and 5000.

[0236] Clause 111. The method according to any one of Clauses 80 to 110, wherein the number of transducers is 2k, where k is a non-negative integer.

[0237] Clause 112. The method according to any one of Clauses 79 to 111 further includes, without any knowledge of the use case of the scan, the processor executing a scan design including the scan sequence instructions and parameters.

[0238] Clause 113. A non-transitory computer-readable storage device, comprising any of the steps disclosed in any of the preceding clauses.

[0239] Clause 114. A method comprising any step disclosed in any of the preceding clauses.

[0240] Clause 115. A system comprising one or more devices configured to perform any of the methods disclosed in any of the preceding clauses.

[0241] Clause 116. An imaging system according to any one of Clauses 1 to 78, wherein the chip includes analog circuitry for transmitting and receiving ultrasound signals.

[0242] Clause 117. An imaging system according to any one of Clauses 1 to 40 and 42, wherein the on-chip input memory is a factory-programmed non-volatile memory.

[0243] Clause 118. An imaging system according to any one of Clauses 1 to 39 and 43 to 44, wherein scan sequence instructions and parameters are stored in a factory-programmed non-volatile input memory.

[0244] Clause 119. The method according to any one of Clauses 79 to 112, wherein the chip includes analog circuitry for transmitting and receiving ultrasonic signals.

[0245] Clause 120. The method according to any one of Clauses 79 to 112, wherein the input memory of the chip is a factory-programmed non-volatile memory.

[0246] Clause 121. The method according to any one of Clauses 79 to 112, wherein the scan sequence instructions and parameters are stored in a factory-programmed non-volatile input memory.

[0247] In some embodiments, any provision of this document may be subordinate to any independent provision or any dependent provision. In one aspect, any provision (e.g., a dependent or independent provision) may be combined with any other provision (e.g., a dependent or independent provision). In one aspect, a claim may include some or all of the words (e.g., steps, operations, apparatus, or components) recited in a provision, sentence, phrase, or paragraph. In one aspect, a claim may include some or all of the words recited in one or more provisions, sentences, phrases, or paragraphs. In one aspect, some words may be removed from each provision, sentence, phrase, or paragraph. In one aspect, additional words or elements may be added to a provision, sentence, phrase, or paragraph. In one aspect, the subject matter may be implemented without utilizing some of the components, elements, functions, or operations described herein. In one aspect, the subject matter may be implemented using additional components, elements, functions, or operations.

[0248] As used herein, the terms "loop" or "component" refer to logic implemented in hardware or firmware, or to a collection of software instructions that may have entry and exit points and are written in a programming language such as C++. Software loops or components may be compiled and linked into an executable program installed in a dynamic link library, or may be written in an interpreted language such as BASIC. It will be understood that software loops or components may be callable from other loops or components or from themselves, and / or may be invoked in response to a detected event or interrupt. Software instructions may be embedded in firmware (such as EPROM or EEPROM). It should also be understood that hardware components may include connected logic units, such as gates and flip-flops, and / or may include programmable units, such as programmable gate arrays or processors. The loops or components described herein are preferably implemented as software loops or components, but may be represented in hardware or firmware.

[0249] It is anticipated that cycles or components can be integrated into a smaller number of cycles or components. A cycle or component can also be divided into multiple cycles or components. The described cycle or component can be implemented as hardware, software, firmware, or any combination thereof. Furthermore, the described cycle or component can reside at different locations connected via wired or wireless networks or the Internet.

[0250] Generally, it will be understood that a processor may include, for example, a computer, program logic, or other low-level configuration representing data and instructions that operate as described herein. In other embodiments, a processor may include a controller circuitry, a processor circuitry, a processor, a general-purpose single-chip or multi-chip microprocessor, a digital signal processor, an embedded microprocessor, a microcontroller, etc.

[0251] Furthermore, it should be understood that, in one embodiment, the program logic can advantageously be implemented as one or more components. Components can advantageously be configured to execute on one or more processors. Components include, but are not limited to, software or hardware components, modules (e.g., software modules), object-oriented software components, class components and task components, processing methods, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuit systems, data, databases, data structures, tables, arrays, and variables.

[0252] The above description is provided to enable those skilled in the art to practice the various configurations described herein. Although the subject matter has been specifically described with reference to various accompanying drawings and configurations, it should be understood that these are for illustrative purposes only and should not be considered as limiting the scope of the subject matter.

[0253] There are many other ways to implement the subject matter. The various functions and elements described herein can be divided differently from those shown without departing from the scope of the subject matter. Those skilled in the art will readily understand the various modifications to these configurations, and the general principles defined herein can be applied to other configurations. Therefore, those skilled in the art can make many changes and modifications to the subject matter without departing from its scope.

[0254] It should be understood that the specific order or hierarchy of steps in the disclosed process is an illustration of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged. Some steps may be performed simultaneously. The appended method claims present the elements of the various steps in an exemplary order and are not intended to imply limitation to the specific order or hierarchy presented.

[0255] Although some of the accompanying figures illustrate certain logical levels in a specific order, levels can be reordered regardless of the order, and other levels can be combined or occur suddenly. While some reorderings or other groupings are specifically mentioned, others will be obvious to those skilled in the art, and therefore the orderings and groupings presented herein are not an exhaustive list of alternatives. Furthermore, it should be recognized that these levels can be implemented in hardware, firmware, software, or any combination thereof.

[0256] It will also be understood that although the terms first, second, etc., are used in some cases herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of the various described embodiments, a first transducer may be referred to as a second transducer, and similarly, a second transducer may be referred to as a first transducer. Both the first sensor and the second sensor are sensors, but they are not the same type of sensor.

[0257] With regard to the terms “include”, “having”, etc., used in the specification or claims, these terms are intended to be inclusive in a manner similar to the term “comprise”, as interpreted when “comprise” is used as a transitional word in the claims.

[0258] As used herein, the term "comprising" means that there are one or more specified integers, but other unspecified integers are permitted. This term does not imply any particular proportion of the specified integers. Variations of the word "comprising," such as "comprise" and "comprises," have correspondingly similar meanings.

[0259] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0260] Unless otherwise specified, references to elements in the singular are not intended to mean "one and only one," but rather "one or more." Male pronouns (e.g., his) include female and neutral pronouns (e.g., her and its), and vice versa. The term "some" refers to one or more. Underlined and / or italicized headings and subheadings are used for convenience only, do not limit the subject matter, and are not incorporated into the interpretation of the description of the subject matter. All structural and functional equivalents of elements in various configurations throughout the description of this disclosure that are known or will be known hereafter by one of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the subject matter. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is expressly stated in the foregoing description.

Claims

1. An imaging system integrated on a chip for autonomous scanning, comprising: an on-chip input memory configured to store scan sequence instructions and parameters; an on-chip processor configured to read the scan sequence instructions and parameters in the input memory; and an on-chip beamformer configured to be programmed and timed by the processor according to the scan sequence instructions and parameters.

2. The imaging system of claim 1, wherein, The imaging system is coupled to an ultrasound transducer.

3. The imaging system of any of the preceding claims, wherein, The chip is an application specific integrated circuit (ASIC).

4. The imaging system of any of the preceding claims, wherein, The processor is configured to autonomously perform a scan, wherein the scan comprises a periodically repeating sequence of events.

5. The imaging system of claim 4, wherein, The sequence of events comprises individual events, a temporal loop of events, a spatial loop of events in x and y, wherein each event and each event loop from the innermost event loop, x loop, and y loop to the outermost scan loop is timed.

6. The imaging system of claim 2, wherein, The imaging system and the ultrasound transducer are packaged within the same ultrasound probe.

7. The imaging system of claim 2, wherein, The imaging system and the ultrasound transducer are integrated.

8. The imaging system of any of the preceding claims, wherein, The autonomous scan comprises beamforming processed by the beamformer.

9. The imaging system of any of the preceding claims, wherein, The processor is an ultrasound dedicated central controller.

10. The imaging system of claim 9, wherein, The ultrasound dedicated central controller is configured to generate a scan sequence based on the scan sequence instructions and parameters.

11. The imaging system of claim 9, wherein, The ultrasound dedicated central controller is configured to execute each event in a scan sequence based on the scan sequence instructions and parameters.

12. The imaging system of claim 11, wherein, The events are transmit and receive events, transmit only events, or receive only events.

13. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters are provided by an external processor external to the chip.

14. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters comprise timing for each event in a scan sequence.

15. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters comprise imaging parameters for each event in a scan sequence.

16. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters are included in a plurality of scan designs.

17. The imaging system of claim 16, wherein, Each of the plurality of scan designs is customized for a different imaging mode, feature, or clinical application selectable by a user.

18. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters comprise programmable nested loops.

19. The imaging system of claim 18, wherein, Each of the programmable nested loops corresponds to a transmit and / or receive event in a scan sequence.

20. The imaging system of claim 19, wherein, Imaging and timing parameters to be updated at that point in the scan sequence precede the transmit and / or receive event.

21. The imaging system of claim 20, wherein, The imaging and timing parameters to be updated are provided from an external user device.

22. The imaging system of claim 20, wherein, The imaging parameters are optimized according to the input memory.

23. The imaging system of any of claims 2 to 22, wherein, The scan sequence instructions and parameters comprise spatial and temporal dimensions of transmit and / or receive events of the transducer.

24. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters are for B-mode.

25. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters are for hybrid mode.

26. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters comprise a scan geometry.

27. The imaging system of claim 26, wherein, The scan geometry is for planar imaging, biplane imaging, or multiplane imaging.

28. The imaging system of claim 26, wherein, The scan geometry is sector, vector, trapezoidal, linear, or linear with adjustable orientation.

29. The imaging system of claim 26, wherein, The scan geometry is for 3D imaging or real-time 3D imaging.

30. The imaging system of claim 26, wherein, The scan geometry is a pyramid, cone, prism, truncated cone, cuboid, or tilted cuboid.

31. The imaging system of any of the preceding claims, wherein, The scan sequence instructions and parameters comprise instructions for sampling in spatial, temporal, and parametric domains.

32. The imaging system of any of the preceding claims, further comprising a detector coupled to the processor and the beamformer.

33. The imaging system of claim 32, further comprising an output memory coupled to the detector and the processor.

34. The imaging system of claim 33, further comprising a transceiver coupled to the output memory, the input memory, the processor, and the beamformer.

35. The imaging system of claim 34, wherein, The transceiver is coupled to an external computing device.

36. The imaging system of any one of claims 2 to 35, wherein, The number of transducers is between 500 and 5000.

37. The imaging system of any one of claims 2 to 36, wherein, The number of transducers is between 100 and 9000.

38. The imaging system of any one of claims 2 to 37, wherein, The number of transducers is 2 k where k is a non-negative integer.

39. The imaging system of any of the preceding claims, wherein, The processor is configured to perform a scan design comprising scan sequence instructions and parameters without any knowledge of a use case of the scan.

40. An imaging system integrated on an application specific integrated circuit (ASIC) chip coupled to ultrasound transducers for autonomous scanning, comprising: an on-chip input memory configured to store scan design data; and an on-chip controller configured to read the scan design data in the input memory and program and time beamforming of the transducers according to the scan design data.

41. An on-chip ultrasound imaging system, comprising: an on-chip controller configured to receive scan design data and program and time beamforming according to the scan design data.

42. The imaging system of claim 41, further comprising an on-chip input memory configured to store the scan design data.

43. The imaging system of any of claims 40 to 42, wherein, The scan design data comprises scan sequence instructions and parameters.

44. The imaging system of claim 43, further comprising an on-chip beamformer configured to be programmed and timed by the controller to perform the beamforming according to the scan sequence instructions and parameters.

45. The imaging system of any of claims 40 to 44, wherein, The imaging system is coupled to ultrasound transducers.

46. The imaging system of any of claims 40 to 45, wherein, The on-chip ultrasound imaging system is an application specific integrated circuit (ASIC).

47. The imaging system of claim 45, wherein, The imaging system and the ultrasound transducers are packaged within the same ultrasound probe.

48. The imaging system of claim 45, wherein, The imaging system and the ultrasound transducers are integrated.

49. The imaging system of any of claims 40 to 48, wherein, The beamforming is included in an autonomous scan.

50. The imaging system of any of claims 40 to 49, wherein, The controller is an ultrasound specific central controller.

51. The imaging system of claim 50, wherein, The ultrasound specific central controller is configured to generate a scan sequence based on the scan design data.

52. The imaging system of claim 50, wherein, The ultrasound specific central controller is configured to execute each event of a transducer in a scan sequence based on the scan design data.

53. The imaging system of claim 52, wherein, The event is a transmit and receive event, a transmit only event, or a receive only event.

54. The imaging system of any of claims 40 to 53, wherein, The scan design data is provided by an external process external to the chip.

55. The imaging system of any of claims 40 to 54, wherein, The scan design data comprises timing for each event in a scan sequence.

56. The imaging system of any of claims 40 to 55, wherein, The scan design data comprises imaging parameters for each event in a scan sequence.

57. The imaging system of any of claims 40 to 56, wherein, The scan design data comprises programmable nested loops.

58. The imaging system of claim 57, wherein, Each of the programmable nested loops corresponds to a transmit and / or receive event in a scan sequence.

59. The imaging system of claim 58, wherein, The imaging and timing parameters to be updated at that point in the scan sequence are prior to the transmit and / or receive event.

60. The imaging system of claim 59, wherein, The imaging and timing parameters to be updated are provided from an external user device.

61. The imaging system of claim 59, wherein, The imaging parameters are optimized according to input memory integrated within the on-chip ultrasound imaging system.

62. The imaging system of any of claims 40 to 60, wherein, The scan design data includes spatial and temporal dimensions of transmit and / or receive events of the transducers.

63. The imaging system of any of claims 40 to 62, wherein, The scan design data is for B-mode.

64. The imaging system of any of claims 40 to 63, wherein, The scan design data is for mixed mode.

65. The imaging system of any of claims 40 to 64, wherein, The scan design data includes scan geometry.

66. The imaging system of claim 65, wherein, The scan geometry is for planar, bi-plane or multi-plane imaging.

67. The imaging system of claim 65, wherein, The scan geometry is sector, vector, trapezoidal, linear or adjustable direction linear.

68. The imaging system of claim 65, wherein, The scan geometry is for 3D or real-time 3D imaging.

69. The imaging system of claim 65, wherein, The scan geometry is pyramid, cone, prism, truncated cone, cuboid or tilted cuboid.

70. The imaging system of any of claims 40 to 69, wherein, The scan design data includes instructions for sampling in spatial, temporal and parametric domains.

71. The imaging system of any one of claims 40 to 70, further comprising a detector coupled with the controller and the beamformer.

72. The imaging system of claim 71, further comprising an output memory coupled with the detector and the controller.

73. The imaging system of claim 72, further comprising a transceiver coupled to the output memory, an input memory, the controller, and the beamformer, wherein, The input memory is configured to store the scan design data.

74. The imaging system of claim 73, wherein, The transceiver is coupled to an external computing device.

75. The imaging system of any of claims 40 to 74, wherein, The number of transducers is between 500 and 5000.

76. The imaging system of any of claims 40 to 75, wherein, The number of transducers is between 100 and 9000.

77. The imaging system of any of claims 40 to 76, wherein, the number of transducers is 2 k where k is a non-negative integer.

78. The imaging system of any of claims 40 to 77, wherein, The controller is configured to perform scan design based on the scan design data without any knowledge of use cases of scans.

79. The imaging system of any of claims 1 to 78, wherein, The chip includes analog circuitry for transmitting and receiving ultrasound signals.

80. The imaging system of any one of claims 1 to 40 and 42, wherein, The on-chip input memory is a factory programmed non-volatile memory.

81. The imaging system of any one of claims 1 to 39 and 43 to 44, wherein, The scan sequence instructions and parameters are stored in a factory programmed non-volatile input memory.

82. A method for autonomous scanning, comprising: at an imaging system integrated on an application specific integrated circuit (ASIC) chip comprising an input memory and a processor: storing scan sequence instructions and parameters in the input memory; reading, by the processor, the scan sequence instructions and parameters in the input memory; and programming and timing beamforming by the processor according to the scan sequence instructions and parameters.

83. The method of claim 82, wherein, The imaging system is coupled to ultrasound transducers.

84. The method of claim 83, wherein, The imaging system and the ultrasound transducers are packaged within the same ultrasound probe.

85. The method of claim 83, wherein, The imaging system and the ultrasound transducers are integrated.

86. The method of any one of claims 79-85, wherein, The autonomous scanning includes beamforming processed by a beamformer.

87. The method of any one of claims 79 to 86, wherein, The processor is an ultrasound dedicated central controller.

88. The method of claim 87, further comprising generating a scan sequence based on the scan sequence instructions and parameters.

89. The method of claim 87, further comprising executing each event of a transducer in a scan sequence based on the scan sequence instructions and parameters.

90. The method of claim 89, wherein, The event is a transmit and receive event, a transmit only event, or a receive only event.

91. The method of any one of claims 79-90, wherein, The scan sequence instructions and parameters are provided by an external process external to the chip.

92. The method of any one of claims 79-91, wherein, The scan sequence instructions and parameters include timing for each event in a scan sequence.

93. The method of any one of claims 79 to 92, wherein, The scan sequence instructions and parameters include imaging parameters for each event in a scan sequence.

94. The method of any one of claims 79-93, wherein, The scan sequence instructions and parameters include programmable nested loops.

95. The method of claim 94, wherein, Each of the programmable nested loops corresponds to a transmit and / or receive event in a scan sequence.

96. The method of claim 95, wherein, Imaging and timing parameters to be updated at this point in the scan sequence precede the transmit and / or receive event.

97. The method of claim 96, wherein, The imaging and timing parameters to be updated are provided from an external user device.

98. The method of claim 96, wherein, The imaging parameters are optimized according to the input memory.

99. The method of any one of claims 83-98, wherein, The scan sequence instructions and parameters include spatial and temporal dimensions of transmit and / or receive events of the transducer.

100. The method of any one of claims 79-99, wherein, The scan sequence instructions and parameters are for B-mode.

101. The method of any one of claims 79-100, wherein, The scan sequence instructions and parameters are for hybrid mode.

102. The method of any one of claims 79-101, wherein, The scan sequence instructions and parameters include scan geometry.

103. The method of claim 102, wherein, The scan geometry is for planar, biplane or multiplanar imaging.

104. The method of claim 102, wherein, The scan geometry is fan, vector, trapezoidal, linear or adjustable direction linear.

105. The method of claim 102, wherein, The scan geometry is for 3D or real-time 3D imaging.

106. The method of claim 102, wherein, The scan geometry is pyramid, cone, prism, truncated cone, cuboid or tilted cuboid.

107. The method of any one of claims 79 to 106, wherein, The scan sequence instructions and parameters include instructions for sampling in spatial, temporal and parametric domains.

108. The method of any one of claims 79-107, wherein, The imaging system further includes a detector and a beamformer, wherein the detector is coupled to the processor and the beamformer.

109. The method of claim 108, wherein, The imaging system further includes an output memory coupled to the detector and the processor.

110. The method of claim 109, wherein, The imaging system further includes a transceiver coupled to the output memory, the input memory, the processor and the beamformer.

111. The method of claim 110, wherein, The transceiver is coupled to an external computing device.

112. The method of any one of claims 83-111, wherein, The number of transducers is between 500 and 5000.

113. The method of claims 83-112, wherein, The number of transducers is between 100 and 9000.

114. The method of claims 83-113, wherein, the number of transducers is 2 k where k is a non-negative integer.

115. The method of any one of claims 79-114, further comprising: A scan design including the scan sequence instructions and parameters is performed by the processor without any knowledge of the use case of the scan.

116. The method of any one of claims 79 to 115, wherein, The chip includes analog circuitry for transmitting and receiving ultrasound signals.

117. The method of any one of claims 79 to 116, wherein, The input memory of the chip is a factory programmed non-volatile memory.

118. The method of any one of claims 79-117, wherein, The scan sequence instructions and parameters are stored in a factory programmed non-volatile input memory.

Images