Physical unclonable function readout device

Abstract

The invention relates to a physical unclonable function (PUF) device. In one example, the PUF device includes a PUF source to output a first signal and a second signal, where a difference between the signals indicates a randomly fabricated difference between components in the PUF source; and an analog-to-digital converter (ADC) for coupling to the PUF source. In this example, the PUF device is configured to operate in a plurality of different modes, the plurality of different modes including at least a PUF coarse measurement mode and a PUF fine measurement mode. When operating in the PUF coarse measurement mode and when operating in the PUF fine measurement mode, the PUF device is configured to generate a digital measurement that is a measure of the difference between the first signal and the second signal using the ADC and to generate a PUF value using the digital measurement. However, when the PUF device operates in the PUF fine measurement mode, the digital measurement has a greater resolution than when operating in the PUF coarse measurement mode.

Description

Technical Field

[0001] This disclosure relates to methods and apparatus for reading PUF values ​​from physically unclonable function (PUF) cells. Background Technology

[0002] A physically unclonable function (sometimes called a physically non-clonable function) or 'PUF' is a physical entity capable of producing an output ('response') for a given input ('challenge') unique to that particular PUF, making it a 'fingerprint'. This capability is typically achieved by designing the PUF such that its output depends on characteristics that vary randomly in each device due to minute manufacturing variations. Therefore, even with complete knowledge of the PUF's circuitry, it may not be possible to easily replicate the PUF using the correct fingerprint. The response can be used for a variety of purposes, such as in cryptographic operations to secure communications to / from devices that include the PUF, or in the process of verifying the identity of devices that include the PUF.

[0003] A PUF device may include: one or more pairs of physical devices, each pair including some physical characteristics that differ randomly due to minute manufacturing variations; and deterministic circuitry configured to read PUF values ​​from a pair of physical devices. The PUF device may be configured such that the deterministic circuitry can read a persistent random PUF value from each of the pairs of physical devices and generate a persistent random number based on the PUF value. This persistent random number can then be used as part of determining a 'response' to a 'challenge'. For example, the PUF device may receive a 'challenge' from another circuit, the deterministic circuitry can then read a persistent random number from the PUF cell, and the PUF device can then determine a 'response' based on the 'challenge' and the persistent random number (e.g., performing some cryptographic operation, such as hashing, XORing, or encryption, using the 'challenge' and the persistent random number). The persistent random number is random in that its value depends on minute random manufacturing variations between different PUF devices. Therefore, different instances of PUF devices, although identical in design, should each generate different persistent random numbers. Random numbers are 'persistent' in that they should remain the same or remain the same within acceptable limits over time. For example, persistent random numbers generated by one or more PUF cells of a PUF device should be the same each time they are generated (or remain the same within acceptable limits, such as allowing the persistent random number to be corrected using an error-correcting code ECC), so that the persistent random number can serve as a reliable fingerprint of the device.

[0004] A random number generator (RNG) or true random number generator (TRNG) is a device that generates 'dynamic' random numbers. Dynamic random numbers are random numbers that, with each new number generated, have an equal or substantially equal probability of having any of their possible values. Because random numbers have the potential to change with each new number generated, they contrast with 'persistent' random numbers, which should remain the same or, within acceptable limits, with each new number generated.

[0005] Dynamic random numbers are used for a variety of purposes, such as as part of a cryptographic process. In some instances, such as when both persistent and dynamic random numbers are used as part of a specific process, such as a cryptographic key generation process, a PUF device is needed to generate persistent random numbers and an RNG device is needed to generate dynamic random numbers. Summary of the Invention

[0006] In a first aspect of this disclosure, a Physically Unclonable Function (PUF) device is provided, the PUF device comprising: a PUF source for outputting a first signal and a second signal, wherein the difference between the first signal and the second signal indicates a random manufacturing difference between components in the PUF source; and an analog-to-digital converter (ADC) for coupling to the PUF source; wherein the PUF device is configured to operate in a plurality of different modes, the plurality of different modes including at least a PUF coarse measurement mode and a PUF fine measurement mode, and wherein when operating in the PUF coarse measurement mode and when operating in the PUF fine measurement mode, the PUF device is configured to use the ADC to generate a digital measurement of a measure of the difference between the first signal and the second signal and to use the digital measurement to generate a PUF value, and wherein when the PUF device operates in the PUF fine measurement mode, the digital measurement has a greater resolution than when operating in the PUF coarse measurement mode.

[0007] In a second aspect of this disclosure, a system is provided comprising: a pair of matched electrical devices; a noise source configured to generate an electrical signal including random noise; and a determining circuit configured to, when the system operates in a Physically Unclonable Function (PUF) mode: use the pair of matched electrical devices to generate a first electrical signal indicating a random manufacturing difference between the pair of matched electrical devices; and generate a PUF value based on the first electrical signal; and wherein the determining circuit is further configured to, when the system operates in a Dynamic Random Number mode: use the noise source to generate a second electrical signal including random noise; and use the second electrical signal to generate a dynamic random number.

[0008] In a third aspect of this disclosure, a Physically Unclonable Function (PUF) system is provided, comprising: a pair of matched devices; and a determining circuit coupled to the pair of matched devices, wherein when the system operates in a registration mode, the determining circuit is configured to: determine whether a magnitude of a random manufacturing difference between the pair of matched devices exceeds a stability threshold; if the magnitude of the random manufacturing difference exceeds the stability threshold, mark the pair of matched devices as suitable for generating a PUF value; and if the magnitude of the random manufacturing difference is less than the stability threshold, mark the pair of matched devices as unsuitable for generating a PUF value, and wherein when the system operates in a PUF mode and the pair of matched devices is marked as suitable for generating a PUF value: determine a measure of the random manufacturing difference between the pair of matched devices; and use the measure of the random manufacturing difference between the pair of matched devices to generate the PUF value. Attached Figure Description

[0009] Referring to the following figures, aspects of this disclosure are described by way of example only, in which:

[0010] Figure 1 An example schematic representation of a PUF device / system according to one aspect of this disclosure is shown;

[0011] Figure 2 A schematic diagram illustrating an example specific implementation of PUF cells and defined units;

[0012] Figure 3A and Figure 3B A schematic diagram illustrating an array of PUF cells;

[0013] Figures 4A to 4C An example schematic circuit and timing diagram of a capacitor-based PUF cell are shown.

[0014] Figure 5A and Figure 5B An example schematic circuit of a resistor-based PUF cell is shown;

[0015] Figure 6 A schematic representation of another example PUF device / system according to one aspect of this disclosure is shown;

[0016] Figure 7 Show Figure 6 Example implementation of the readout unit of a PUF device / system;

[0017] Figure 8A and Figure 8B Show Figure 6 Another example of the specific implementation and operation of the readout unit of the PUF device / system;

[0018] Figure 9A and Figure 9B Show Figure 6 Another example of the specific implementation and operation of the readout unit of the PUF device / system;

[0019] Figure 10A and Figure 10B Show Figure 6 Another example of a specific implementation and operation of a part of the readout unit of a PUF device / system;

[0020] Figure 11A and Figure 11B Showing the use Figure 10A A visualization of examples of measurements performed by the readout unit;

[0021] Figure 12A and Figure 12B Show Figure 6 Another example of the specific implementation and operation of the readout unit of the PUF device / system

[0022] Figure 13A An example representation of an RC filter circuit is shown;

[0023] Figure 13B An example representation of a switched capacitor circuit is shown;

[0024] Figures 14A to 14G An example representation of a noise generator circuit according to one aspect of this disclosure is shown;

[0025] Figure 15 An example diagram illustrating the generation of dynamic random numbers according to one aspect of this disclosure is shown; and

[0026] Figures 16A to 16C Show Figure 6 Example implementation and operation of the readout unit of the PUF device / system. Detailed Implementation

[0027] This document discloses various circuit designs for improving the accuracy and / or versatility of PUF devices. In one aspect, a PUF device can be configured to operate in a variety of different modes. For example, to generate a PUF value (e.g., 0 or 1), a measure of the difference between two signals can be determined. The difference between two signals can indicate a random manufacturing difference between a pair of matched electronic devices (e.g., two electrical components intended to be identical but which will have some random difference between them due to the manufacturing process). The signal can be measured in a way that indicates which of the two signals is larger, which determines whether the PUF value is 0 or 1. However, a PUF device can be configured to operate to measure the two signals with different accuracies for each operating mode, but still using at least some of the same components and circuitry. For example, in one mode, the measurement can be the magnitude of the difference between the signals and also the sign (positive or negative) of the difference, and in another mode, the measurement can be simply the sign of the difference. Additionally or alternatively, PUF device 100 can be configured to operate in a self-registration mode, in which at least some of the same signal measurement circuitry is reused again. In this mode, the magnitude of the difference can be measured against a stability threshold, which indicates how stable the PUF values ​​generated using those two signals will be. For example, if the difference between two signals is found to be very small and below the threshold, there is a risk that the PUF values ​​generated using those signals in the future will change from 0 to 1 (or vice versa), thus failing to meet the 'persistence' requirement. In this case, it can be recorded that the pair of signals will not be used for PUF output generation in the future. Additionally or alternatively, the PUF device includes a random noise source, and the PUF device can be configured to operate in a mode that reuses at least some of the signal measurement devices and circuitry used for PUF-related measurements to generate dynamic random numbers.

[0028] Due to the reconfigurability of the PUF device in this aspect of the disclosure, a highly versatile device can be implemented with limited component costs and in a relatively small area, because many readout components / circuits are reused for each operating mode.

[0029] In other aspects of this disclosure, the PUF device can be configured to operate in only one mode. In those instances, the PUF device can generate PUF values ​​with greater accuracy or reliability than prior art devices, for example, by measuring the difference between signals more accurately and / or more quickly and / or more efficiently.

[0030] Figure 1 An example schematic representation of a PUF device / system 100 according to one aspect of this disclosure is shown. The PUF device includes a plurality of PUF cells 105. x,y The designation unit 170 and the challenge / response unit 180 are shown. Only PUF cell 105 is represented.x,y A 2x2 array, but it will be understood that arrays of any size and dimensions or any number of PUF cells (e.g., 8, 12, 20, 32, 128, 256, etc.) can exist in any suitable configuration.

[0031] The determination unit 170 is configured to use multiple PUF cells 105 x,y To determine the PUF output. The PUF output is a persistent random number. Each PUF cell is 10⁵. x,y Includes a pair of physical components / devices, wherein the determining unit 170 measures a specific PUF cell 105. x,y The difference in physical properties of the pair of components / devices is used to determine the persistent random PUF value. The determining unit 170 can target multiple PUF cells 105. x,y Repeat this process, and then use the determined persistent random values ​​to generate the PUF output (e.g., each persistent random value can be a 1-bit value or a multi-bit value that forms part of the PUF output). In a particular non-limiting example, the PUF output can be a 128-bit word, and each of the 128 PUF cells can contribute 1 bit to the 128-bit word.

[0032] Challenge / Response Unit 180 is configured to receive a 'challenge' from an external entity, request and obtain PUF output from Determination Unit 170, and then determine and return a response based on the challenge and the PUF output. Challenge / Response Unit 180 may be configured to operate in any suitable manner that will be clearly understood by those skilled in the art of PUF devices. Challenge / Response Unit 180 may be a separate unit or may be part of Determination Unit 170. This disclosure specifically relates to the configuration and operation of Determination Unit 170, as described in detail below. Further reference or explanation of Challenge / Response Unit 180 is given only where it is helpful to illustrate the operation of Determination Unit 170.

[0033] Example PUF cell specific implementation

[0034] Each PUF cell is 10⁵ x,y It may include a pair of any suitable physical devices / components, which are configured to be compared to determine the difference in their physical characteristics caused by random manufacturing defects.

[0035] For example, each PUF cell is 10⁵ x,y It may include a pair of matched transistors, and determining cell 170 may be configured to determine the PUF output based on the difference between the physical characteristics of the transistors (such as gate-source voltage) caused by random manufacturing defects. U.S. Patent Application No. 16 / 296,998 ('998 application) provides a PUF cell 105 therein. x,yVarious example embodiments of a PUF device / system 100, each comprising a pair of transistors, are described herein by reference in their entirety. The '998 filing... Figure 2 Two specific example implementations are disclosed up to Figure 9 and between line 16 on page 10 and line 6 on page 26, some of which are reproduced in part below.

[0036] Figure 2 (It originates from US Patent Application No. US16 / 296,998) Figure 2 (Reproduced) A schematic diagram of an example specific implementation of PUF cell 105 and a determination unit 170 configured to determine the PUF value of PUF cell 105 is shown.

[0037] Figure 3A (It is reproduced from Figure 3 of U.S. Patent Application No. US16 / 296,998) showing that each is configured to be with Figure 2 The PUF cell 105 represented in the figure is the same as the PUF cell 105. x,y A schematic diagram of the array.

[0038] return Figure 2 PUF cell 105 includes a pair of matched transistors 210. The term 'matched' in this disclosure means that the pair of transistors have the same design. Although Figure 2 A representation of a pair of matched p-type FETs is shown, but it will be understood that throughout this disclosure, in each different described aspect, the pair of matched transistors 210 can be any transistor type, such as p-type, n-type, enhancement-mode, depletion-mode, FETs (such as MOSFETs, JFETs, MESFETs, etc.), BJTs (such as IGBTs, heterojunction bipolar transistors, etc.), etc. For simplicity, the focus is specifically on FETs, but it should be understood that the terms 'gate', 'source', and 'drain' as used herein encompass the terms 'base', 'emitter', and 'collector' for BJTs.

[0039] Although the two transistors constituting the matched pair 210 have the same design, small random manufacturing variations will inevitably exist between them. These manufacturing variations may include at least one of the following: differences in gate oxide thickness, differences in doping density, differences in carrier mobility, differences in device size, etc. These manufacturing variations result in variations in transistor on-state characteristics / performance, such as differences in turn-on threshold voltage, differences in β, differences in back-gate effect, etc. As used herein, the term 'on-state' refers to the operating characteristics of a transistor associated with its normal on-state operation, such as turn-on threshold voltage, gate-source voltage, drain current, linear resistivity, saturation point, transconductance, etc. By exploring on-state characteristics in contrast to off-state characteristics (such as off-state leakage current) or fault characteristics (such as dielectric breakdown), the reliability of the PUF device 100 can be increased because no high voltage is applied, the gate oxide does not degrade, etc.

[0040] The determining unit 170 is configured to determine a transistor difference based at least in part on a comparison of the on-state characteristics of the pair of matched transistors 210, wherein the transistor difference indicates one or more random manufacturing differences between the pair of matched transistors 210. In this specific embodiment, the on-state characteristics of the pair of matched transistors 210 being compared are the gate-source voltages (V0) of the two transistors. GS ). The V of the two transistors GS It can vary due to one or more different random manufacturing differences, which result in differences, for example, in the transistor's turn-on threshold voltage, and / or β, and / or back-gate effect.

[0041] The drains of the matched transistors 210 are coupled to ground. The determining unit 170 includes a selector circuit 220 configured to apply a suitable voltage to the gates of the matched transistors 210 to turn them on. This voltage serves as a 'selection potential', which is referred to below. Figure 3A To elaborate further, the determining unit 170 also includes a first current source 232 and a second current source 234 configured to provide the same amount of current to each other. The current from the first current source 232 can be applied as a first input signal to the source of the first transistor in the pair of matched transistors 210, and the current from the second current source 234 can be applied as a second input signal to the source of the second transistor in the pair of matched transistors 210. If the pair of matched transistors 210 were truly identical, their source voltages would be exactly the same. However, due to random manufacturing variations, the gate-source voltages of the two transistors may differ, and since the gate voltages applied to the pair of matched transistors 210 are the same, the source voltages of the pair of matched transistors 210 should be somewhat different.

[0042] The determining unit 170 also includes an ADC 250 configured to measure the difference between the gate-source voltages and output a digital value indicating that difference. However, it is recognized that there may be some mismatch between the current supplied by the first current source 232 and the current supplied by the second current source 234. Therefore, a chopper circuit 236 can be provided such that a first input signal (current from the first current source 232) can be applied to the first transistor, a second input signal (current from the second current source 234) can be applied to the second transistor, and the first transistor comparison value is determined by the ADC 250 by comparing the gate-source voltages of the paired matched transistors 210. The chopper circuit 236 can then switch the coupling between the first current source 232 and the second current source 234, such that the first input signal is applied to the second transistor, the second input signal is applied to the first transistor, and the second transistor comparison value is determined by the ADC 250 by comparing the gate-source voltages of the paired matched transistors 210.

[0043] The comparison value of the first transistor and the comparison value of the second transistor can be expressed as:

[0044] First transistor mismatch value = ΔV GS +Mismatch +Noise1

[0045] Second transistor mismatch value = ΔV GS –Mismatch + Noise2

[0046] Next, the transistor difference of PUF cell 105 can be determined based on the first transistor comparison value and the second transistor comparison value (e.g., based on the sum or average of the first transistor comparison value and the second transistor comparison value).

[0047] For example, the transistor difference can be expressed as:

[0048] Transistor difference = First mismatch value + Second mismatch value

[0049] =2*ΔV GS +Noise1 +Noise2

[0050] or

[0051] Transistor difference = average of the first mismatch value and the second mismatch value

[0052] =ΔV GS +(Noise1+Noise2) / 2

[0053] In this way, any measurement inaccuracies caused by the mismatch between the first current source 232 and the second current source 234 can be eliminated without significantly increasing the signal-to-noise ratio. It will be understood that the chopper circuit 236 is optional, and the determining unit 170 can be configured to determine the transistor difference based on a single comparison of the gate-source voltages, for example, if the first and second current sources are considered to be matched to a sufficiently high accuracy.

[0054] Alternatively, another chopper circuit 240 may be provided at the input of ADC 250. It may operate similarly to and simultaneously with chopper circuit 236 to switch the coupling between the differential input and the comparator in ADC 250. However, in this case, due to the switching of the input and the comparator in ADC 250, the ΔV in the first transistor comparison value... GS The sign of the component will differ from ΔV in the second transistor comparison value. GS The sign of the components. For example, when using both chopper circuits 236 and 240:

[0055] First transistor mismatch value = ΔV GS +Mismatch +Offset +Noise 1

[0056] The second transistor mismatch value = -ΔV GS +Mismatch +Offset +Noise2

[0057] The offset is the offset of ADC 250.

[0058] In this case, the transistor difference can be determined by taking the difference between the first transistor comparison value and the second transistor comparison value. For example:

[0059] Transistor difference = First mismatch value - Second mismatch value

[0060] =2*ΔV GS +Noise 1 - Noise 2

[0061] Using the chopper circuit 236 in this manner helps eliminate any offset in the ADC 250 and any mismatch between the first current source 232 and the second current source 234. Furthermore, ΔV GS The components have been increased by 2X, and the low-frequency components of noise 1 and noise 2 should almost cancel each other out. However, it will be understood that the chopper circuit 240 is optional, depending on the configuration of the ADC 250 and the quality of the components constituting the ADC 250. Furthermore, the determining unit 170 may not include the ADC 250, and may instead use any other suitable circuit system (e.g., a purely analog circuit system) to determine the transistor difference.

[0062] Chopper circuit 236 and another chopper circuit 240 can be configured in any suitable manner to perform the switching / chopping function described above. For example, each of the two chopper circuits may include one or more switches, which can be controlled (e.g., by...) Figure 2 The control unit (not shown in the text) is used to switch / chop the coupling described above.

[0063] The transistor difference indicates which transistor in the pair of matched transistors 210 has a larger / smaller V. GS And the magnitude of that difference. For example, it could be V, which indicates the first transistor. GS Compared to the V of the second transistor GS Large quantities are positive numbers, and can be V, which indicates the first transistor. GS Compared to the V of the second transistor GS The negative value of a small quantity.

[0064] Turning Figure 3A Multiple PUF cells 105 were shown. x,y Where x = 1, 2, ..., X-1, X, and y = 1, 2, ..., Y-1, Y, such that the PUF cell is 105. x,y The total number is X*Y. In this example, the PUF cell is 10⁵. x,y The array is configured to include X columns and Y rows. The selector circuit 220 has Y outputs, one for each row of the array, and each output is coupled to all matching transistor pairs 210 in that particular row. x,y The gate (e.g., the first output is coupled to transistor pair 210) x,1 The second output is coupled to transistor pair 210. x,2 (etc.). To select PUF cell line 105. x,y For a specific row, selector circuit 210 applies a selection potential to that row (e.g., a potential exceeding the turn-on threshold voltage of the transistor) to turn on the matching transistor pair 210 in that row. x,y A non-selective potential is applied to all other rows (e.g., a potential less than the transistor's turn-on threshold voltage). Therefore, it can be seen that in this example, each matched transistor pair 210 x,y It is used not only to determine transistor differences, but also as its PUF cell 105. x,y The selection mechanism. This is achieved by using each pair of matched transistors 210. x,y To achieve these two objectives, the size of the PUF cell array can be reduced compared to an array that includes a pair of transistors for determining the PUF value and one or more additional transistors for selecting the PUF cell.

[0065] It can also be seen that the determining unit 170 includes X first current sources 232 x Second current source 234 x X chopper circuits 236 x X additional chopper circuits 240 x And X ADCs 250 x Therefore, X pairs of transistors 210 in the selected row can be determined in parallel. x,y The transistor difference increases the operating speed. Furthermore, each group of first current sources 232... x Second current source 234 x Chopper circuit 236 x Another chopper circuit 240 x and ADC 250 x It can be shared by columns of the PUF array, thereby reducing the number of components required and thus reducing the overall size, cost and power consumption of the PUF device 100.

[0066] Figure 3A The determining unit 170, as indicated herein, also includes a PUF output unit 310, which: a) outputs data from each ADC 250 x Receive the determined transistor difference, or b) from each ADC x The determined first transistor comparison value and second transistor comparison value are received, and then a transistor difference is determined based on the first transistor comparison value and the second transistor comparison value (e.g., by averaging the first transistor comparison value and the second transistor comparison value).

[0067] Unit 170 can be determined by selecting a row of PUF cells 105. x,y And it operates by determining the transistor difference for each selected PUF cell. Then, the next row of PUF cells 105 can be selected. x,y And determine its transistor difference. The operation of selector circuit 220, chopper circuit 236x and additional chopper circuit 240x can be controlled by any suitable means, such as by PUF output unit 310 or any other suitable controller. For simplicity, Figure 3A The control interconnect is not indicated in the text.

[0068] Figure 3B (From US Patent Application No. US16 / 296,998) Figure 6 (Reproduction) shows PUF cell 105 x,y A schematic diagram of the array and an alternative configuration of the determining unit 170. A detailed explanation of the circuit operation is given on page 18, line 5 to page 23, line 23 of US16 / 296,998 and will not be repeated herein for efficiency. However, it will be understood that... Figure 3BHow should the PUF device 100 be implemented to enable the processing of multiple PUF cells 105? x,y Parallel measurement of physical properties and analysis of multiple PUF cells 105 x,y Another example of parallel readout.

[0069] The PUF output determined by PUF output unit 310 is a persistent random number, which can be, for example, a multi-bit number. This will be explained in more detail later in the "Configuration" and "Readout" sections. However, in general, the measured transistor difference of a particular PUF cell can be used to set the value of one or more bits of the multi-bit PUF output (i.e., "0" or "1"). Since the result of each transistor comparison depends on the pair of matched transistors 210... x,y The random manufacturing difference between them means that the PUF output should be random, since each different instance of the PUF device 100 is very likely to produce randomly different PUF outputs.

[0070] In another specific implementation example, each PUF cell is 10⁵. x,y It may include a pair of capacitors, and determining unit 170 may be configured to determine the PUF output based on differences between the physical characteristics (such as capacitance) of the capacitors caused by random manufacturing variations. Various example embodiments of a PUF device / system 100 in which each of PUF cells 105x,y includes a pair of matched capacitors are given in U.S. Patent Application No. US16 / 716,435 ('435 application), the entire contents of which are incorporated herein by reference. Figure 2 A to Figure 6 Various example implementations are disclosed in section B and between page 10, line 10 and page 22, line 31, some of which are partially reproduced below.

[0071] Figure 4A (from U.S. Patent Application No. US16 / 716,435) Figure 2 A (reproduced) shows a schematic diagram of a circuit used to determine the capacitor difference value, which indicates the random manufacturing difference between a pair of capacitors 2100.

[0072] Figure 4C (Reproduced from Figure 3 of U.S. Patent Application No. US16 / 296,998) showing that each is configured to be with Figure 4A The PUF cell 105 represented in the figure is the same as the PUF cell 105. x,y A schematic diagram of the array.

[0073] return Figure 4A Each PUF cell is 10⁵ x,y May include a pair of capacitors 2100 x,yThis makes each PUF cell 105 x,y This can be used to generate the corresponding capacitor difference, and based on this capacitor difference, the PUF cell 105 can be determined. x,y Persistent random PUF value (as referenced above) Figure 3A (Similar to the description). Next, based on multiple PUF cells 105... x,y The PUF output is determined by a plurality of persistent random PUF values. However, for simplicity, the determination of the capacitor difference from a single pair of capacitors 2100 should be described below.

[0074] The capacitor pair 2100 can be a matched pair of capacitors, or it can be different capacitors. The term 'matched' in this disclosure means that the capacitor pair has the same design. Although the two capacitors constituting the matched capacitor pair 2100 have the same design, small random manufacturing variations will inevitably exist between the two capacitors in practice. These manufacturing variations may include at least one of the following: differences in the distance between the capacitor plates (e.g., caused by differences in dielectric thickness), differences in the overlap area of ​​the two plates, differences in dielectric constant, etc. These manufacturing variations result in variations in the capacitance between the two capacitors constituting the matched capacitor pair 2100. Although the following description will focus on a matched pair of capacitors 2100 for simplicity, it should be understood that in alternatives, the two capacitors 2100 may have different designs. In this case, there will be some expected difference between their capacitances, in addition to random manufacturing variations that should introduce some random variation around the expected difference. Therefore, the capacitor difference determined according to the process described below performs the same function as when the capacitors are matched, but an offset is applied to the random variation that is equal to the design difference in capacitance between the two capacitors.

[0075] Figure 4A The circuit includes a switch group 2300, which can be used to set bias conditions for determining a capacitor difference value indicating a random manufacturing difference between a first capacitor C1 and a second capacitor C2. The first capacitor C1 and the second capacitor C2 are configured as a capacitor divider, wherein the two capacitors share a common node or center tap. The circuit further includes a buffer 2200 for buffering a signal at the common node between the first capacitor C1 and the second capacitor C2. The buffer may be configured to output a voltage V indicating the common node or center tap of the capacitor divider. i voltage V o Or any suitable type of voltage buffer for the current (e.g., source follower, simple operational amplifier, etc.). Each of the switches in the circuit can be implemented as any suitable type of controllable switch; for example, each switch can be implemented as a transistor, such as a FET or bipolar transistor. The state of each switch can be controlled by a controller; for simplicity, Figure 4AThe controller is not shown in the text.

[0076] Figure 4B (from U.S. Patent Application No. US16 / 716,435) Figure 2 B (reproduced) shows Figure 4A Example timing diagram of circuit operation. Figure 4B The timing diagram in the image represents the switch control signal. and And relative voltages V1, V2 and V o Timing. First, set the initial bias conditions, where... Close the reset switch so that the common-mode voltage V cm (An initial voltage, which can be, for example, depending on the components in the circuit (such as which buffer 2200 is used, etc.) or any suitable voltage level) is applied to the common node or center tap of the two capacitors. During the initial bias conditions, the voltage V2 is kept relatively high (V hi And keep the voltage V1 relatively low (V lo V can be adjusted, for example, according to the size and type of capacitor used. hi and V lo Set to any suitable value. The output voltage at time t0 during the initial bias condition can be expressed as:

[0077] V o (t0)=V cm +V off +V n (t0)

[0078] Where V off The read offset is caused by any inherent offset in buffer 2200, and V n (t0) is the random readout noise at time t0.

[0079] Next, by disconnecting the reset switch, the common node is no longer held at V. cm Next, the first bias condition is set. This means applying a first bias voltage V across the capacitor pair 2100 without the common node or center tap being held to any specific potential. hi -V lo The first bias condition thus sets the corresponding first charge distribution between the two capacitors. Figure 4B In the timing diagram, when the bias condition changes from the initial condition to the first condition, it indicates that V o The change is a result of charge injection into the reset switch and capacitive coupling. The output voltage at time t1 during the first bias condition can be expressed as:

[0080] V o (t1)=Vcm +V off +V ci +V ktc +V n (t1)

[0081] Where V ci This is due to the charge injection into the reset switch caused by the switch being opened, V n (t1) is the random readout noise at time t1, and V ktc This is KTC noise sampled from two capacitors. Value V o (t1) should be referred to as the first node measurement, which indicates the voltage at the common node of the capacitor divider 2100 during the first bias condition.

[0082] Next, by applying a first bias voltage to the pair of capacitors 2100 in the opposite direction, the voltage across the pair of capacitors 2100 is –(V hi -V lo This is used to set the second bias condition. This is done by controlling switch group 2300 to set V... lo Apply to V2 and V hi This is achieved by applying it to V1. Figure 4B In the timing diagram, when the bias condition changes from the first condition to the second condition, V can be seen. o The change is due to the redistribution of charge between the first and second capacitors. When the second bias condition is applied, V o This is represented by a decrease, which is a result of C2's capacitance being greater than C1's capacitance. However, if C1's capacitance is greater than C2's capacitance, then when the second bias condition is applied, V o Instead, it will increase. The output voltage at time t2 during the second bias condition can be expressed as:

[0083] V o (t2)=V cm +V off +V ci +V ktc +V n (t2)+((C1-C2) / (C1+C2))*(V hi -V lo )

[0084] Value V o (t2) should be referred to as the second node measurement, which indicates the voltage at the common node of the capacitor divider 2100 during the first bias condition.

[0085] Since the capacitor pair is matched, its capacitance is designed to be C1 = C2 = C. However, in reality, there is a small random difference in the capacitance, such that C1 - C2 = dC. Therefore, the actual capacitances C1 and C2 can be expressed as:

[0086] C1 = C + dC / 2

[0087] C2=C–dC / 2

[0088] Substituting this into the above equation, we get:

[0089] V o (t2)=V cm +V off +V ci +V ktc +V n (t2)+(dC / 2C)*(V hi -V lo )

[0090] Although V o (t2) is a function of the random manufacturing difference (dC) between capacitors, but is also affected by several different noise sources. Therefore, V o (t2) may not be a reliable indicator of random manufacturing defects, especially given that dC can be very small and therefore prone to loss due to noise.

[0091] However, by taking V o (t2)–V o The difference between (t1) yields:

[0092] V o (t2)–V o (t1)=(dC / 2C)*(V hi -V lo )+V n (t2)–V n (t1)

[0093] By taking the difference in this way, the KTC noise V ktc Offset V off Charge injection signal V ci and common-mode signal V cm All canceled out. In addition, the readout noise V n (t0) and V n Any low-frequency components in (t1) should also be largely eliminated. Therefore, by measuring V under the first bias condition and the second bias condition... o Furthermore, a more accurate measure of the random manufacturing difference between the two capacitors C1 and C2 can be found. V o (t2) and V oThe difference between (t1) can be called the capacitor difference, which indicates the random manufacturing difference between the pair of capacitors 2100. This more accurate measure can then be used to determine the persistent random PUF value, based on which the PUF output can be determined, for example, setting the value of one bit in the multi-bit PUF output, as explained in more detail below in the "Configuration" and "Readout" sections.

[0094] For example, a specific PUF cell 105 can be used. x,y Capacitor difference (V) o (t2)-V o The persistent random PUF value (e.g., set to "0" or "1") is determined by the magnitude of (t1), and this persistent random PUF value then serves as one or more bits of the multi-bit PUF output. Since the capacitor difference V has been determined in a manner that maximizes the accuracy of the dC measurement by removing almost all noise,... o (t2)-V o (t1), therefore the value of the PUF output is determined almost uniquely by randomly generating the difference. This should make the value of the PUF output sufficiently random to meet the PUF requirements.

[0095] Turning Figure 4C The determining unit 170 includes a MUX 5100, a PUF output unit 5300, and a switch group 2300. The PUF output unit 5300 is configured to control the switch group 2300 and the MUX 5100 to output voltage V. hi and V lo A specific row of PUF cells is applied, and a deselection voltage is applied to all other rows of PUF cells. This allows for the parallel measurement of the physical properties of the multiple PUF cells in the selected row. Therefore, very fast measurement and readout can be achieved.

[0096] In another specific implementation example, each PUF cell is 10⁵. x,y Resistors may be included, and the determining unit 170 may be configured to determine the PUF output based on the difference between the physical characteristics (such as resistance) of the resistors caused by random manufacturing defects.

[0097] Figure 5AAn example PUF cell 105x,y including resistors is shown. In this case, the pair of devices in the PUF cell is not a pair of single-component devices (as in Figures 3 and 4 above), but a pair of composite devices. Each device constituting the pair is a potential divider, and the two potential dividers are coupled together to form an H-bridge configuration, wherein the divider ratio of each of the potential dividers is matched (i.e., the design ratio Ra1:Ra2 is the same as the design ratio Rb1:Rb2). The design resistances of resistors Ra1, Ra2, Rb1, and Rb2 may all be the same (i.e., they may all be matched resistors). Alternatively, Ra1 and Rb1 may have the same design resistance (i.e., they may be matched resistors), and Ra2 and Rb2 may have the same design resistance (i.e., they may be matched resistors). Alternatively, each of Ra1, Ra2, Rb1, and Rb2 can have different design resistances, but the two potential dividers have the same design impedance ratio, i.e., Ra1:Ra2 = Rb1:Rb2. In each example, the two devices (e.g., the two potential dividers) are matched because both devices have the same design impedance ratio and therefore should theoretically output the same voltage division (i.e., theoretically Va should equal Vb). However, it will be understood that due to manufacturing differences, the actual resistance of the resistors will differ at least slightly from the design resistance. Therefore, for the same PUF cell 105 x,y For each of the measurements, the voltage at measurement point A may differ from the voltage at measurement point B by a random amount.

[0098] Figure 5B Shows the configuration for selecting and reading. Figure 5A One or more PUF cells of the type represented in the figure 105 x,y A non-limiting example implementation of the determining unit 170 is provided. The determining unit 170 includes a selection unit 810, which is configured to use control signals CS1 to CS2. X One or more columns of PUF cells are enabled to selectively apply bias or stimulation voltages VBIAS_HIGH to VBIAS_LOW to the H-bridges in the PUF cells within the enabled columns. Selection unit 810 is further configured to use control signals ROW_SELECT1 to ROW_SELECT Y Select PUF-enabled cell 105 x,y One or more of them are available for reading. The determining unit 170 further includes readout units 8201 to 820 configured to determine the difference between Va and Vb of a selected PUF cell. X The following discloses various techniques for determining the difference between Va and Vb (especially measuring the sign and magnitude of the difference between Va and Vb) by determining unit 170.

[0099] For the foregoing, several specific examples of various types of PUF cells have been disclosed, which can be used to determine physical characteristics for the purpose of determining PUF values ​​(e.g., the difference in resistance, capacitance, turn-on threshold voltage, etc., between a pair of matched devices). However, it will be understood that many other types of possible PUF cells exist and this disclosure is not limited to any particular type of PUF cell. For example, each PUF cell may include a pair of devices, where each device is a single active or passive component, such as a pair of transistors or capacitors; or each PUF cell may include a pair of devices, where each device is a more complex composite device comprising multiple components, such as a pair of ring oscillators or a pair of potential dividers, etc. It will be understood that this disclosure is not limited to any particular specific implementation of a PUF cell and can be applied to any specific implementation in which physical characteristics indicating random variations between a pair of devices can be used to determine persistent random PUF values. This disclosure specifically focuses on a technique for determining random manufacturing variations between a pair of devices by measuring one or more voltages of an indication difference (in most instances, 'measurement' determines both the sign and magnitude of the voltage, but in some instances, 'measurement' may determine only the sign of the voltage).

[0100] Figure 6 An example UF device according to one aspect of this disclosure is shown. The device includes a plurality of PUF cells 105. x,y As described above. The device also includes a row of RNG cell 605. X The RNG cell 605 will be described in more detail later. X Including RNG cells is optional and is included. Figure 6 The image shows the readout unit 620. x How can it be used to measure RNG cell 605? x The output voltage and the voltage generated by PUF cell 105 x,y The output voltage. In some implementations, the RNG cells can be omitted entirely. In other implementations, two or more rows of RNG cells may be included.

[0101] Determining unit 170 includes selection unit 610, which is configured to select a specific row of PUF cells 105 using the PUF_ROW_SELECT line and the RNG_ROW_SELECT line. x,y Or a single line of RNG cell 620 x For readability. The configuration of selection unit 610 and the connection of the ROW_SELECT line may depend on the specific design and configuration of the PUF cell and RNG cell, and therefore for simplicity, Figure 6Details are not shown in the text. The method of selecting unit 610 and selectable rows is not the focus of this disclosure and will therefore not be described further. However, the above text... Figure 2 , Figure 3A , Figure 3B , Figures 4A to 4C and Figure 5B Some non-restrictive examples are given below.

[0102] The determining unit 170 also includes a readout unit 620 for each column of PUF cells / RNG cells. x Each readout unit is coupled to the readout line of its corresponding column. For example, readout unit 6201 is coupled to the differential readout lines carrying load voltages Va1 and Vb1, and readout unit 620... X Coupled to the carrying voltage Va X and Vb X The differential readout line. Figure 2 , Figure 3A and Figure 3B An example of such a differential readout line is shown, wherein the differential voltage Va-Vb (or Vb-Va) output from the selected PUF cell to the readout line indicates random manufacturing differences within the selected PUF cell. Each readout cell 620 x Configured to output the differential voltage Va it receives x -Vb x The measurement 625 x .exist Figure 6 In the configuration shown, parallel readout is possible because selection unit 610 can select a row of PUF cells or RNG cells, and readout unit 620 can read them. x Multiple measurements of corresponding selected PUF cells or RNG cells were determined in parallel 625 x In an alternative, a single readout unit can be provided for two or more columns of PUF / RNG cells, where a multiplexer selects which of the selected cells the readout unit will read. From each readout unit 620 x Output metric 625 x According to the readout unit 620 x The configuration and use of metric 625 when determining PUF values ​​or dynamic random numbers. x It can be presented in several different forms. For example, the measurement 625 x It can simply indicate the sign of Va-Vb (or Vb-Va), for example, whether it is a positive or negative value; or measure 625. x It can indicate the sign and value of Va-Vb (or Vb-Va). This disclosure specifically focuses on the readout unit 620. x And subsequently, the output metric 625 can be used. x The different methods of implementation.

[0103] As explained in detail below, the PUF device 100, particularly the determining unit 170, can operate in any one or more different modes. For example, it can be configured to switch between two or more different modes. These modes may include PUF modes in which PUF values ​​are determined based on random manufacturing differences between devices with matching pairs, such as a coarse PUF measurement mode and / or a fine PUF measurement mode. Additionally or alternatively, these modes may include a PUF self-test mode and / or a dynamic random number mode.

[0104] Physically Unclonable Function Mode

[0105] Figure 7 An example implementation of a readout unit 620 including a chopper 710 and an ADC 720 is shown. The chopper 710 can be configured in any suitable manner that a person skilled in the art will well understand to controllably chop or switch the inputs of the ADC 720. Specifically, the chopper 710 can couple Va to the positive input "+" of the ADC 720 and Vb to the negative input "-" of the ADC 720 to perform analog-to-digital conversion of the signals Va-Vb. The chopper 710 can then be controlled to chop or switch the couplings such that Va is coupled to the negative input "-" of the ADC 720 and Vb is coupled to the positive input "+" of the ADC 720 to perform analog-to-digital conversion of the signals Vb-Va. The benefits of doing so are explained in more detail below.

[0106] The readout unit 620 can be configured in several different ways depending on whether it is intended to read only PUF cells, only RNG cells, or both PUF and RNG cells. Furthermore, the readout unit 620 can be configured to generate multi-bit digital words as output quantity 625 (indicating the sign and magnitude of Va-Vb), or to generate single-bit values ​​as output quantity 625 (indicating only the sign of Va-Vb), or can be controlled to output either multi-bit words or single-bit values ​​according to the desired operation of the readout unit 620. Each of these possibilities will be described in more detail below.

[0107] When configured to generate multi-bit digital words to determine the sign and magnitude of Va-Vb, using a chopper 710 and performing two digital conversions can help improve measurement accuracy. Specifically, this can help reduce the size of the measurement, which can be reduced by the selection unit 610 and the PUF cell 105. x,y And / or system offset and delay errors introduced by components within readout cell 620. For example, switches in those cells can cause charge injection mismatch in the signals Va and Vb, resulting in a certain degree of mismatch between Va and Vb, which is not present in PUF cell 105. x,yThe random manufacturing differences between a pair of devices within the unit are a result of this. Additionally or alternatively, any amplifier within the readout unit 620 (e.g., within the ADC 720) may have an inherent offset between its inputs, and / or any comparator within the readout unit 620 (e.g., within the ADC 720) may have comparator delay and / or offset. All these factors can be grouped together into a “systematic error” that remains substantially the same at each digital conversion.

[0108] The first digital conversion between Va and Vb can be expressed as:

[0109] D1( <x:0>)==ΔPUF+System Error+Noise1

[0110] ΔPUF is the Va-Vb component caused by the random manufacturing difference between a pair of devices in a PUF cell.

[0111] Noise 1 includes, for example, thermal noise and 1 / f noise.

[0112] Between the first and second digital conversions, the chopper 710 can be controlled to chop / switch the input of the ADC 720, ensuring that the second digital conversion is a signal Vb-Va. The second digital conversion of Vb-Va can be expressed as:

[0113] D2( <x:0>) = -ΔPUF + System error + Noise 2

[0114] D2 includes the value -ΔPUF because ΔPUF is defined as the component of Va-Vb caused by random manufacturing differences. Due to chopping, the ADC 720 converts Vb-Va, so that D2 represents the value -ΔPUF (+ the other components shown above).

[0115] Then, by discovering D1–D2, we obtain:

[0116] D1-D2=2*ΔPUF+(Noise1–Noise2)

[0117] In this case, the output measure 625 can be the value D1-D2. As explained later, the readout unit 620 can be configured to store D1 in, for example, a memory (not shown in the figure for simplicity) after the first conversion, or the readout unit 620 can be configured to save D1 in some other way (explained later) such that D2 can then be subtracted from D1 to obtain the output measure 625.

[0118] The systematic error can be largely or completely removed. There is a noise trade-off due to the increased thermal noise. However, the 1 / f noise is significantly reduced. In summary, the signal-to-noise ratio of D1-D2 is increased compared to D1 or D2.

[0119] Therefore, it can be seen that by performing two conversions and chopping between the two conversions, the accuracy of the output metric 625 can be significantly improved. This means that any PUF value subsequently determined using the output metric 625 can be more random because various potential inherent biases are reduced or removed, and random values ​​can be generated more consistently over time, resulting in more durable PUF values.

[0120] PUF fine measurement mode

[0121] Figure 8A Show how it can be implemented Figure 6 A non-limiting example of the readout unit 620. In this example, the ADC720 is a ramp ADC (sometimes also called a slope ADC), which consists of a ramp generator 805 (sometimes also called a slope generator) as part of the PUF device 100 (e.g., as part of the determination unit 170), a comparator 812 including a preamplifier 810 and a regenerative or latching comparator stage 815, and a counter 820. The comparator 812 may be an auto-zero comparator, or other sampling comparator, as described later. The ramp generator 805 is configured to generate two ramp signals: a first ramp_up that rises from a lower value to a higher value over time; and a second ramp_up that falls from a higher value to a lower value over time. p_down. The ramp generator 805 can be implemented in any suitable manner that a person skilled in the art will well understand. The ramp generator 805 can be a single unit that generates the ramp_up signal and the ramp_down signal, or a separate ramp generator can be used to generate each ramp signal. In a non-limiting example, the ramp generator 805 can be a DAC ramp generator that includes a digital-to-analog converter (DAC) configured to receive a multi-bit binary count value, which is converted into two analog ramp signals. The "higher value" mentioned above can be the maximum DAC output voltage and the "lower value" can be the minimum DAC output voltage.

[0122] The preamplifier 810 can be any suitable type of differential amplifier that a technician will understand well. See below for reference. Figure 9A To describe a specific example in more detail, the preamplifier 810 can be a single-stage or multi-stage amplifier. Furthermore, the preamplifier 810 may optionally include an automatic zeroing function, as referenced below. Figure 9A A more detailed description follows. Using the auto-zero preamplifier 810 is beneficial, but it is not essential, and the readout unit 620 can operate without the auto-zero preamplifier 810.

[0123] Comparator stage 815 can be a stage (e.g., an operational amplifier) ​​that compares two voltages at its inputs and sets the output to a value (e.g., indicating which is a higher or lower value) to favor a suitable stage. This will be well understood by those skilled in the art. Comparator stage 815 can be a fully differential comparator stage 815 and output a differential signal, or it can be configured to output a single-ended signal. For example, if comparator stage 815 is fully differential, it can be configured to output a differential signal 1 or -1 based on the comparison of signals at the inputs. A single-ended output can be configured to output a signal 1 or 0 (or alternatively 1 or -1) based on the comparison of signals at the inputs. In a non-limiting example, comparator stage 815 can be a regenerative latch comparator, which can help improve the stability of decisions within a threshold. Alternatively, a set / reset (SR) latch can also be coupled to the output to help latch the output to improve noise immunity (for simplicity, ...). Figure 8A (Not indicated in the text).

[0124] Counter 820 can be any suitable type of counter, for example, configured to increment or decrement. Counter 820 can be a simple binary counter or a Gray code counter. Using a Gray code counter is advantageous because each increment or decrement of the count results in a single bit change, giving counter 820 a consistent current footprint during counting. This helps prevent side-channel attacks targeting the current or power consumption of the readout unit 620. Figure 8A In the example, counter 820 is implemented as a single counter, but it can alternatively be implemented as two praise counters, as referenced below. Figure 9A The explanation.

[0125] Figure 8B The diagram shows the device is operable when in PUF fine measurement mode. Figure 8A A timing diagram of one mode of readout unit 620. In this operating mode, if the PUF device includes two or more PUF cells that can be connected to readout unit 620 (e.g., such as...), Figure 6 As shown in the diagram), the selection unit 610 can use the row_select signal to control the PUF cell 105 to output signals Va and Vb to the readout unit 620, while other cells are disconnected from or decoupled from the readout unit 610 (or not driven / stimulated to output any signals), so that only one PUF cell outputs Va and Vb to the readout unit 620 (e.g., as shown in the diagram). Figure 5B (As shown in the diagram). The readout unit 620 generates a multi-bit measurement 825 of both the sign and magnitude of the indication values ​​Va-Vb. Figure 9B In the example shown, Vb is greater than Va.

[0126] First, the switch controlled by signal SW0 is closed to switch the PUF cell 105 via chopper circuit 710. x,y Coupled to preamplifier 810, the preamplifier inputs Vpos and Vneg are kept at Va-Vb. Although the switch controlled by SW0 is shown located on the comparator 812 side of chopper circuit 710, the switch can alternatively be located on the PUF cell 105 side of chopper circuit. In another alternative, the switch may not form part of readout unit 620, but rather be part of PUF cell 105 and controlled to couple or decouple PUF cell 105 from readout unit 620 as needed (e.g., when multiple PUF cells 105 are coupled to readout unit 620, the switch can be used to decouple all but one PUF cell 105 from readout unit 620 at any given time). Figure 5B An example of this situation is shown in the diagram. In this example, the chopper 710 first couples Va to the positive input of comparator 812 and Vb to the negative input of comparator 812. Since Vb > Va, therefore, as in... Figure 9B As can be seen, voltage Vneg is greater than voltage Vpos. Comparator 812 can be configured to sample those signals in any suitable manner, an example of which is shown in [example missing]. Figure 9A As shown in the diagram, the switch controlled by signals OP and OP_bar is also controlled to close the switch, thereby coupling the output of comparator 812 to the input of counter 820 and opening the switch controlled by OP_bar. Alternatively, instead of using a switch, one or more gated logic cells can be used, configured to switch between coupling the output Comp_out to counter 820 or to output 826 based on the control signal OP.

[0127] Next, the switch controlled by signal SW0 is disconnected, and the sampled values ​​of Va and Vb are held at the positive and negative inputs of comparator 812, respectively. Then, the switch controlled by SW1 is closed to couple the ramp_up and ramp_down signal lines to the input of comparator 812. At this point, the ramp_down signal is at its maximum value, ready to ramp down; and the ramp_up signal is at its minimum value, ready to ramp up. During this stage, the initialization of the first digital conversion is complete.

[0128] When the clock signal clk starts, switch 1 is enabled. The clock signal can be generated by the clock generator within the determination unit 170, or it can be a local clock signal within the device implementing the PUF device 100. The clock signal can have any suitable frequency depending on the configuration of the ramp generator 805 and the counter 820. Figure 8B The diagram illustrates the ramp_up and ramp_down signals and how they affect the voltages at Vneg and Vpos. The ramp signal can continue until ramp_down reaches its minimum value and ramp_up reaches its maximum value, at which point the ramp generator 805 can be reset.

[0129] In this example, counter 820 is initially configured to count the clock signal while Comp_out is low. When Vpos becomes greater than Vneg, Comp_out goes high, at which point counter 820 stops counting. The count value 825 is V... a –V b +Offset / Delay +Noise 1 multi-bit digital representation, where offset / delay is a non-ideal factor caused by the circuit (as previously explained).

[0130] Counter 825 can be configured to increment or decrement in any suitable manner, such as using standard binary counting or Gray code counting. As those skilled in the art will understand, in Gray code counting, with each increment or decrement, the value of only one bit in a multi-bit word changes. This can benefit the PUF device 100 by helping to maintain a constant current consumption throughout the counting period, thereby reducing the likelihood of side-channel attacks targeting the device's power footprint.

[0131] Once the number of clock cycles for Clk reaches the full scale of conversion 1 (hereinafter referred to as Fullscale_conv1), the conversion is complete and the Clk signal terminates. For example, if Fullscale_conv1 is 7 bits, the number of clock cycles is 2. 7 =128. Switch signal SW0 changes state to recouple PUF cell 105 to the input of comparator 812 via chopper circuit 710. Switch signal SW1 also changes state to disconnect ramp generator 805 from the input of preamplifier comparator 812. Finally, chopper signal changes state to chop the input of comparator 812 by chopper circuit 710. In this example, since chopper circuit 710 couples Va to the positive input of comparator 812 and Vb to the negative input of comparator 812 during transition 1, when chopper signal changes state, chopper circuit 710 couples Va to the negative input of comparator 812 and Vb to the positive input of comparator 812. Therefore, the value -(Va-Vb) (i.e., Vb-Va) is now held at the input of comparator 812. When the switch control signal SW0 changes state again (from high to low), the preamplifier 810 samples this signal, thereby disconnecting the preamplifier 810 from the PUF cell 105. The switch signal SW1 also changes state (from low to high), thereby recoupled the ramp signal to the input of the comparator 812. The ADC is now ready for the second conversion.

[0132] When the clock signal is restarted, the second transition begins, causing counter 825 to start counting again and ramp generator 805 to enable ramp signals ramp_up and ramp_down.

[0133] The counter 825 can be operated in many different ways. Figure 8B In the example shown, counter 825 is used as a pure up-counter (but can alternatively be used as a pure down-counter). In this example, the signal "chopper" is used to control not only the chopper circuit 710 but also the operation of counter 820. Specifically, a change in the state of the chopper signal alters the nature of the signal that will cause counter 820 to start and stop counting. In this particular example, when chopper is low, counter 820 is configured to count when comp_out is low and stop counting when comp_out is high. When chopper is high, counter 820 is configured to count when comp_out is high and stop counting when comp_out is low. Therefore, as in Figure 8B As can be seen, during transition 2, counter 820 initially does not count, but then when Vpos becomes greater than Vneg and the comp_out signal goes high, counter 820 starts counting the Clk signal in a loop. At the end of transition 2, the Clk signal terminates and the entire transition is complete, so that the output 825 of the count represents the measure of Va-Vb. In this example, due to the chopping performed by chopper circuit 710 and the change in the operation of counter 820 caused by the chopping signal, the count during transition 2 is equal to: Fullscale_conv2 – (Vb-Va + offset / delay + noise2), where Fullscale_conv2 is the full-scale count of counter 820 during transition 2 (which is the same as the full-scale count of counter 820 during transition 1).

[0134] The value of Count1 (i.e., the amount counted during transition 1, which can be called the first digit value) plus the value of Count2 (i.e., the amount counted during transition 2, which can be called the second digit value) is:

[0135] [Va–Vb+offset / delay+noise1]+[Fullscale_conv2–(Vb-Va+offset / delay+noise)] 2)]

[0137] = 2(Va–Vb) + noise1 - noise2 + Full scale_conv2

[0138] Therefore, it can be seen that the digital measurement of Va-Vb is obtained from the first and second digital values ​​(in this case, by adding them together). In this example, counter 825 is made to continue incrementing (or decrementing if counter 825 is a decrementing counter) its count between transition 1 and transition 2, such that the counter output 825 equals Count1 + Count2 at the end of transition 2. Therefore, in this operating mode, the digital measurement 625 of Va-Vb is the count value 825 at the end of transition 2. As can be seen above (and explained in more detail previously), the offset / delay value is completely or substantially eliminated, and the output 825 is a more accurate measure of the signal Va-Vb. Furthermore, counter 820 can be a simple type of counter, thus serving as a simple incrementing or decrementing counter. The control of the counter is also simple, as in Figure 8B As can be seen, and since counter 820 only continues its counting between transition 1 and transition 2, there is no need to store the value Count1 in memory. This further simplifies the operation and requirements of the readout unit 620.

[0139] In this example, the full-amplitude count for each transition (e.g., Fullscale_conv1 and Fullscale_conv2) can be the same as the full-amplitude of the difference between the maximum and minimum values ​​of the ramp signal generated by the ramp generator (and the same as the full-amplitude of the digital value used by the DAC in ramp generator 805 to generate the ramp signal). The full-amplitude count for each transition (e.g., Fullscale_conv1 and Fullscale_conv2) can be 50% (or less than 50%) of the full-amplitude count that counter 820 is capable of achieving. For example, if counter 820 is configured to generate an 8-bit count, the full-amplitude count for each transition can be 7 bits (i.e., 128). Therefore, it can be seen from the above formula that when 2(Va–Vb) + noise1 - noise2 is positive (i.e., Va>Vb, assuming the noise component is small), the 8-bit count at the end of transition 2 will have an MSB of 1 (i.e., the 8-bit word equals 128 + a positive number). However, if 2(Va–Vb) + noise1 - noise2 is negative (i.e., Vb > Va, assuming the noise component is small), then the 8-bit count at the end of conversion 2 will have an MSB of 0 (i.e., the 8-bit word equals 128 + a negative number). If the MSB is 1, the remaining 7 bits will represent the magnitude of 2(Va–Vb) + noise1 - noise2; and if the MSB is 0, the remaining 7 bits will represent the 7-bit full magnitude minus the magnitude of 2(Va–Vb) + noise1 - noise2 (thus, the magnitude of 2(Va–Vb) + noise1 - noise2 can be obtained directly as desired, for example, by toggling the value of each of the 7 bits if counter 820 is a standard binary counter). Therefore, the MSB of count 825 at the end of conversion 2 indicates the sign of Va - Vb. This characteristic has several useful applications, which will be explained later. It will be understood that the 8-bit counter is just an example, and the counter 825 can be configured to have any suitable full amplitude greater than the count in each of conversions 1 and 2.

[0140] While this is a particularly useful implementation and operation of counter 820, many other implementations and operations are possible. For example, in another implementation, counter 820 can be reset between transition 1 and transition 2, wherein the count value 825 (e.g., a first digital value) at the end of transition 1 is stored in memory and then added to the count value 825 (e.g., a second digital value) at the end of transition 2. In this case, another processing unit / block ( Figure 8A (Not shown in the text) can be configured to sum the two count values ​​together, resulting in a fully converted digital measurement of Va-Vb. The full scale of counter 820 can be the same as or greater than the full scale of the count in each of conversions 1 and 2 (e.g., Fullscale_conv1 and Fullscale_conv2).

[0141] In another possibility, counter 820 may not use a chopping signal, allowing it to be triggered to start and stop counting in the same manner during transitions 1 and 2. In this case, the number counted by counter 820 during transition 2 can be represented as: -(Va-Vb) + offset / delay + noise². In this case, the number counted by counter 820 during transition 1 can be stored in memory and then processed by another processing unit / block ( Figure 8A (Not shown) Subtract the number counted during conversion 2 from the count to obtain the digital measurement of Va-Vb. The full scale of counter 820 may be the same as or greater than the full scale of the counts in each of conversions 1 and 2 (e.g., Fullscale_conv1 and Fullscale_conv2).

[0142] In another alternative, instead of storing the count during transition 1, an up / down counter can be used at counter 820. In this case, counter 820 can be operated to increment (or decrement) during transition 1, and then decrement (or increment) during transition 2, where the count value 825 at the end of transition 2 can be a digital measurement of Va-Vb. The full scale of counter 820 can be the same as or greater than the full scale of the counts in each of transitions 1 and 2 (e.g., Fullscale_conv1 and Fullscale_conv2).

[0143] Figure 8B (and in other timing diagrams disclosed herein, such as Figure 9B , Figure 10B , Figure 16C The various control signals and their timing represented in the diagram can be set by the control unit. For simplicity, Figure 8A The control unit is not represented in the text. The control unit can be any suitable type that a person skilled in the art will understand well; for example, the control unit can be some kind of processor, such as a microcontroller or microprocessor, or the control unit can be programmable logic, such as an FPGA or dedicated control circuitry.

[0144] Figure 9A A specific example implementation of the preamplifier 810 is shown. In this example, the preamplifier 810 is a two-stage auto-zero sampling amplifier comprising two gain / amplifier stages 910 and 920, wherein capacitors C1a and C1b are located at the input of the first gain stage 910 and capacitors C2a and C2b are located at the input of the second gain stage 920. While this example represents a two-stage layout, it will be understood that alternatively this example could be a single-stage layout (in which case the gain stage 920, capacitors C2a and C2b, and auto-zero switch AZ2 would be omitted), or a three- or more-stage layout.

[0145] Figure 9B Shown in Figure 9A The example timing diagram illustrates how digital measurements of Va-Vb can be determined during the circuit periods shown. Most operations of the layout are related to... Figure 8B The same applies as described above, and those operational parts will not be repeated here. Furthermore, the clock signal Clk and the switch control signal OP will be... Figure 8B The operation is the same as that shown in the text and is for simplicity. Figure 9B The Chinese side did not indicate this.

[0146] Before conversion 1, control signals AZ1 and AZ2 are set high to automatically zero the two stages of the preamplifier. Subsequently, AZ1 and AZ2 are set low to disconnect the automatic zeroing switch, and control signal SW0 goes low to connect the preamplifier 810 to the PUF cell 105. x,y The connection is disconnected, and the values ​​Va and Vb are sampled at the input capacitors C1a and C1b. Therefore, capacitors C1a and C1b effectively hold or store the values ​​Va-Vb at the input of gain stage 910. By automatically zeroing the preamplifier 810 before conversion, the residual amplifier offset is reduced, thus minimizing the magnitude of the "offset" component within the measurement performed by conversion 1 (as previously referenced). Figure 8B (A more detailed description) can be made smaller. After the preamplifier 810 has been automatically zeroed and the voltages Va and Vb have been sampled, the following steps are taken, referencing the above. Figure 8B The conversion 1 is performed in the same manner as described.

[0147] After conversion 1 and before conversion 2, control signals AZ1 and AZ2 are set high again to automatically zero the two stages of the preamplifier, thereby reducing the residual amplifier offset of conversion 2 again. Control signals SW0 and chopper go high to recouple Va and Vb to the input of preamplifier 810 (but chopping the input coupling via chopper circuit 710), and control signal SW1 goes low to disconnect ramp generator 805. Subsequently, control signals AZ1 and AZ2 go low, and control signal SW0 goes low to reconnect preamplifier 810 to PUF cell 105. x,y Disconnect the circuit and sample the values ​​Va and Vb at input capacitors C1a and C1b, and raise the control signal SW1 high. Then, refer to the above... Figure 8B The same method described is used to perform conversion 2.

[0148] The use of an auto-zero preamplifier 810 is not essential, but it can have the benefit of reducing amplifier offset, thereby improving the accuracy of Va-Vb measurements. Using a multi-stage amplifier 810 can have the same benefit, especially when the multi-stage amplifier 810 is an auto-zero preamplifier 810, because it helps to reduce the total input correlation offset. Specifically, it reduces the kTC noise mismatch generated in the first gain stage, and reduces the input correlation offset of the kTC noise mismatch at the second gain stage by a factor equal to the gain of the first gain stage. However, regardless of whether the preamplifier 810 is an auto-zero amplifier, the preamplifier 810 may have only a single gain stage or it may be a multi-stage amplifier (i.e., it may have two or more gain stages).

[0149] exist Figure 8A , Figure 8B , Figure 9A and Figure 9B In this designation, comparator 815 is indicated as having a single-ended output, which is set high or low based on a comparison of the voltage at the input terminals of comparator 815. Alternatively, comparator 815 may have a differential output, wherein the output differential voltage is high or low (e.g., positive or negative) compared to the voltage at the input terminals of comparator 815. As those skilled in the art will appreciate, such a differential voltage can be used to control a previous reference. Figure 8B and Figure 9B The operation of the counter 820 is described (e.g., using only one of the two output signals to control the start / stop of the counter 820, or using the counter 820 configured to start / stop based on whether the differential voltage output from the comparator stage 815 is positive or negative).

[0150] Figure 10A Showing what can be used as an alternative Figure 8A and Figure 9A The single counter 820 shown is an alternative type of counter 1020. Counter 1020 is a praise counter that includes counter A 1022 and counter B 1024. Counter 1020 is configured such that during operation, counter A 1022 counts the Clk signal while counter B 1024 does not count, and counter B 1024 counts the Clk signal while counter A 1022 does not count. Each of counter A 1022 and counter B 1024 can be a standard binary counter, a Gray code counter, or any other type of counter.

[0151] Figure 10B Example timing diagrams are shown to help illustrate the operation of the praise counter 1020. The operation of the readout unit 620 is generally similar to that in the reference diagram. Figure 8B or Figure 9B The description is the same, except for the operation of the praise counter 1020. Therefore, for simplicity, Figure 10B The following explanation focuses specifically on the operation of the praise counter 1020. Counter A 1022 is configured to operate in the same manner as counter 820 described above with reference to Figures 8 and 9. Therefore, during transition 1, when Comp_out is low (e.g., when the positive output terminal of comparator 812 is low), counter A 1022 counts the Clk signal; and during transition 2, when Comp_out is high (e.g., when the positive output terminal of comparator 812 is high), counter A 1022 counts the Clk signal. Counter B 1024 praises counter A 1022, and therefore, when counter A 1022 does not count, i.e., when Comp_out is high during transition 1 (e.g., when the negative output terminal of comparator 812 is high) and when Comp_out is low during transition 2 (e.g., when the negative output terminal of comparator 812 is low), counter B 1024 counts the Clk signal. Next, the measure of Va-Vb can be determined using the count 825A of counter A 1022 for transition 2 and the count 825A of counter A 1022 for transition 1 (as previously described), or using the count 825B of counter B 1024 at the end of transition 2 and the count 825B of counter B 1024 at the end of transition 1 (which will give a measure of –(Va-Vb)). For example, in a chopper counter implementation, this can be achieved by allowing the counter to accumulate counts for both the first and second transitions (as previously explained). Alternatively, the counter can be reset between transitions, where the count value at the end of transition 1 is stored and then the count value at the end of transition 2 is subtracted from that count value.

[0152] Although the operation of the comparator counter 1020 has been specifically described in the case of the comparator stage 815 with differential output, it will be readily understood that the operation will be the same in the case of the comparator stage 815 with single-ended output.

[0153] The benefit of the praise counter 1020 is that it keeps counting throughout every transition, regardless of the values ​​of Va and Vb. This means that the circuit has a constant current consumption at every transition, regardless of the analog value being converted. This should help reduce the likelihood of side-channel attacks based on focusing on the circuit's power consumption.

[0154] Another benefit is achieved in the case of PUF self-checks, which can take the form of PUF self-registration or PUF health checks.

[0155] Optionally, when the PUF device 100 includes components configured to operate in parallel (e.g., to measure two or more differential signals output by the PUF cell 105 in parallel, such as...), Figure 5B and Figure 6 Two or more readout units 620 (as shown) x In this case, a single ramp generator 805 can be used, and the readout units 620 share the ramp_up and ramp_down signals. In this example, the first ADC will be formed by the ramp generator 805, comparator 812, and counter 820 of the first readout unit 6201. The second ADC will be formed by the ramp generator 805, comparator 812, and counter 820 of the second readout unit 6202, and so on. A switch controlled by signal SW1 can be configured for each readout unit 620. x Part of it may exist as a single pair of switches controlled by SW1, the state of which determines whether the ramp_up and ramp_down signals are supplied to all readout units 620. x Still not supplied to read unit 620 x This enables parallel readout and PUF value generation, significantly increasing the speed at which PUF outputs can be generated, while minimizing the number of parallel components / circuits and thus minimizing cost and space.

[0156] Alternatively or additionally, not each read unit 620 has its own counter 820, but there may be two or more read units 620. x Each of the components shares a single counter. In this case, each readout unit may include a latching device that latches the output of the single counter when the output of comparator 815 changes, such that each readout unit 620... x The count can still be obtained depending on the signal Va-Vb being measured.

[0157] PUF self-test mode

[0158] In some PUF systems, it may be desirable to identify PUF cells for which the measured physical characteristics have a relatively large difference (resulting in a relatively large Va-Vb), and mark those PUF cells as the cells to be used for subsequent PUF value determination. This is referred to as 'registration'. Optionally, the PUF device 100 of the present disclosure may operate in a self-test mode, in which the PUF device 100 performs self-registration (e.g., using circuitry local to the PUF device 100 to register the PUF cells). Registration may be performed because PUF cells with small measured physical characteristics may be prone to having PUF values that change over time. Specifically, if Va>Vb gives a PUF value of 0 and Va<Vb gives a PUF value of 1, if Va-Vb is very small, then due to changes in environmental conditions, component wear, and / or read noise, it is more likely that the PUF value of the cell may change from 0 to 1 or vice versa over time.

[0159] Thus, after device fabrication, registration may be performed, in which Va-Vb is measured for each PUF cell and those PUF cells having a relatively large Va-Vb may be marked as suitable for use, and those PUF cells having a relatively small Va-Vb may be marked as not suitable for use. Previously, this may have required determining the full measure of Va-Vb (e.g., using any of the techniques described above) and then comparing the value to a threshold to determine if it is large enough for future use. However, using the glorify counter 1020, the registration process can be made significantly more efficient.

[0160] PUF health checking also involves determining whether the Va-Vb of the PUF cells is relatively large, but the result of the comparison is to generate a status report indicating the likelihood that the PUF device will produce a persistent PUF output, rather than marking the PUF cells as suitable or not suitable for generating PUF values. More specifically, if the PUF device 100 has multiple PUF cells 105, the magnitude of Va-Vb for each cell 105 may change or drift over time. Cells with a relatively small magnitude of Va-Vb are more likely to have a change in the PUF value they produce. The greater the number of cells that experience this change, the more likely the final PUF output (which is generated using PUF values that are generated using each of the cells 105) will become no longer reliably persistent. Thus, throughout the life of the PUF device 100, the PUF device 100 may periodically or intermittently operate in the PUF self-test mode to evaluate how many cells now have a relatively small magnitude of Va-Vb, based on which the statistical likelihood of producing a persistent PUF output can be determined. The status report may indicate the likelihood of producing a persistent PUF output in one or more different ways, the one or more different ways including: identifying the number or proportion of cells having a relatively small magnitude of Va-Vb; identifying the statistical likelihood of producing a persistent PUF output (e.g., a score out of 100), etc.

[0161] Therefore, the PUF self-test mode may include operating the PUF device 100 in either a self-registration mode or a health check mode. In some instances, the PUF device 100 may be configured to operate in self-registration mode for cell registration (or re-registration) throughout its lifespan, for example, when the device is turned on (and optionally, occasionally again during its lifespan), and periodically or intermittently in health check mode at other times. In both operations, determining whether the values ​​of Va-Vb are relatively small will now be described further.

[0162] Figure 11A Examples showing relatively small Va-Vb are given, and Figure 11B Examples of relatively large Va-Vb values ​​are shown. During registration, refer to... Figure 10B As described above, the readout unit 620 is operated to determine the magnitude of Va-Vb. The only difference is that counters A1022 and B1024 are configured to stop counting at the end of transitions 1 and 2 (i.e., when the ramp signal completes its ramp). Instead, the readout unit 620 is configured to... Figure 10B The process represented in the diagram normally stops counting, then continues counting for n cycles up to Clk (e.g., in...). Figure 10B In the scenario described, counter B 1024 can continue counting n cycles of Clk at the end of transition 1, and counter A 1022 can continue counting n cycles of Clk at the end of transition 2, or both counter A 1022 and counter B 1024 can count n cycles of Clk at the end of either transition 1 or transition 2. Figure 11A As will be seen, the n cycles of Clk equal the additional threshold count and define the stability threshold used to determine whether Va-Vb is considered sufficiently large to be reliably stable. The larger the number n, the larger the magnitude of Va-Vb must be for the PUF cell to meet the threshold requirement for reliable stability.

[0163] To further explain this, Figure 11A The diagram shows a bell-shaped distribution, representing the statistical distribution of Va-Vb values ​​in PUF cells. As can be seen, approximately 50% of PUF cells have negative Va-Vb and approximately 50% have positive Va-Vb (as is required for PUF cells to generate random PUF values), where the values ​​are approximately normally or Gaussian distributed. In this example, "0" is the midpoint between counters A and B (e.g., "0" represents 50% of the maximum possible value at the end of transition 2) and indicates no difference between Va and Vb. The number 1105 represents counter A 1022 according to... Figure 10B The number represents the process count, and 1110 represents the corresponding measurement size of 2(Va-Vb). Number 1115 indicates an additional threshold count when counter A 1022 is configured to count when operating in PUF self-test mode. Number 1120 represents the final value measured by counter A 1022 at the end of the process. Number 1155 indicates the count of counter B 1024 according to... Figure 10B The number represents the process count, and 1160 represents the corresponding measurement size of 2(Vb-Va). The number 1165 indicates an additional threshold count when counter B 1024 is configured to count when operating in PUF self-test mode. The number 1170 represents the final value measured by counter B 1024 at the end of the process.

[0164] As can be seen in this example, since threshold count 1115 has flipped the count of counter A 1022 from negative to positive, the measured values ​​1120 and 1170 have the same sign.

[0165] In contrast, turning Figure 11B We can see that value 1120 is negative and value 1170 is positive. This is because Va-Vb has a large magnitude, so the additional threshold count 1115 is insufficient to flip the count of counter A 1022 from negative to positive. Therefore, by using additional threshold counts 1115 and 1165 (which will have the same size as each other), it is possible to quickly determine whether Va-Vb is large enough to exceed the stability threshold with minimal additional time and processing. If, during PUF self-test mode, counter outputs 1025A and 1025B both have the same sign, then Va-Vb is relatively small and less than the stability threshold, indicating that the PUF cell is unlikely to be stable enough for the sign of Va-Vb to remain the same over time. If counter outputs 1025A and 1025B have different signs, then Va-Vb is relatively large and the PUF cell should be used in the future. As you will understand, in this example, since both counters are up-counters, values ​​1120 and 1170 will both be positive or will have different signs. However, if the counters were down-counters, values ​​1120 and 1180 would both be negative or will have different signs. Therefore, it is important to consider whether two values ​​have the same sign (positive or negative), in which case the PUF cell should not be used in the future unless they have different signs. This can be quickly determined, for example, by XORing the MSBs of counters A 1022 and B 1024.

[0166] The positive or negative count value output by the counter can be determined very quickly from the MSB of the count alone. If the MSB of the counter is 0, the count is negative, and if the MSB is 1, the count is positive. Therefore, it can be determined very quickly by executing the reference... Figure 10B The described operation uses the additional threshold count described above and then examines whether the MSBs of the outputs 1025A and 1025B of counters A 1022 and B 1024 are the same (in which case the PUF cell can be considered unstable) or different (in which case the PUF cell can be considered stable) to very quickly determine the stability of the PUF cell.

[0167] Another benefit of this approach is that the PUF value of a PUF cell is never disclosed. Specifically, checking whether the signs of the values ​​counted by counters A1022 and B1024 are the same does not indicate whether Va-Vb is positive or negative (and therefore does not indicate whether the PUF value of that cell is 1 or 0). This means that self-tests can be performed more safely, and results can be reported more openly without revealing the PUF value of each individual cell.

[0168] In an alternative approach, instead of using additional threshold counting to determine whether the values ​​of Va-Vb are greater than or less than a stability threshold, the values ​​of Va-Vb can be measured as described with reference to Figures 8 through 10, and then compared with a stability threshold in further processing. For example, the measured values ​​of Va-Vb can be stored in memory and then arithmetically compared with a predetermined stability threshold.

[0169] When a health check is performed, once one or more PUF cells 105 are examined to see if their Va-Vb values ​​are less than the stability threshold, a status report can be generated as described above.

[0170] When self-registration mode is executed, once PUF cell 105 is checked to see if its Va-Vb values ​​are less than a stability threshold, the PUF cell can be marked by saving, for example, a record of the PUF cell ID and a flag indicating whether the cell is suitable for generating PUF values ​​in memory. Self-registration can be repeated periodically or intermittently in the field throughout the life of PUF device 100 to ensure that each of the PUF cells used to generate PUF output remains reliably stable.

[0171] By configuring the readout unit 620 disclosed herein, the same device can be used to perform self-tests or generate PUF values ​​without requiring additional dedicated circuitry, thereby saving costs and reducing the size of the PUF device.

[0172] In the above explanation of PUF value generation with reference to Figures 8, 9, and 10, the readout unit 620 operates in one mode such that the Va-Vb measurement 625 is a relatively fine measure of Va-Vb. However, the readout unit 620 can also be configured to operate to generate PUF values ​​by determining a coarser measure of Va-Vb, which can be achieved faster and / or with lower power consumption. This operating mode is referred to as 'coarse PUF measurement'.

[0173] PUF coarse measurement mode

[0174] In one example of this operating mode, the control signal OP can be set low (and correspondingly OP_bar can be set high) to disconnect counters 820 and 1020 from the output of comparator 812 and to directly couple the output of comparator 812 to the output 826 of readout unit 620.

[0175] Figure 12A This diagram shows a simplified representation of the readout unit 620 when control signals OP and SW1 are set as described above. In this example, the preamplifier 810 is... Figure 9A The same multi-stage auto-zero preamplifier, but preamplifier 810 may alternatively have any number of gain stages (e.g., one, three, four, etc.), or may alternatively be any suitable type of sampling preamplifier, with or without auto-zero functionality.

[0176] In the coarse measurement operation mode, the readout unit 620 is configured such that the measurement 625 of Va-Vb is a single-bit value 826 indicating the sign (rather than the magnitude) of Va-Vb. More specifically, the comparator 812 acts as a single-bit quantizer ADC that sets the value of its single-bit output based on the relative magnitudes of Va and Vb. This operation mode is particularly useful for PUF devices that have been registered (as previously described), where the PUF value of the cell read out is set high or low (e.g., 1 or 0) depending on whether Va-Vb of cell 105 is positive or negative (hence the term 'weak' PUF). It will be understood that this example of the coarse measurement operation mode is faster than the fine measurement operation mode previously described. By having a reconfigurable readout unit 620 capable of operating in either the fine or coarse measurement mode (and optionally, also in the self-test mode), the same PUF device 100 can be used for a variety of different purposes. For example, the same hardware can be used for device registration (e.g., self-registration), generating PUF values ​​using multi-bit measurements of Va-Vb (which can be 'strong' or 'weak' PUF operations), or generating PUF values ​​faster using single-bit measurements of Va-Vb (e.g., 'weak' PUF operations).

[0177] return Figure 12A The example of a coarse PUF measurement, as illustrated, shows that the single-bit measurement 826 of Va-Vb can be implemented in two different ways. The first technique, the 'chopping technique,' utilizes a chopper circuit 710 such that the input to the comparator stage 815 is ultimately 2(Va-Vb), where system errors associated with the circuit (e.g., bias voltage in the preamplifier 810) are reduced or completely eliminated from the signal at the input of the comparator stage 815.

[0178] Figure 12B An example timing diagram of operation in the 'chopping technique' is shown. The switch controlled by SW1 is always open to completely decouple the ramp generator 805 from the comparator 812. For simplicity, Figure 12B Signal SW1 is not shown. First, the auto-zero switch controlled by signals AZ1 and AZ2 is closed and the coupling switch controlled by signal SW0 is opened. Next, comparator 812 is coupled to PUF cell 105 by closing the switch controlled by signal SW0 (e.g., Va can be coupled to C1a and Vb can be coupled to C1b). Then, the auto-zero switch is opened by controlling signals AZ1 and AZ2 (simultaneously or at a slightly offset time). Finally, chopper circuit 710 is controlled by signal 'chopper' to switch the coupling of voltages Va and Vb with the input of comparator 812 (e.g., Va can now be coupled to C1b and Vb can now be coupled to C1a). At this time, the input of comparator stage 815 will include a component equal to 2(Va-Vb). Auto-zeroing preamplifier 810 should reduce or eliminate residual offset in preamplifier 810, and therefore should reduce or eliminate systematic error of the signal at the input of comparator stage 815. Furthermore, by operating the circuit in this manner and generating a signal comprising 2(Va-Vb) at the input of comparator stage 815, the magnitudes of the signals (Va and Vb) compared by comparator stage 815 are doubled, which should further improve the accuracy of the comparison by comparator stage 815. Therefore, the single-bit measurement 826 should accurately indicate whether Va>Vb or Vb>Va.

[0179] The second technique used for the PUF coarse readout mode is called the 'pre-bias technique'. In the pre-bias technique, the sampling capacitor of the preamplifier 810 is pre-biased to a common voltage before the Va-Vb comparison. In this example, this is implemented using a ramp generator 805, but this can alternatively be achieved by coupling the input of comparator 812 to any suitable reference voltage. The ramp generator 805 is controlled, for example, by setting the DAC in the ramp generator 805 to its neutral voltage to output a common voltage (e.g., the same voltage) on both of its output lines. First, the auto-zero switch controlled by signals AZ1 and AZ2 is closed and the coupling switch controlled by signals SW0 and SW1 is opened. Then, the coupling switch controlled by SW1 is closed to couple the ramp generator 805 to the input of the preamplifier 810, thereby pre-biasing the sampling capacitor of the preamplifier 810. Next, comparator 812 is coupled to PUF cell 105 by closing a switch controlled by signal SW0 (e.g., depending on the state of chopper circuit 710, Va can be coupled to C1a and Vb to C1b, or Vb can be coupled to C1a and Va to C1b). Finally, the auto-zero switch is turned off by control signals AZ1 and AZ2 (simultaneously or at a slightly offset time). At this point, the input to comparator stage 815 will include a component equal to (Va-Vb). Auto-zeroing preamplifier 810 should reduce or eliminate residual offset in preamplifier 810, and therefore should reduce or eliminate systematic error in the signal at the input of comparator stage 815. Thus, single-bit measurement 826 should accurately indicate whether Va>Vb or Vb>Va.

[0180] In both of these techniques used for coarse PUF measurement modes, the readout unit 620 is operated to perform a coarse 1-bit digital conversion on Va-Vb, indicating whether Va-Vb is greater than or less than 0 (e.g., indicating which of Va and Vb is larger). Therefore, the measurement of Va-Vb that can be used to generate the PUF value can be read very quickly (on the order of a microscopic fragment, e.g., within about 10 µs).

[0181] In an alternative example of the coarse measurement mode, see the previous reference. Figure 8B , Figure 9B or Figure 10B The readout unit 620 is operated as described in either of the above, but only conversion 1 is performed. The count values ​​825 and 1025A at the end of conversion 1 will indicate Va-Vb (as previously explained), but will also include some system offset components that make it less accurate than the fine measurement operating mode. Furthermore, the count values ​​825 and 1025A will include fewer bits than the final digital measure of Va-Vb obtained from the PUF fine measurement mode (e.g., it could be 7 bits, while the final digital measure obtained from the PUF fine measurement mode could be 8 bits). However, for some uses / applications of the PUF device 100, and especially in cases where self-registration has been performed, the accuracy may still be sufficient such that any inaccuracy in the measurement should be less than the registration stability threshold, such that the inaccuracy should not cause the PUF value generated by the coarse measurement based on Va-Vb to become unstable (e.g., not persistent).

[0182] In all the examples of the PUF coarse measurement mode described above, the digital measurement of Va-Vb has greater resolution (i.e., more bits) when operating in the PUF fine measurement mode compared to the coarse measurement mode. Alternatively, the coarse and fine measurement modes can each produce digital measurements of Va-Vb with the same number of bits, but the readout unit 620 can be operated to consume less power in the coarse measurement mode than in the fine measurement mode. For example, the bias current of comparator 812 can be reduced in the coarse measurement mode, and / or the auto-zero time can be shortened in the coarse measurement mode, and / or the sampling time can be shortened in the coarse measurement mode.

[0183] Dynamic random number mode

[0184] As previously referenced Figure 6 As explained, the PUF device 100 may optionally be configured to include one or more RNG cells 605. x This is used to generate dynamic random numbers (e.g., random numbers that are substantially equal in probability of being any of their multiple possible values ​​each time they are generated). The PUF device 100 can be configured to operate in a dynamic random number mode, in which the readout unit 620 reads from the RNG cell 605. x Read the value and use it to generate dynamic random numbers. For example, in... Figure 6 As can be seen, for example, the PUF device 100 can be configured to cause the readout unit 620 to... x Coupled to one or more PUF cells 105 x,y and RNG Cell 605 x (Or, in alternative implementations, coupled to more than one RNG cell). Although Figure 6 It was not stated in the text, but it will be understood that this can be achieved by controlling it within the cell (e.g. Figure 5B The output of each of the cells (as shown) and the output of the cell go to the readout unit 620 x The switch between the two signal lines is used to read the unit 620. x It can be coupled or decoupled from any of the cells in the column (e.g., readout unit 6201 can be coupled or decoupled from any of the cells in column 1). Alternatively, there may not be any switch of that type, but the cell can be configured such that when selection unit 610 is not selected and stimulates / activates the cell, it is coupled or decoupled from readout unit 620. x Effective isolation. In this way, selection unit 610 can select only one cell in each column at any given time, allowing readout unit 620 to... x Only read the signal output from this cell.

[0185] When operating in dynamic random number mode, selection unit 610 can control one or more RNG cells 605 in a manner similar to that previously described regarding the selection of PUF cells. x (It can also be referred to as one or more noise sources because it is configured to output a first noise signal and a second noise signal, as described later.) For example, selection unit 610 can use the RNG_ROW_SELECT signal to select RNG cell 605. x The row is selected and the PUF_ROW_SELECT signal is used to deselect all PUF cells 105. x,y This makes the readout unit 620 x Each of them is coupled to the corresponding RNG cell 605 x .

[0186] Each of the RNG cells 605x may include one or more components / circuits configured to generate an electrical signal with random components (e.g., noise), such as voltage. For example, each RNG cell 605 may include one or more switched capacitor circuits configured to generate and output a voltage signal including random kTC noise.

[0187] Figure 13A An example representation of an RC filter circuit is shown to help illustrate the kTC noise that can be generated by a capacitor. The RC filter circuit has a resistor R and a capacitor C, and the thermal noise v in the signal VOUT is... n This can be expressed as:

[0188]

[0189] in

[0190] T = Temperature

[0191] k B = Boltzmann constant

[0192] Thermal noise v n This is commonly referred to as kTC noise, which is also the case in the remainder of this disclosure for thermal noise v. n The term "kTC noise" is used to describe noise that is random and follows a Gaussian distribution. σ is a Gaussian distribution.

[0193] In the example, at a temperature of 27°C (300K), the kTC noise of capacitor C will be:

[0194]

[0195] Figure 13B An example representation of a basic switched capacitor layout for generating kTC noise is shown. This switch SW can be modeled as a varying resistor depending on its state. The kTC noise generated by this circuit is related to... Figure 13A The noise in the RC filter circuit shown is the same. When the switch changes from the ON (i.e., closed) state to the OFF (i.e., open) state, kTC noise is injected into the capacitor C. Therefore, changing the state of switch SW from the OFF state to the OFF state can be regarded as generating the capacitor voltage VOUT, which includes kTC noise.

[0196] Figure 14A An example specific implementation of a noise generator circuit 1400 is shown. The noise generator circuit 1400 includes a switch 1410 and a capacitor 3140 and is configured such that when the state of the switch 1410 changes from closed to open, a bias voltage V is applied to the capacitor 1420. BIAS Sampling is performed on the kTC noise. Bias voltage V BIAS It can be set to any voltage, including positive voltage, negative voltage, or 0V. Switch 1410 can be any suitable type of controllable switch, such as a transistor, like a MOS transistor, which can be set according to V... BIAS The voltage level is either p-type or n-type. The noise generator circuit 1400 further includes components configured to buffer the capacitor voltage V. C A buffer 1430 is used to generate a buffer voltage 1415. The buffer can be of any suitable type, such as a source follower.

[0197] Figure 14B Another example implementation of the noise generator circuit 1400 is shown. The noise generator circuit 1400 has the same characteristics as... Figure 14A The design shown is the same, but the noise generator circuit 1400 has a different type of buffer 1440. In this example, buffer 1440 is a differential amplifier with negative feedback and can be any suitable type, such as an operational amplifier. Both buffers 1430 and 1440 provide the function of isolating the low-capacitance circuit located before the buffer from the potentially relatively high input capacitance at the input of the readout unit 620. Therefore, this helps to maintain a small capacitance used to generate kTC noise, thereby increasing the magnitude of the generated kTC noise. Furthermore, both buffers 1430 and 1440 provide the ability to increase the drive strength of the kTC noise signal (i.e., the drive strength of the buffer voltage 1415 is greater than the capacitor voltage V). C This functionality makes it easier for the determination unit 170 to use kTC noise when generating random numbers. The main difference between the two buffers 1430 and 1440 is that buffer 1430 can have a larger offset voltage than buffer 1440, but this offset voltage should be largely or completely eliminated by double sampling of capacitor 1420 and by the operation of readout unit 620, as described later.

[0198] Figure 14C and Figure 14D Other example implementations of the noise generator circuit 1400 are shown. Figure 14C In the specific implementation, a single-ended amplifier 1450 is used (any suitable type of single-ended amplifier, such as a simple single-stage common-source amplifier). In Figure 14D In specific implementations, a differential amplifier 1440 is used. In two specific implementations, the noise generator circuit 1400 is configured such that the buffered output voltage 1415 is a gain version of the capacitor voltage (which includes kTC noise), wherein the gain is equivalent to the ratio of the input capacitance of amplifiers 1440 / 1450 to the capacitance of capacitor 1420.

[0199] Figure 14E , Figure 14F and Figure 14G Other example implementations of the noise generator circuit 1400 are shown. These implementations are very similar to... Figure 14C and Figure 14D These embodiments include, but also include, an additional capacitor 1460, which has a relatively large capacitance compared to the capacitor 1420 used for kTC noise generation. In all three embodiments, the noise generator circuit 1400 is configured such that the buffered output voltage 1415 is a gained version of the capacitor voltage (which includes kTC noise), where the gain corresponds to the ratio of the capacitance of capacitor 1460 to the capacitance of capacitor 1420.

[0200] All Figure 14A , Figure 14B , Figure 14D , Figure 14E , Figure 14F and Figure 14G The voltages shown are all relative to ground, but the circuit may alternatively be configured to use any other suitable reference voltage.

[0201] Figure 15 An example diagram is shown that can generate dynamic random numbers.

[0202] In step S1510, at a first time point, the noise generator circuit 1400 generates a first capacitor voltage across capacitor 1420, wherein the first capacitor voltage includes a first kTC noise. A first buffered voltage, as a buffered version of the first capacitor voltage, is output from the noise generator circuit 1400. The noise generator circuit 1400 can be controlled to change the state of switch 1410 from a closed state to an open state. This control can be implemented, for example, via selection unit 610, for example, by transmitting control signals through one or more RNG_ROW_SELECT control lines. Selection unit 610 or other control unit can take any suitable form that a person skilled in the art will well understand; for example, selection unit 610 can be implemented by dedicated circuitry / logic, or an FPGA, or a microcontroller or processor, or any other type of logic configured to control the state of switch 1410.

[0203] In step S1520, the readout circuit 620 reads the first buffer voltage from the noise generator circuit 1400. As explained in more detail below, this first buffer voltage may be sampled by the readout unit 620 or otherwise held / stored by the determination unit 170 for later use in generating random numbers.

[0204] In step S1530, at a second time point following the first time point, the noise generator circuit 1400 generates a second capacitor voltage across capacitor 1420, wherein the second capacitor voltage includes the second kTC noise. A second buffered voltage, as a buffered version of the second capacitor voltage, is output from the noise generator circuit 1400. This can be done by first returning the state of switch 1410 to the closed state and then changing the state of switch 1410 from the closed state to the open state at the second time point. Furthermore, this control can be implemented in any suitable manner, as explained above.

[0205] In step S1540, the readout unit 620 reads the second buffer voltage from the noise generator circuit 1400. As explained in more detail below, this second buffer voltage may be sampled by the readout unit 620 or otherwise held / stored by the determination unit 170 for later use in generating random numbers.

[0206] In step S1550, random numbers can be generated based on the first buffer voltage and the second buffer voltage.

[0207] Figure 16A The noise source, or RNG cell 605, is shown. x,y A specific implementation of the readout unit 620 is provided to demonstrate how dynamic random numbers can be generated using the previously described readout unit 620. In this example, the comparator 812 has a single gain stage 910, but it may alternatively include multiple gain stages, such as two or more gain stages (e.g., as shown in the example). Figure 12A (As shown in the diagram). The switch controlled by signals SW1 and OP remains open throughout the generation of dynamic random numbers; therefore, for simplicity, the ramp generator 805, counter 820 / 1020, and the switch controlled by SW1 and OP are all omitted in this diagram. In this example, the noise source (RNG cell 605) x,y This includes two noise generator circuits: a first noise generator circuit 14001 and a second noise generator circuit 14002. The first and second noise generator circuits may have the same design and may be implemented in either of the previously described methods, for example... Figures 14A to 14G As shown in the image. Refer to the reference above. Figure 15 In the described process, at a first time point in step S1510, by controlling the corresponding capacitor switch (e.g., using control signal SW2, which will be described in more detail later), the first noise generator circuit 14101 can generate a first capacitor voltage (wherein the first capacitor voltage includes first kTC noise) on its capacitor 14201, and the second noise generator circuit 14102 can generate a third capacitor voltage (wherein the third capacitor voltage includes third kTC noise) on its capacitor 14202. A first buffer voltage Va is output from the first noise generator circuit 14101 and a third buffer voltage Vb is output from the second noise generator circuit 14102, causing the noise source to output a first noise signal and a second noise signal. These two buffer voltage signals together form a first differential signal. The term "differential" as used in this disclosure includes true differential or full differential (where the signals constituting the differential signal are generated by a single structure centered on a common mode voltage) and pseudo-differential (where each of the two signals constituting the differential signal is generated by a differential structure that does not necessarily center on a common mode voltage, but where the two structures are designed to have the same DC bias, as... Figure 16A (The situation is the same in the example) Both.

[0208] In step S1520, the readout unit 620 reads the first differential signal from the first noise generator circuit and the second noise generator circuit, and samples the first differential signal using the sampling capacitor of the preamplifier 810.

[0209] In step S1530, at a second time point following the first time point, by controlling the corresponding capacitor switches, the first noise generator circuit 14001 generates a second capacitor voltage (wherein the second capacitor voltage includes second kTC noise) on its capacitor 14201, and the second noise generator circuit 14002 generates a fourth capacitor voltage (wherein the fourth capacitor voltage includes fourth kTC noise) on its capacitor 14202, as previously described. A second buffer voltage Va is output from the first noise generator circuit 14001, and a fourth buffer voltage Vb is output from the second noise generator circuit 14002. These two buffer voltage signals together form a second differential signal.

[0210] In step S1540, the readout unit 620 reads the second differential signal from the first noise generator circuit and the second noise generator circuit, and compares it with the previously sampled first differential signal (explained in more detail later).

[0211] In step S1550, the readout unit 620 outputs a random number in the form of a single-bit value 826, which is a measure of the difference between the first differential signal and the second differential signal. In other words, the output of the comparator 812 is a coarse conversion or quantization of the difference between the first and second differential signals, and indicates the sign of the difference (e.g., whether the first differential signal is greater than or less than the second differential signal). Since both the first and second differential signals should be random and centered on the same common voltage, the probability that their difference is positive or negative should be approximately equal, making the measurement 826 a 1-bit dynamic random number.

[0212] Figure 16B Example specific implementations of the first noise generator 14001 and the second noise generator 14002 are shown, but it will be understood that for each noise generator, any other suitable configuration in which a capacitor voltage including kTC noise and a buffered signal output can be used (e.g. Figures 14A to 14F The noise generator can be any of the specific implementations thereof, or any other suitable implementation thereof, or any other suitable type of circuit actually configured to generate and output a noise signal. Switches 1410 of each of the noise generators are implemented using FETs, the state of which is controlled by a control signal SW. Buffers for each of the noise generators are implemented using corresponding current sources I1 and I2 and corresponding FETs MP1 and MP2. The difference in the components of each of the noise generators can cause a buffer voltage V. A and V B The presence of unwanted signal components may reduce the effectiveness of the buffer voltage V. A and V B The randomness of the generated numbers. For example, each of the generated capacitor voltages may have a slightly different DC offset due to the difference between switches 14101 and 14102 and / or the difference between capacitors 14201 and 14202, which will carry over to the buffered output voltage V. A and V B Additionally or alternatively, each of the buffers may have a different offset due to component differences, which will result in the buffered output voltage V A With V B There is an offset between them. However, since the differential signal at the first time point (the first differential signal) is compared with the differential signal at the signal time point (the second differential signal) to generate random numbers, and each of those differential signals should have the same or very similar offset components, those unwanted signals can be significantly reduced or completely eliminated, leaving only kTC noise for random number generation.

[0213] exist Figure 16A and Figure 16B In the diagram, the two noise generation circuits 14001 and 14002 are represented as differential structures that do not necessarily center on the common-mode voltage, so that the signal V A and V B Together they form a pseudo-differential signal. However, it can alternatively be configured such that signal V A and V B Together, they form a true / fully differential signal. For example, instead of using a separate buffer for each kTC capacitor 1420, a single differential buffer can be used, such that the capacitor voltage (including kTC noise) of each of capacitors 14201 and 14202 is received at the corresponding input of the differential buffer. Those skilled in the art will readily understand the various types of suitable differential buffers that can be used. In this case, the first noise generator circuit and the second noise generator circuit can be considered together as including the first capacitor 14201 and the second capacitor 14202, and the differential buffer configured to output a differential signal based on the capacitor voltages of the first capacitor 14201 and the second capacitor 14202.

[0214] Figure 16C A timing diagram illustrating example operation of the PUF device 100 when operating in dynamic random number mode is shown. Throughout operation, the switch controlled by SW0 can be closed, and the switch controlled by signals SW1 and OP can be opened. Furthermore, the chopper circuit 710 is not used during operation, so the chopper control signal remains constant throughout. First, in step S1510, in the auto-zero state, the auto-zero switch AZ1 is closed, and the switches of noise generators 14001 and 14002 are closed to couple the first buffered differential signal to the auto-zero preamplifier. At step S1520, the switch signal SW3 then goes low, causing the first buffered differential signal to be sampled through capacitors C1a and C1b. Figure 16C The example differential signal V is shown in the figure. A and V B And vin1 and vin2. It will be understood that these are only one example, and their magnitudes and relative polarities may vary depending on the kTC noise of the signal output by the noise generator circuit. The sampled first differential signal includes the difference between the kTC noise generated by the first noise generator circuit 14001 and the kTC noise generated by the second noise generator circuit 14002 during the first switching event of the noise generator capacitor, and any DC offset between the two signals constituting the differential signal (e.g., caused by one or more of low-frequency noise, offset of the drive voltage of the noise generator circuit, offset caused by the buffer of the noise generator circuit, etc.).

[0215] Subsequently, the automatic zeroing state is ended by disconnecting the automatic zeroing switch AZ1. In steps S1530 and S1540, the noise generator circuit is reset by closing and then subsequently opening the switch controlled by signal SW3, causing a second switching event to occur in the noise generator circuit to generate new kTC noise in its capacitor, and outputting a second buffered differential voltage from the noise generator circuit. The second buffered differential voltage includes the difference between the kTC noise generated by the first noise generator circuit 14001 and the kTC noise generated by the second noise generator circuit 14002 during the second switching event of the noise generator capacitor, and any DC offset between the two signals constituting the differential signal. The second buffered differential signal is sampled onto capacitors C1a and C1b. Therefore, since both the first and second buffered differential signals are sampled onto capacitors C1a and C1b without any reset of capacitors C1a and C1b, and the two sampled signals include the same (or substantially the same) DC component, the differential signal at the input of comparator stage 815 represents an amplified version of the difference between the first and second buffered differential voltages. Thus, the signal at the input of comparator stage 815 includes the difference between the differential voltage of the kTC noise generated by the first noise generator circuit 14001 and the second noise generator circuit 14002 in the first switching event and the differential voltage of the kTC noise generated by the first noise generator circuit 14001 and the second noise generator circuit 14002 in the second switching event. The output of comparator stage 815 indicates the polarity of the differential signal at its input, which in turn indicates whether the combined kTC noise generated by the first noise generator 14001 through its two switched capacitor kTC events is greater than or less than the combined kTC noise generated by the second noise generator 14002 through its two switched capacitor kTC events. Therefore, the output of comparator 812 will be randomly 0 or 1. Optionally, at step S450, comparator stage 815 can be latched such that its output Comp_out is stored at the output. In this case, the latched value of Comp_out is measurement 826, which is also a 1-bit random number 125.

[0216] By performing automatic zeroing in this manner, the residual offset of the preamplifier and the offset voltage between the two buffers of the two noise generation circuits can be significantly reduced. This helps to reduce any bias in the random number, thereby improving the randomness of the number. In addition, automatic zeroing in this manner also helps to reduce 1 / f noise in the signal at the input of comparator 815.

[0217] exist Figures 16A to 16C In the example, by considering the differential voltage signal consisting of the outputs of two identical noise-generating circuits, signal V A and V B At least some of the DC components in the differential signal should be canceled out, such that any offset between the differential signal, including the kTC noise, and the buffer of the noise generator circuit (which is then eliminated by determining a random number based on two kTC noise events from each of the noise generator circuits, i.e., by determining a random number using the first differential signal and the second differential signal).

[0218] Alternatively, comparator stage 815 may not be configured to latch, such that its output is set only based on a comparison of its input voltage at that time. Additionally or alternatively, a set / reset (SR) latch may be present at the output of comparator 812 to store the output value of comparator 812 (or alternatively, the output value may be stored in any other suitable manner, such as using memory). Furthermore, the output of comparator stage 815 may be single-ended or differential, as previously explained.

[0219] It will be understood that it can be achieved through having Figure 6 The multiple readout units 520x and multiple RNG cells 605x, as shown in the diagram, are used to generate multi-bit dynamic random numbers. The readout unit 625x can be operated as described above, such that each measurement 625x output by the readout unit 620x... x These are single bits 826x with random values, each of which is used as a bit in a multi-bit dynamic random number. Therefore, the readout unit 6201, used to read signals from PUF cell 105 when the device operates in PUF mode, can also be used to read signals from RNG cell 605 when the device operates in dynamic random number mode. Thus, the device 100 can also have dynamic random number generation functionality without requiring any additional readout circuitry simply by including one or more noise sources (RNG cell 605) within it and operating it as described above. Since both dynamic random number generation and PUF output generation are highly useful for device and / or data security, it is highly advantageous to have a device 100 capable of performing both functions with very limited additional components and size cost.

[0220] Another benefit associated with dynamic random number generation is enhanced protection against third-party attacks on PUF devices, such as side-channel attacks. For example, a third party might attempt to influence the device to generate dynamic random numbers of a third party's choice instead of genuine dynamic random numbers. In one example, a third party might attempt to alter the operation of the PUF device so that its output is all 0s or all 1s of dynamic random numbers. This could be done by modifying the PUF device's power supply level and / or focusing EM waves of a specific frequency, such as laser beams, onto the PUF device. Such side-channel attacks typically aim to alter the operation of the readout circuitry to generate specific dynamic random numbers desired by the third party. This makes cryptographic operations performed using dynamic random numbers (e.g., hashing / hiding sensitive private keys such as PUF outputs) predictable, potentially exposing the private key. However, the way an attack on a PUF device affects dynamic random number generation should also affect the PUF outputs generated by the device. For example, if a third party influences the readout circuitry so that the system's readouts are all 0s or all 1s, any PUF outputs generated by the readout circuitry will also be all 0s or all 1s. Therefore, even if a third party successfully attacks the dynamic random number generator to invalidate the cryptographic operations performed on the PUF output and expose the PUF output, the PUF output should be incorrect anyway, so the third party will not learn anything useful.

[0221] For this reason, the PUF device can be optionally configured to periodically or intermittently switch between dynamic random number mode and PUF generation mode, rendering side-channel attacks ineffective. The PUF device can be configured to make it difficult to predict when it will switch between the two modes, for example, by switching intermittently based on the time since the last dynamic random number or the number of PUF outputs generated. This makes it more difficult for a third party to terminate their attack when the device may switch to PUF generation mode. Additionally or alternatively, the PUF device can be configured so that there is no dedicated RNG line, but rather RNG cells 605x can be interspersed within the PUF cell lines. In this way, whenever a PUF line is selected and read, that line will include RNG cells 605x, making attacks on the device designed to influence dynamic random numbers inevitably affect the PUF output as well. Alternatively, the selection unit 610 can be configured to select cells cell by cell rather than column by column, and for each read operation, it can be configured to select several RNG cells 605x and several PUF cells 105, so that PUF values ​​and dynamic random values ​​are generated again for each read operation.

[0222] In summary, the PUF device 100 disclosed herein can be controlled to operate in at least two different modes, including: a coarse PUF measurement mode; a fine PUF measurement mode; a PUF self-test mode; and a dynamic random number mode. Therefore, a single readout unit / circuit can be used to operate the PUF device 100 in a variety of different ways. This means that the PUF device 100 can operate very flexibly throughout its lifespan without incurring additional component and space costs, as well as complexity.

[0223] In another alternative implementation, the PUF device 100 may be configured to operate only in one of these modes. For example, operation in the fine measurement mode significantly improves the accuracy of Va-Vb measurements. This means that the accuracy of any subsequent processes using Va-Vb measurements (e.g., using Va-Vb to generate PUF values, or using Va-Vb to perform registration and / or health checks) should also be improved. Therefore, it should still be beneficial to implement a PUF device that can measure Va-Vb only in the manner described above with reference to the fine measurement mode.

[0224] Those skilled in the art will readily understand that various changes or modifications can be made to the aspects of this disclosure described above without departing from the scope of this disclosure.

[0225] For example, a PUF device 100 is shown having a plurality of PUF cells, each having a pair of matched devices (which may each have a single component or multiple components arranged together to form a complex device, such as an oscillator or a string of logic gates). One or more PUF cells may be referred to together as a PUF source, which is configured to output a first signal (e.g., a first voltage) and a second voltage (e.g., a second voltage) indicating a random manufacturing difference between the components within the PUF source. However, instead of having one or more PUF cells, the PUF device 100 may have a PUF source comprising multiple pairs of reconfigurable matched devices. For example, if three matched transistors are present, the first two transistors may represent a first pair, the last two transistors may represent a second pair, and the first transistor and the third transistor may represent a third pair. A determination unit 170 may be configured to select which devices constitute a matched pair at a specific time, and then a readout unit 520 uses the selected pairs to generate a PUF value, or as referenced herein. Figures 6 to 1 Either of the methods described in 2 shall perform self-registration on the selected pair.

[0226] Furthermore, it does not have multiple PUF cells 105 configured as a matrix, and multiple readout units 620, such as Figure 5B and Figure 6 As shown, the PUF device 100 may include a single readout unit 620 and multiple PUF cells (or multiple pairs of devices arranged differently from PUF cells, such as those described above), wherein each of the PUF cells 105 is serially read by the readout unit 620 to produce a multi-bit PUF output. Alternatively, multiple readout units 620 may be present, and the number of readout units may be the same as the number of PUF cells 105.

[0227] Although the signals output from PUF cell 105 and RNG cell 605 are voltage signals Va and Vb in the above disclosure, the PUF device can 100 alternatively be configured such that PUF cell 105 and RNG cell 605 output different types of signals, such as current signals or charge signals. In this case, the readout unit 620 can be configured to determine a measure of the difference between the two signals it receives.

[0228] The term "coupled" as used above encompasses both direct electrical connections between two components and indirect electrical connections between two components via one or more intermediate components.

[0229] While in the specific example described above, the readout unit 620 may be configured to function as a slope converter when the PUF device 100 operates in PUF fine measurement mode or PUF self-test mode, in alternatives, the readout unit 620 may include the circuitry and components required for use as a SAR converter rather than a slope converter. The operation of a SAR converter will be readily understood by those skilled in the art, and therefore will not be described further. When implemented as a SAR converter, instead of having a ramp generator 805 and a counter 820, the PUF device 100 may have a DAC and a SAR controller (such as a counter that outputs digital values ​​to the DAC), where the ADC is formed by the DAC, the SAR controller, and the comparator 812. In this case, when operating in PUF fine measurement mode or PUF self-test mode, the PUF device may be configured to couple the DAC output to the input of the comparator 812 and operate the SAR controller such that a multi-bit digital measurement of Va-Vb is determined by the SAR ADC. When operating in PUF coarse measurement mode or dynamic random number mode, the DAC can be decoupled from the input of comparator 812 (e.g., by controlling a switch that couples / decouples the DAC output from the input of comparator 812), and the SAR controller and DAC can be turned off. The readout unit can then be operated exactly as described above with reference to Figures 12 and 16.

[0230] All aspects of this disclosure

[0231] Examples of this disclosure are stated in the following non-restrictive clauses:

[0232] Clause 1: A Physically Unclonable Function (PUF) device, the PUF device comprising: a PUF source for outputting a first signal and a second signal, wherein the difference between the first signal and the second signal indicates a random manufacturing difference between components in the PUF source; and an analog-to-digital converter (ADC) for coupling to the PUF source; wherein the PUF device is configured to operate in a plurality of different modes, the plurality of different modes including at least a PUF coarse measurement mode and a PUF fine measurement mode, and wherein when operating in the PUF coarse measurement mode and when operating in the PUF fine measurement mode, the PUF device is configured to: use the ADC to generate a digital measurement, the digital measurement being a measure of the difference between the first signal and the second signal; and use the digital measurement to generate a PUF value, and wherein when the PUF device operates in the PUF fine measurement mode, the digital measurement has a greater resolution than when operating in the PUF coarse measurement mode.

[0233] Clause 2: The PUF device according to Clause 1, wherein when operating in the PUF fine measurement mode, the digital measurement is a multi-bit value indicating the sign and magnitude of the difference between the first signal and the second signal.

[0234] Clause 3: The PUF device according to Clause 1 or 2, wherein when operating in the PUF coarse measurement mode, the digital measurement is a single-bit value indicating the sign of the difference between the first signal and the second signal.

[0235] Clause 4: The PUF device according to any one of Clauses 1 to 3, wherein the ADC includes a comparator for use in the PUF coarse measurement mode and the PUF fine measurement mode to generate the digital measurement.

[0236] Clause 5: The PUF device according to any one of Clauses 1 to 4, wherein when operating in the PUF coarse measurement mode, the ADC is configured to function as a single-bit quantizer for setting the value of a single bit based on the relative magnitudes of the first signal and the second signal.

[0237] Clause 6: A PUF device according to any one of Clauses 1 to 5, wherein when operating in the PUF fine measurement mode, the PUF device is configured to: perform a first digital conversion using the ADC to generate a first digital value indicating the difference between the first signal and the second signal; perform a second digital conversion using the ADC to generate a second digital value indicating the difference between the second signal and the first signal; and use the first digital value and the second digital value to generate the digital measurement.

[0238] Clause 7: The PUF device according to Clause 6, wherein the digital measurement is generated by combining the first digital value and the second digital value such that the systematic error components of the first digital value and the second digital value are reduced or substantially canceled out.

[0239] Clause 8: The PUF device according to Clause 6 or Clause 7, the PUF device further includes a chopper circuit coupled to a first input and a second input of the ADC, wherein the first digital conversion is performed using the first chopper circuit that couples the first signal to the first input of the ADC and the second signal to the second input of the ADC, and wherein the second digital conversion is performed using the chopper circuit that couples the first signal to the second input of the ADC and the second signal to the first input of the ADC.

[0240] Clause 9: A PUF device according to any one of Clauses 1 to 8, wherein the ADC comprises: a ramp generator configured to generate at least one ramp signal that increases or decreases over time; and a comparator whose two inputs form a first input and a second input of the ADC, wherein when operating in the PUF fine measurement mode, the ADC is configured to function as a ramp ADC and the at least one ramp signal is applied to at least one of the comparator inputs.

[0241] Clause 10: The PUF device according to Clause 9, wherein the at least one ramp signal comprises: a ramp-up signal that increases from a lower value to a higher value over a period of time; and a ramp-down signal that decreases from the higher value to the lower value over the period of time, wherein when operating in the PUF fine measurement mode, the ramp-up signal is applied to one of the comparator inputs and the ramp-down signal is applied to the other of the comparator inputs.

[0242] Clause 11: The PUF device according to Clause 9 or Clause 10, wherein when operating in the fine measurement mode: the PUF source is further configured to output a third signal and a fourth signal, wherein the difference between the third signal and the fourth signal indicates a random manufacturing difference between other components in the PUF source, and the PUF device further includes another ADC coupled to the PUF source to receive the third signal and the fourth signal, wherein the other ADC includes: a ramp generator; and another comparator coupled to the ramp generator for applying the at least one ramp signal to at least one input of the other comparator, wherein the other ADC is configured to function as a ramp ADC in parallel with the ADC and to produce another digital measurement that is a measure of the difference between the third signal and the fourth signal.

[0243] Clause 12: A PUF device according to any one of Clauses 9 to 11, wherein when operating in the PUF fine measurement mode, the PUF device is configured to: perform a first digital conversion using the ADC to generate a first digital value; perform a second digital conversion using the ADC to generate a second digital value; and generate the digital measurement using the first digital value and the second digital value.

[0244] Clause 13: The PUF device according to Clause 12, wherein the difference between the higher value and the lower value is the full amplitude of the ramp generator, and wherein one of the first digital value and the second digital value is a measure of the difference between the first signal and the second signal, the measure being equal to the full amplitude of the ramp generator minus a measure of the difference between the second signal and the first signal.

[0245] Clause 14: The PUF device according to Clause 13, wherein the digital measurement is generated by summing the first digital value and the second digital value, such that the digital measurement indicates the full amplitude of the ramp generator plus twice the difference between the first signal and the second signal.

[0246] Clause 15: A PUF device according to any one of Clauses 9 to 14, wherein the ADC further includes a counter, and wherein when operating in a PUF fine measurement mode: the ramp generator receives a clock signal to generate the at least one ramp signal, and the counter counts the clock signal when the output of the comparator is a specific value, wherein the digital measurement is generated using the count of the counter.

[0247] Clause 16: The PUF device according to Clause 15, when attached to any one of Clauses 12 to 14, wherein the first digital value corresponds to the number of clock cycles counted by the counter during the first digital conversion, and the second digital value corresponds to the number of clock cycles counted by the counter during the second digital conversion.

[0248] Clause 17: The PUF device according to Clause 16, wherein the counter is configured to count the clock signal during a first digital conversion when the output of the comparator is a first value, and during a second digital conversion when the output of the comparator is a second value.

[0249] Clause 18: The PUF device according to Clause 16 or Clause 17, wherein the ADC is configured to generate the digital measurement by operating the counter to cumulatively count between the first digital conversion and the second digital conversion, wherein the count value at the end of the second digital conversion is the digital measurement.

[0250] Clause 19: A PUF device according to any one of Clauses 15 to 18, wherein the counter is a praise counter comprising a first counter and a second counter, wherein when the PUF device is operating in PUF fine measurement mode, during digital conversion, the second counter is configured to count the clock signal whenever the first counter does not count the clock signal.

[0251] Clause 20: A PUF device according to any one of Clauses 1 to 19, wherein the PUF source comprises a plurality of PUF cells, wherein each PUF cell comprises a pair of devices, and when operating in the PUF coarse measurement mode or the PUF fine measurement mode, the PUF cell is configured to output a corresponding first signal and a second signal indicating a random manufacturing difference between the pair of devices.

[0252] Clause 21: The PUF device according to Clause 20, wherein the ADC is selectively coupled to either a first PUF cell or a second PUF cell among the plurality of PUF cells, such that when the ADC is coupled to the first PUF cell, the digital measurement is a measure of the difference between the first signal and the second signal output by the first PUF cell, and when the ADC is coupled to the second PUF cell, the digital measurement is a measure of the difference between the first signal and the second signal output by the second PUF cell.

[0253] Clause 22: The PUF device according to Clause 20, wherein the ADC is coupled to a third PUF cell among the plurality of PUF cells and the digital measurement is a measure of the difference between the first signal and the second signal output by the third PUF cell, and wherein the PUF device further includes another ADC coupled to a fourth PUF cell among the plurality of PUF cells and configured to generate another digital measurement, the other digital measurement being a measure of the difference between the first signal and the second signal output by the fourth PUF cell, and wherein the ADC and the other ADC are configured to operate in parallel.

[0254] Clause 23: The PUF device according to any one of Clauses 1 to 22, the PUF device further comprising a noise source for outputting a first noise signal and a second noise signal, wherein the ADC is configured to be selectively coupled to either the noise source or the PUF source, wherein the multiple different modes further include a dynamic random number mode, and wherein when operating in the dynamic random number mode, the PUF device is configured to: use the ADC to generate dynamic random numbers using the first noise signal and the second noise signal.

[0255] Clause 24: The PUF device according to Clause 23, wherein the ADC includes a comparator, and wherein when operating in the dynamic random number mode, the ADC is configured to use the comparator to generate the dynamic random number; and wherein when operating in the PUF coarse measurement mode and when operating in the PUF fine measurement mode, the ADC is configured to use the comparator to generate the digital measurement.

[0256] Clause 25: The PUF device according to Clause 23 or Clause 24, wherein the PUF device further includes a selection circuit configured to: control the noise source to output the first noise signal and the second noise signal when the PUF device operates in the dynamic random number mode; and control the PUF source to output the first signal and the second signal when the PUF device operates in the PUF coarse measurement mode and when the PUF device operates in the PUF fine measurement mode.

[0257] Clause 26: A PUF device according to any one of Clauses 1 to 25, wherein the PUF source comprises a pair of devices, wherein the first signal and the second signal indicate a random manufacturing difference between the pair of devices, and wherein the multiple different modes further include a PUF self-test mode, and wherein when operating in the PUF self-test mode, the PUF device is configured to: use the ADC to generate the digital measurement, wherein the digital measurement indicates the magnitude of the difference between the first signal and the second signal; and determine whether the magnitude of the difference between the first signal and the second signal is greater than or less than a PUF stability threshold.

[0258] Clause 27: The PUF device according to Clause 26, wherein when operating in the PUF self-test mode, the PUF device is configured to record that the pair of devices is not suitable for generating PUF values ​​when the magnitude of the difference between the first signal and the second signal is less than the PUF stability threshold.

[0259] Clause 28: The PUF device according to Clause 26 or Clause 27, wherein when operating in the PUF self-test mode, the PUF device is configured to generate a status report based on whether the magnitude of the difference between the first signal and the second signal is greater than or less than a PUF stability threshold, wherein the status report indicates the likelihood that the PUF device will generate a persistent PUF output.

[0260] Clause 29: A PUF device according to any one of Clauses 26 to 28, wherein the ADC includes a praise counter, the praise counter including a first counter and a second counter, wherein the number counted by the first counter is equal to the sum of a first value indicating the sign and magnitude of the difference between the first signal and the second signal and an additional threshold count corresponding to the stability threshold; and wherein the number counted by the second counter is equal to the sum of a third value indicating the sign and magnitude of the difference between the second signal and the first signal and the additional threshold count, wherein if the number counted by the first counter has the same sign as the number counted by the second counter, then the magnitude of the difference between the first signal and the second signal is less than the PUF stability threshold, and wherein if the number counted by the first counter has a different sign than the number counted by the second counter, then the magnitude of the difference between the first signal and the second signal is greater than the PUF stability threshold.

[0261] Clause 30: A system comprising: a pair of matched electrical devices; a noise source configured to generate an electrical signal including random noise; and a determining circuit configured to, when the system operates in a Physically Unclonable Function (PUF) mode: use the pair of matched electrical devices to generate a first electrical signal indicating a random manufacturing difference between the pair of matched electrical devices; and generate a PUF value based on the first electrical signal, wherein the determining circuit is further configured to, when the system operates in a Dynamic Random Number (DRN) mode: use the noise source to generate a second electrical signal including random noise; and use the second electrical signal to generate a dynamic random number.

[0262] Clause 31: The system according to Clause 30, wherein the determining circuit includes a comparator for generating the PUF value when the system operates in the PUF mode and for generating the dynamic random number when the system operates in the dynamic random number mode.

[0263] Clause 32: The system according to Clause 31, wherein the determining circuit is configured to couple the input of the comparator to the pair of matched electrical devices when the system operates in the PUF mode, such that the comparator receives the first electrical signal; and wherein the determining circuit is configured to couple the input of the comparator to the noise source when the system operates in the dynamic random number mode, such that the preamplifier receives the second electrical signal.

[0264] Clause 33: A system according to any one of Clauses 30 to 32, wherein when the system operates in the PUF mode, the determining circuit is configured to determine a measure of the first electrical signal and use the measure of the first electrical signal to generate the PUF value, and wherein when the system operates in the dynamic random number mode, the determining circuit is configured to determine a measure of the second electrical signal and use the measure of the second electrical signal to generate the dynamic random number.

[0265] Clause 34: In the system according to Clause 33, the measure of the first electrical signal is a digital value indicating the sign of the first electrical signal, and the measure of the second electrical signal is a digital value indicating the sign of the second electrical signal.

[0266] Clause 35: A system according to any one of Clauses 30 to 34, wherein each electrical device constituting the pair of mating devices includes at least one electrical component.

[0267] Clause 36: A system according to any one of Clauses 30 to 35, wherein the first signal is a differential or pseudo-differential signal, and wherein the second signal is a differential or pseudo-differential signal.

[0268] Clause 37: A Physically Unclonable Function (PUF) system, the PUF system comprising: a pair of matched devices; and determining circuitry coupled to the pair of matched devices, wherein when the system operates in a registration mode, the determining circuitry is configured to: determine whether a magnitude of a random manufacturing difference between the pair of matched devices exceeds a stability threshold; if the magnitude of the random manufacturing difference exceeds the stability threshold, mark the pair of matched devices as suitable for generating PUF values; and if the magnitude of the random manufacturing difference is less than the stability threshold, mark the pair of matched devices as unsuitable for generating PUF values, and wherein when the system operates in a PUF mode and the pair of matched devices is marked as suitable for generating PUF values: determine a measure of the random manufacturing difference between the pair of matched devices; and use the measure of the random manufacturing difference between the pair of matched devices to generate the PUF values.

[0269] Clause 38: The PUF system according to Clause 37, wherein the determining circuitry includes a comparator for determining the magnitude of the random manufacturing difference when the system operates in the registration mode, and for determining the measure of the random manufacturing difference when the system operates in the PUF mode.

[0270] Clause 39: The PUF system according to Clause 37 or Clause 38 is configured to operate intermittently or periodically in the registration mode throughout the lifetime of the PUF system.

Claims

1. A physically unclonable function, PUF, device, the PUF device comprising: a PUF source, the PUF source to output a first signal and a second signal, wherein a difference between the first signal and the second signal is indicative of a random manufacturing difference between components in the PUF source; and an analog-to-digital converter, ADC, the ADC to be coupled to the PUF source; wherein the PUF device is configured to operate in a plurality of different modes, the plurality of different modes comprising at least a PUF coarse measurement mode and a PUF fine measurement mode, and wherein, when operating in the PUF coarse measurement mode and when operating in the PUF fine measurement mode, the PUF device is configured to: use the ADC to produce a digital measurement, the digital measurement being a measure of the difference between the first signal and the second signal; and use the digital measurement to produce a PUF value, and wherein, when the PUF device is operating in the PUF fine measurement mode, the digital measurement has a greater resolution than when operating in the PUF coarse measurement mode.

2. The PUF device of claim 1, wherein, when operating in the PUF fine measurement mode, the digital measurement is a multi-bit value indicative of a sign and a magnitude of the difference between the first signal and the second signal.

3. The PUF device of any preceding claim, wherein, when operating in the PUF coarse measurement mode, the digital measurement is a single-bit value indicative of a sign of the difference between the first signal and the second signal.

4. The PUF device of any preceding claim, wherein the ADC comprises a comparator, the comparator to be used in the PUF coarse measurement mode and the PUF fine measurement mode to produce the digital measurement.

5. The PUF device of any preceding claim, wherein, when operating in the PUF coarse measurement mode, the ADC is configured to function as a single-bit quantizer that sets a value of a single bit based on a relative size of the first signal and the second signal.

6. The PUF device of any preceding claim, wherein, when operating in the PUF fine measurement mode, the PUF device is configured to: perform a first digital conversion using the ADC to produce a first digital value indicative of a difference between the first signal and the second signal; perform a second digital conversion using the ADC to produce a second digital value indicative of a difference between the second signal and the first signal; and use the first digital value and the second digital value to produce the digital measurement.

7. The PUF device of claim 6, wherein the digital measurement is produced by combining the first digital value and the second digital value such that systematic error components of the first digital value and the second digital value are reduced or substantially cancelled out.

8. The PUF device of claim 6 or claim 7, the PUF device further comprising a chopping circuit coupled to a first input and a second input of the ADC, and wherein the first digital conversion is performed using the first chopper circuit that couples the first signal to the first input of the ADC and the second signal to the second input of the ADC, and wherein the second digital conversion is performed using the chopper circuit that couples the first signal to the second input of the ADC and the second signal to the first input of the ADC.

9. The PUF device of any preceding claim, wherein the ADC comprises: a ramp generator configured to generate at least one ramp signal that increases or decreases over time, and a comparator whose two inputs form the first and second inputs of the ADC, wherein when operating in the PUF fine measurement mode, the ADC is configured to function as a ramp ADC and the at least one ramp signal is applied to at least one of the comparator inputs.

10. The PUF device of any preceding claim, further comprising a noise source for outputting first and second noise signals, wherein the ADC is configured to selectively couple to either of the noise source and the PUF source, wherein the plurality of different modes further comprises a dynamic random number mode, and wherein when operating in the dynamic random number mode, the PUF device is configured to: use the ADC to generate a dynamic random number using the first and second noise signals.

11. The PUF device of claim 10, wherein the ADC comprises a comparator, and wherein when operating in the dynamic random number mode, the ADC is configured to use the comparator to generate the dynamic random number; and wherein when operating in the PUF coarse measurement mode and when operating in the PUF fine measurement mode, the ADC is configured to use the comparator to generate the digital measurement.

12. The PUF device of any preceding claim, wherein the PUF source comprises a pair of devices, wherein the first and second signals are indicative of a random manufacturing difference between the pair of devices, and wherein the plurality of different modes further comprises a PUF self-test mode, and wherein when operating in the PUF self-test mode, the PUF device is configured to: use the ADC to generate the digital measurement, wherein the digital measurement is indicative of a magnitude of the difference between the first and second signals; and determine whether the magnitude of the difference between the first and second signals is greater than or less than a PUF stability threshold.

13. A system, the system comprising: a pair of matched electrical devices; a noise source configured to generate electrical signals comprising random noise; and determination circuitry configured to, when the system is operating in a physical unclonable function (PUF) mode: use the pair of matched electrical devices to generate a first electrical signal indicative of a random manufacturing difference between the pair of matched electrical devices; and use the ADC to generate a second electrical signal indicative of a second random manufacturing difference between the pair of matched electrical devices. generating a PUF value based on the first electrical signal, and wherein the determination circuit is further configured to, when the system is operating in a dynamic random number mode: generate a second electrical signal comprising random noise using the noise source; and generate a dynamic random number using the second electrical signal.

14. The system of claim 13, wherein the determination circuit comprises a comparator for generating the PUF value when the system is operating in the PUF mode and for generating the dynamic random number when the system is operating in the dynamic random number mode.

15. The system of claim 14, wherein the determination circuit is configured to, when the system is operating in the PUF mode, couple inputs of the comparator to the pair of matched electrical devices such that the comparator receives the first electrical signal; and wherein the determination circuit is configured to, when the system is operating in the dynamic random number mode, couple the inputs of the comparator to the noise source such that the preamplifier receives the second electrical signal.

16. The system of any one of claims 13 to 15, wherein, when the system is operating in the PUF mode, the determination circuit is configured to determine a measure of the first electrical signal and to generate the PUF value using the measure of the first electrical signal, and wherein, when the system is operating in the dynamic random number mode, the determination circuit is configured to determine a measure of the second electrical signal and to generate the dynamic random number using the measure of the second electrical signal.

17. The system of claim 16, wherein the measure of the first electrical signal is a numerical value indicative of a sign of the first electrical signal, and wherein the measure of the second electrical signal is a numerical value indicative of a sign of the second electrical signal.

18. A physically unclonable function (PUF) system, the PUF system comprising: a pair of matched devices; and a determination circuit coupled to the pair of matched devices, wherein, when the system is operating in an enrollment mode, the determination circuit is configured to: determine whether a magnitude of a random manufacturing difference between the pair of matched devices exceeds a stability threshold; if the magnitude of the random manufacturing difference exceeds the stability threshold, label the pair of matched devices as suitable for generating PUF values; and if the magnitude of the random manufacturing difference is less than the stability threshold, label the pair of matched devices as unsuitable for generating PUF values, and wherein, when the system is operating in a PUF mode and the pair of matched devices is labeled as suitable for generating PUF values: determine a measure of the random manufacturing difference between the pair of matched devices; and generate the PUF value using the measure of the random manufacturing difference between the pair of matched devices.

19. The PUF system of claim 18, wherein the determination circuitry comprises a comparator for determining the magnitude of the random manufacturing difference when the system is operated in the enrollment mode and for determining the measure of the random manufacturing difference when the system is operated in the PUF mode.

20. The PUF system of claim 18 or claim 19, configured to operate intermittently or periodically in the enrollment mode throughout the lifetime of the PUF system.

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