Pixel and display device

Abstract

A pixel according to one embodiment of the present invention comprises: a light emitting element connected between a first power supply line and a first node; a first transistor including a first electrode, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line, a second electrode electrically connected to a fourth node, and a gate electrode for receiving a scan signal; a third transistor; a fourth transistor; and a first capacitor.

Description

Technical Field

[0001] The embodiments relate to a pixel and display device with improved display quality. Background Technology

[0002] A display device is a device that includes various electronic components such as a display panel for displaying images, input sensors for sensing external inputs, and electronic modules. These electronic components are electrically connected to each other via signal lines arranged in various ways. The display panel includes multiple pixels. Each pixel includes a light-emitting element that generates light and a pixel driving circuit that controls the amount of current flowing through the light-emitting element. In the event of leakage current in the pixel driving circuit of a pixel, the change in the amount of current flowing through the light-emitting element leads to a deterioration in display quality. Summary of the Invention Technical issues

[0003] The embodiment provides a pixel and a display device with improved display quality. Technical solution

[0004] According to an embodiment, a pixel may include: a light-emitting element connected between a first node and a first power line for providing a first power supply; a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line for providing a data signal, a second electrode electrically connected to a fourth node, and a gate electrode for receiving a scan signal; a third transistor including a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode for receiving a compensation scan signal; a fourth transistor including a first electrode electrically connected to the third node, a second electrode electrically connected to the fourth node, and a gate electrode for receiving a first light-emitting signal; and a first capacitor connected between the second node and the fourth node.

[0005] The pixel may further include a fifth transistor, the fifth transistor including a first electrode connected to the second node, a second electrode electrically connected to a second power supply line for providing a second power supply having a voltage level lower than that of the first power supply, and a gate electrode for receiving the first light emission signal.

[0006] The pixel may further include a sixth transistor, the sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to an initialization voltage line for providing an initialization voltage, and a gate electrode for receiving a compensation scan signal.

[0007] The pixel may further include a 6-1 transistor, the 6-1 transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first power line, and a gate electrode for receiving a compensation scan signal.

[0008] The pixel may further include a seventh transistor, the seventh transistor including a first electrode connected to the first node, a second electrode connected to the first electrode of the first transistor, and a gate electrode for receiving a second light emission signal.

[0009] The pixel may further include a second capacitor connected between the fourth node and the second power line.

[0010] The compensation scan signal and the first emission signal can have an effective level during the first time period.

[0011] The first power source can be supplied to the third node during the first time period.

[0012] The compensation scan signal and the second emission signal can have an effective level during the second time period after the first time period.

[0013] During the second time period, the voltage value obtained by subtracting the threshold voltage of the first transistor from the first power supply can be provided to the second node.

[0014] The scanning signal can have an effective level during the third time period following the second time period.

[0015] Data signals can be provided to the fourth node during the third time period.

[0016] The first and second light-emitting signals can have valid levels during the fourth time period following the third time period.

[0017] According to an embodiment, the display device may include: a display panel including a plurality of pixels, each of the plurality of pixels including: a light-emitting element connected between a first node and a first power line for providing a first power supply; a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line for providing a data signal, a second electrode electrically connected to a fourth node, and a gate electrode for receiving a scan signal; a third transistor including a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode for receiving a compensation scan signal; a fourth transistor including a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode for receiving a first light-emitting signal; and a first capacitor connected between the second node and the fourth node.

[0018] Each of the plurality of pixels may further include a fifth transistor, the fifth transistor including a first electrode connected to the second node, a second electrode electrically connected to a second power supply line for providing a second power supply having a voltage level lower than that of the first power supply, and a gate electrode for receiving the first light emission signal.

[0019] Each of the plurality of pixels may further include a sixth transistor, the sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to an initialization voltage line for providing an initialization voltage, and a gate electrode for receiving a compensation scan signal.

[0020] Each of the plurality of pixels may further include a 6-1 transistor, the 6-1 transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first power line, and a gate electrode for receiving a compensation scan signal.

[0021] Each of the plurality of pixels may further include a seventh transistor, the seventh transistor including a first electrode connected to the first node, a second electrode connected to the first electrode of the first transistor, and a gate electrode for receiving a second light emission signal.

[0022] Each of the plurality of pixels may further include a second capacitor connected between the fourth node and the second power line.

[0023] The compensation scan signal and the first emission signal can have an effective level during the first time period.

[0024] The compensation scan signal and the second emission signal can have an effective level during the second time period after the first time period.

[0025] The scanning signal can be at an active level during the third time period following the second time period.

[0026] The first and second light-emitting signals can have valid levels during the fourth time period following the third time period.

[0027] According to an embodiment, a pixel may include: a light-emitting element connected between a first node and a first power line for providing a first power supply; a first transistor connected between the first node and a second node, and including a gate electrode electrically connected to a third node; a second transistor connected between a fourth node and a data line for providing a data signal, and including a gate electrode for receiving a scan signal; a third transistor connected between the first node and the third node, and including a gate electrode for receiving a compensation scan signal; a fourth transistor connected between the third node and the fourth node, and including a gate electrode for receiving a first light-emitting signal; a fifth transistor connected between the second node and a second power line for providing a second power supply having a voltage level lower than the voltage level of the first power supply, and including a gate electrode for receiving the first light-emitting signal; and a sixth transistor connected between the first node and an initialization voltage line for providing an initialization voltage, and including a gate electrode for receiving a compensation scan signal.

[0028] The pixel may further include: a first capacitor connected between the second node and the fourth node.

[0029] The pixel may further include a seventh transistor connected between the first node and the first transistor and include a gate electrode for receiving a second light-emitting signal.

[0030] The pixel may further include a second capacitor connected between the fourth node and the second power line. Beneficial effects

[0031] As described above, the threshold voltage of the first transistor can remain unaffected by the drive current flowing through the light-emitting element. Regardless of the characteristics of the first transistor, the drive current can be proportional to the square of the difference between the data signal and the initialization voltage. Consequently, the brightness of the image output from the display panel can remain uniform. Consequently, pixels with improved display quality and a display device including the pixels can be provided.

[0032] Furthermore, as described above, the first and second power supplies can remain unaffected by the driving current flowing through the light-emitting element. Regardless of the voltage values ​​of the first and second power supplies, the driving current can be proportional to the square of the difference between the data signal and the initialization voltage. Consequently, the brightness of the image output from the display panel can remain uniform. Consequently, pixels with improved display quality and a display device including the pixels can be provided. Attached Figure Description

[0033] Figure 1 This is a schematic perspective view of a display device according to an embodiment.

[0034] Figure 2 This is a block diagram of a display device according to an embodiment.

[0035] Figure 3 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0036] Figure 4 This is a timing diagram illustrating the operation of a display device according to an embodiment.

[0037] Figure 5 , Figure 6 , Figure 7 and Figure 8 This is a schematic diagram illustrating the operation of pixels according to an embodiment.

[0038] Figure 9 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0039] Figure 10 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0040] Figure 11 This is a timing diagram illustrating the operation of a display device according to an embodiment.

[0041] Figure 12 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0042] Figure 13 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0043] Figure 14 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment. Detailed Implementation

[0044] In the following description, numerous specific details are set forth for illustrative purposes in order to provide a thorough understanding of various embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of the apparatuses or methods disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Herein, the various embodiments are not necessarily exclusive, nor are they intended to limit this disclosure. For example, particular shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment.

[0045] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clearly define the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of crosshairs or shading does not express or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between illustrated elements, and / or any other characteristics, properties, etc., of the elements. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. A particular process sequence may be performed differently than is described when embodiments can be implemented differently. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0046] When an element or layer is referred to as being "on" another element or layer, "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to that other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to," or "directly attached to" another element or layer, an intermediary element or layer is not present. Therefore, the term "connection" may refer to a physical, electrical, and / or fluid connection, with or without an intermediary element. Furthermore, the axes of the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of a Cartesian coordinate system, such as the X, Y, and Z axes, and may be interpreted in a broader sense. For example, the axes of the first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Furthermore, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0047] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0048] In this document, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used for descriptive purposes to describe the relationship of one element to another(s) as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to further include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “the (described)” are intended to also include the plural forms. Furthermore, when used in this specification, the terms “comprising” and / or “including” and variations thereof indicate the presence of said features, integrals, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to explain the inherent biases of measured values, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0050] Various embodiments are described herein with reference to cross-sectional and / or exploded views, which are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations are expected due to, for example, manufacturing techniques and / or tolerances. Consequently, the embodiments disclosed herein are not necessarily to be construed as limited to a specific shape of the illustrated area, but rather include shape deviations due to, for example, manufacturing processes. In this way, the areas illustrated in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0051] In accordance with the conventions of the art, some embodiments are described and illustrated in the accompanying drawings based on functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electrical (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module may be implemented by dedicated hardware, or may be implemented as a combination of dedicated hardware for performing some functions and processors (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, each block, unit, and / or module of some embodiments may be physically separated into two or more interactive and discrete blocks, units, and / or modules without departing from the scope of the invention. Furthermore, some embodiments of blocks, units, and / or modules can be physically combined into more complex blocks, units, and / or modules without departing from the scope of the invention.

[0052] In this document, embodiments will be described with reference to the accompanying drawings.

[0053] Figure 1 This is a schematic perspective view of a display device according to an embodiment.

[0054] refer to Figure 1 According to an embodiment, the display device DD may have a shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. However, the shape of the display device DD is not limited to this, and various display devices DD having various shapes can be provided.

[0055] According to embodiments, the display device DD may include large-sized display devices such as televisions or monitors, or small-to-medium-sized display devices such as cellular phones, tablet computers, vehicle navigation systems, or game consoles. The above examples are provided for illustrative purposes only, and it is obvious that the display device DD can be applied to any other electronic device without departing from the scope of this disclosure.

[0056] like Figure 1 As shown, the display device DD can display an image IM on a display surface FS that is parallel to the first direction DR1 and the second direction DR2, on a third direction DR3 that intersects with the first direction DR1 and the second direction DR2. The display surface FS on which the image IM can be displayed can correspond to the front of the display device DD.

[0057] The display surface FS of the display device DD can be divided into multiple regions. The display surface FS of the display device DD can be divided into a display area DA and a non-display area NDA.

[0058] The display area DA can be an area in which the image IM is displayed. A user can view the image IM through the display area DA. The shape of the display area DA can be defined by the non-display area NDA. However, the above structure is provided for illustrative purposes. For example, the non-display area NDA can be configured to be adjacent only to one side of the display area DA, or it can be omitted. The display device DD according to embodiments can include various embodiments, and embodiments are not limited thereto.

[0059] The non-display area NDA, which is adjacent to the display area DA, can be an area in which the image IM is not displayed. The border area of ​​the display device DD can be defined by the non-display area NDA.

[0060] The non-display area NDA may surround the display area DA. However, this structure is provided for illustrative purposes. For example, the non-display area NDA may be adjacent only to a portion of the edge of the display area DA, and is not limited to any particular embodiment.

[0061] Figure 2 This is a block diagram of a display device according to an embodiment.

[0062] refer to Figure 2 The display device DD may include a display panel DP, a drive controller 100, a data drive circuit 200, and a voltage generator 300.

[0063] According to embodiments, the display panel DP can be an emitting display panel, and the embodiments are not limited thereto. For example, the display panel DP can be an organic light-emitting display panel, a quantum dot light-emitting display panel, a micron-sized light-emitting diode (LED) display panel, or a nano-LED display panel. The light-emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots or quantum rods, etc. The light-emitting layer of a micron-sized LED display panel may include micron-sized LEDs. The light-emitting layer of a nano-LED display panel may include nano-sized LEDs.

[0064] The drive controller 100 can receive input image signals RGB and CTRL. The drive controller 100 can generate image data signals DATA by converting the data format of the input image signal RGB to match (or be compatible with) the interface specification of the data drive circuit 200. The drive controller 100 can output scan control signals SCS, data control signals DCS, and illumination control signals ECS.

[0065] The data drive circuit 200 can receive data control signals DCS and image data signals DATA from the drive controller 100. The data drive circuit 200 can convert the image data signal DATA into a data signal Vdata (see [link to relevant documentation]). Figure 3 ), and the data signal Vdata (see Figure 3 These can be output to data lines DL1 through DLm respectively. The data signal Vdata (see...) Figure 3 () can be an analog voltage corresponding to the grayscale value of the image data signal DATA.

[0066] According to an embodiment, the data driving circuit 200 can, during the duration of one frame, respectively transmit the data signal Vdata corresponding to the image data signal DATA (see [link to embodiment]). Figure 3 Output to data lines DL1 to DLm.

[0067] Voltage generator 300 can generate the voltage required for the operation of display panel DP. According to an embodiment, voltage generator 300 can generate a first power supply ELVDD, a second power supply ELVSS, and an initialization voltage Vcint. The first power supply ELVDD can have a higher voltage level than the second power supply ELVSS.

[0068] The display panel DP may include scan lines GCL1 to GCLn and GWL1 to GWLn, light emission control lines EML11 to EML1n and EML21 to EML2n, data lines DL1 to DLm, and pixels PX. The display panel DP may further include scan drive circuitry SD and light emission drive circuitry EDC.

[0069] The scan drive circuit SD can be arranged on the first side of the display panel DP. Scan lines GCL1 to GCLn and GWL1 to GWLn can extend from the scan drive circuit SD in the first direction DR1.

[0070] The light-emitting drive circuit EDC can be located on the second side of the display panel DP. The light-emitting control lines EML11 to EML1n and EML21 to EML2n can extend from the light-emitting drive circuit EDC in the opposite direction to the first direction DR1.

[0071] The scan lines GCL1 to GCLn and GWL1 to GWLn, as well as the light emission control lines EML11 to EML1n and EML21 to EML2n, can be arranged spaced apart from each other on the second direction DR2.

[0072] Scan lines GCL1 to GCLn and GWL1 to GWLn may include compensation scan lines GCL1 to GCLn and write scan lines GWL1 to GWLn.

[0073] The light emission control lines EML11 to EML1n and EML21 to EML2n may include the first light emission control lines EML11 to EML1n and the second light emission control lines EML21 to EML2n.

[0074] Data lines DL1 to DLm can extend from the data drive circuit 200 in a direction opposite to the second direction DR2. Data lines DL1 to DLm can be arranged spaced apart from each other in the first direction DR1.

[0075] according to Figure 2 In the embodiment shown, the scan driving circuit SD and the light-emitting driving circuit EDC can be arranged facing each other with the pixel PX located between them. However, the embodiment is not limited to this. For example, the scan driving circuit SD and the light-emitting driving circuit EDC can be located adjacent to each other on one of the first and second sides of the display panel DP. According to the embodiment, the scan driving circuit SD and the light-emitting driving circuit EDC can be implemented as a single circuit.

[0076] Multiple pixels PX can be electrically connected to scan lines GCL1 to GCLn and GWL1 to GWLn, light emission control lines EML11 to EML1n and EML21 to EML2n, and data lines DL1 to DLm. According to an embodiment, each of the multiple pixels PX can be electrically connected to two scan lines and two light emission control lines.

[0077] Each of the pixels PX may include a light-emitting element LD (see Figure 3 ) and the LD used to control the light-emitting element (see Figure 3 The pixel circuit unit is responsible for the light-emitting operation of the pixel. Details will be described later.

[0078] The light-emitting element LD in each of the pixels PX (see Figure 3 A pixel PX can produce light of different colors. For example, a pixel PX may include a red pixel for producing red light, a green pixel for producing green light, and a blue pixel for producing blue light. The light-emitting elements of the red pixel, the green pixel, and the blue pixel may include light-emitting layers containing different materials.

[0079] The pixel circuit unit may include at least one transistor and at least one capacitor. Details will be described later. The scan drive circuit (SD) and the light-emitting drive circuit (EDC) may include transistors formed using the same process as the transistors contained in the pixel circuit unit.

[0080] Each of the multiple pixels PX can receive a first power supply ELVDD, a second power supply ELVSS, and an initialization voltage Vcint from the voltage generator 300.

[0081] The scan drive circuit SD can receive the scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit SD can output scan signals to scan lines GCL1 to GCLn and GWL1 to GWLn.

[0082] The light-emitting drive circuit EDC can output a light-emitting signal to the light-emitting control lines EML11 to EML1n and EML21 to EML2n in response to the light-emitting control signal ECS from the drive controller 100.

[0083] According to an embodiment, the drive controller 100 can determine the drive frequency and control the data drive circuit 200, the scan drive circuit SD, and the light emission drive circuit EDC according to the determined drive frequency.

[0084] Figure 3 This is an equivalent circuit diagram of the pixels according to the embodiment. Figure 2 Each of the pixels PX shown can have the same as Figure 3 The equivalent circuit of the pixel PXij shown has the same circuit structure.

[0085] refer to Figure 3 Pixel PXij can be connected to the j-th data line DLj among data lines DL1 to DLm, the i-th compensation scan line GCLi among compensation scan lines GCL1 to GCLn, the i-th write scan line GWLi among write scan lines GWL1 to GWLn, the i-th first light emission control line EML1i among first light emission control lines EML11 to EML1n, and the i-th second light emission control line EML2i among second light emission control lines EML21 to EML2n. Here, "i" and "j" can be natural numbers.

[0086] Pixel PXij may include a light-emitting element LD and a pixel driving circuit PCij. The light-emitting element LD may be a light-emitting diode, and for example, an organic light-emitting diode including an organic light-emitting layer. The pixel driving circuit PCij may be connected to the light-emitting element LD to control the amount of current flowing through the light-emitting element LD, and the light-emitting element LD may generate light with a specific brightness according to the amount of current supplied.

[0087] The pixel driving circuit PCij may include a first transistor to a seventh transistor T1, T2, T3, T4, T5, T6 and T7, and a first capacitor Cst.

[0088] According to an embodiment, pixel PXij can be referred to as having a 7T-1C structure.

[0089] According to an embodiment, the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can all be N-type transistors having a semiconductor layer comprising an oxide semiconductor. However, this is provided for illustrative purposes only. The semiconductor layer according to the embodiment can include low-temperature polycrystalline silicon or crystalline silicon, without limitation. The first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be implemented in an N-type configuration, thereby reducing or minimizing variations in device characteristics or transient image retention. However, this is provided for illustrative purposes only, and the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can all be P-type transistors. According to an embodiment, at least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be an N-type transistor, and the remaining transistors of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 can be P-type transistors.

[0090] Scan lines GCLi and GWLi can transmit scan signals GC and GW respectively, and light emission control lines EML1i and EML2i can transmit light emission signals EM1 and EM2 respectively. The j-th data line DLj can transmit the data signal Vdata. The data signal Vdata can have the same input to the display device DD (see...). Figure 2 The image data signal DATA corresponds to the voltage level of the grayscale value.

[0091] The first power supply line PL1 can provide the first power supply ELVDD. The second power supply line PL2 can provide the second power supply ELVSS. The second power supply ELVSS can have a voltage level lower than that of the first power supply ELVDD. The initialization voltage line PL3 can provide the initialization voltage Vcint.

[0092] The light-emitting element (LD) can be connected between the first power line PL1, which is supplied with the first power supply ELVDD, and the first node N1. The light-emitting element LD may include an anode AND and a cathode CTD. The anode AND can be connected to the first power line PL1. The cathode CTD can be connected (e.g., electrically connected) to the second power line PL2 via the seventh transistor T7, the first transistor T1, and the fifth transistor T5.

[0093] When the light-emitting element (LD) is an organic light-emitting element, the LD may further include an organic layer between the anode AND and the cathode CTD. The cathode CTD of the LD can be connected to the pixel driving circuit PCij via a first node N1. The LD can emit light in response to the amount of current Id flowing through the first transistor T1 of the pixel driving circuit PCij.

[0094] The first transistor T1 may include a first electrode connected (e.g., electrically connected) to a first node N1 via a seventh transistor T7, a second electrode connected (e.g., electrically connected) to a second node N2, and a gate electrode connected (e.g., electrically connected) to a third node N3. The first transistor T1 may be referred to as a driving transistor. The first electrode of the first transistor T1 may be connected (e.g., electrically connected) to a fifth node N5. The first transistor T1 may be connected between the first node N1 and the second node N2.

[0095] According to an embodiment, the first transistor T1 can be an N-type transistor. The cathode CTD of the light-emitting element LD can be connected to the drain (or first electrode) of the first transistor T1. For example, even if the light-emitting element LD deteriorates, the voltage at the source (or second electrode) terminal of the first transistor T1 can remain unchanged. Even if the light-emitting element LD deteriorates, the gate-source voltage (referred to as Vgs) of the first transistor T1 can remain unchanged. Therefore, although the usage time of pixel PXij increases, the range of variation in the amount of current flowing through the first transistor T1 can be reduced, thereby reducing the display panel DP (see...). Figure 2 To address image retention defects (or long-term image retention defects) and improve the display panel's display panel output (see [reference]). Figure 2 The lifespan of the pixel PXij. Correspondingly, the pixel PXij has improved display quality, and the display device DD including the pixel PXij (see [reference]). Figure 1 (This can be provided.)

[0096] The second transistor T2 may include a first electrode connected (e.g., electrically connected) to the j-th data line DLj to which the data signal Vdata is provided, a second electrode electrically connected to the fourth node N4, and a gate electrode for receiving the scan signal GW. The gate electrode of the second transistor T2 may be connected to the write scan line GWLi. The second transistor T2 may be referred to as a switching transistor. The second transistor T2 may be connected between the j-th data line DLj and the fourth node N4.

[0097] The third transistor T3 may include a first electrode connected (e.g., electrically connected) to the first node N1, a second electrode connected (e.g., electrically connected) to the third node N3, and a gate electrode for receiving the compensation scan signal GC. The gate electrode of the third transistor T3 may be connected to the compensation scan line GCLi. The third transistor T3 may be connected between the first node N1 and the third node N3.

[0098] The fourth transistor T4 may include a first electrode connected (e.g., electrically connected) to the third node N3, a second electrode connected (e.g., electrically connected) to the fourth node N4, and a gate electrode for receiving the second light-emitting signal EM2. The gate electrode of the fourth transistor T4 may be connected to the second light-emitting control line EML2i. The fourth transistor T4 may be connected between the third node N3 and the fourth node N4.

[0099] The fifth transistor T5 may include a first electrode connected (e.g., electrically connected) to the second node N2, a second electrode connected (e.g., electrically connected) to the second power supply line PL2, and a gate electrode for receiving the second light emission signal EM2. The gate electrode of the fifth transistor T5 may be connected to the second light emission control line EML2i. The fifth transistor T5 is connected between the second node N2 and the second power supply line PL2.

[0100] The sixth transistor T6 may include a first electrode connected (e.g., electrically connected) to the first node N1, a second electrode connected (e.g., electrically connected) to the initialization voltage line PL3, and a gate electrode for receiving the compensation scan signal GC. The gate electrode of the sixth transistor T6 may be connected (e.g., electrically connected) to the compensation scan line GCLi. The sixth transistor T6 may be connected between the first node N1 and the initialization voltage line PL3.

[0101] The seventh transistor T7 may include a first electrode connected (e.g., electrically connected) to the first node N1, a second electrode connected (e.g., electrically connected) to the fifth node N5, and a gate electrode for receiving the first light-emitting signal EM1. The gate electrode of the seventh transistor T7 may be connected to the first light-emitting control line EML1i. The seventh transistor T7 may be connected between the first node N1 and the first electrode of the first transistor T1.

[0102] The first capacitor Cst can be connected between the second node N2 and the fourth node N4.

[0103] In another example, the pixel driving circuit may include at least two capacitors. For example, the pixel driving circuit may include a storage capacitor and a holding capacitor. For example, the capacitance of each of the plurality of capacitors may be proportional to the area. Where higher capacitance is required, the area of ​​the capacitors may be increased. Accordingly, the physical area (or size) of the pixel driving circuit may increase. Accordingly, the number of pixels arranged in a particular area may be relatively reduced, resulting in a possible decrease in pixel density. However, according to an embodiment, the pixel PXij may include only one capacitor Cst in a 7T-1C structure. The area of ​​the pixel driving circuit PCij may be relatively reduced. The pixel density of the pixel PXij may be increased. Accordingly, higher resolution pixels can be easily designed. Accordingly, the pixel PXij with improved display quality and the display device DD including the pixel PXij (see...) Figure 1 (This can be provided.)

[0104] Figure 4 This is a timing diagram illustrating the operation of a display device according to an embodiment, and Figures 5 to 8 This is a schematic diagram illustrating the operation of pixels according to an embodiment. See the following references. Figures 5 to 8In the description, the same reference numerals are assigned to the reference figures. Figure 3 The same parts are described, and for ease of description, their details will be omitted.

[0105] refer to Figure 2 and Figure 4 The display panel DP can be operated in units of frame duration FP to display image IM (see [link]). Figure 1 The duration of any frame FP can include the first to fourth time periods t1, t2, t3, and t4.

[0106] The first to third time periods, t1, t2, and t3, can be referred to as non-light-emitting periods. For example, the first time period t1 can be called the initialization period. The second time period t2 can be called the compensation period. The third time period t3 can be called the input period.

[0107] The fourth time period, t4, can be referred to as the luminescent period.

[0108] Figure 5 This is a schematic diagram illustrating the operation of pixel PXij during the first time period t1 of frame duration FP.

[0109] refer to Figure 4 and Figure 5 During the first time period t1, the compensation scan signal GC and the second emission signal EM2 can have an effective level. The effective level of each of the compensation scan signal GC and the second emission signal EM2 can be a high level VGH. However, this embodiment is provided for illustrative purposes only, and the effective level of the signals according to the embodiment is not limited thereto. For example, the effective level of the signal can be a low level VGL.

[0110] The first light-emitting signal EM1 and the scan signal GW may have inactive levels. The inactive level of each of the first light-emitting signal EM1 and the scan signal GW may be a low level VGL. However, this embodiment is provided for illustrative purposes only, and the inactive levels of the signals according to the embodiment are not limited thereto. For example, the inactive level of the signal may be a high level VGH.

[0111] The sixth transistor T6 can be turned on in response to the compensation scan signal GC. The initialization voltage Vcint can be provided (or applied) to the first node N1 through the sixth transistor T6. The first node N1 can be charged with the initialization voltage Vcint.

[0112] The third transistor T3 can be turned on in response to the compensation scan signal GC. The initialization voltage Vcint can be provided (or applied) to the third node N3 through the sixth transistor T6 and the third transistor T3. The third node N3 can be charged with the initialization voltage Vcint.

[0113] During the first time period t1, the gate electrode of the first transistor T1 can be initialized to the initialization voltage Vcint. For example, the voltage of the third node N3 can be changed from the data signal Vdata during the duration of the previous frame to the initialization voltage Vcint.

[0114] The fifth transistor T5 can be turned on in response to the second light-emitting signal EM2. The second power supply ELVSS can be supplied (or applied) to the second node N2 through the fifth transistor T5. The second node N2 can be charged with the second power supply ELVSS.

[0115] During the first time period t1, the source (or second electrode) of the first transistor T1 can be initialized to the second power supply ELVSS. Pixel PXij can initialize the source of the first transistor T1 with the second power supply ELVSS without using a separate initialization voltage.

[0116] According to an embodiment, in voltage generator 300 (see...) Figure 2 In the original text, the separate power supply line used to provide the initialization voltage to the second electrode of the first transistor T1 can be omitted. The non-display area NDA (see...) Figure 1 The area of ​​the pixel PXij can be reduced. For example, the number of power lines included in the pixel PXij can be reduced. The spacing between the lines included in the pixel PXij can be increased. Signal interference between the lines can be reduced. Accordingly, the pixel PXij and the display device DD (see...) Figure 1 It can have improved display quality.

[0117] The fourth transistor T4 can be turned on in response to the second light emission signal EM2. The initialization voltage Vcint can be provided (or applied) to the fourth node N4 through the fourth transistor T4. At least a portion of the initialization voltage Vcint can be charged to the fourth node N4 through the first capacitor Cst.

[0118] Figure 6 This is a schematic diagram illustrating the operation of pixel PXij during the second time period t2 of frame duration FP.

[0119] refer to Figure 4 and Figure 6 The second time period t2 can occur after the first time period t1. During the second time period t2, the compensation scan signal GC and the first emission signal EM1 can have valid levels. The valid level of each of the compensation scan signal GC and the first emission signal EM1 can be a high level VGH.

[0120] The second light-emitting signal EM2 and the scan signal GW can have inactive levels. The inactive level of each of the second light-emitting signal EM2 and the scan signal GW can be a low level VGL.

[0121] The sixth transistor T6 can be turned on in response to the compensation scan signal GC. The initialization voltage Vcint can be provided (or applied) to the first node N1 through the sixth transistor T6. The first node N1 can be charged with the initialization voltage Vcint.

[0122] The third transistor T3 can be turned on in response to the compensation scan signal GC. The initialization voltage Vcint can be provided (or applied) to the third node N3 through the sixth transistor T6 and the third transistor T3. The third node N3 can be charged with the initialization voltage Vcint.

[0123] The first transistor T1 can be turned on in response to the initialization voltage Vcint provided (or applied) to the gate electrode.

[0124] The seventh transistor T7 can be turned on in response to the first light-emitting signal EM1. The initialization voltage Vcint can be provided (or applied) to the fifth node N5 through the seventh transistor T7. The fifth node N5 can be charged with the initialization voltage Vcint.

[0125] During the second time period t2, the first transistor T1 can operate as a source follower. A voltage lower than the threshold voltage (referred to as Vth) of the first transistor T1 that is supplied (or applied) to the third node N3 can be supplied (or applied) to the second node N2. For example, a voltage lower than the threshold voltage of the first transistor T1 that is lower than the initialization voltage Vcint can be supplied (or applied) to the second node N2. The second node N2 can be charged with a voltage of "Vcint - Vth".

[0126] Figure 7 This is a schematic diagram illustrating the operation of pixel PXij during the third time period t3 of frame duration FP.

[0127] refer to Figure 4 and Figure 7 The third time period t3 can occur after the second time period t2. During the third time period t3, the compensation scan signal GC, the first light emission signal EM1, and the scan signal GW can all have active levels. The active level of each of the compensation scan signal GC, the first light emission signal EM1, and the scan signal GW can be a high level VGH.

[0128] The second light-emitting signal EM2 may have an inactive level. Each of the inactive levels in the second light-emitting signal EM2 may have a low level VGL.

[0129] The third transistor T3 and the sixth transistor T6 can be turned on in response to the compensation scan signal GC. The first node N1 and the third node N3 can be charged with the initialization voltage Vcint.

[0130] The seventh transistor T7 can be turned on in response to the first light-emitting signal EM1. The fifth node N5 can be charged with the initialization voltage Vcint.

[0131] The first transistor T1 can operate as a source follower. The second node N2 can be charged with a voltage of Vcint-Vth.

[0132] The second transistor T2 can be turned on in response to the scan signal GW. The data signal Vdata provided through the j-th data line DLj can be provided (or applied) to the fourth node N4.

[0133] A first capacitor Cst can be positioned between the second node N2 and the fourth node N4. The first capacitor Cst can store the differential voltage between the second node N2 and the fourth node N4. The voltage level at one terminal of the first capacitor Cst (e.g., the voltage level at the fourth node N4) can be changed to the voltage level of the data signal Vdata.

[0134] When the second transistor T2 is turned on, the voltage of the second node N2 can be increased (e.g., momentarily increased) by the data signal Vdata and then return to normal. For example, the voltage level of the second node N2 can be changed from a voltage of "Vcint-Vth+Vdata" to a voltage of "Vcint-Vth".

[0135] The voltage level of the opposite terminals of the first capacitor Cst, such as the voltage level of the second node N2, can be a voltage level of "Vcint-Vth". The first capacitor Cst can store the charge corresponding to the voltage difference "Vcint-Vth-Vdata" between the second node N2 and the fourth node N4. The first capacitor Cst can be referred to as a storage capacitor.

[0136] Figure 8 This is a schematic diagram illustrating the operation of pixel PXij during the fourth time period t4 of frame duration FP.

[0137] refer to Figure 4 and Figure 8 The fourth time period t4 can occur after the third time period t3. During the fourth time period t4, the first light-emitting signal EM1 and the second light-emitting signal EM2 can have valid levels. The valid level of each of the first light-emitting signal EM1 and the second light-emitting signal EM2 can be a high level VGH.

[0138] The compensation scan signal GC and the scan signal GW can have inactive levels. The inactive level of each of the compensation scan signal GC and the scan signal GW can be a low level VGL.

[0139] The seventh transistor T7 can be turned on in response to the first light-emitting signal EM1. The fifth transistor T5 can be turned on in response to the second light-emitting signal EM2.

[0140] When the fifth transistor T5 and the seventh transistor T7 are turned on, a current path can be formed from the first power line PL1 to the light-emitting element LD, the seventh transistor T7, the first transistor T1, the fifth transistor T5, and the second power line PL2. For example, the drive current Id can flow through the first power line PL1, the light-emitting element LD, the seventh transistor T7, the first transistor T1, the fifth transistor T5, and the second power line PL2.

[0141] The voltage value of the second power supply ELVSS can be less than the value obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the initialization voltage Vcint.

[0142] If the second power supply ELVSS is greater than the value obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the initialization voltage Vcint, a current path may not be formed. However, according to the embodiment, the second power supply ELVSS can be less than the value obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the initialization voltage Vcint. A current path can be easily formed. The light-emitting element LD can easily emit light. Accordingly, the pixel PXij and the display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0143] The fourth transistor T4 can be turned on in response to the second light-emitting signal EM2. A voltage equal to the amount of charge stored in the first capacitor Cst can be supplied (or applied) to the gate electrode voltage of the first transistor T1 through the fourth node N4 and the third node N3.

[0144] When from the display panel DP (see Figure 2 ) data drive circuit 200 (see Figure 2 When the output data signal Vdata is written, the light-emitting element LD can emit light. The driving current Id can be expressed by the following formula.

[0145] [Formula 1]

[0146]

[0147] [Formula 2]

[0148]

[0149] [Formula 3]

[0150]

[0151] [Formula 4]

[0152]

[0153] [Formula 5]

[0154]

[0155] In the above formula, "μ" can be the electric field mobility, "Cox" can be the capacitance of the gate insulating layer, "W" and "L" can be the width and length of the first transistor T1, and "Vgs" can be the gate-source voltage of the first transistor T1. For example, "μ" and "Cox" can be constants. For example, "α" can be a constant.

[0156] The gate-source voltage of the first transistor T1 can be obtained by subtracting the voltage of the second node N2 from the voltage of the third node N3.

[0157] Formula 4 can be a rearrangement of Formula 2 and Formula 3 in Formula 1. Formula 5 can be a rearrangement of Formula 4.

[0158] Pixel PX (see Figure 2 The threshold voltage (Vth) of the first transistor T1 included in each of the following can be varied according to the characteristics of the first transistor T1. However, according to an embodiment, the threshold voltage (Vth) of the first transistor T1 can remain unaffected by the driving current Id flowing through the light-emitting element LD during the first to fourth time periods t1, t2, t3, and t4. Referring to Formula 5, the driving current Id flowing through the light-emitting element LD during the fourth time period t4 can be unaffected by the threshold voltage (Vth) of the first transistor T1. Regardless of the characteristics of the first transistor T1, the driving current Id can be proportional to the square of the difference between the data signal Vdata and the initialization voltage Vcint. Accordingly, from the display panel DP (see...) Figure 2 The output image IM can maintain uniform brightness. Correspondingly, the pixel PXij and display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0159] The voltage level of the first power supply ELVDD in the first power supply line PL1 may change due to a voltage drop (referred to as IR drop). For example, the voltage level of the second power supply ELVSS in the second power supply line PL2 may change due to a voltage drop. However, according to the embodiment, through the first to fourth time periods t1, t2, t3, and t4, the first power supply ELVDD and the second power supply ELVSS can remain unaffected by the driving current Id flowing through the light-emitting element LD. Referring to Formula 5, the driving current Id flowing through the light-emitting element LD during the fourth time period t4 can be unaffected by the first power supply ELVDD and the second power supply ELVSS. Regardless of the voltage values ​​of the first power supply ELVDD and the second power supply ELVSS, the driving current Id can be proportional to the square of the difference between the data signal Vdata and the initialization voltage Vcint. Accordingly, from the display panel DP (see...) Figure 2 The output image IM can maintain uniform brightness. Correspondingly, the pixel PXij and display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0160] Furthermore, according to an embodiment, the first transistor T1 can be an N-type transistor, and the cathode CTD of the light-emitting element LD can be connected (e.g., electrically connected) to the drain (or first electrode) of the first transistor T1. For example, even if the light-emitting element LD deteriorates, the voltage at the source terminal of the first transistor T1, which affects the drive current Id, can remain unchanged. For example, even if the light-emitting element LD deteriorates, the gate-source voltage (Vgs) of the first transistor T1 can remain unchanged. Accordingly, despite the increase in usage time, the range of variation in the amount of current flowing through the first transistor T1 can be reduced, making the display panel DP (see...) more stable. Figure 2 Image retention defects (or long-term image retention defects) can be reduced, and the display panel DP (see...) Figure 2 The lifespan of the pixels (PXij) can be increased. Correspondingly, the pixel quality of the display device (DD) can be improved. Figure 1 (This can be provided.)

[0161] Figure 9 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment. See the following reference... Figure 9 In the description, the same reference numerals will be assigned to the reference figures. Figure 3 The same parts are described, and for ease of description, their details will be omitted.

[0162] refer to Figure 4 and Figure 9 The pixel PX-1ij may include a light-emitting element LD and a pixel driving circuit PC-1ij.

[0163] The pixel driving circuit PC-1ij may include a first transistor to a seventh transistor T1, T2, T3, T4, T5, T6-1, T7 and a first capacitor Cst.

[0164] Transistor T6-1 (6-1) may include a first electrode connected (e.g., electrically connected) to a first node N1, a second electrode connected (e.g., electrically connected) to a first power supply line PL1, and a gate electrode for receiving a compensation scan signal GC. The gate electrode of transistor T6-1 (6-1) may be connected (e.g., electrically connected) to the compensation scan line GCLi.

[0165] According to an embodiment, in voltage generator 300 (see...) Figure 2 In the original text, the separate power supply line used to provide the initialization voltage to the gate electrode of the first transistor T1 can be omitted. The non-display area NDA (see...) Figure 1 The area of ​​the pixel PX-1ij can be reduced. For example, the number of power lines included in the pixel PX-1ij can be reduced. The spacing between the lines included in the pixel PX-1ij can be increased. Signal interference between the lines can be reduced. Accordingly, the pixel PX-1ij and the display device DD (see [link to display device]) have improved display quality. Figure 1 (This can be provided.)

[0166] Pixel PX-1ij can be driven during the first to fourth time periods t1, t2, t3, and T4.

[0167] During the first time period t1, the third node N3 can be initialized to the first power supply ELVDD via the 6-1 transistor T6-1.

[0168] When from the display panel DP (see Figure 2 ) data drive circuit 200 (see Figure 2 When the output data signal is written, the light-emitting element LD can emit light. The driving current Id can be expressed by the following formula.

[0169] [Formula 6]

[0170] Id = α(Vdata-ELVDD) 2

[0171] The threshold voltage (Vth) of the first transistor T1 included in pixel PX-1ij can be varied according to the characteristics of the first transistor T1. However, according to an embodiment, the threshold voltage (Vth) of the first transistor T1 can remain unaffected by the driving current Id flowing through the light-emitting element LD during the first to fourth time periods t1, t2, t3, and t4. Referring to Formula 6, the driving current Id flowing through the light-emitting element LD during the fourth time period t4 can be unaffected by the threshold voltage (Vth) of the first transistor T1. Regardless of the characteristics of the first transistor T1, the driving current Id can be proportional to the square of the difference between the data signal Vdata and the first power supply ELVDD. Accordingly, from the display panel DP (see...) Figure 2 The output image IM can maintain uniform brightness. Correspondingly, the pixel PX-1ij and display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0172] For example, the voltage level of the second power supply ELVSS in the second power line PL2 may change due to voltage drop. However, according to the embodiment, through the first to fourth time periods t1, t2, t3, and t4, the second power supply ELVSS can not affect the drive current Id flowing through the light-emitting element LD. Referring to Formula 6, during the fourth time period t4, the drive current Id flowing through the light-emitting element LD can be unaffected by the second power supply ELVSS. Regardless of the voltage value of the second power supply ELVSS, the light-emitting element LD can be proportional to the square of the difference between the data signal Vdata and the first power supply ELVDD. Accordingly, from the display panel DP (see...) Figure 2 The output image IM can maintain uniform brightness. Correspondingly, the pixel PX-1ij and display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0173] Furthermore, according to an embodiment, the first transistor T1 can be an N-type transistor, and the cathode CTD of the light-emitting element LD can be connected (e.g., electrically connected) to the drain of the first transistor T1. For example, even if the light-emitting element LD deteriorates, the voltage at the source terminal of the first transistor T1, which affects the drive current Id, can remain unchanged. For example, even if the light-emitting element LD deteriorates, the gate-source voltage (Vgs) of the first transistor T1 can remain unchanged. Accordingly, although the usage time increases, the range of variation in the amount of current flowing through the first transistor T1 can be reduced, making the display panel DP (see...) more stable. Figure 2 Image retention defects (or long-term image retention defects) can be reduced, and the display panel DP (see...) Figure 2 The lifespan of the pixel PX-1ij and the display device DD (see [reference]) can be improved. Correspondingly, the pixel PX-1ij and the display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0174] Figure 10 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment, and Figure 11 This is a timing diagram illustrating the operation of a display device according to an embodiment. (See the following references.) Figure 10 In the description, the same reference numerals are assigned to the reference figures. Figure 9 The same parts are described, and for ease of description, their details will be omitted. For example, in the following references Figure 11 In the description, the same reference numerals are assigned to the reference figures. Figure 4 The same parts are described, and for ease of description, their details will be omitted.

[0175] refer to Figure 10 and Figure 11 The pixel PX-2ij may include a light-emitting element LD and a pixel driving circuit PC-2ij.

[0176] The pixel driving circuit PC-2ij may include a first transistor to a sixth transistor T1, T2, T3, T4, T5 and T6-1 and a first capacitor Cst.

[0177] The first electrode of the first transistor T1 can be connected (e.g., directly connected) to the first node N1.

[0178] According to the embodiment, the pixel PX-2ij can be referred to as having a 6T-1C structure.

[0179] According to an embodiment, in the light-emitting drive circuit EDC (see...) Figure 2 In the above, the first light emission control lines EML11 to EML1n, used to provide the first light emission signal to pixel PX-2ij (see...) Figure 2 The ) can be omitted. The non-display area NDA (see...) Figure 1 The area of ​​the pixel PX-2ij can be reduced. For example, the number of light-emitting control lines included in the pixel PX-2ij can be reduced. The spacing between the lines included in the pixel PX-2ij can be increased. Signal interference between the lines can be reduced. Accordingly, the pixel PX-2ij and the display device DD (see [link to display device]) have improved display quality. Figure 1 (This can be provided.)

[0180] According to an embodiment, the pixel driving circuit PC-2ij may have a slave pixel driving circuit PC-1ij (see...) Figure 9 The seventh transistor T7 is omitted in (see) Figure 9 The structure of the pixel driving circuit PC-2ij is described. According to an embodiment, the area of ​​the pixel driving circuit PC-2ij can be relatively reduced. The pixel density of the pixel PX-2ij can be increased. Accordingly, a pixel PX-2ij with improved display quality and a display device DD including the pixel PX-2ij can be provided.

[0181] Display panel DP (see) Figure 2 It can be operated in units of frame duration FP-1 to display the image IM (see Figure 1 The duration of any frame FP-1 can include the first to the fourth time periods t1-1, t2-1, t3-1, and t4-1.

[0182] The first to third time periods, t1-1, t2-1, and t3-1, can be referred to as non-light-emitting periods. For example, the first time period, t1-1, can be called the initialization period. The second time period, t2-1, can be called the compensation period. The third time period, t3-1, can be called the input period.

[0183] The fourth period, t4-1, can be referred to as the luminescent period.

[0184] During the first time period t1-1, the compensation scan signal GC and the second emission signal EM2 can have valid levels. The scan signal GW can have invalid levels.

[0185] Transistor T6-1 (6-1) can be turned on in response to the compensation scan signal GC. A first power supply ELVDD can be provided (or applied) to the first node N1 through transistor T6-1. The first node N1 can be charged with the first power supply ELVDD.

[0186] The third transistor T3 can be turned on in response to the compensation scan signal GC. The first power supply ELVDD can be supplied (or applied) to the third node N3 through the sixth transistor T6 and the third transistor T3. The third node N3 can be charged with the first power supply ELVDD.

[0187] During the first time period t1-1, the gate electrode of the first transistor T1 can be initialized to the first power supply ELVDD. For example, the voltage of the third node N3 can be changed from the data signal Vdata of the previous frame duration to the first power supply ELVDD.

[0188] The fifth transistor T5 can be turned on in response to the second light-emitting signal EM2. The second power supply ELVSS can be supplied (or applied) to the second node N2 through the fifth transistor T5. The second node N2 can be charged with the second power supply ELVSS.

[0189] The second time period t2-1 can occur after the first time period t1-1. During the second time period t2-1, the compensation scan signal GC can have an active level. The second emission signal EM2 and the scan signal GW can have inactive levels.

[0190] The first transistor T1 can be turned on in response to a first power supply ELVDD provided (or applied) to the gate electrode by the third transistor T3 and the sixth-first transistor T6-1.

[0191] During the second time period t2-1, the first transistor T1 can operate as a source follower. A voltage lower than the threshold voltage of the first transistor T1 that is supplied (or applied) to the third node N3 can be supplied (or applied) to the second node N2. The second node N2 can be charged to the voltage “ELVDD-Vth”.

[0192] The third time period t3-1 can occur after the second time period t2-1. During the third time period t3-1, the compensation scan signal GC and the scan signal GW can have active levels. The second emission signal EM2 can have inactive levels.

[0193] The second transistor T2 can be turned on in response to the scan signal GW. The data signal Vdata provided through the j-th data line DLj can be provided (or applied) to the fourth node N4.

[0194] The first capacitor Cst can be located between the second node N2 and the fourth node N4. The first capacitor Cst can store the differential voltage between the second node N2 and the fourth node N4. The voltage level at one terminal of the first capacitor Cst (e.g., the voltage level at the fourth node N4) can be changed to the voltage level of the data signal Vdata. For example, the voltage level at the opposite terminal of the first capacitor Cst (e.g., the voltage level at the second node N2) can be “ELVDD-Vth”. The first capacitor Cst can store the charge corresponding to the voltage difference “ELVDD-Vth-Vdata” between the second node N2 and the fourth node N4.

[0195] The fourth time period t4-1 can be performed after the third time period t3-1. During the fourth time period t4-1, the second emission signal EM2 can have an active level. The compensation scan signal GC and the scan signal GW can have inactive levels.

[0196] The fifth transistor T5 can be turned on in response to the second light-emitting signal EM2.

[0197] When the fifth transistor T5 is turned on, a current path can be formed from the first power line PL1 to the light-emitting element LD, the first transistor T1, the fifth transistor T5, and the second power line PL2. For example, the drive current Id can flow through the first power line PL1, the light-emitting element LD, the first transistor T1, the fifth transistor T5, and the second power line PL2.

[0198] The driving current Id of pixel PX-2ij can be calculated using formula 6.

[0199] Pixel PX (see Figure 2 The threshold voltage (Vth) of the first transistor T1 included in each of the following can be varied according to the characteristics of the first transistor T1. However, according to an embodiment, due to the first to fourth time periods t1-1, t2-1, t3-1, and t4-1, the threshold voltage (Vth) of the first transistor T1 may not affect the driving current Id flowing through the light-emitting element LD. Referring to Formula 6, the driving current Id flowing through the light-emitting element LD during the fourth time period t4 may be unaffected by the threshold voltage (Vth) of the first transistor T1. Regardless of the characteristics of the first transistor T1, the driving current Id can be proportional to the square of the difference between the data signal Vdata and the first power supply ELVDD. Accordingly, from the display panel DP (see...) Figure 2 The output image IM can maintain uniform brightness. Correspondingly, the pixel PX-2ij and display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0200] For example, the voltage level of the second power supply ELVSS in the second power line PL2 may change due to voltage drop. However, according to the embodiment, due to the first to fourth time periods t1-1, t2-1, t3-1, and t4-1, the second power supply ELVSS may not affect the drive current Id flowing through the light-emitting element LD. Referring to Formula 6, the drive current Id flowing through the light-emitting element LD during the fourth time period t4-1 may be unaffected by the second power supply ELVSS. Regardless of the voltage value of the second power supply ELVSS, the drive current Id can be proportional to the square of the difference between the data signal Vdata and the first power supply ELVDD. Accordingly, from the display panel DP (see...) Figure 2 The output image IM can maintain uniform brightness. Correspondingly, the pixel PX-2ij and display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0201] For example, according to an embodiment, the first transistor T1 may be an N-type transistor, and the cathode CTD of the light-emitting element LD may be connected (e.g., electrically connected) to the drain of the first transistor T1. For example, even if the light-emitting element LD deteriorates, the voltage at the source terminal of the first transistor T1, which affects the drive current Id, may not shift. For example, even if the light-emitting element LD deteriorates, the gate-source voltage (Vgs) of the first transistor T1 may not change. Accordingly, although the usage time increases, the range of variation in the amount of current flowing through the first transistor T1 can be reduced, making the display panel DP (see...) more stable. Figure 2 Image retention defects (or long-term image retention defects) can be reduced, and the display panel DP (see...) Figure 2The lifespan of the PX-2ij pixel and the display device DD (see [reference]) can be improved. Correspondingly, the PX-2ij pixel and the display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0202] Figure 12 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment. See the following reference... Figure 12 In the description, the same reference numerals are assigned to the reference figures. Figure 3 The same parts are described, and for ease of description, their details will be omitted.

[0203] refer to Figure 11 and Figure 12 The pixel PX-3ij may include a light-emitting element LD and a pixel driving circuit PC-3ij.

[0204] The pixel driving circuit PC-3ij may include a first transistor to a sixth transistor T1, T2, T3, T4, T5 and T6, and a first capacitor Cst.

[0205] The first electrode of the first transistor T1 can be connected (e.g., directly connected) to the first node N1.

[0206] According to the embodiment, the pixel PX-3ij can be referred to as having a 6T-1C structure.

[0207] According to an embodiment, the pixel driving circuit PC-3ij may have wherein the pixel driving circuit PCij (see...) Figure 3 The seventh transistor T7 is omitted in (see) Figure 9 The structure of ).

[0208] According to an embodiment, in the light-emitting drive circuit EDC (see...) Figure 2 In the above, the first light emission control lines EML11 to EML1n, used to provide the first light emission signal to pixel PX-3ij (see...) Figure 2 The ) can be omitted. The non-display area NDA (see...) Figure 1 The area of ​​the pixel PX-3ij can be reduced. For example, the number of light-emitting control lines included in the pixel PX-3ij can be reduced. The spacing between the lines included in the pixel PX-3ij can be increased. Signal interference between the lines can be reduced. Accordingly, the pixel PX-3ij and the display device DD (see [link to display device]) have improved display quality. Figure 1 (This can be provided.)

[0209] According to an embodiment, the pixel driving circuit PC-3ij may have wherein the pixel driving circuit PCij (see...) Figure 3 The seventh transistor T7 is omitted in (see) Figure 3The structure of the pixel driving circuit PC-3ij is described. According to an embodiment, the area of ​​the pixel driving circuit PC-3ij can be relatively reduced. The pixel density of the pixel PX-3ij can be increased. Accordingly, a pixel PX-3ij with improved display quality and a display device DD including the pixel PX-3ij can be provided.

[0210] The driving current Id of pixel PX-3ij can be calculated using formula 5.

[0211] Pixel PX (see Figure 2 The threshold voltage (Vth) of the first transistor T1 included in each of the following can be varied according to the characteristics of the first transistor T1. However, according to an embodiment, due to the first to fourth time periods t1-1, t2-1, t3-1, and t4-1, the threshold voltage (Vth) of the first transistor T1 may not affect the driving current Id flowing through the light-emitting element LD. Referring to Formula 5, the driving current Id flowing through the light-emitting element LD during the fourth time period t4-1 may be unaffected by the threshold voltage (Vth) of the first transistor T1. Regardless of the characteristics of the first transistor T1, the driving current Id can be proportional to the square of the difference between the data signal Vdata and the initialization voltage Vcint. Accordingly, from the display panel DP (see...) Figure 2 The output image IM can maintain uniform brightness. Correspondingly, the pixel PX-3ij and display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0212] The voltage level of the first power supply ELVDD in the first power supply line PL1 may change due to voltage drop. Similarly, the voltage level of the second power supply ELVSS in the second power supply line PL2 may change due to voltage drop. However, according to the embodiment, due to the first to fourth time periods t1-1, t2-1, t3-1, and t4-1, the first power supply ELVDD and the second power supply ELVSS may not affect the driving current Id flowing through the light-emitting element LD. Referring to Formula 5, the driving current Id flowing through the light-emitting element LD in the fourth time period t4-1 may be unaffected by the first power supply ELVDD and the second power supply ELVSS. Regardless of the voltage values ​​of the first power supply ELVDD and the second power supply ELVSS, the driving current Id can be proportional to the square of the difference between the data signal Vdata and the initialization voltage Vcint. Accordingly, from the display panel DP (see...) Figure 2 The output image IM can maintain uniform brightness. Correspondingly, the pixel PX-3ij and display device DD (see [reference]) have improved display quality. Figure 1 (This can be provided.)

[0213] Furthermore, according to an embodiment, the first transistor T1 can be an N-type transistor, and the cathode CTD of the light-emitting element LD can be connected (e.g., electrically connected) to the drain (or first electrode) of the first transistor T1. For example, even if the light-emitting element LD deteriorates, the voltage at the source terminal of the first transistor T1, which affects the drive current Id, can remain unchanged. For example, even if the light-emitting element LD deteriorates, the gate-source voltage (Vgs) of the first transistor T1 can remain unchanged. Accordingly, although the usage time increases, the range of variation in the amount of current flowing through the first transistor T1 can be reduced, making the display panel DP (see...) more stable. Figure 2 Image retention defects (or long-term image retention defects) can be reduced, and the display panel DP (see...) Figure 2 The lifespan of the PX-3ij pixel and the DD display device (see [reference]) can be increased. Correspondingly, the PX-3ij pixel and the DD display device have improved display quality. Figure 1 (This can be provided.)

[0214] Figure 13 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment. See the following reference... Figure 13 In the description, the same reference numerals are assigned to the reference figures. Figure 10 The same parts are described, and for ease of description, their details will be omitted.

[0215] refer to Figure 11 and Figure 13 The pixel PX-4ij may include a light-emitting element LD and a pixel driving circuit PC-4ij.

[0216] The pixel driving circuit PC-4ij may include first transistors to sixth transistors T1, T2, T3, T4, T5 and T6-1, as well as capacitors Cst and Chold.

[0217] Capacitors Cst and Chold can include a first capacitor Cst and a second capacitor Chold.

[0218] The second capacitor Chold can be connected between the fourth node N4 and the second power line PL2.

[0219] The first electrode of the first transistor T1 can be connected (e.g., directly connected) to the first node N1.

[0220] According to the embodiment, the pixel PX-4ij can be referred to as having a 6T-2C structure.

[0221] One electrode of the second capacitor Chold can be connected to the second power line PL2, which supplies the second power supply ELVSS, and the opposite electrode of the second capacitor Chold can be connected to the fourth node N4. The second capacitor Chold can store a charge corresponding to the voltage difference between the second power supply ELVSS and the fourth node N4. The second capacitor Chold can be referred to as a holding capacitor. The second capacitor Chold can have a higher capacitance than the first capacitor Cst. For example, the second capacitor Chold can have a higher storage capacity than the first capacitor Cst.

[0222] According to the embodiment, the pixel driving circuit PC-4ij may have, in addition to the pixel driving circuit PC-2ij (see...). Figure 10 In addition to the structure of the second capacitor Chold, it further includes the structure of the second capacitor Chold.

[0223] According to an embodiment, the second capacitor Chold can minimize the voltage change at the fourth node N4 in response to the voltage change at the second node N2. The reliability of the voltage supplied (or applied) to the third node N3 and the gate electrode of the first transistor T1 can be improved. Accordingly, the pixel PX-4ij with improved display quality and the display device DD including the pixel PX-4ij (see [link to embodiment]) are also improved. Figure 1 (This can be provided.)

[0224] Figure 14 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment. See the following reference... Figure 14 In the description, the same reference numerals are assigned to the reference figures. Figure 12 and Figure 13 The same parts will be described, and their details will be omitted.

[0225] refer to Figure 11 and Figure 14 The pixel PX-5ij may include a light-emitting element LD and a pixel driving circuit PC-5ij.

[0226] The pixel driving circuit PC-5ij may include first transistors to sixth transistors T1, T2, T3, T4, T5 and T6, as well as capacitors Cst and Chold.

[0227] Capacitors Cst and Chold can include a first capacitor Cst and a second capacitor Chold.

[0228] The second capacitor Chold can be connected between the fourth node N4 and the second power line PL2.

[0229] The first electrode of the first transistor T1 can be connected (e.g., directly connected) to the first node N1.

[0230] According to the embodiment, the pixel PX-5ij can be referred to as having a 6T-2C structure.

[0231] According to the embodiment, the pixel driving circuit PC-5ij may have features other than the pixel driving circuit PC-3ij (see also...). Figure 11 In addition to the structure of the second capacitor Chold, it further includes the structure of the second capacitor Chold.

[0232] In summarizing the detailed description, those skilled in the art will understand that various changes and modifications can be made to the embodiments without substantially departing from the principles, spirit, and scope of this disclosure. Therefore, the disclosed embodiments are for general and descriptive purposes only and are not intended to be limiting. Industrial applicability

[0233] According to one embodiment of the invention, regardless of the characteristics of the first transistor, the light-emitting element can be proportional to the square of the difference between the data signal and the initialization voltage. Accordingly, the brightness of the image output from the display panel can remain uniform. Therefore, the present invention, relating to pixels and display devices including pixel circuitry, has high industrial applicability.

Claims

1. A pixel comprising: a light emitting element connected between a first node and a first power supply line for supplying a first power supply; a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line for supplying a data signal, a second electrode electrically connected to a fourth node, and a gate electrode for receiving a scan signal; a third transistor including a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode for receiving a compensation scan signal; a fourth transistor including a first electrode electrically connected to the third node, a second electrode electrically connected to the fourth node, and a gate electrode for receiving a first emission signal; and a first capacitor connected between the second node and the fourth node.

2. The pixel according to claim 1, further comprising: a fifth transistor including a first electrode connected to the second node, a second electrode electrically connected to a second power supply line for supplying a second power supply having a voltage level lower than that of the first power supply, and a gate electrode for receiving the first emission signal.

3. The pixel according to claim 2, further comprising: a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to an initialization voltage line for supplying an initialization voltage, and a gate electrode for receiving the compensation scan signal.

4. The pixel according to claim 2, further comprising: a 6-1 transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first power supply line, and a gate electrode for receiving the compensation scan signal.

5. The pixel according to claim 3, further comprising: a seventh transistor including a first electrode connected to the first node, a second electrode connected to the first electrode of the first transistor, and a gate electrode for receiving a second emission signal.

6. The pixel according to claim 2, further comprising: a second capacitor connected between the fourth node and the second power supply line. the compensation scan signal and the first emission signal have an active level during a first period.

7. The pixel of claim 5, wherein, the first power supply is supplied to the third node during the first period.

8. The pixel of claim 7, wherein, the compensation scan signal and the second emission signal have an active level during a second period after the first period.

9. The pixel of claim 7, wherein, a voltage value obtained by subtracting a threshold voltage of the first transistor from the first power supply is supplied to the second node during the second period.

10. The pixel of claim 9, wherein, the scan signal has the active level during a third period after the second period.

11. The pixel of claim 9, wherein, the data signal is supplied to the fourth node during the third period.

12. The pixel of claim 11, wherein, the first emission signal and the second emission signal have an active level during a fourth period after the third period.

13. The pixel of claim 11, wherein, 14. A display device comprising: a display panel including a plurality of pixels, wherein each of the plurality of pixels includes: ​ a light emitting element connected between a first node and a first power supply line for supplying a first power supply; a first transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a second node, and a gate electrode electrically connected to a third node; a second transistor including a first electrode electrically connected to a data line for supplying a data signal, a second electrode electrically connected to a fourth node, and a gate electrode for receiving a scan signal; a third transistor including a first electrode connected to the first node, a second electrode connected to the third node, and a gate electrode for receiving a compensation scan signal; a fourth transistor including a first electrode connected to the third node, a second electrode connected to the fourth node, and a gate electrode for receiving a first light emitting signal; and a first capacitor connected between the second node and the fourth node.

15. The display device of claim 14, wherein, each of the plurality of pixels further includes: a fifth transistor including a first electrode connected to the second node, a second electrode electrically connected to a second power supply line for supplying a second power supply having a voltage level lower than a voltage level of the first power supply, and a gate electrode for receiving the first light emitting signal.

16. The display device of claim 15, wherein, each of the plurality of pixels further includes: a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to an initialization voltage line for supplying an initialization voltage, and a gate electrode for receiving the compensation scan signal.

17. The display device of claim 15, wherein, each of the plurality of pixels further includes: a 6-1 transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the first power supply line, and a gate electrode for receiving the compensation scan signal.

18. The display device of claim 16, wherein, each of the plurality of pixels further includes: a seventh transistor including a first electrode connected to the first node, a second electrode connected to the first electrode of the first transistor, and a gate electrode for receiving a second light emitting signal.

19. The display device of claim 15, wherein, each of the plurality of pixels further includes: a second capacitor connected between the fourth node and the second power supply line.

20. The display device of claim 18, wherein, the compensation scan signal and the first light emitting signal have active levels during a first period.

21. The display device of claim 20, wherein, the compensation scan signal and the second light emitting signal have active levels during a second period after the first period.

22. The display device of claim 21, wherein, the scan signal has an active level during a third period after the second period.

23. The display device of claim 22, wherein, the first light emitting signal and the second light emitting signal have active levels during a fourth period after the third period.

24. A pixel comprising: a light emitting element connected between a first node and a first power supply line for supplying a first power supply; a first transistor connected between the first node and a second node, the first transistor including a gate electrode electrically connected to a third node; a second transistor connected between a fourth node and a data line for supplying a data signal, the second transistor including a gate electrode for receiving a scan signal; a third transistor connected between the first node and the third node, the third transistor including a gate electrode for receiving a compensation scan signal; a fourth transistor connected between the third node and the fourth node, the fourth transistor including a gate electrode for receiving a first light emitting signal; and a first capacitor connected between the second node and the fourth node. a fourth transistor connected between the third node and the fourth node, the fourth transistor including a gate electrode for receiving a first emission signal; a fifth transistor connected between the second node and a second power supply line for supplying a second power supply having a voltage level lower than that of the first power supply, the fifth transistor including a gate electrode for receiving the first emission signal; and a sixth transistor connected between the first node and an initialization voltage line for supplying an initialization voltage, the sixth transistor including a gate electrode for receiving the compensation scan signal.

25. The pixel according to claim 24, further comprising: a first capacitor connected between the second node and the fourth node.

26. The pixel according to claim 25, further comprising: a seventh transistor connected between the first node and the first transistor, the seventh transistor including a gate electrode for receiving a second emission signal.

27. The pixel according to claim 26, further comprising: a second capacitor connected between the fourth node and the second power supply line.

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