Pattern generating device

Abstract

Provided is a pattern generation device, comprising: a timing generation unit for generating a clock signal; a data generation unit that generates multi-bit data for the generation of a multi-valued signal having a level of 3 or more; and a control unit that controls the generation of the data by the data generation unit. The control part outputs a trigger signal to trigger the generation of the data by the data generation part on the basis of the clock pulse signal; the data generation unit outputs the multi-bit data to at least one of a positive edge and a negative edge of the clock signal in accordance with the trigger signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a pattern generating apparatus. BACKGROUND

[0002] In Patent Literature 1, there is described a test apparatus for judging the good or bad of a memory element 10.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1 Japanese Patent Laid-Open No. 2004-30775

[0006] Patent Literature 2 Japanese Patent Laid-Open No. 2003-508758

[0007] Patent Literature 3 Japanese Patent Laid-Open No. Hei 8-211126 SUMMARY

[0008] In a first aspect of the present application, there is provided a pattern generating apparatus, comprising: a timing generating section generating a clock signal; a data generating section generating multi-bit data for generation of a multi-value signal having 3 or more levels; and a control section controlling generation of data by the data generating section; the control section outputting a trigger signal to trigger generation of data by the data generating section based on the clock signal; the data generating section outputting the multi-bit data for at least one of a rising edge and a falling edge of the clock signal in response to the trigger signal.

[0009] In the pattern generating apparatus, the data generating section can have a calculation data output section to output data based on a calculation instruction from the control section in response to the trigger signal.

[0010] In any of the pattern generating apparatuses, the calculation instruction can include an arithmetic algorithm. The calculation data output section can output algorithmic data in accordance with the arithmetic algorithm.

[0011] In any of the pattern generating apparatuses, the data generating section can have a stored data output section to output stored data in response to the trigger signal.

[0012] In any of the pattern generating apparatuses, the stored data output section can include a continuous data output section to output continuous data in response to the trigger signal.

[0013] In any of the pattern generating apparatuses, the storage data output section can include a plurality of data output sections to output data corresponding to the number of bits of the multi-bit data in response to the trigger signal.

[0014] In any of the pattern generating apparatuses, the plurality of data output sections can output data corresponding to the number of bits of the multi-value signal.

[0015] In any of the pattern generating apparatuses, the multi-value signal can be 4-level. The plurality of data output sections can output 2-bit data for each cycle of the clock signal.

[0016] In any of the pattern generating apparatuses, the data generating section can include a data selection section to select the output data from among the data output by the calculation data output section and the storage data output section.

[0017] In any of the pattern generating apparatuses, the data selection section can include a plurality of multiplexers to select the output data from among the data output by the calculation data output section and the storage data output section.

[0018] In any of the pattern generating apparatuses, the data selection section can use the plurality of multiplexers corresponding to the number of bits of the multi-bit data to select the output data.

[0019] In any of the pattern generating apparatuses, the multi-value signal can be 4-level. The data generating section can output 2-bit data for at least one of the positive and negative edges of the clock signal in response to the trigger signal.

[0020] In any of the pattern generating apparatuses, the multi-value signal can be 4-level. The data generating section can output 2-bit data for each of the positive and negative edges of the clock signal in response to the trigger signal.

[0021] In a second aspect of the present invention, a test apparatus is provided, including any of the pattern generating apparatuses.

[0022] In a third aspect of the invention, there is provided a pattern generation method, comprising: a stage of generating a clock signal by a computer; a stage of generating multi-bit data for generation of a multi-value signal having three or more levels by the computer; and a stage of controlling generation of the data by the computer; the stage of controlling generation of the data has a stage of outputting a trigger signal based on the clock signal to trigger generation of the data; the stage of generating the data has a stage of outputting the multi-bit data for at least one edge of a positive edge and a negative edge of the clock signal in response to the trigger signal.

[0023] In a fourth aspect of the invention, there is provided a program to be executed by a computer to cause the computer to function as: a timing generation section to generate a clock signal; a data generation section to generate multi-bit data for generation of a multi-value signal having three or more levels; and a control section to control generation of the data by the data generation section; the control section outputs a trigger signal based on the clock signal to trigger generation of the data by the data generation section; and the data generation section outputs the multi-bit data for at least one edge of a positive edge and a negative edge of the clock signal in response to the trigger signal.

[0024] In addition, the above summary of the invention does not list all the features of the invention. Also, sub-combinations of these groups of features can also be inventions. BRIEF DESCRIPTION OF DRAWINGS

[0025] [ Figure 1 ]An example of the structure of the test device 100 is shown together with the test element 10.

[0026] [ Figure 2 ]An example of the structure of the pattern generation device 20 is shown.

[0027] [ Figure 3A ]An example of the output of the data DAT by the data generation section 24 is shown.

[0028] [ Figure 3B ]A variation of the output of the data DAT by the data generation section 24 is shown.

[0029] [ Figure 4 ]An example of the output of the data by the calculation data output section 240 is shown.

[0030] [ Figure 5A ]An example of the output of the data by the continuous data output section 244 is shown.

[0031] [ Figure 5B ]An example of the output of the data by the few data output section 246 is shown.

[0032] Figure 6 FIG. 7 shows an example of a change in output of data DAT performed by the data generation section 24.

[0033] Figure 7 FIG. 8 shows an example of generation of a multivalued signal performed by the waveform generation section 30.

[0034] Figure 8 FIG. 9 shows an example of a computer 1000 in which the present application can be embodied in its entirety or in part. DETAILED DESCRIPTION

[0035] Hereinafter, the present application will be described through embodiments of the application, but the following embodiments are not intended to limit the application with respect to the claims. Also, not all combinations of features described in the embodiments are necessary means for solving the problems of the application.

[0036] Figure 1 An example of the structure of the test device 100 is shown together with the test element 10. The test device 100 includes the pattern generation device 20, the waveform generation section 30, the input section 40, the acquisition section 50, and the determination section 60, to test the test element 10 such as an analog circuit, a digital circuit, a memory, and a system on chip (SOC). The test device 100 inputs a test signal to the test element 10, and determines the quality of the test element 10 based on a response signal output from the test element 10 in response to the test signal.

[0037] The test signal can also be a multivalued signal having three or more levels. In this case, the test element 10 can be an element that can transmit a signal in a PAM (Pulse Amplitude Modulation) system. As an example, the test element 10 is a memory that can transmit a signal in a PAM 4 system. In this case, the test signal is a multivalued signal having four levels.

[0038] The pattern generation device 20 generates, through the data generation section 24 described later, multibit data DAT for generation of a multivalued signal having three or more levels. The multibit data can be data having more bits than one.

[0039] The waveform generation section 30 generates a multivalued signal DQ having three or more levels using the multibit data DAT generated by the pattern generation device 20. As an example, the pattern generation device 20 generates two-bit data DAT, and the waveform generation section 30 generates a multivalued signal DQ having four levels. The number of levels of the multivalued signal DQ generated by the waveform generation section 30 is not limited to this. The waveform generation section 30 can also generate a multivalued signal DQ having three levels, and can generate a multivalued signal DQ having five or more levels.​​​

[0040] The input section 40 generates a test signal based on the multivalued signal DQ generated by the waveform generation section 30, and inputs the test signal to the device under test 10. The acquisition section 50 acquires a response signal output by the device under test 10.

[0041] The determination section 60 compares the response signal of the device under test 10 acquired by the acquisition section 50 with a predetermined expected value signal. The determination section 60 determines the good or bad of the device under test 10 based on the comparison result of the response signal and the expected value signal.

[0042] Figure 2 An example of the structure of the pattern generation device 20 is shown. The pattern generation device 20 includes a control section 22, a data generation section 24, and a timing generation section 28.

[0043] The data generation section 24 generates data DAT of a number of bits used for generation of the multivalued signal DQ having 3 or more levels. The data generation section 24 can generate data DAT of a number of bits corresponding to the number of levels of the multivalued signal DQ. The data generation section 24 can generate data DAT of a number of bits corresponding to the number of levels of the multivalued signal DQ generated by the waveform generation section 30. As an example, in the case where the multivalued signal DQ has 4 levels, data DAT of 2 bits is generated by the data generation section 24.

[0044] The control section 22 controls generation of the data DAT by the data generation section 24. The timing generation section 28 generates a clock signal CLK. The control section 22 outputs a trigger signal TRIG to trigger generation of the data DAT by the data generation section 24 based on the clock signal CLK.

[0045] The data generation section 24 can have a calculation data output section 240, a storage data output section 242, and a data selection section 250.

[0046] The calculation data output section 240 can output data based on a calculation instruction from the control section 22 in response to the trigger signal TRIG. The calculation data output section 240 of this example outputs data Dl. Details of the output and calculation instruction of the data Dl by the calculation data output section 240 are described later.

[0047] The storage data output section 242 can output stored data in response to the trigger signal TRIG. The storage data output section 242 can be a register that stores data to be output, or a memory that stores data to be output. The structure of the storage data output section 242 is not limited to these. The storage data output section 242 can include a continuous data output section 244 and a few data output section 246.

[0048] The continuous data output section 244 can output continuous data in response to the trigger signal TRIG. The continuous data output section 244 of the present example outputs continuous data D2. The continuous data output section 244 can output continuous data D2 that is continuous by a predetermined number of data. For example, the continuous data output section 244 outputs continuous data D2 that is continuous by 16 times. The number of times of continuity of the continuous data D2 is not limited to this. Details of the output of the continuous data D2 by the continuous data output section 244 are described later.

[0049] The few data output section 246 can output data that is less continuous than the continuous data in response to the trigger signal TRIG. The few data output section 246 of the present example outputs data D3. For example, in the case where the number of times of continuity of the continuous data D2 is 16, the few data output section 246 outputs data D3 that is continuous by 4 times. The number of times of continuity of the data D3 is not limited to this. Details of the output of the data D3 by the few data output section 246 are described later.

[0050] In addition, the continuous data output section 244 and the few data output section 246 can be provided as independent different structures, or can be provided as the same configuration. For example, the number of times of continuity of the continuous data D2 output by the continuous data output section 244 or the number of times of continuity of the data D3 output by the few data output section 246 can be made changeable, whereby the operation of both the continuous data output section 244 and the few data output section 246 can be realized.

[0051] The data selection section 250 selects the data to be output from the data output by the calculation data output section 240 and the storage data output section 242. The data selection section 250 can select the data to be output from the data output by the calculation data output section 240, the continuous data output section 244, and the few data output section 246. The control section 22 can control the data selection section 250 so as to select the data to be output.

[0052] The data selection section 250 can include a plurality of multiplexers 252 to select the data to be output from the data output by the calculation data output section 240 and the storage data output section 242. The data selection section 250 can include a plurality of multiplexers 252 to select the data to be output from the data output by the calculation data output section 240, the continuous data output section 244, and the few data output section 246. The data selection section 250 of the present example includes four multiplexers 252. The number of multiplexers 252 included in the data selection section 250 can be three or less, or five or more.

[0053] The data selection section 250 can select data output using a number of multiplexers 252 corresponding to the number of bits of the multi-bit data DAT. For example, in a case where the number of bits of the multi-bit data DAT is 2, the data selection section 250 can select data output using 4 multiplexers 252.

[0054] The number of multiplexers 252 that the data selection section 250 has can be the same as and can be different from the number of multiplexers 252 used to select data output by the data selection section 250. That is, the data selection section 250 can have a number of multiplexers 252 corresponding to the number of bits of the multi-bit data DAT or more, and can select data output using some or all of the multiplexers 252.

[0055] Figure 3A An example of output of the data DAT by the data generation section 24 is shown. The data generation section 24 of this example generates multi-bit data DAT in an SDR (Single Data Rate) mode for performing data transfer at the positive edge of the clock signal CLK.

[0056] The data generation section 24 outputs multi-bit data DAT corresponding to the trigger signal TRIG at at least one edge of the positive edge and the negative edge of the clock signal CLK. The data generation section 24 of this example outputs multi-bit data DAT at the positive edge of the clock signal CLK.

[0057] In a case where the multi-value signal DQ is 4 levels, 2-bit data DAT can be output by the data generation section 24 corresponding to the trigger signal TRIG at at least one edge of the positive edge and the negative edge of the clock signal CLK. The data generation section 24 of this example outputs 2-bit data DAT at the positive edge of the clock signal CLK. As an example, the data generation section 24 outputs 2-bit data DAT represented in any one of "00", "01", "10", or "11".

[0058] The data generation section 24 can generate data DAT of a predetermined number of cycles corresponding to the trigger signal TRIG. The data generation section 24 of this example generates multi-bit data DAT of 4 cycles corresponding to the trigger signal TRIG. That is, the data generation section 24 of this example generates multi-bit data DAT at each of the positive edges of 4 cycles. The data generation section 24 can generate multi-bit data DAT of 3 cycles or less, and can generate multi-bit data DAT of 5 cycles or more.

[0059] Figure 3BThis example illustrates a variation in the output of the data DAT generated by the data generation unit 24. In this example, the data generation unit 24 generates a multi-bit data DAT in DDR (Double Data Rate) mode for data transmission at the positive and negative edges of the clock signal CLK. Figure 3A The implementation methods differ.

[0060] The data generation unit 24, corresponding to the trigger signal TRIG, outputs multi-bit data DAT for at least one edge of the positive and negative edges of the clock signal CLK. In this example, the data generation unit 24 outputs multi-bit data DAT for each edge of the positive and negative edges of the clock signal CLK.

[0061] When the multi-valued signal is at level 4, the data generation unit 24 can output 2 bits of data corresponding to the trigger signal TRIG and each edge of the positive and negative edges of the clock signal CLK. As an example, the data generation unit 24 outputs 2 bits of data DAT represented by any one of "00", "01", "10", or "11".

[0062] The data generation unit 24 can generate a predetermined number of data DAT cycles in response to the trigger signal TRIG. In this example, the data generation unit 24 generates a multi-bit data DAT with 2 cycles in response to the trigger signal TRIG. That is, in this example, the data generation unit 24 generates a multi-bit data DAT for each positive edge and each negative edge of 2 cycles. The data generation unit 24 can generate a multi-bit data DAT with 1 cycle, or a multi-bit data DAT with 3 or more cycles.

[0063] As described above, in this example, the data generation unit 24 outputs a multi-bit data DAT for at least one edge of the positive and negative edges of the clock signal CLK. This allows for rapid testing of the device under test 10 operating with PAM-type signal transmission. Alternatively, the data generation unit 24 can output a single-bit data DAT for at least one edge of the positive and negative edges of the clock signal CLK, thus enabling testing of the device under test 10 operating with NRZ (Non-Return to Zero)-type signal transmission. In other words, by adjusting the number of bits in the output data DAT, the data generation unit 24 in this example can perform tests based on either NRZ or PAM-type signal transmission.

[0064] Figure 4This illustrates an example of data output by the calculation data output unit 240. The calculation data output unit 240 can output data by performing calculations based on calculation instructions from the control unit 22 in response to the trigger signal TRIG. The calculation instructions may include instructions for addition, subtraction, etc., of the data D1. The calculation data output unit 240 can perform calculations on the data D1 based on the calculation instructions to update the output data D1.

[0065] The calculation instructions may include a calculation algorithm. The calculation algorithm is an algorithm used to perform a predetermined series of calculations. The calculation data output unit 240 can output data based on the algorithm.

[0066] The calculation data output unit 240 can output data D1 in each cycle, corresponding to the number of bits of the multi-valued signal DQ. In this example, the calculation data output unit 240 outputs 2 bits of data in each cycle. In this case, the multi-valued signal DQ can be 4 levels.

[0067] Figure 5A This illustrates an example of data output by the continuous data output unit 244. The continuous data output unit 244 outputs continuous data in response to the trigger signal TRIG. The continuous data output unit 244 can output continuous data D2 with a predetermined number of consecutive occurrences. In this example, the continuous data output unit 244 outputs continuous data D2 with a number of consecutive occurrences of 16.

[0068] The continuous data output unit 244 can output continuous data D2 corresponding to the number of levels of the multi-value signal DQ in each cycle. In this example, the continuous data output unit 244 outputs 2 bits of data in each cycle. In this case, the multi-value signal DQ can be 4 levels.

[0069] The control unit 22 can specify a storage address AP as the starting address of the data D2 output by the continuous data output unit 244. The control unit 22 can specify any starting address. In this example, the control unit 22 specifies address A5 as the starting address. The continuous data output unit 244 can use the storage address AP specified by the control unit 22 as the starting address and output continuous data D2 with a predetermined number of consecutive iterations. In this example, the continuous data output unit 244 outputs continuous data D2 up to address A20, starting from address A5 specified by the control unit 22.

[0070] Figure 5B This illustrates an example of data output by the minority data output unit 246. The minority data output unit 246 can output data with fewer consecutive occurrences than continuous data in response to the trigger signal TRIG. In this example, the minority data output unit 246 outputs data D3 with 4 consecutive occurrences, which is fewer than the 16 consecutive occurrences of continuous data D2.

[0071] The minority data output unit 246 can output data in bits corresponding to the number of levels of the multi-valued signal DQ. That is, the number of consecutive times the data D3 output by the minority data output unit 246 can correspond to the number of levels of the multi-valued signal DQ. In this example, the minority data output unit 246 outputs 2 bits of data. In this case, the multi-valued signal DQ can be 4 levels.

[0072] The minority data output unit 246 can output data D3 in each cycle, corresponding to the number of bits of the multi-value signal DQ. In this example, the minority data output unit 246 outputs 2 bits of data in each cycle. In this case, the multi-value signal DQ can be 4 levels. That is, the number of consecutive times the data D3 output by the minority data output unit 246 is consistent with the number of data output by the minority data output unit 246 in each cycle.

[0073] The control unit 22 can specify a storage address AP as the starting address of the data D3 output by the minority data output unit 246. The control unit 22 can specify any starting address. In this example, the control unit 22 specifies address A12 as the starting address in the first loop and address A4 as the starting address in the third loop. The minority data output unit 246 can use the storage address AP specified by the control unit 22 as the starting address and output data D3 with fewer consecutive occurrences compared to the consecutive data D2. In this example, the minority data output unit 246 outputs data D3 up to address A15 in the first loop using address A12 specified by the control unit 22 as the starting address, and outputs data D3 up to address A7 in the third loop using address A4 specified by the control unit 22 as the starting address.

[0074] As described above, the data generation unit 24 in this example has a stored data output unit 242, and is capable of generating continuous data starting from any arbitrary starting address. Therefore, compared to the case where the data generation unit 24 only has a calculated data output unit 240, it can output arbitrary data that is not limited to a calculation algorithm. Since the data generation unit 24 in this example can output arbitrary data, the degree of freedom in testing the test element 10, which operates via PAM signal transmission, can be increased.

[0075] Furthermore, the storage data output unit 242 in this example includes a continuous data output unit 244 and a few-data output unit 246, thus enabling the output of arbitrary data with different consecutive counts. This increases the degree of freedom in testing the test element 10, which operates via PAM signal transmission.

[0076] Figure 6This example illustrates a variation in the output of data DAT generated by the data generation unit 24. In this example, data D1 output by the calculation data output unit 240, data D2 output by the continuous data output unit 244, data D3 output by the minority data output unit 246, and data DAT output by the data generation unit 24 are represented together with the clock signal CLK. In this example, the data generation unit 24 generates 2-bit data DAT for each edge of the positive and negative edges of the clock signal CLK. Furthermore, the storage address AP is omitted in this example.

[0077] The data selection unit 250 can select output data from the data output by the calculation data output unit 240 and the storage data output unit 242. The data selection unit 250 can also select output data from the data output by the calculation data output unit 240, the continuous data output unit 244, and the minority data output unit 246. The control unit 22 controls the data selection unit 250 to select the output data.

[0078] In this example, the selected data is indicated by a thick box. In this example, the data selection unit 250 selects data D1 output by the calculated data output unit 240 as output data DAT in the first and third cycles, selects data D2 output by the continuous data output unit 244 as output data DAT in the second cycle, and selects data D3 output by the minority data output unit 246 as output data DAT in the fourth cycle. The data selection unit 250 can use multiple multiplexers 252 to select the output data DAT.

[0079] For the positive edge of the first cycle, the data generation unit 24 outputs two bits of data "01" corresponding to the first half of the data D1 selected by the data selection unit 250; for the negative edge of the first cycle, it outputs two bits of data "10" corresponding to the second half of the data D1 selected by the data selection unit 250. For the positive edge of the second cycle, the data generation unit 24 outputs two bits of data "01" corresponding to the first half of the data D2 selected by the data selection unit 250; for the negative edge of the second cycle, it outputs two bits of data "11" corresponding to the second half of the data D2 selected by the data selection unit 250.

[0080] For the positive edge of the third cycle, the data generation unit 24 outputs two bits of data "00" corresponding to the first half of the data D1 selected by the data selection unit 250; for the negative edge of the third cycle, it outputs two bits of data "11" corresponding to the second half of the data D1 selected by the data selection unit 250. For the positive edge of the fourth cycle, the data generation unit 24 outputs two bits of data "00" corresponding to the first half of the data D3 selected by the data selection unit 250; for the negative edge of the fourth cycle, it outputs two bits of data "01" corresponding to the second half of the data D3 selected by the data selection unit 250.

[0081] As described above, in this example, the data generation unit 24 outputs multi-bit data DAT for at least one edge of the positive and negative edges of the clock signal CLK. This allows for rapid testing of the test element 10, which operates via signal transmission in PAM format.

[0082] In this example, the data selection unit 250 selects any one of the following data for each loop: data D1 output by the calculation data output unit 240, data D2 output by the continuous data output unit 244, and data D3 output by the minority data output unit 246. The data selection method performed by the data selection unit 250 is not limited to this. The data selection unit 250 may also select a combination of data D1 output by the calculation data output unit 240, data D2 output by the continuous data output unit 244, and data D3 output by the minority data output unit 246 for each loop.

[0083] Figure 7 This example illustrates the generation of a multi-valued signal DQ by the waveform generation unit 30. The waveform generation unit 30 uses multi-bit data DAT generated by the graphics generation device 20 to generate a multi-valued signal DQ with a level of 3 or more. In this example, the waveform generation unit 30 uses 2-bit data DAT generated by the graphics generation device 20 to generate a multi-valued signal DQ with a level of 4. The waveform generation unit 30 can generate a waveform corresponding to the level of the data generated by the graphics generation device 20.

[0084] In this example, the generated waveforms are represented by thick lines. For the positive edge of the first cycle, the waveform generation unit 30 generates a waveform corresponding to the first level of the data "01" generated by the graphics generation device 20; for the negative edge of the first cycle, it generates a waveform corresponding to the second level of the data "10" generated by the graphics generation device 20. For the positive edge of the second cycle, the waveform generation unit 30 generates a waveform corresponding to the first level of the data "01" generated by the graphics generation device 20; for the negative edge of the second cycle, it generates a waveform corresponding to the third level of the data "11" generated by the graphics generation device 20.

[0085] For the positive edge of the third cycle, the waveform generation unit 30 generates a waveform corresponding to the zero level of the data "00" generated by the graphics generation device 20; for the negative edge of the third cycle, it generates a waveform corresponding to the third level of the data "11" generated by the graphics generation device 20. For the positive edge of the fourth cycle, the waveform generation unit 30 generates a waveform corresponding to the zero level of the data "00" generated by the graphics generation device 20; for the negative edge of the fourth cycle, it generates a waveform corresponding to the first level of the data "01" generated by the graphics generation device 20.

[0086] As described above, the pattern generating device 20 in this example outputs multi-bit data DAT for at least one edge of the positive and negative edges of the clock signal CLK. Therefore, the waveform generating unit 30 can generate a multi-valued signal DQ with a level of 3 or higher, enabling rapid testing of the test element 10, which operates via PAM signal transmission.

[0087] Various embodiments of the present invention may be described with reference to flowcharts and block diagrams, wherein a block may be represented as (1) a stage of a program performing an operation or (2) a segment of a device having a task of performing an operation. Specific stages and segments may be constructed by dedicated circuitry, programmable circuitry supplied together with computer-readable instructions stored on a computer-readable medium, and / or a processor supplied together with computer-readable instructions stored on a computer-readable medium. Dedicated circuitry may include digital and / or analog hardware circuitry, and may include integrated circuits (ICs) and / or discrete circuitry. Programmable circuitry includes memory components such as AND, OR, XOR, NAND, NOR, and other logic operations, flip-flops, registers, field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), etc., and may include reconfigurable hardware circuitry.

[0088] Computer-readable media may contain any tangible element capable of storing instructions executable by suitable elements. As a result, a computer-readable medium having instructions stored therein comprises a product containing instructions configured to perform and execute operations specified by a flowchart or block diagram. Examples of computer-readable media include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, etc. More specific examples of computer-readable media may include floppy disks (registered trademark), floppy diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), electrically erasable programmable read-only memory (EEPROM), static random-access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), Blu-ray (RTM (Release To Manufacturing)) discs, memory sticks, integrated circuit cards, etc.

[0089] Computer-readable instructions may include any of the following: assembly language instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode instructions, firmware instructions, state setting data, or source code or object code written in Smalltalk (registered trademark), JAVA (registered trademark), or a combination of one or more existing programming languages ​​including object-oriented programming languages ​​such as C++, and the "C" programming language or similar programming languages.

[0090] Computer-readable instructions (CMIs) can be provided to the processor or programmable circuitry of a programmable data processing device such as a computer via a local area network (LAN) or a wide area network (WAN). These CMIs execute the instructions to create a means for performing operations specified by a flowchart or block diagram. Here, a computer can be a PC (Personal Computer), tablet computer, smartphone, workstation, server computer, general-purpose computer, or special-purpose computer, or a computer system composed of multiple connected computers. Such a computer system composed of multiple connected computers is also called a distributed computer system, which is a broad definition of a computer. In a distributed computer system, multiple computers each execute a part of a program, and data is transferred between computers as needed during program execution, thereby enabling the aggregation of multiple computers to execute the program.

[0091] Examples of processors include computer processors, central processing units (CPUs), processing units, microprocessors, digital signal processors, controllers, and microcontrollers. A computer may include one or more processors. In a multiprocessor system with multiple processors, each processor executes a portion of a program individually, and data is transferred between processors as needed during program execution, thereby enabling multiple processors to execute the program. For example, in multi-tasking, multiple processors perform task switching at each time slot to subdivide and execute each part of the task. In this case, which part of a program is executed by each processor changes dynamically. Alternatively, which part of the program is executed by multiple processors can be statically defined by recognizing the programming nature of the multiprocessor system.

[0092] Figure 8 This describes an example of a computer 1000 that can embody various aspects of the present invention, either wholly or partially. A program installed on the computer 1000 functions as an operation of a device associated with an embodiment of the present invention, or performs one or more sections of that device, and / or executes a program associated with an embodiment of the present invention on the computer 1000. Such a program can be executed by the CPU 1012 to perform specific operations associated with several or all of the blocks in the flowcharts or block diagrams described in this specification.

[0093] The computer 1000 of this embodiment includes a CPU 1012, RAM 1014, an image controller 1016, and a display element 1018, which are interconnected via a host controller 1010. The computer 1000 also includes input / output units such as a communication interface 1022, a hard disk drive 1024, a DVD-ROM drive 1026, and an IC card driver, which are connected to the host controller 1010 via an input / output controller 1020. Furthermore, the computer includes conventional input / output units such as a ROM 1030 and a keyboard 1042, which are connected to the input / output controller 1020 via an input / output chip 1040.

[0094] The CPU 1012 operates according to the program stored in the ROM 1030 and RAM 1014, and thereby controls each unit. The image controller 1016 obtains image data generated by the CPU 1012 from the frame buffer or other storage provided in the RAM 1014 or from itself, and sets the image data to be displayed on the display element 1018.

[0095] Communication interface 1022 communicates with other electronic components via a network. Hard disk drive 1024 stores programs and data used by CPU 1012 within computer 1000. DVD-ROM drive 1026 reads programs or data from DVD-ROM 1027 and provides programs or data to hard disk drive 1024 via RAM 1014. IC card drive reads programs and data from IC card and / or writes programs and data to IC card.

[0096] The ROM 1030 stores the boot program executed by the computer 1000 when the computer is started, and / or programs compatible with the hardware of the computer 1000. Furthermore, the input / output chip 1040 connects various input / output units to the input / output controller 1020 via parallel ports, serial ports, keyboards, mouse pads, etc.

[0097] The program is provided by a computer-readable medium such as a DVD-ROM 1027 or an IC card. The program is read from the computer-readable medium, installed in a hard disk drive 1024, RAM 1014, or ROM 1030 (also examples of computer-readable media), and executed by the CPU 1012. The information processing described within this program is read into the computer 1000, establishing a connection between the program and the various types of hardware resources. The apparatus or method can be configured to perform operations or processing based on information used by the computer 1000.

[0098] For example, in the case of communication between computer 1000 and external components, CPU 1012 can execute a communication program loaded in RAM 1014, and based on the processing described in the communication program, issue instructions to communication interface 1022 to perform communication processing. Under the control of CPU 1012, communication interface 1022 reads transmission data stored in the transmission buffer processing area provided in recording media such as RAM 1014, hard disk drive 1024, DVD-ROM 1027, or IC card, and transmits the read transmission data to the network, or writes received data received from the network into the receive buffer processing area provided on the recording media.

[0099] Furthermore, the CPU 1012 can read all or a portion of files or databases stored on external recording media such as the hard disk drive 1024, DVD-ROM drive 1026 (DVD-ROM 1027), and IC card into the RAM 1014, and perform various types of processing on the data in the RAM 1014. The CPU 1012 then writes the processed data back to the external recording media.

[0100] Various types of information, such as programs, data, tables, and databases, can be stored in recording media and processed. The CPU 1012 performs various types of processing on data read from RAM 1014, including operations, information processing, conditional judgments, conditional divergences, unconditional divergences, information retrieval / replacement, etc., specified by the program's instruction sequence as described throughout this disclosure, and writes the results back to RAM 1014. Furthermore, the CPU 1012 can retrieve information from files, databases, etc., within the recording media. For example, when multiple input entries, each having an attribute value of a first attribute that is additionally associated with a second attribute, are stored in the recording media, the CPU 1012 retrieves an input entry from the multiple input entries that matches the condition specifying the attribute value of the first attribute, and reads the attribute value of the second attribute stored within that input entry, thereby obtaining the attribute value of the second attribute additionally associated with the first attribute satisfying a predetermined condition.

[0101] The described program or software module may be stored on computer 1000 or on a computer-readable medium near computer 1000. Alternatively, a recording medium such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet may be used as a computer-readable medium, thereby providing the program to computer 1000 via the network.

[0102] The present invention has been described above using embodiments, but the scope of the present invention is not limited to the scope described in the embodiments. Those skilled in the art will understand that various variations or modifications can be applied to the embodiments. It is clear from the claims that forms with such variations or modifications are also included within the scope of the present invention.

[0103] The order in which actions, procedures, steps, and stages are performed in the apparatus, system, program, and method shown in the claims, specification, and drawings should be noted. Unless specifically and explicitly stated as "preceding," "prior," or using a preceding process in a subsequent process, they can be performed in any order. Even if terms such as "firstly" or "next" are used for convenience in describing the flow of actions in the claims, specification, and drawings, this does not imply that they must be performed in this order.

[0104] Explanation of icon numbers

[0105] 10: Test Component

[0106] 20: Graphic generating device

[0107] 22: Control Department

[0108] 24: Data Generation Department

[0109] 28: Timing Generation Department

[0110] 30: Waveform Generation Section

[0111] 40: Input Section

[0112] 50: Obtaining Department

[0113] 60: Judgment Department

[0114] 100: Test apparatus

[0115] 240: Calculation Data Output Section

[0116] 242: Storage Data Output Section

[0117] 244: Continuous Data Output Section

[0118] 246: Minor Data Output Department

[0119] 250: Data Selection Department

[0120] 252: Multiplexer

[0121] 1000: Computer

[0122] 1010: Host Controller

[0123] 1012: CPU

[0124] 1014: RAM

[0125] 1016: Image Controller

[0126] 1018: Display Components

[0127] 1020: Input / Output Controller

[0128] 1022: Communication Interface

[0129] 1024: Hard Drive

[0130] 1026: DVD-ROM drive

[0131] 1027: DVD-ROM

[0132] 1030: ROM

[0133] 1040: Input / Output Chip

[0134] 1042: Keyboard

Claims

1. A pattern generating apparatus comprising: a timing generating section generating a clock signal; a data generating section generating a plurality of bits of data for generation of a multivalued signal having 3 or more levels; and a control section controlling generation of data by the data generating section; the control section outputting a trigger signal to trigger generation of data by the data generating section based on the clock signal; the data generating section outputting the plurality of bits of data corresponding to the trigger signal for at least one edge of a positive edge and a negative edge of the clock signal.

2. The pattern generating apparatus according to claim 1, wherein the data generating section has a calculation data output section to output data based on a calculation instruction from the control section to perform a calculation corresponding to the trigger signal.

3. The pattern generating apparatus according to claim 2, wherein the calculation instruction includes a calculation algorithm; the calculation data output section outputs data according to the algorithm of the calculation algorithm.

4. The pattern generating apparatus according to claim 2 or 3, wherein the data generating section has a stored data output section to output stored data corresponding to the trigger signal.

5. The pattern generating apparatus according to claim 4, wherein the stored data output section includes a continuous data output section to output continuous data corresponding to the trigger signal.

6. The pattern generating apparatus according to claim 5, wherein the stored data output section includes a few data output section to output data of a number less than a number of times of continuity of the continuous data corresponding to the trigger signal.

7. The pattern generating apparatus according to claim 6, wherein the few data output section outputs data of a number of bits corresponding to a number of levels of the multivalued signal.

8. The pattern generating apparatus according to claim 6 or 7, wherein the multivalued signal is 4-level; the few data output section outputs 2 bits of data per 1 cycle of the clock signal.

9. The pattern generating apparatus according to any one of claims 4 to 8, wherein the data generating section has a data selection section to select output data from data output by the calculation data output section and the stored data output section.

10. The pattern generating apparatus according to claim 9, wherein the data selection section includes a plurality of multiplexers to select output data from data output by the calculation data output section and the stored data output section.

11. The pattern generating apparatus according to claim 10, wherein the data selection section uses a number of the plurality of multiplexers corresponding to a number of bits of the plurality of bits of data to select output data.

12. The pattern generating apparatus according to any one of claims 1 to 11, wherein the multivalued signal is 4-level; the data generating section outputs 2 bits of data corresponding to the trigger signal for at least one edge of a positive edge and a negative edge of the clock signal.

13. The pattern generating apparatus according to any one of claims 1 to 12, wherein the multivalued signal is 4-level; The data generation section outputs 2-bit data corresponding to the trigger signal for each edge of the positive edge and the negative edge of the clock signal.

14. A test apparatus comprising the pattern generation apparatus according to any one of claims 1 to 13.

15. A pattern generation method comprising: a stage of generating, by a computer, a clock signal; a stage of generating, by the computer, multi-bit data for generation of a multi-value signal having 3 or more levels; and a stage of controlling, by the computer, generation of data; the stage of controlling generation of the data has a stage of outputting a trigger signal based on the clock signal to trigger generation of data; the stage of generating the data has a stage of outputting the multi-bit data corresponding to the trigger signal for at least one edge of the positive edge and the negative edge of the clock signal.

16. A program executed by a computer to cause the computer to function as: a clock generation section that generates a clock signal; a data generating section that generates a plurality of bits of data used for generation of a multivalued signal having 3 or more levels; and a control section that controls generation of data by the data generation section; the control section outputs a trigger signal based on the clock signal to trigger generation of data by the data generation section; the data generation section outputs the multi-bit data corresponding to the trigger signal for at least one edge of the positive edge and the negative edge of the clock signal.

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