Electronic component

Abstract

An electronic component includes: a cover object; an electrode disposed on the covering object and having an electrode side wall on the covering object; a wiring disposed around the electrode on the object to be covered; an insulating inorganic film that has an inner cover part that covers the electrode so as to expose the electrode side wall, and an outer cover part that covers the wiring line at a distance from the inner cover part; and an insulating organic film that extends across the inner cover portion and the outer cover portion and covers the electrode between the inner cover portion and the outer cover portion.

Description

Technical Field

[0001] This application claims priority to Japan Patent Application No. 2023-091948, filed on June 2, 2023, the entire contents of which are incorporated herein by reference. This disclosure relates to electronic components. Background Technology

[0002] Patent document 1 (US2019 / 0080976A1) discloses a semiconductor device comprising a semiconductor substrate, an interlayer insulating layer, electrodes, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has an opening that exposes the semiconductor substrate. Electrodes extend from the interlayer insulating layer into the opening and are electrically connected to the semiconductor substrate within the opening. The inorganic protective layer covers the edges of the electrodes. The organic protective layer covers the electrodes and the interlayer insulating layer through the inorganic protective layer.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2019-0080976 Summary of the Invention

[0006] This disclosure provides an electronic component with a novel layout.

[0007] This disclosure provides an electronic component comprising: a cover object; an electrode disposed on the cover object and having an electrode sidewall on the cover object; wiring disposed on the cover object around the electrode; an insulating inorganic film having an inner cover portion and an outer cover portion, wherein the inner cover portion covers the electrode in such a way that the electrode sidewall is exposed, and the outer cover portion covers the wiring portion spaced apart from the inner cover portion; and an insulating organic film spanning the inner cover portion and the outer cover portion and covering the electrode between the inner cover portion and the outer cover portion.

[0008] This disclosure provides an electronic component comprising: a terminal electrode; wiring disposed around the terminal electrode; an insulating inorganic film that covers the wiring at a distance from the terminal electrode; and an insulating organic film having a portion that directly covers the terminal electrode and a portion that covers the wiring through the inorganic film.

[0009] This disclosure provides an electronic component comprising: an electrode disposed in a first region having a first electric field; wiring disposed around the electrode in a second region having a second electric field higher than the first electric field; an insulating inorganic film exposing the electrode and covering the wiring; and an insulating organic film having a portion directly covering the electrode and a portion covering the wiring through the inorganic film.

[0010] This disclosure provides an electronic component comprising: a chip having a main surface; an active region disposed within the main surface; a peripheral region disposed at the periphery of the main surface; a device structure formed on the main surface in the active region; an impurity region formed on the surface portion of the main surface in the peripheral region; an electrode disposed on the main surface in the active region and electrically connected to the device structure; wiring disposed on the main surface in the peripheral region and electrically connected to the impurity region; an insulating inorganic film exposing the electrode and covering the wiring; and an insulating organic film having a portion directly covering the electrode and a portion covering the wiring through the inorganic film.

[0011] This disclosure provides an electronic component comprising: a cover object; a gate electrode disposed on the cover object and having an electrode sidewall thereon; a gate wiring disposed on the cover object around the gate electrode; an insulating inorganic film having an inner cover portion and an outer cover portion, wherein the inner cover portion covers the gate electrode in such a way that the electrode sidewall is exposed, and the outer cover portion covers the gate wiring spaced apart from the inner cover portion; and an insulating organic film spanning the inner cover portion and the outer cover portion, and covering the gate electrode between the inner cover portion and the outer cover portion.

[0012] This disclosure provides an electronic component comprising: a cover object; a source electrode disposed on the cover object and having an electrode sidewall thereon; a gate wiring disposed on the cover object around the source electrode; an insulating inorganic film having an inner cover portion and an outer cover portion, wherein the inner cover portion covers the source electrode in such a way that the electrode sidewall is exposed, and the outer cover portion covers the gate wiring spaced apart from the inner cover portion; and an insulating organic film spanning the inner cover portion and the outer cover portion, and covering the source electrode between the inner cover portion and the outer cover portion.

[0013] This disclosure provides an electronic component comprising: a cover object; a gate electrode disposed on the cover object and having an electrode sidewall thereon; a source wiring disposed on the cover object around the gate electrode; an insulating inorganic film having an inner cover portion and an outer cover portion, wherein the inner cover portion covers the gate electrode in such a way that the electrode sidewall is exposed, and the outer cover portion covers the source wiring spaced apart from the inner cover portion; and an insulating organic film spanning the inner cover portion and the outer cover portion, and covering the gate electrode between the inner cover portion and the outer cover portion.

[0014] The above or other objects, features, and effects become clear from the detailed description with reference to the accompanying drawings. Attached Figure Description

[0015] Figure 1 This is a top view of a semiconductor device.

[0016] Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown.

[0017] Figure 3 It is along Figure 1 The cross-sectional view along line III-III shown.

[0018] Figure 4 This is a top view showing an example layout of the first main surface.

[0019] Figure 5 This is an enlarged top view showing a major part of the active region.

[0020] Figure 6 It is along Figure 5 The sectional view along line VI-VI is shown.

[0021] Figure 7 It is along Figure 5 The sectional view along line VII-VII shown.

[0022] Figure 8 This is an enlarged top view showing a major part of the first side end region.

[0023] Figure 9 It is along Figure 8 The cross-sectional view of the IX-IX line shown.

[0024] Figure 10 It is along Figure 8 The sectional view shown is along line XX.

[0025] Figure 11 It is along Figure 8The sectional view of the XI-XI line shown.

[0026] Figure 12 It is along Figure 8 The cross-sectional view of line XII-XII shown.

[0027] Figure 13 This is an enlarged top view showing a major part of the first terminal area.

[0028] Figure 14 It is along Figure 13 The cross-sectional view of line XIV-XIV shown.

[0029] Figure 15 This is an enlarged top view showing a major part of the third terminal area.

[0030] Figure 16 It is along Figure 15 The cross-sectional view of the XVI-XVI line shown.

[0031] Figure 17 It is along Figure 1 A cross-sectional view of line XVII-XVII shown.

[0032] Figure 18 It is along Figure 1 The cross-sectional view of line XVIII-XVIII shown.

[0033] Figure 19 This is a top view showing an example of the layout of the main electrodes.

[0034] Figure 20 This is a top view showing a first layout example of the second inorganic membrane.

[0035] Figure 21 This is an enlarged top view showing a major part of the second inorganic membrane.

[0036] Figure 22A This is a cross-sectional view showing a second layout example of a second inorganic membrane.

[0037] Figure 22B This is a cross-sectional view showing a third layout example of the second inorganic membrane.

[0038] Figure 22C This is a cross-sectional view showing a fourth layout example of the second inorganic membrane.

[0039] Figure 22D This is a cross-sectional view showing a fifth layout example of the second inorganic membrane.

[0040] Figure 22E This is a cross-sectional view showing the sixth layout example of the second inorganic membrane.

[0041] Figure 22FThis is an enlarged top view showing the seventh layout example of the second inorganic membrane.

[0042] Figure 22G This is an enlarged top view showing the eighth layout example of the second inorganic membrane.

[0043] Figure 22H This is an enlarged top view showing the ninth layout example of the second inorganic membrane.

[0044] Figure 22I This is an enlarged top view of the tenth layout example of the second inorganic membrane.

[0045] Figure 22J This is an enlarged top view showing the eleventh layout example of the second inorganic membrane.

[0046] Figure 22K This is an enlarged top view of the twelfth layout example of the second inorganic membrane.

[0047] Figure 22L This is a cross-sectional view showing the thirteenth layout example of the second inorganic membrane.

[0048] Figure 22M This is a cross-sectional view showing the fourteenth layout example of the second inorganic membrane.

[0049] Figure 22N This is a cross-sectional view showing the fifteenth layout example of the second inorganic membrane.

[0050] Figure 22O This is a cross-sectional view showing the sixteenth layout example of the second inorganic membrane.

[0051] Figure 22P This is a cross-sectional view showing the seventeenth layout example of the second inorganic membrane.

[0052] Figure 22Q This is a cross-sectional view showing the eighteenth layout example of the second inorganic membrane.

[0053] Figure 22R This is a cross-sectional view showing the nineteenth layout example of the second inorganic membrane. Detailed Implementation

[0054] The specific methods are described in detail below with reference to the accompanying drawings. The drawings are schematic diagrams and not strictly schematic; relative positions, scales, proportions, angles, etc., may not be consistent. Corresponding structures in different drawings are labeled with the same reference numerals, and repeated descriptions are omitted or simplified. For structures where descriptions are omitted or simplified, the description preceding the omission or simplification applies.

[0055] When the term "substantially" is used in this specification, it includes not only the numerical value (morphology) that is equal to the numerical value (morphology) of the comparison object, but also a numerical error (morphological error) within a range of ±10% based on the numerical value (morphology) of the comparison object. In the following description, terms such as "first," "second," and "third" are used, but these are notations used to specify the order of description of each construction, and are not intended to limit the names of each construction.

[0056] In the following description, "p-type" or "n-type" is used to refer to the conductivity type of the semiconductor (impurity). "P-type" can also be called the "first conductivity type," and "n-type" the "second conductivity type." Conversely, "n-type" can also be called the "first conductivity type," and "p-type" the "second conductivity type." "P-type" is a conductivity type derived from trivalent elements, and "n-type" is a conductivity type derived from pentavalent elements. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0057] Figure 1 This is a top view showing semiconductor device 1 (electronic component). Figure 2 It is along Figure 1 The cross-sectional view along line II-II shown. Figure 3 It is along Figure 1 The cross-sectional view along line III-III shown. Figure 4 This is a top view showing an example layout of the first main surface 3. The semiconductor device 1 is a semiconductor switching device including an insulated-gate type transistor structure Tr. The transistor structure Tr can be called a MISFET structure (Metal Insulator Semiconductor Field Effect Transistor structure).

[0058] Reference Figures 1-4 In this embodiment, semiconductor device 1 includes a chip 2 comprising a single crystal of a wide-bandgap semiconductor, formed in a hexahedral shape (specifically a cuboid shape). That is, semiconductor device 1 is a "wide-bandgap semiconductor device". Chip 2 may also be referred to as a "semiconductor chip", "wide-bandgap semiconductor chip", etc.

[0059] A wide bandgap semiconductor is a semiconductor having a bandgap greater than that of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, chip 2 is a "SiC chip" comprising a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. That is, semiconductor device 1 is a "SiC semiconductor device".

[0060] Semiconductor device 1 can also be referred to as "SiC-MISFET". Hexagonal SiC single crystals have various polymorphs, including 2H (Hexagonal)-SiC single crystals, 4H-SiC single crystals, 6H-SiC single crystals, etc. In this embodiment, chip 2 is represented as an example containing 4H-SiC single crystals, but chip 2 can also contain other polymorphs.

[0061] Chip 2 has: a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are quadrilateral in shape when viewed from the vertical direction Z (hereinafter referred to as "top view"). The vertical direction Z is also the thickness direction of chip 2.

[0062] The first main surface 3 and the second main surface 4 are preferably formed from the c-plane of a SiC single crystal. In this case, it is preferred that the first main surface 3 is formed from the silicon surface ((0001) surface) of the SiC single crystal and the second main surface 4 is formed from the carbon surface ((000-1) surface) of the SiC single crystal.

[0063] First side surface 5A and second side surface 5B extend along a first direction X along the first main surface 3 and are opposite each other along the first main surface 3 in a second direction Y intersecting the first direction X. Specifically, the second direction Y is orthogonal to the first direction X. Third side surface 5C and fourth side surface 5D extend along the second direction Y and are opposite each other in the first direction X.

[0064] In this method, the first direction X is the a-axis direction of the SiC single crystal (directions [11-20]), and the second direction Y is the m-axis direction of the SiC single crystal (directions [1-100]). Alternatively, the first direction X can be the m-axis direction of the SiC single crystal, and the second direction Y can be the a-axis direction. Hereinafter, the direction extending along the first principal surface 3 will sometimes be represented as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, which is orthogonal to the vertical direction Z.

[0065] The first principal surface 3 and the second principal surface 4 may have a deviation angle that is tilted at a predetermined angle relative to the c-plane in a predetermined deviation direction. The deviation direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The deviation angle may exceed 0° and be less than 10°. The deviation angle is preferably less than 5°.

[0066] Chip 2 (first main surface 3 and second main surface 4) has a deviation angle that is tilted at a predetermined angle in a predetermined deviation direction relative to the c-plane of the SiC single crystal. That is, the amount of the deviation angle by which the c-axis ((0001) axis) of the SiC single crystal is tilted from the vertical line toward the deviation direction. In addition, the amount of the deviation angle by which the c-plane of the SiC single crystal is tilted relative to the horizontal plane.

[0067] The deviation direction is preferably the a-axis direction (i.e., the first direction X) of the SiC single crystal. The deviation angle can be greater than 0° and less than 10°. The deviation angle can have a value belonging to at least one of the following ranges: greater than 0° and less than 1°, greater than 1° and less than 2.5°, greater than 2.5° and less than 5°, greater than 5° and less than 7.5°, and greater than 7.5° and less than 10°.

[0068] The deviation angle is preferably 5° or less. Particularly preferred is a deviation angle of 2° or more but less than 4.5°. Typically, the deviation angle is set in the range of 4° ± 0.1°. This specification does not exclude a deviation angle of 0° (i.e., the first main surface 3 is facing the front relative to surface c).

[0069] Semiconductor device 1 includes an n-type first semiconductor region 6 formed on the surface portion of the second main surface 4 of chip 2. A drain potential, which is a first potential (high potential), is applied to the first semiconductor region 6. The first semiconductor region 6 may also be referred to as a "semiconductor layer", "first semiconductor layer", "drain region", etc. The first semiconductor region 6 is formed in a layered shape extending along the second main surface 4 and exposed from the second main surface 4 of chip 2 and the first to fourth side surfaces 5A to 5D of chip 2.

[0070] In this embodiment, the first semiconductor region 6 is composed of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is composed of a substrate (SiC substrate) containing a SiC single crystal (semiconductor single crystal), forming the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The first semiconductor region 6 (substrate) has the aforementioned offset direction and offset angle.

[0071] The first semiconductor region 6 may have a thickness of 10 μm or more and 500 μm or less. The thickness of the first semiconductor region 6 may have a value belonging to at least one of the following ranges: 10 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 300 μm or less, 300 μm or more and 400 μm or less, and 400 μm or more and 500 μm or less.

[0072] Semiconductor device 1 includes an n-type second semiconductor region 7 formed on the surface layer of a first main surface 3 of chip 2. The second semiconductor region 7 may also be referred to as a "semiconductor layer", "second semiconductor layer", "drift region", etc. The second semiconductor region 7 has an n-type impurity concentration that is lower than that of the first semiconductor region 6.

[0073] The second semiconductor region 7 is formed as a layer extending along the first main surface 3 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is exposed from the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. In this embodiment, the second semiconductor region 7 is composed of an n-type semiconductor layer.

[0074] In this embodiment, the second semiconductor region 7 is composed of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is composed of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal), forming the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The second semiconductor region 7 (epitaxy layer) has the aforementioned offset direction and offset angle.

[0075] The second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6. Of course, the thickness of the second semiconductor region 7 can also be greater than that of the first semiconductor region 6. The thickness of the second semiconductor region 7 can also be 5 μm or more and 50 μm or less.

[0076] The thickness of the second semiconductor region 7 may have a value belonging to at least one of the following ranges: 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, and 45 μm or more and 50 μm or less.

[0077] Semiconductor device 1 includes a first facet 8, a second facet 9, and first to fourth connecting facest 10A to 10D formed on a first main surface 3. The first facet 8, the second facet 9, and the first to fourth connecting facest 10A to 10D divide the first main surface 3 into mesa 11. The first facet 8, the second facet 9, and the first to fourth connecting facest 10A to 10D (i.e., mesa 11) can also be regarded as constituent elements of chip 2 (first main surface 3).

[0078] The first face 8 can also be called the "active surface", the second face 9 can be called the "outer surface", the first to fourth connecting faces 10A to 10D can be called the "connecting surface", and the platform 11 can be called the "active mesa".

[0079] The first facet 8 is formed at intervals from the periphery (first to fourth side surfaces 5A to 5D) of the first main facet 3 inwards. The first facet 8 has a flat surface extending in the horizontal direction and is formed by the c-surface (Si-surface). In this embodiment, the first facet 8 is formed as a polygon (specifically a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D when viewed from above. The planar area of ​​the first facet 8 is preferably 50% or more and 90% or less of the planar area of ​​the first main facet 3.

[0080] The second facet 9 is located on the peripheral side of the first main surface 3 relative to the first facet 8, and is recessed from the height of the first facet 8 toward the thickness direction of the chip 2 (towards the second main surface 4). When viewed from above, the second facet 9 extends in a strip along the first facet 8, forming a ring (specifically a four-sided ring) surrounding the first facet 8. The second facet 9 is connected to the first to fourth side surfaces 5A to 5D.

[0081] The second facet 9 is formed substantially parallel to the first facet 8 and has a flat surface extending in the horizontal direction. In this embodiment, the second facet 9 is formed from a c-plane (Si plane). The second facet 9 is formed in the second semiconductor region 7 at a distance from the first semiconductor region 6. That is, the second facet 9 is recessed to a depth less than the thickness of the second semiconductor region 7, exposing the second semiconductor region 7.

[0082] The second face 9 has a depth of 0.1 μm or more and 3 μm or less. The depth of the second face 9 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The depth of the second face 9 is preferably 1.5 μm or more and 2.5 μm or less.

[0083] The first to fourth connecting faces 10A to 10D extend in the vertical direction Z and connect with the first face 8 and the second face 9. The first connecting face 10A is located on the first side 5A, the second connecting face 10B is located on the second side 5B, the third connecting face 10C is located on the third side 5C, and the fourth connecting face 10D is located on the fourth side 5D. The first connecting face 10A and the second connecting face 10B extend in the first direction X and are opposite each other in the second direction Y. The third connecting face 10C and the fourth connecting face 10D extend in the second direction Y and are opposite each other in the first direction X.

[0084] Thus, the mesa 11 is divided into a protruding (convex) shape on the first main surface 3. The mesa 11 is formed only in the second semiconductor region 7 and not in the first semiconductor region 6. The first to fourth connecting surfaces 10A to 10D can also extend substantially perpendicularly between the first surface 8 and the second surface 9, dividing the mesa 11 into a quadrangular prism shape.

[0085] The first to fourth connecting faces 10A to 10D can be inclined downwards from the first face 8 toward the second face 9, dividing the area into a frustum-shaped platform 11. The first to fourth connecting faces 10A to 10D can also be inclined relative to the first face 8 at an angle greater than 90° and less than 135°.

[0086] Reference Figure 3 The semiconductor device 1 includes, on the first main surface 3, an active region 12, a first side end region 13, a second side end region 14, a first terminal region 15, a second terminal region 16, a third terminal region 17, a fourth terminal region 18, and a peripheral region 19.

[0087] The active region 12 is the region that contains the device structure (transistor structure Tr) and generates the output current (drain current). The active region 12 is located inside the first facet 8. Specifically, the active region 12 is located inside the first facet 8 at intervals from the periphery of the first facet 8 (the first to fourth connecting facets 10A to 10D). In this embodiment, the active region 12 is configured as a polygon (specifically a quadrilateral shape) with four sides parallel to the first to fourth facets 5A to 5D when viewed from above.

[0088] The active region 12 preferably occupies 50% or more and 95% or less in the first facial area 8. The proportion of the active region 12 can be any value within the range of 50% or more and 60% or more, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and 95% or less. The proportion of the active region 12 is preferably 70% or more.

[0089] The first side region 13 is disposed on one side (the third connecting face 10C side) of the first face 8 relative to the active area 12 in the first direction X, and is opposite to the active area 12 in the first direction X. In this embodiment, the first side region 13 extends in a strip shape in the second direction Y when viewed from above.

[0090] The second side region 14 is disposed on the opposite side of the active area 12 in the first face 8 in the first direction X (the fourth connecting face 10D side), and is opposite the first side region 13 in the first direction X, separated by the active area 12. In this configuration, the second side region 14 extends in a strip shape in the second direction Y when viewed from above.

[0091] The first terminal region 15 is disposed on one side of the active region 12 in the second direction Y (the side of the first connecting face 10A), and is opposite to the active region 12 in the second direction Y. In this embodiment, the first terminal region 15 extends in the first direction X when viewed from above, and is opposite to the first side end region 13 and the second side end region 14 in the second direction Y.

[0092] The second terminal region 16 is disposed on the other side of the active region 12 in the second direction Y (the side of the second connecting face 10B), and is opposite the first terminal region 15 in the second direction Y, separated by the active region 12. In this configuration, the second terminal region 16 extends in the first direction X when viewed from above, and is opposite the first side end region 13 and the second side end region 14 in the second direction Y, separated by the active region 12.

[0093] The third terminal region 17 is disposed on one side of the first terminal region 15 in the second direction Y (the side of the first connecting face 10A), and is opposite the active region 12 in the second direction Y, separated by the first terminal region 15. The third terminal region 17 is disposed in the area between the periphery of the first face 8 and the first terminal region 15. In this embodiment, the third terminal region 17 extends in a strip shape in the first direction X when viewed from above, and is opposite the first side end region 13 and the second side end region 14, separated by the first terminal region 15.

[0094] The fourth terminal region 18 is disposed on the opposite side of the second terminal region 16 in the second direction Y (the side of the second connecting face 10B), and is opposite the active region 12 in the second direction Y, separated by the second terminal region 16. The fourth terminal region 18 is disposed in the area between the periphery of the first face 8 and the third terminal region 17. In this configuration, the fourth terminal region 18 extends in a strip shape in the first direction X when viewed from above, and is opposite the first side end region 13 and the second side end region 14, separated by the second terminal region 16.

[0095] The peripheral region 19 is disposed as a non-active region on the second face surface 9. In this embodiment, the peripheral region 19 is configured as a ring (specifically a four-sided ring) surrounding the first face surface 8 (table surface 11) when viewed from above. That is, the peripheral region 19 surrounds the active region 12, the first side end region 13, the second side end region 14, the first terminal region 15, the second terminal region 16, the third terminal region 17, and the fourth terminal region 18 when viewed from above.

[0096] The structure of active region 12 will be described below. Figure 5 This is an enlarged top view showing a major part of the active region 12. Figure 6 It is along Figure 5 The sectional view along line VI-VI is shown. Figure 7 It is along Figure 5 The sectional view along line VII-VII shown.

[0097] Reference Figures 5-7 The semiconductor device 1 includes a p-type body region 20 formed in the surface portion of the first surface area 8 (first main surface 3) in the active region 12. The body region 20 may also be referred to as a "channel region," "substrate region," etc. A source potential, which is a second potential (low potential) different from the first potential (high potential), is assigned to the body region 20. The source potential can be a reference potential that serves as a reference for circuit operation. The reference potential can be a ground potential or a potential other than a ground potential.

[0098] The body region 20 is formed at intervals from the bottom of the second semiconductor region 7 toward the first surface region 8, and is opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 in between. The body region 20 is formed at intervals from the depth of the second surface region 9 toward the first surface region 8.

[0099] The body region 20 is formed in a layered manner extending along the first face 8. In this embodiment, the body region 20 is formed over the entire area of ​​the first face 8, exposed from the first to the fourth connecting faces 10A to 10D. Of course, the body region 20 may also be formed at intervals from the periphery of the first face 8 inward.

[0100] Semiconductor device 1 includes an n-type source region 21 (impurity region) formed in the surface portion of a first surface region 8 (first main surface 3) in an active region 12. A source potential is assigned to the source region 21. The source region 21 has an n-type impurity concentration that is higher than that of the second semiconductor region 7.

[0101] Source region 21 is formed on the surface portion of body region 20. Specifically, source region 21 is formed at intervals from the bottom of body region 20 toward the first surface portion 8. That is, source region 21 is formed relative to the area of ​​body region 20 formed on the first surface portion 8. Source region 21 forms a transistor channel with second semiconductor region 7 within body region 20.

[0102] In this configuration, source regions 21 are formed at intervals from the periphery of the first face 8 inwards. Therefore, source regions 21 are not exposed from the first to fourth connecting faces 10A to 10D. In this configuration, source regions 21 are formed only in the active region 12 and not in areas other than the active region 12.

[0103] Of course, the source region 21 can also be formed in at least one of the first side region 13, the second side region 14, the first terminal region 15, the second terminal region 16, the third terminal region 17, and the fourth terminal region 18, within a range that does not affect the electrical characteristics. Of course, the source region 21 can also be formed on the entire surface of the first face 8, exposed from the first to the fourth connecting faces 10A to 10D.

[0104] Semiconductor device 1 includes a plurality of trench-type (trench electrode type) gate structures 25 formed in an active region 12 on a first surface 8 (first main surface 3). The gate structures 25 may also be referred to as "trench structures" or "trench gate structures". A gate potential, serving as a control potential, is applied to the plurality of gate structures 25. The plurality of gate structures 25 control the inversion and non-inversion of the channel within the body region 20 in response to the gate potential.

[0105] Multiple gate structures 25 are spaced apart from the periphery of the first facet 8 (first to fourth connecting faces 10A to 10D) and are disposed inwardly on the first facet 8, dividing the interior of the first facet 8 into active regions 12. That is, the multiple gate structures 25 are formed only in the active regions 12, and are not formed in the first side end region 13, the second side end region 14, the first terminal region 15, the second terminal region 16, the third terminal region 17, and the fourth terminal region 18.

[0106] The plurality of gate structures 25 extend in a strip-like shape in the first direction X when viewed from above, and are arranged at intervals in the second direction Y. That is, the plurality of gate structures 25 are arranged in a stripe-like shape extending in the first direction X when viewed from above.

[0107] Multiple gate structures 25 penetrate the body region 20 and the source region 21 in a manner that reaches the second semiconductor region 7. That is, the body region 20 and the source region 21 are located on both sides of the multiple gate structures 25, respectively.

[0108] Multiple gate structures 25 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first surface region 8, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. In this configuration, the multiple gate structures 25 are formed substantially perpendicular to the first surface region 8. Of course, the multiple gate structures 25 can also be formed into a pointed shape toward the bottom of the second semiconductor region 7.

[0109] The sidewalls of the multiple gate structures 25 are formed from the m-plane ((1-100) plane) of the SiC single crystal. Of course, the sidewalls of the multiple gate structures 25 can also be formed from the a-plane ((11-20) plane) of the SiC single crystal, depending on the extension direction of the gate structure 25. The sidewalls of the multiple gate structures 25 are formed approximately perpendicular to the first main surface 3.

[0110] The bottom walls of the plurality of gate structures 25 are formed from the c-plane (Si plane) of a SiC single crystal. The bottom walls of the plurality of gate structures 25 preferably extend in a generally flat manner along the horizontal direction. Of course, the bottom walls of the plurality of gate structures 25 may also be curved in an arc shape toward the second main surface 4.

[0111] The tilt angle (absolute value) of the sidewall of the gate structure 25, referenced to a vertical line, can be 85° or more and 95° or less. The tilt angle can have a value belonging to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The tilt angle is preferably 87° or more and 93° or less.

[0112] The gate structure 25 may have a width of 0.1 μm or more and 3 μm or less. The width of the gate structure 25 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the width of the gate structure 25 is 0.5 μm or more and 2 μm or less.

[0113] The gate structure 25 preferably has a depth less than that of the second face 9. Of course, the depth of the gate structure 25 may be approximately equal to or greater than the depth of the second face 9.

[0114] The depth of the gate structure 25 can be 0.1 μm or more and 3 μm or less. The depth of the gate structure 25 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the gate structure 25 is 0.5 μm or more and 1.5 μm or less.

[0115] The structure of a gate structure 25 will be described below. The gate structure 25 includes a first trench 26, a first insulating film 27, and a first buried electrode 28. The first trench 26 is formed on the first surface 8, defining the walls (side walls and bottom walls) of the gate structure 25.

[0116] A first insulating film 27 covers the walls of the first trench 26. The first insulating film 27 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this embodiment, the first insulating film 27 has a single-layer structure composed of a silicon oxide film. The first insulating film 27 is particularly preferably composed of a silicon oxide film made of an oxide of the chip 2.

[0117] The first insulating film 27 includes a first film portion and a second film portion. The first film portion covers the sidewalls of the first trench 26 in a film-like form. The second film portion covers the bottom wall of the first trench 26 in a film-like form and is connected to the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.

[0118] The first insulating film 27 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the first insulating film 27 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0119] The first buried electrode 28 is buried in the first trench 26 through the first insulating film 27. The first buried electrode 28 may comprise one or both of p-type conductive polysilicon and n-type conductive polysilicon. The first buried electrode 28 is opposite to the trench through the first insulating film 27. That is, the first buried electrode 28 is opposite to the second semiconductor region 7, the body region 20, and the source region 21 through the first insulating film 27.

[0120] The first embedded electrode 28 has an electrode surface exposed from the first trench 26. The height position of the electrode surface of the first embedded electrode 28 relative to the first surface 8 is located on the bottom wall side of the first trench 26. The depth position of the electrode surface of the first embedded electrode 28 relative to the bottom of the body region 20 is located on the first main surface 3 side. The electrode surface of the first embedded electrode 28 has a groove that is recessed in a tapering shape towards the bottom wall side of the first trench 26.

[0121] Semiconductor device 1 includes a plurality of trench-type (trench electrode type) first source structures 30 formed on a first main surface 3 (first surface 8) in an active region 12. The first source structures 30 may also be referred to as "trench structure", "trench source structure", "first trench source structure", etc. A source potential is assigned to the plurality of first source structures 30.

[0122] Multiple first source structures 30 are formed in the active region 12 on the first surface area 8 in such a manner that they are adjacent to multiple gate structures 25 in the second direction Y. Specifically, the multiple first source structures 30 are respectively disposed in the regions between the multiple gate structures 25 and are opposite to the multiple gate structures 25 in the second direction Y. That is, the multiple first source structures 30 are alternately arranged with the multiple gate structures 25 in the second direction Y.

[0123] Multiple first source structures 30 extend in a strip-like shape in the first direction X when viewed from above. In this embodiment, the multiple first source structures 30 are led out from the active region 12 to one or both (in this embodiment, both) of the first side end region 13 and the second side end region 14. The multiple first source structures 30 are opposite to the gate structure 25 in the second direction Y in the active region 12, and are not opposite to the gate structure 25 in the second direction Y in the first side end region 13 (second side end region 14).

[0124] Multiple first source structures 30 are exposed from at least one of the third connecting face 10C and the fourth connecting face 10D. In this embodiment, the multiple first source structures 30 penetrate both the third connecting face 10C and the fourth connecting face 10D and are exposed from both the third connecting face 10C and the fourth connecting face 10D.

[0125] Multiple first source structures 30 penetrate the body region 20 and the source region 21 in a manner that reaches the second semiconductor region 7. That is, the body region 20 and the source region 21 are located on both sides of the multiple first source structures 30, respectively.

[0126] Multiple first source structures 30 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first face 8, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. In this embodiment, the multiple first source structures 30 are formed substantially perpendicular to the first face 8. Of course, the multiple first source structures 30 may also be formed into a pointed shape toward the bottom of the second semiconductor region 7.

[0127] The sidewalls of the multiple first source structures 30 are formed by the m-faces of the SiC single crystal, respectively. Of course, the sidewalls of the multiple first source structures 30 can also be formed by the a-faces of the SiC single crystal, respectively, according to the extension direction of the first source structure 30. The sidewalls of the multiple first source structures 30 are formed approximately perpendicular to the first main surface 3.

[0128] The bottom walls of the plurality of first source structures 30 are formed by the c-plane (Si plane) of a SiC single crystal. The bottom walls of the plurality of first source structures 30 preferably extend in a generally flat manner along the horizontal direction. Of course, the bottom walls of the plurality of first source structures 30 may also be curved in an arc shape toward the second main surface 4.

[0129] The tilt angle (absolute value) of the sidewall of the first source structure 30, based on a vertical line, can be 85° or more and 95° or less. The tilt angle can have a value belonging to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The tilt angle is preferably 87° or more and 93° or less.

[0130] The first source structure 30 preferably has a width larger than that of the gate structure 25. Of course, the width of the first source structure 30 may be approximately equal to or smaller than that of the gate structure 25.

[0131] The width of the first source structure 30 can be 0.1 μm or more and 3 μm or less. The width of the first source structure 30 can also have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the width of the first source structure 30 is 0.5 μm or more and 2 μm or less.

[0132] The first source structure 30 preferably has a depth greater than the depth of the gate structure 25. Of course, the depth of the first source structure 30 may be approximately equal to or less than the depth of the gate structure 25. The depth of the first source structure 30 preferably is approximately equal to the depth of the second facet 9. Of course, the depth of the first source structure 30 may be less than or greater than the depth of the second facet 9.

[0133] The ratio (depth ratio) of the depth of the first source structure 30 to the depth of the gate structure 25 is preferably 1 or more and 3 or less. The depth ratio may have a value belonging to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less. The depth ratio is preferably 1.5 or more and 2.5 or less.

[0134] The depth of the first source structure 30 can be 0.1 μm or more and 3 μm or less. The depth of the first source structure 30 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the first source structure 30 is 1.5 μm or more and 2.5 μm or less.

[0135] The structure of a first source structure 30 is described below. The first source structure 30 includes a second trench 31, a second insulating film 32, and a second embedded electrode 33. The second trench 31 is formed on the first facet 8, defining the walls (side walls and bottom walls) of the first source structure 30. The side walls of the second trench 31 are connected to one or both (in this embodiment, both) of the third connecting facet 10C and the fourth connecting facet 10D. The bottom wall of the second trench 31 is connected to the second facet 9.

[0136] The second insulating film 32 covers the wall of the second trench 31. The second insulating film 32 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the second insulating film 32 comprises the same insulating material as the insulating material of the first insulating film 27. In this embodiment, the second insulating film 32 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the second insulating film 32 comprises a silicon oxide film composed of the oxide of the chip 2.

[0137] The second insulating film 32 includes a first film portion and a second film portion. The first film portion covers the sidewalls of the second trench 31 in a film-like form. The second film portion covers the bottom wall of the second trench 31 in a film-like form and is connected to the first film portion.

[0138] The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion can be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the second insulating film 32 can also be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the second insulating film 32 can also be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0139] The second insulating film 32 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the second insulating film 32 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0140] The second embedded electrode 33 is embedded in the second trench 31 through the second insulating film 32. The second embedded electrode 33 may comprise one or both of p-type and n-type conductive polysilicon. Preferably, the second embedded electrode 33 comprises the same conductive material as the first embedded electrode 28. The second embedded electrode 33 is positioned opposite the second semiconductor region 7, the body region 20, and the source region 21 through the second insulating film 32.

[0141] The second embedded electrode 33 has an electrode surface exposed from the second trench 31. The height position of the electrode surface of the second embedded electrode 33 relative to the first surface 8 is located on the bottom wall side of the second trench 31. The depth position of the electrode surface of the second embedded electrode 33 relative to the bottom of the body region 20 is located on the second main surface 4 side. The electrode surface of the second embedded electrode 33 has a groove that is recessed in a pointed shape towards the bottom wall side of the second trench 31.

[0142] Semiconductor device 1 includes a plurality of p-type first well regions 35 formed on the surface portion of a first surface area 8 (first main surface 3) of active region 12 along a region of a plurality of gate structures 25. The first well regions 35 have a p-type impurity concentration that is higher than that of the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the first well regions 35 may also be lower than that of the p-type impurity concentration of the body region 20.

[0143] Multiple first well regions 35 are formed in a one-to-one correspondence with multiple gate structures 25. The multiple first well regions 35 are formed at intervals from the multiple first source structures 30 in regions along the corresponding gate structures 25.

[0144] Multiple first well regions 35 are formed along the sidewalls and bottom walls of the corresponding gate configuration 25, and are electrically connected to the body region 20 at the surface portion of the first face region 8. The multiple first well regions 35 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first face region 8, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. The multiple first well regions 35 and the second semiconductor region 7 form a pn junction.

[0145] Semiconductor device 1 includes a plurality of p-type second well regions 36 formed on the surface portion of a first surface region 8 (first main surface 3) of active region 12 along a region of a plurality of first source structures 30. The second well regions 36 have a p-type impurity concentration higher than that of the body region 20. However, the p-type impurity concentration of the second well regions 36 may also be lower than that of the body region 20. Preferably, the p-type impurity concentration of the second well regions 36 is approximately equal to that of the first well regions 35.

[0146] Multiple second well regions 36 are formed in a one-to-one correspondence with multiple first source structures 30. The multiple second well regions 36 are formed at intervals from the multiple gate structures 25 in regions along the corresponding first source structures 30.

[0147] Multiple second well regions 36 are formed along the sidewalls and bottom walls of the corresponding first source structure 30, and are electrically connected to the body region 20 at the surface portion of the first face 8. The multiple second well regions 36 extend along the walls of the corresponding first source structure 30 in the active region 12, the first side end region 13 and the second side end region 14, and are exposed from the third connection face 10C and the fourth connection face 10D.

[0148] A plurality of second well regions 36 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first surface region 8, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. The depth of the bottom of the plurality of second well regions 36 relative to the bottom of the plurality of first well regions 35 is located at the bottom side of the second semiconductor region 7. The plurality of second well regions 36 and the second semiconductor region 7 form a pn junction.

[0149] Semiconductor device 1 includes a plurality of p-type contact regions 37 formed on the surface portion of a first surface area 8 (first main surface 3) of active region 12 along a region of a plurality of first well regions 35. The contact regions 37 may also be referred to as "back gate regions". The contact regions 37 have a higher p-type impurity concentration than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the contact regions 37 is higher than the p-type impurity concentration of the first well regions 35 (second well regions 36).

[0150] Multiple contact regions 37 are formed within multiple second well regions 36. The multiple contact regions 37 extend along the wall of the corresponding first source structure 30 within the corresponding second well region 36. The multiple contact regions 37 are formed in a one-to-many correspondence with respect to a corresponding first source structure 30.

[0151] Multiple contact regions 37 are formed at intervals along the corresponding first source structure 30 in the first direction X. The multiple contact regions 37 are led out from the surface portion of the body region 20 along the wall of the corresponding first source structure 30 within the corresponding second well region 36 and exposed from the first face surface 8.

[0152] In this configuration, the plurality of contact areas 37 extend in a strip-like shape in the first direction X when viewed from above. The length of the plurality of contact areas 37 in the first direction X is preferably greater than the width of the first source structure 30 in the second direction Y. The length of the plurality of contact areas 37 is preferably greater than the distance between two adjacent contact areas 37 in the first direction X.

[0153] Multiple contact areas 37 along one first source configuration 30 are opposite to multiple contact areas 37 along other first source configurations 30 in the second direction Y. That is, in this configuration, the multiple contact areas 37 are arranged in a matrix at intervals in the first direction X and the second direction Y when viewed from above.

[0154] The multiple contact areas 37 along one first source structure 30 can also be staggered in the first direction X in a manner that is opposite to the regions between multiple contact areas 37 along other first source structures 30 in the second direction Y. That is, the multiple contact areas 37 can also be arranged in a staggered pattern as a whole in the first direction X and the second direction Y when viewed from above.

[0155] The structure of the first side region 13 will be described below. Figure 8 This is an enlarged top view showing a major part of the first side end region 13. Figure 9 It is along Figure 8 The cross-sectional view of the IX-IX line shown. Figure 10 It is along Figure 8 The sectional view shown is along line XX. Figure 11 It is along Figure 8 The sectional view of the XI-XI line shown. Figure 12It is along Figure 8 The cross-sectional view of line XII-XII shown.

[0156] The layout of the second side region 14 is the same as that of the first side region 13, therefore, the description of the layout of the second side region 14 is omitted. The layout of the second side region 14 is obtained by replacing "first side region 13" with "second side region 14" and "third connecting face 10C" with "fourth connecting face 10D" in the description of the first side region 13.

[0157] Reference Figures 8-12 The semiconductor device 1 includes a plurality of trench-type (trench electrode type) second source structures 40 formed on a first surface 8 (first main surface 3) in a first side end region 13. A source potential is assigned to the plurality of second source structures 40. The second source structure 40 may also be referred to as a "trench structure," "source side end structure," "trench source structure," "second trench source structure," etc.

[0158] Multiple second source structures 40 are respectively disposed in the region between the periphery of the first surface portion 8 (the third connecting surface portion 10C) and the multiple gate structures 25. The multiple second source structures 40 are respectively disposed in the regions between the multiple first source structures 30, and are opposite to the multiple first source structures 30 in the second direction Y. That is, the multiple second source structures 40 are alternately arranged with the multiple first source structures 30 in the second direction Y.

[0159] Multiple second source structures 40 are positioned in a one-to-one correspondence with multiple gate structures 25 in the first direction X, and together with the multiple gate structures 25, they divide multiple side-end islets. The multiple side-end islets are arranged in a row in the second direction Y. Of course, the multiple side-end islets can also be arranged staggered in one direction and another direction of the first direction X, without being closely opposite to other side-end islets in the second direction Y.

[0160] Multiple second source structures 40 extend in a strip-like shape in the first direction X when viewed from above. In this configuration, the multiple second source structures 40 penetrate the third connecting face 10C and are exposed from the third connecting face 10C. The multiple second source structures 40 penetrate the body region 20 in a manner that reaches the second semiconductor region 7. The multiple second source structures 40 are formed at intervals from the bottom of the second semiconductor region 7 toward the first face 8 and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7.

[0161] In this configuration, a plurality of second source structures 40 are formed approximately perpendicular to the first face 8. Of course, the plurality of second source structures 40 may also be formed in a pointed shape toward the bottom of the second semiconductor region 7.

[0162] The sidewalls of the multiple second source structures 40 are formed from the m-plane of the SiC single crystal, respectively. Of course, the sidewalls of the multiple second source structures 40 can also be formed from the a-plane of the SiC single crystal, respectively, according to the extension direction of the second source structures 40. The sidewalls of the multiple second source structures 40 are formed approximately perpendicular to the first main surface 3.

[0163] The bottom walls of the plurality of second source structures 40 are formed by the c-plane (Si plane) of a SiC single crystal. Preferably, the bottom walls of the plurality of second source structures 40 extend in a generally flat manner along the horizontal direction. Of course, the bottom walls of the plurality of second source structures 40 may also be curved in an arc shape toward the second main surface 4.

[0164] The tilt angle (absolute value) of the sidewall of the second source structure 40, referenced to a vertical line, can be 85° or more and 95° or less. The tilt angle can have a value belonging to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The tilt angle is preferably 87° or more and 93° or less.

[0165] The second source structure 40 preferably has a width larger than that of the gate structure 25. Of course, the width of the second source structure 40 can be approximately equal to or smaller than the width of the gate structure 25. The width of the second source structure 40 is preferably approximately equal to that of the first source structure 30.

[0166] The width of the second source structure 40 can be 0.1 μm or more and 3 μm or less. The width of the second source structure 40 can also have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the width of the second source structure 40 is 0.5 μm or more and 2 μm or less.

[0167] The second source structure 40 preferably has a depth greater than that of the gate structure 25. Of course, the depth of the second source structure 40 may be approximately equal to or less than the depth of the gate structure 25.

[0168] The depth of the second source structure 40 is preferably approximately equal to the depth of the second face 9. Of course, the depth of the second source structure 40 can be less than or greater than the depth of the second face 9. The depth of the plurality of second source structures 40 is preferably approximately equal to the depth of the plurality of first source structures 30.

[0169] The ratio (depth ratio) of the depth of the second source structure 40 to the depth of the gate structure 25 is preferably 1 or more and 3 or less. The depth ratio may have a value belonging to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less. The depth ratio is preferably 1.5 or more and 2.5 or less.

[0170] The depth of the second source structure 40 can also be 0.1 μm or more and 3 μm or less. The depth of the second source structure 40 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the second source structure 40 is 1.5 μm or more and 2.5 μm or less.

[0171] Multiple second source structures 40 and multiple gate structures 25 are arranged apart from each other by a first interval in a first direction X. The first interval is preferably more than 0.5 times and less than 2 times the width of the second source structures 40.

[0172] Multiple second source structures 40 are arranged at a second interval in the second direction Y, separated from the multiple source structures by a second space. The second space may also be approximately equal to the first space. The second space may be larger or smaller than the first space. Preferably, the second space is 0.5 times or more and less than 2 times the width of the second source structure 40.

[0173] The first gap (second gap) can be 0.1 μm or more and 3 μm or less. The first gap (second gap) can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. The first gap (second gap) is preferably 0.5 μm or more and 2 μm or less.

[0174] The structure of a second source structure 40 is described below. The second source structure 40 includes a third trench 41, a third insulating film 42, and a third embedded electrode 43. The third trench 41 is formed on the first surface 8, dividing the walls (side walls and bottom walls) of the second source structure 40. The side walls of the third trench 41 are connected to the third connecting surface 10C. The bottom wall of the third trench 41 is connected to the second surface 9.

[0175] The third insulating film 42 covers the wall of the third trench 41. The third insulating film 42 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the third insulating film 42 comprises the same insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the third insulating film 42 has a single-layer structure composed of a silicon oxide film. The third insulating film 42 is particularly preferably composed of a silicon oxide film composed of the oxide of the chip 2.

[0176] The third insulating film 42 includes a first film portion and a second film portion. The first film portion covers the sidewalls of the third trench 41 in a film-like form. The second film portion covers the bottom wall of the third trench 41 in a film-like form and is connected to the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion can be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the third insulating film 42 can also be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the third insulating film 42 can also be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0177] The third insulating film 42 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the third insulating film 42 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0178] The third embedded electrode 43 is embedded in the third trench 41 through the third insulating film 42. The third embedded electrode 43 may comprise one or both of p-type and n-type conductive polysilicon. Preferably, the third embedded electrode 43 comprises the same conductive material as the first embedded electrode 28 (second embedded electrode 33). The third embedded electrode 43 is positioned opposite the second semiconductor region 7 and the body region 20 through the third insulating film 42.

[0179] The third embedded electrode 43 has an electrode surface exposed from the third trench 41. The height position of the electrode surface of the third embedded electrode 43 relative to the first surface 8 is located on the bottom wall side of the third trench 41. The depth position of the electrode surface of the third embedded electrode 43 relative to the bottom of the body region 20 is located on the second main surface 4 side. The electrode surface of the third embedded electrode 43 has a groove that is recessed in a pointed shape towards the bottom wall side of the third trench 41.

[0180] Semiconductor device 1 includes a plurality of p-type third well regions 44 formed on the surface of a first facet 8 (first main facet 3) of a first side end region 13 along a region of a plurality of second source structures 40. The third well regions 44 have a p-type impurity concentration higher than that of the body region 20. However, the p-type impurity concentration of the third well regions 44 may also be lower than that of the body region 20. Preferably, the p-type impurity concentration of the third well regions 44 is approximately equal to that of the first well region 35 (second well region 36).

[0181] Multiple third well regions 44 are formed in a one-to-one correspondence with multiple second source structures 40. The multiple third well regions 44 are formed separately from the multiple first well regions 35 and the multiple second well regions 36 in regions along the corresponding second source structures 40. Alternatively, the multiple third well regions 44 can be formed integrally with the multiple first well regions 35. They can also be formed integrally with the multiple second well regions 36.

[0182] Multiple third well regions 44 are formed along the sidewalls and bottom walls of the corresponding second source structure 40, and are electrically connected to the body region 20 on the surface of the first face 8. The multiple third well regions 44 are exposed from the third connection face 10C.

[0183] A plurality of third well regions 44 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first surface region 8, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. The bottom of the plurality of third well regions 44 is located at a depth relative to the bottom of the plurality of first well regions 35 at the bottom side of the second semiconductor region 7. The bottom of the plurality of third well regions 44 is formed at a depth approximately equal to the bottom of the plurality of second well regions 36. The plurality of third well regions 44 and the second semiconductor region 7 form a pn junction.

[0184] The structure of the first terminal region 15 will be described below. Figure 13 This is an enlarged top view showing a major part of the first terminal area 15. Figure 14 It is along Figure 13 The cross-sectional view of line XIV-XIV shown.

[0185] The layout of the second terminal region 16 is the same as that of the first terminal region 15, therefore, the description of the layout of the second terminal region 16 is omitted. The layout of the second terminal region 16 is obtained by replacing "first terminal region 15" with "second terminal region 16" and "first connecting face 10A" with "second connecting face 10B" in the description of the first terminal region 15.

[0186] Semiconductor device 1 includes a plurality of dummy gate structures 50 of trench type (trench electrode type) formed on a first surface 8 (first main surface 3) in a first terminal region 15. The dummy gate structures 50 may also be referred to as "trench structure," "trench terminal structure," "gate terminal structure," "dummy trench structure," or "dummy trench gate structure." A source potential is assigned to the plurality of dummy gate structures 50. That is, the plurality of dummy gate structures 50 do not contribute to the inversion or non-inversion of the channel.

[0187] Multiple dummy gate structures 50 are formed in the region on the side of the first connection face 10A opposite to the active region 12. When viewed from above, the multiple dummy gate structures 50 extend in a stripe shape in the first direction X and are arranged at intervals in the second direction Y. That is, when viewed from above, the multiple dummy gate structures 50 are arranged in a stripe shape extending in the first direction X. The multiple dummy gate structures 50 are opposite to the multiple gate structures 25 and the multiple first source structures 30 in the second direction Y.

[0188] In this configuration, multiple dummy gate structures 50 are led out in the second direction Y to regions that are opposite to one or both (in this configuration, both) of the first side region 13 and the second side region 14, and are opposite to multiple second source structures 40 in the second direction Y.

[0189] Multiple dummy gate structures 50 are exposed from at least one of the third connection face 10C and the fourth connection face 10D. In this embodiment, the multiple dummy gate structures 50 penetrate both the third connection face 10C and the fourth connection face 10D and are exposed from both the third connection face 10C and the fourth connection face 10D.

[0190] Multiple dummy gate structures 50 penetrate the body region 20 to reach the second semiconductor region 7. The multiple dummy gate structures 50 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first face 8, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. In this configuration, the multiple dummy gate structures 50 are formed substantially perpendicular to the first face 8. Alternatively, the multiple dummy gate structures 50 may be formed in a pointed shape toward the bottom of the second semiconductor region 7.

[0191] The sidewalls of the multiple dummy gate structures 50 are each formed from the m-plane of a SiC single crystal. Alternatively, the sidewalls of the multiple dummy gate structures 50 can also be formed from the a-plane of a SiC single crystal, depending on the extension direction of the dummy gate structures 50. The sidewalls of the multiple dummy gate structures 50 are formed approximately perpendicular to the first main surface 3.

[0192] The bottom walls of the plurality of dummy gate structures 50 are formed from the c-plane (Si plane) of a SiC single crystal. The bottom walls of the plurality of dummy gate structures 50 preferably extend in a generally flat manner along the horizontal direction. Of course, the bottom walls of the plurality of dummy gate structures 50 may also be curved in an arc shape toward the second main surface 4.

[0193] The tilt angle (absolute value) of the sidewall of the dummy gate structure 50, referenced to a vertical line, can be 85° or more and 95° or less. The tilt angle can have a value belonging to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The tilt angle is preferably 87° or more and 93° or less.

[0194] The dummy gate structure 50 preferably has a width approximately equal to that of the gate structure 25. Of course, the width of the dummy gate structure 50 can be larger or smaller than the width of the gate structure 25. The width of the dummy gate structure 50 is preferably smaller than the width of the first source structure 30 (second source structure 40). Of course, the width of the dummy gate structure 50 can be approximately equal to or larger than the width of the first source structure 30 (second source structure 40).

[0195] The width of the dummy gate structure 50 can be 0.1 μm or more and 3 μm or less. The width of the dummy gate structure 50 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the width of the dummy gate structure 50 is 0.5 μm or more and 2 μm or less.

[0196] The depth of the dummy gate structure 50 is preferably less than the depth of the second facet 9. Of course, the depth of the dummy gate structure 50 can be approximately equal to or greater than the depth of the second facet 9. The dummy gate structure 50 preferably has a depth approximately equal to the depth of the gate structure 25. Of course, the depth of the dummy gate structure 50 can be greater than or less than the depth of the gate structure 25.

[0197] The depth of the dummy gate structure 50 is preferably less than the depth of the first source structure 30 (second source structure 40). Of course, the depth of the dummy gate structure 50 can be approximately equal to the depth of the first source structure 30 (second source structure 40), or it can be greater than the depth of the first source structure 30 (second source structure 40).

[0198] The depth of the dummy gate structure 50 can be 0.1 μm or more and 3 μm or less. The depth of the dummy gate structure 50 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the dummy gate structure 50 is 1.5 μm or more and 2.5 μm or less.

[0199] The structure of a dummy gate structure 50 will be described below. The dummy gate structure 50 includes a fourth trench 51, a fourth insulating film 52, and a fourth buried electrode 53. The fourth trench 51 is formed on the first face 8 and divides the walls (side walls and bottom walls) of the dummy gate structure 50.

[0200] A fourth insulating film 52 covers the wall of the fourth trench 51. The fourth insulating film 52 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the fourth insulating film 52 comprises the same insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the fourth insulating film 52 has a single-layer structure composed of a silicon oxide film. The fourth insulating film 52 is particularly preferably composed of a silicon oxide film composed of the oxide of the chip 2.

[0201] The fourth insulating film 52 includes a first film portion and a second film portion. The first film portion covers the sidewalls of the fourth trench 51 in a film-like shape. The second film portion covers the bottom wall of the fourth trench 51 in a film-like shape and is connected to the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion can be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the fourth insulating film 52 can be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the fourth insulating film 52 can also be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0202] The fourth insulating film 52 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the fourth insulating film 52 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0203] The fourth buried electrode 53 is buried in the fourth trench 51 through the fourth insulating film 52. The fourth buried electrode 53 may also comprise one or both of p-type and n-type conductive polysilicon. Preferably, the fourth buried electrode 53 comprises the same conductive material as the first buried electrode 28 (second buried electrode 33). The fourth buried electrode 53 is positioned opposite the second semiconductor region 7 and the body region 20 through the fourth insulating film 52.

[0204] The fourth embedded electrode 53 has an electrode surface exposed from the fourth trench 51. The height position of the electrode surface of the fourth embedded electrode 53 relative to the first surface 8 is located on the bottom wall side of the fourth trench 51. The depth position of the electrode surface of the fourth embedded electrode 53 relative to the bottom of the body region 20 is located on the first main surface 3 side. The electrode surface of the fourth embedded electrode 53 has a groove that is recessed in a pointed shape towards the bottom wall side of the fourth trench 51.

[0205] Semiconductor device 1 includes a plurality of trench-type (trench electrode type) third source structures 55 formed in a first terminal region 15 on a first surface 8 (first main surface 3). Source potentials are assigned to the plurality of third source structures 55. The third source structures 55 may also be referred to as "trench structure," "source terminal structure," "trench source structure," "third trench source structure," etc.

[0206] Multiple third source structures 55 are formed in the region on the first connection face 10A side relative to the active region 12. The multiple third source structures 55 are formed in the first terminal region 15 adjacent to the multiple dummy gate structures 50 in the second direction Y. Specifically, the multiple third source structures 55 are respectively disposed in the regions between the multiple dummy gate structures 50, and are opposite to the multiple dummy gate structures 50 in the second direction Y.

[0207] That is, multiple third source structures 55 are alternately arranged with multiple dummy gate structures 50 in the second direction Y. The multiple third source structures 55 extend in a strip shape in the first direction X when viewed from above. The multiple third source structures 55 are opposite to multiple gate structures 25 and multiple first source structures 30 in the second direction Y.

[0208] In this configuration, a plurality of third source structures 55 are led out in the second direction Y to a region opposite to one or both (in this configuration, both) of the first side region 13 and the second side region 14, and are opposite to a plurality of second source structures 40 in the second direction Y. In this configuration, the plurality of third source structures 55 are opposite to the plurality of second source structures 40 in the second direction Y, separated by a plurality of dummy gate structures 50.

[0209] Multiple third source structures 55 are exposed from at least one of the third connecting face 10C and the fourth connecting face 10D. In this embodiment, the multiple third source structures 55 penetrate both the third connecting face 10C and the fourth connecting face 10D and are exposed from both the third connecting face 10C and the fourth connecting face 10D.

[0210] Multiple third source structures 55 penetrate the body region 20 to reach the second semiconductor region 7. The multiple third source structures 55 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first face 8, and are opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. In this configuration, the multiple third source structures 55 are formed substantially perpendicular to the first face 8. Alternatively, the multiple third source structures 55 may be formed in a pointed shape toward the bottom of the second semiconductor region 7.

[0211] The sidewalls of the multiple third source structures 55 are formed from the m-faces of the SiC single crystal, respectively. Alternatively, the sidewalls of the multiple third source structures 55 can also be formed from the a-faces of the SiC single crystal, depending on the extension direction of the third source structure 55. The sidewalls of the multiple third source structures 55 are formed approximately perpendicular to the first main surface 3.

[0212] The bottom walls of the plurality of third source structures 55 are formed by the c-plane (Si plane) of a SiC single crystal. Preferably, the bottom walls of the plurality of third source structures 55 extend in a generally flat manner along the horizontal direction. Of course, the bottom walls of the plurality of third source structures 55 may also be curved in an arc shape toward the second main surface 4.

[0213] The tilt angle (absolute value) of the sidewall of the third source electrode structure 55, referenced to a vertical line, can be 85° or more and 95° or less. The tilt angle can have a value belonging to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The tilt angle is preferably 87° or more and 93° or less.

[0214] The third source structure 55 preferably has a width larger than that of the dummy gate structure 50. Of course, the width of the third source structure 55 can be approximately equal to or smaller than the width of the dummy gate structure 50. The width of the third source structure 55 is preferably approximately equal to the width of the first source structure 30 (second source structure 40). Of course, the width of the third source structure 55 can also be larger or smaller than the width of the first source structure 30 (second source structure 40).

[0215] The width of the third source structure 55 can be 0.1 μm or more and 3 μm or less. The width of the third source structure 55 can have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the width of the third source structure 55 is 0.5 μm or more and 2 μm or less.

[0216] The third source structure 55 preferably has a depth greater than that of the dummy gate structure 50 (gate structure 25). Of course, the depth of the third source structure 55 may be approximately equal to or less than that of the dummy gate structure 50 (gate structure 25).

[0217] The depth of the third source structure 55 is preferably approximately equal to the depth of the first source structure 30 (second source structure 40). Of course, the depth of the third source structure 55 may be less than or greater than the depth of the first source structure 30 (second source structure 40). The depth of the third source structure 55 is preferably approximately equal to the depth of the second face 9. Of course, the depth of the third source structure 55 may be less than or greater than the depth of the second face 9.

[0218] The depth ratio of the third source structure 55 to the depth of the gate structure 25 (dummy gate structure 50) is preferably 1 or more and 3 or less. The depth ratio may have a value belonging to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less. The depth ratio is preferably 1.5 or more and 2.5 or less.

[0219] The depth of the third source structure 55 can be 0.1 μm or more and 3 μm or less. The depth of the third source structure 55 can also have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the third source structure 55 is 1.5 μm or more and 2.5 μm or less.

[0220] The structure of a third source electrode structure 55 is described below. The third source electrode structure 55 includes a fifth trench 56, a fifth insulating film 57, and a fifth embedded electrode 58. The fifth trench 56 is formed on the first facet 8, dividing the walls (side walls and bottom walls) of the third source electrode structure 55. The side walls of the fifth trench 56 are connected to one or both (in this embodiment, both) of the third connecting facet 10C and the fourth connecting facet 10D. The bottom wall of the fifth trench 56 is connected to the second facet 9.

[0221] The fifth insulating film 57 covers the walls of the fifth trench 56. The fifth insulating film 57 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the fifth insulating film 57 comprises the same insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the fifth insulating film 57 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the fifth insulating film 57 comprises a silicon oxide film composed of the oxide of the chip 2.

[0222] The fifth insulating film 57 includes a first film portion and a second film portion. The first film portion covers the sidewalls of the fifth trench 56 in a film-like form. The second film portion covers the bottom wall of the fifth trench 56 in a film-like form and is connected to the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion can be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the fifth insulating film 57 can also be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the fifth insulating film 57 can also be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0223] The fifth insulating film 57 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the fifth insulating film 57 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0224] The fifth buried electrode 58 is buried in the fifth trench 56 through the fifth insulating film 57. The fifth buried electrode 58 may comprise one or both of p-type and n-type conductive polysilicon. Preferably, the fifth buried electrode 58 comprises the same conductive material as the first buried electrode 28 (second buried electrode 33). The fifth buried electrode 58 is positioned opposite the second semiconductor region 7 and the body region 20 through the fifth insulating film 57.

[0225] The fifth embedded electrode 58 has an electrode surface exposed from the fifth trench 56. The height position of the electrode surface of the fifth embedded electrode 58 relative to the first surface 8 is located on the bottom wall side of the fifth trench 56. The depth position of the electrode surface of the fifth embedded electrode 58 relative to the bottom of the body region 20 is located on the second main surface 4 side. The electrode surface of the fifth embedded electrode 58 has a groove that is recessed in a pointed shape towards the bottom wall side of the fifth trench 56.

[0226] Semiconductor device 1 includes a plurality of p-type fourth well regions 59 formed on the surface portion of a first facet 8 (first main facet 3) of a first terminal region 15 along a region of a plurality of dummy gate structures 50. The fourth well regions 59 have a p-type impurity concentration higher than that of the body region 20. However, the p-type impurity concentration of the fourth well regions 59 may also be lower than that of the body region 20. Preferably, the p-type impurity concentration of the fourth well regions 59 is approximately equal to that of the first well region 35 (second well region 36).

[0227] Multiple fourth well regions 59 are formed in a one-to-one correspondence with multiple dummy gate structures 50. The multiple fourth well regions 59 are spaced apart from the multiple third source structures 55 and formed along the regions of the corresponding dummy gate structures 50. The multiple fourth well regions 59 are formed along the sidewalls and bottom walls of the corresponding dummy gate structures 50, and are electrically connected to the body region 20 at the surface portion of the first facet 8.

[0228] A plurality of fourth well regions 59 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first face region 8, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. The bottom of the plurality of fourth well regions 59 is located at a depth relative to the bottom of the plurality of second well regions 36 on the side of the first face region 8. In this configuration, the plurality of fourth well regions 59 are exposed from one or both (in this configuration, both) of the third connecting face region 10C and the fourth connecting face region 10D. The plurality of fourth well regions 59 form a pn junction with the second semiconductor region 7.

[0229] Semiconductor device 1 includes a plurality of p-type fifth well regions 60 formed on the surface portion of a first facet 8 (first main facet 3) of a first terminal region 15 along a region of a plurality of third source structures 55. The fifth well regions 60 have a higher p-type impurity concentration than the p-type impurity concentration of the body region 20. However, the p-type impurity concentration of the fifth well regions 60 may also be lower than the p-type impurity concentration of the body region 20. Preferably, the p-type impurity concentration of the fifth well regions 60 is approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).

[0230] Multiple fifth well regions 60 are formed in a one-to-one correspondence with multiple third source structures 55. The multiple fifth well regions 60 are formed spaced apart from the multiple dummy gate structures 50 in regions along the corresponding third source structures 55. The multiple fifth well regions 60 are formed along the sidewalls and bottom walls of the corresponding third source structures 55, and are electrically connected to the body region 20 at the surface portion of the first facet 8.

[0231] A plurality of fifth well regions 60 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first face region 8, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. The bottom of the plurality of fifth well regions 60 is located at a depth relative to the bottom of the plurality of fourth well regions 59 at the bottom side of the second semiconductor region 7.

[0232] The bottoms of the plurality of fifth well regions 60 are formed at a depth approximately equal to the bottoms of the plurality of second well regions 36. In this configuration, the plurality of fifth well regions 60 are exposed from one or both (in this configuration, both) of the third connecting face 10C and the fourth connecting face 10D. The plurality of fifth well regions 60 form a pn junction with the second semiconductor region 7.

[0233] The structure of the third terminal region 17 will be described below. Figure 15 This is an enlarged top view showing a major part of the third terminal area 17. Figure 16 It is along Figure 15 The cross-sectional view of the XVI-XVI line shown.

[0234] The layout of the fourth terminal region 18 is the same as that of the third terminal region 17; therefore, the description of the layout of the fourth terminal region 18 is omitted. The layout of the fourth terminal region 18 is obtained by replacing "third terminal region 17" with "fourth terminal region 18", "first terminal region 15" with "second terminal region 16", and "first connecting face 10A" with "second connecting face 10B" in the description of the third terminal region 17.

[0235] Semiconductor device 1 includes a plurality of trench-type (trench electrode type) fourth source structures 65 formed on a first surface 8 (first main surface 3) in a third terminal region 17. Source potentials are assigned to the plurality of fourth source structures 65. The fourth source structures 65 may also be referred to as "trench structure," "source terminal structure," "trench source structure," "fourth trench source structure," etc.

[0236] Multiple fourth source structures 65 are formed in the region on the side of the first connecting face 10A relative to the active region 12 (first terminal region 15). When viewed from above, the multiple fourth source structures 65 extend in a strip-like pattern in the first direction X and are arranged at intervals in the second direction Y. That is, when viewed from above, the multiple fourth source structures 65 are arranged in a stripe-like pattern extending in the first direction X. The multiple fourth source structures 65 are adjacent to each other without passing through other trench structures.

[0237] Multiple fourth source structures 65 are positioned opposite the active region 12 (multiple gate structures 25 and multiple first source structures 30) in the second direction Y, separated by the first terminal region 15 (multiple dummy gate structures 50 and multiple third source structures 55).

[0238] In this configuration, a plurality of fourth source structures 65 are led out in the second direction Y to a region opposite to one or both (in this configuration, both) of the first side region 13 and the second side region 14, and are opposite to a plurality of second source structures 40 in the second direction Y. In this configuration, the plurality of fourth source structures 65 are opposite to the plurality of second source structures 40 across the first terminal region 15 (the plurality of dummy gate structures 50 and the plurality of third source structures 55).

[0239] A plurality of fourth source structures 65 are exposed from at least one of the third connecting face 10C and the fourth connecting face 10D. In this embodiment, the plurality of fourth source structures 65 penetrate both the third connecting face 10C and the fourth connecting face 10D and are exposed from both the third connecting face 10C and the fourth connecting face 10D.

[0240] A plurality of fourth source structures 65 penetrate the body region 20 to reach the second semiconductor region 7. The plurality of fourth source structures 65 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first face 8, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. In this configuration, the plurality of fourth source structures 65 are formed substantially perpendicular to the first face 8. Alternatively, the plurality of fourth source structures 65 may be formed in a pointed shape toward the bottom of the second semiconductor region 7.

[0241] The sidewalls of the multiple fourth source structures 65 are each formed from the m-plane of a SiC single crystal. Alternatively, the sidewalls of the multiple fourth source structures 65 can also be formed from the a-plane of a SiC single crystal, depending on the extension direction of the fourth source structure 65. The sidewalls of the multiple fourth source structures 65 are formed approximately perpendicular to the first principal plane 3.

[0242] The bottom walls of the plurality of fourth source structures 65 are formed by the c-plane (Si plane) of a SiC single crystal. The bottom walls of the plurality of fourth source structures 65 preferably extend in a generally flat manner along the horizontal direction. Of course, the bottom walls of the plurality of fourth source structures 65 may also be curved in an arc shape toward the second main surface 4.

[0243] The tilt angle (absolute value) of the sidewall of the fourth source structure 65, referenced to a vertical line, can be 85° or more and 95° or less. The tilt angle can have a value falling within at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less. The tilt angle is preferably 87° or more and 93° or less.

[0244] The fourth source structure 65 preferably has a width larger than that of the gate structure 25. Of course, the width of the fourth source structure 65 can be approximately equal to or smaller than the width of the gate structure 25. The width of the fourth source structure 65 is preferably approximately equal to the width of the first source structure 30 (second source structure 40). Of course, the width of the fourth source structure 65 can be larger or smaller than the width of the first source structure 30 (second source structure 40).

[0245] The width of the fourth source structure 65 can also be 0.1 μm or more and 3 μm or less. The width of the fourth source structure 65 can also have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the width of the fourth source structure 65 is 0.5 μm or more and 2 μm or less.

[0246] The fourth source structure 65 preferably has a depth greater than that of the gate structure 25. Of course, the depth of the fourth source structure 65 may be approximately equal to or less than the depth of the gate structure 25.

[0247] The depth of the fourth source structure 65 is preferably approximately equal to the depth of the first source structure 30 (second source structure 40). Of course, the depth of the fourth source structure 65 may be less than or greater than the depth of the first source structure 30 (second source structure 40). The depth of the fourth source structure 65 is preferably approximately equal to the depth of the second facet 9. Of course, the depth of the fourth source structure 65 may be less than or greater than the depth of the second facet 9.

[0248] The depth ratio (depth ratio) of the fourth source structure 65 to the depth of the gate structure 25 (dummy gate structure 50) is preferably 1 or more and 3 or less. The depth ratio may have a value belonging to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less. The depth ratio is preferably 1.5 or more and 2.5 or less.

[0249] The depth of the fourth source structure 65 can also be 0.1 μm or more and 3 μm or less. The depth of the fourth source structure 65 can also have a value belonging to at least one of the following ranges: 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the depth of the fourth source structure 65 is 1.5 μm or more and 2.5 μm or less.

[0250] The ratio (spacer ratio) of the spacing of the plurality of fourth source structures 65 relative to the spacing of the gate structure 25 and the first source structure 30 is preferably 0.5 or more and 2 or less. The spacer ratio may have a value belonging to at least one of the following ranges: 0.5 or more and 0.75 or less, 0.75 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, and 1.75 or more and 2 or less. The spacer ratio is preferably 0.75 or more and 1.25 or less.

[0251] The structure of a fourth source structure 65 is described below. The fourth source structure 65 includes a sixth trench 66, a sixth insulating film 67, and a sixth embedded electrode 68. The sixth trench 66 is formed on the first facet 8, dividing the walls (side walls and bottom walls) of the fourth source structure 65. The side walls of the sixth trench 66 are connected to one or both (in this embodiment, both) of the third connecting facet 10C and the fourth connecting facet 10D. The bottom wall of the sixth trench 66 is connected to the second facet 9.

[0252] The sixth insulating film 67 covers the wall of the sixth trench 66. The sixth insulating film 67 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the sixth insulating film 67 comprises the same insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the sixth insulating film 67 has a single-layer structure composed of a silicon oxide film. The sixth insulating film 67 is particularly preferably composed of a silicon oxide film composed of the oxide of the chip 2.

[0253] The sixth insulating film 67 includes a first film portion and a second film portion. The first film portion covers the sidewalls of the sixth trench 66 in a film-like form. The second film portion covers the bottom wall of the sixth trench 66 in a film-like form and is connected to the first film portion. The second film portion has a thickness greater than that of the first film portion. The thickness of the second film portion can be approximately equal to the thickness of the first film portion. The thickness of the first film portion of the sixth insulating film 67 can also be approximately equal to the thickness of the first film portion of the first insulating film 27. The thickness of the second film portion of the sixth insulating film 67 can also be approximately equal to the thickness of the second film portion of the first insulating film 27.

[0254] The sixth insulating film 67 may have a thickness of 10 nm or more and 150 nm or less. The thickness of the sixth insulating film 67 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.

[0255] The sixth buried electrode 68 is buried in the sixth trench 66 through a sixth insulating film 67. The sixth buried electrode 68 may comprise one or both of p-type and n-type conductive polysilicon. Preferably, the sixth buried electrode 68 comprises the same conductive material as the first buried electrode 28 (second buried electrode 33). The sixth buried electrode 68 is positioned opposite the second semiconductor region 7 and the body region 20 through the sixth insulating film 67.

[0256] The sixth embedded electrode 68 has an electrode surface exposed from the sixth trench 66. The height position of the electrode surface of the sixth embedded electrode 68 relative to the first surface 8 is located on the bottom wall side of the sixth trench 66. The depth position of the electrode surface of the sixth embedded electrode 68 relative to the bottom of the body region 20 is located on the second main surface 4 side. The electrode surface of the sixth embedded electrode 68 has a groove that is recessed in a tapering shape towards the bottom wall side of the sixth trench 66.

[0257] Semiconductor device 1 includes a plurality of p-type sixth well regions 69 formed on the surface portion of a first facet 8 (first main facet 3) of a third terminal region 17 along a region of a plurality of fourth source structures 65. The sixth well regions 69 have a p-type impurity concentration higher than that of the body region 20. However, the p-type impurity concentration of the sixth well regions 69 can be lower than that of the body region 20. Preferably, the p-type impurity concentration of the sixth well regions 69 is approximately equal to that of the first well region 35 (second well region 36).

[0258] Multiple sixth well regions 69 are formed in a one-to-one correspondence with multiple fourth source structures 65. The multiple sixth well regions 69 are formed at intervals along the regions of the corresponding fourth source structures 65. The multiple sixth well regions 69 are formed along the sidewalls and bottom walls of the corresponding fourth source structures 65, and are electrically connected to the body region 20 on the surface portion of the first face 8.

[0259] A plurality of sixth well regions 69 are formed spaced apart from the bottom of the second semiconductor region 7 toward the first face 8, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. The bottom of the plurality of sixth well regions 69 is located at the bottom side of the second semiconductor region 7 relative to the bottom of the plurality of first well regions 35. In this configuration, the plurality of sixth well regions 69 are exposed from one or both (in this configuration, both) of the third connecting face 10C and the fourth connecting face 10D. The plurality of sixth well regions 69 form a pn junction with the second semiconductor region 7.

[0260] The structure of the 19 sides of the outer perimeter region will be described below. Figure 17 It is along Figure 1 A cross-sectional view of line XVII-XVII shown. Figure 18 It is along Figure 1 A cross-sectional view along line XVIII-XVIII shown. (Refer to...) Figure 17 and Figure 18 The semiconductor device 1 includes a p-type outer well region 70 formed on the surface portion of the second face 9 in the peripheral region 19. A source potential is assigned to the outer well region 70.

[0261] The outer well region 70 has a lower p-type impurity concentration than the contact region 37. The p-type impurity concentration in the outer well region 70 is higher than that in the body region 20. Of course, the p-type impurity concentration in the outer well region 70 can also be lower than that in the body region 20. Preferably, the outer well region 70 has a p-type impurity concentration that is approximately equal to that in the first well region 35 (second well region 36).

[0262] When viewed from above, an outer trap region 70 is formed at intervals from the periphery of the second face 9 (first to fourth side surfaces 5A to 5D) toward the first face 8. The outer trap region 70 extends in a band along the first face 8 when viewed from above.

[0263] In this configuration, the outer well region 70, when viewed from above, is formed as a polygonal ring with four sides parallel to the periphery of the chip 2 (in this configuration, a quadrilateral ring), surrounding the first face 8. The outer well region 70 may also have an edge portion where the portion extending in the first direction X and the portion extending in the second direction Y are connected in an arc shape (preferably a quarter arc shape).

[0264] The outer well region 70 extends from the surface portion of the second face 9 toward the surface portions of the first to fourth connecting faces 10A to 10D, and has a portion extending along the first to fourth connecting faces 10A to 10D in the vertical direction Z. The outer well region 70 is electrically connected to the body region 20 at the surface portion of the first face 8. The outer well region 70 is connected to the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, and the sixth well region 69 at the third connecting face 10C (fourth connecting face 10D).

[0265] The outer well region 70 is formed spaced apart from the bottom of the second semiconductor region 7 toward the second face 9, and is opposed to the first semiconductor region 6 across a portion of the second semiconductor region 7. The depth of the bottom of the outer well region 70 relative to the bottom wall of the gate structure 25 is located on the bottom side of the second semiconductor region 7. The depth of the bottom of the outer well region 70 relative to the bottom wall of the first source structure 30 (second source structure 40) is also located on the bottom side of the second semiconductor region 7.

[0266] The bottom of the outer well region 70 is located at the bottom side of the second semiconductor region 7 relative to the depth of the contact region 37. The bottom of the outer well region 70 is preferably formed at a depth that is approximately equal to the bottom of the second well region 36 (third well region 44).

[0267] The outer well region 70 forms a pn junction with the second semiconductor region 7. When a reverse bias voltage is applied, the outer well region 70 causes the depletion layer to extend into the second semiconductor region 7. The depletion layer of the outer well region 70 extends in both the horizontal and thickness directions and is integrated with the depletion layer extending from the active region 12 side. The outer well region 70 causes the depletion layer extending from the active region 12 to extend towards the periphery of the second face 9, mitigating the electric field intensity (electric field concentration) at the periphery of the first face 8 (first to fourth connecting faces 10A to 10D).

[0268] Semiconductor device 1 includes a p-type outer contact region 71 formed on the surface portion of the second facet 9 in the outer peripheral region 19. The outer contact region 71 has a higher p-type impurity concentration than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the outer contact region 71 is higher than the p-type impurity concentration of the outer well region 70. Preferably, the p-type impurity concentration of the outer contact region 71 is approximately equal to the p-type impurity concentration of the contact region 37.

[0269] The outer contact region 71 is formed on the surface of the second face 9, spaced apart from the periphery of the first face 8 (first to fourth connecting faces 10A to 10D) and the periphery of the second face 9 (first to fourth side faces 5A to 5D) when viewed from above. Specifically, the outer contact region 71 is formed on the surface of the outer well region 70. The outer contact region 71 is formed spaced apart from the bottom of the outer well region 70 toward the second face 9, and is opposed to the second semiconductor region 7 across a portion of the outer well region 70.

[0270] The outer contact area 71 extends in a strip shape along the first surface 8 when viewed from above. In this embodiment, the outer contact area 71 is formed as a polygonal ring (in this embodiment, a quadrilateral ring) with four sides parallel to the periphery of the chip 2 when viewed from above, surrounding the first surface 8. The outer contact area 71 may have an edge portion where the portion extending in the first direction X and the portion extending in the second direction Y are connected in an arc shape (preferably a quarter arc shape).

[0271] The bottom of the outer well region 70 is located at the bottom side of the second semiconductor region 7 at a depth relative to the bottom wall of the gate structure 25. The bottom of the outer well region 70 is located at the bottom side of the second semiconductor region 7 at a depth relative to the bottom wall of the first source structure 30 (second source structure 40). The bottom of the outer contact region 71 is preferably formed at a depth approximately equal to the bottom of the contact region 37.

[0272] Semiconductor device 1 includes at least one p-type field region 72 formed on the surface portion of a second facet 9 in an outer peripheral region 19. The plurality of field regions 72 can be formed in an electrically suspended state or fixed at a source potential. The plurality of field regions 72 mitigate the electric field within the chip 2 in the outer peripheral region 19.

[0273] The number of field regions 72 is arbitrary. The number of field regions 72 can be more than one and less than 20. The number of field regions 72 can also have values ​​falling within at least one of the following ranges: more than one and less than five, more than five and less than ten, more than ten and less than fifteen, and more than fifteen and less than twenty. Typically, the number of field regions 72 is more than one and less than eight. In this embodiment, the semiconductor device 1 includes four field regions 72.

[0274] Multiple field areas 72 are formed on the surface of the second face 9 at intervals from the periphery of the first face 8 (first to fourth connecting faces 10A to 10D) and the periphery of the second face 9 (first to fourth side faces 5A to 5D) when viewed from above. Specifically, multiple field areas 72 are formed at intervals from the outer well region 70 toward the periphery of the second face 9 in the region between the periphery of the second face 9 and the outer well region 70.

[0275] Multiple field regions 72 are formed at intervals from the bottom of the second semiconductor region 7 toward the second face 9, and are opposed to the first semiconductor region 6 with a portion of the second semiconductor region 7 between them. The multiple field regions 72 extend in a strip shape along the first face 8 when viewed from above.

[0276] In this configuration, the plurality of field regions 72 are each formed as a polygonal ring (in this configuration, a quadrilateral ring) with four sides parallel to the periphery of the chip 2 when viewed from above, surrounding the first face 8. The plurality of field regions 72 may also have an edge portion where the portion extending in the first direction X and the portion extending in the second direction Y are connected in an arc shape (preferably a quarter arc shape).

[0277] Multiple field regions 72 respectively form pn junctions with the second semiconductor region 7. When a reverse bias voltage is applied, the multiple field regions 72 cause the depletion layer to extend into the second semiconductor region 7.

[0278] The depletion layers of the multiple field regions 72 extend in both the horizontal and thickness directions, and are integrated with the depletion layer of the outer well region 70. The multiple field regions 72 cause the depletion layer extending from the active region 12 to extend towards the periphery of the second face 9, thereby mitigating the electric field intensity (electric field concentration) at the periphery of the first face 8 (first to fourth connecting faces 10A to 10D).

[0279] The width, depth, spacing, and p-type impurity concentration of the multiple field regions 72 are arbitrary and can be selected from various values ​​according to the electric field to be mitigated. The width of the multiple field regions 72 can be approximately fixed or non-uniform. The width of the multiple field regions 72 can gradually increase towards the periphery of the second face 9. The width of the multiple field regions 72 can also gradually decrease towards the periphery of the second face 9.

[0280] The depths of the multiple field zones 72 can be roughly fixed or uneven. The depths of the multiple field zones 72 can gradually increase towards the periphery of the second face 9. Alternatively, the depths of the multiple field zones 72 can gradually decrease towards the periphery of the second face 9.

[0281] The spacing between the multiple field areas 72 can be roughly fixed or uneven. The spacing between the multiple field areas 72 can gradually increase towards the periphery of the second face 9. The spacing between the multiple field areas 72 can also gradually decrease towards the periphery of the second face 9.

[0282] The concentration of p-type impurities in the multiple field regions 72 can be approximately fixed or non-uniform. The concentration of p-type impurities in the multiple field regions 72 can gradually increase towards the periphery of the second face 9. Alternatively, the concentration of p-type impurities in the multiple field regions 72 can gradually decrease towards the periphery of the second face 9.

[0283] The p-type impurity concentrations in multiple field regions 72 can be approximately equal to the p-type impurity concentrations in the body region 20. The p-type impurity concentrations in multiple field regions 72 can be higher or lower than the p-type impurity concentrations in the body region 20.

[0284] The p-type impurity concentrations of the multiple field regions 72 can be approximately equal to the p-type impurity concentrations of the first well region 35 (second well region 36). The p-type impurity concentrations of the multiple field regions 72 can be higher or lower than the p-type impurity concentrations of the first well region 35 (second well region 36).

[0285] The p-type impurity concentrations in multiple field regions 72 can be approximately equal to the p-type impurity concentrations in the outer well region 70. The p-type impurity concentrations in multiple field regions 72 can be higher or lower than the p-type impurity concentrations in the outer well region 70.

[0286] The p-type impurity concentrations in multiple field regions 72 can be approximately equal to the p-type impurity concentrations in contact region 37 (outer contact region 71). The p-type impurity concentrations in multiple field regions 72 can be higher or lower than the p-type impurity concentrations in contact region 37 (outer contact region 71).

[0287] Semiconductor device 1 includes a first inorganic film 75 that selectively covers a first main surface 3, providing insulation. The first inorganic film 75 is an example of a "covered object". The first inorganic film 75 may also be referred to as an "inorganic insulating film (first inorganic insulating film)" or the like.

[0288] The first inorganic membrane 75 selectively covers the first face 8, the second face 9, and the first to fourth connecting faces 10A to 10D. In this embodiment, the first inorganic membrane 75 is connected to the periphery (first to fourth side faces 5A to 5D) of the second face 9. That is, the first inorganic membrane 75 is formed to be coplanar with the periphery (first to fourth side faces 5A to 5D) of the second face 9.

[0289] The first inorganic membrane 75 has a laminated structure comprising a lower inorganic membrane 76 and an upper inorganic membrane 77. The lower inorganic membrane 76 may also be referred to as a "lower insulating membrane," "main surface insulating membrane," etc. The upper inorganic membrane 77 may also be referred to as an "upper insulating membrane," "interlayer insulating membrane," "intermediate insulating membrane," etc.

[0290] The lower inorganic film 76 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the lower inorganic film 76 comprises an insulating material of the same type as the insulating material such as the first insulating film 27. In this embodiment, the lower inorganic film 76 has a single-layer structure composed of a silicon oxide film. Particularly preferably, the lower inorganic film 76 comprises a silicon oxide film composed of the oxide of the chip 2.

[0291] The lower inorganic membrane 76 selectively covers the first facet 8, the second facet 9, and the first to fourth connecting facets 10A to 10D. The lower inorganic membrane 76 is connected to the first insulating membrane 27, the second insulating membrane 32, the third insulating membrane 42, the fourth insulating membrane 52, the fifth insulating membrane 57, and the sixth insulating membrane 67 at the first facet 8, thereby exposing the first embedded electrode 28, the second embedded electrode 33, the third embedded electrode 43, the fourth embedded electrode 53, the fifth embedded electrode 58, and the sixth embedded electrode 68.

[0292] The lower inorganic membrane 76 covers the outer well region 70, the outer contact region 71, and multiple field regions 72 on the second face 9. The lower inorganic membrane 76 is connected to the second insulating membrane 32, the third insulating membrane 42, the fourth insulating membrane 52, the fifth insulating membrane 57, and the sixth insulating membrane 67 on the first to fourth connecting faces 10A to 10D, thereby exposing the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.

[0293] The lower inorganic membrane 76 comprises the first to fourth connecting face 10A to 10D covering region 20, the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, the sixth well region 69, and the outer well region 70.

[0294] The upper inorganic film 77 may comprise at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The upper inorganic film 77 preferably comprises a silicon oxide film. The upper inorganic film 77 preferably comprises an insulating material having properties different from the insulating material of the lower inorganic film 76.

[0295] For example, the upper inorganic membrane 77 preferably has a single-layer or multilayer structure comprising at least one of a phosphorus-containing silicon oxide membrane (PSG membrane), a phosphorus and boron-containing silicon oxide membrane (BPSG membrane), an impurity-free silicon oxide membrane (NSG membrane), and a tetraethyl orthosilicate membrane (TEOS membrane). For example, the upper inorganic membrane 77 may also have a multilayer structure comprising an NSG membrane stacked on top of the lower inorganic membrane 76, and a PSG membrane (or BPSG membrane) stacked on top of the NSG membrane.

[0296] An upper inorganic film 77 is stacked on top of a lower inorganic film 76 and selectively covers the first face portion 8, the second face portion 9, and the first to fourth connecting face portions 10A to 10D through the lower inorganic film 76. The upper inorganic film 77 covers a plurality of gate structures 25 (first buried electrodes 28), a plurality of first source structures 30 (second buried electrodes 33), a plurality of second source structures 40 (third buried electrodes 43), a plurality of dummy gate structures 50 (fourth buried electrodes 53), a plurality of third source structures 55 (fifth buried electrodes 58), and a plurality of fourth source structures 65 (sixth buried electrodes 68) on the first face portion 8.

[0297] The upper inorganic film 77 covers the outer well region 70, the outer contact region 71, and multiple field regions 72 across the lower inorganic film 76 on the second face 9. The upper inorganic film 77 covers multiple first source structures 30 (second buried electrodes 33), multiple second source structures 40 (third buried electrodes 43), multiple dummy gate structures 50 (fourth buried electrodes 53), multiple third source structures 55 (fifth buried electrodes 58), and multiple fourth source structures 65 (sixth buried electrodes 68) on the first to fourth connecting faces 10A to 10D.

[0298] Refer again Figures 8-12 The semiconductor device 1 includes a plurality of gate connection electrodes 78 that selectively cover a plurality of gate structures 25 in an active region 12. The gate connection electrodes 78 may also be referred to as "connection electrodes", "connection electrode films", "gate connection electrode films", etc.

[0299] The gate connection electrode 78 can be considered as a component of the gate structure 25. The plurality of gate connection electrodes 78 comprise one or both of p-type or n-type conductive polysilicon. Preferably, the plurality of gate connection electrodes 78 comprise the same conductive material as the conductive material of the first buried electrode 28.

[0300] Multiple gate connection electrodes 78 are respectively disposed between multiple gate structures 25 and the upper inorganic film 77. That is, multiple gate connection electrodes 78 are respectively disposed on multiple gate structures 25 and covered by the upper inorganic film 77.

[0301] In this configuration, a plurality of gate connection electrodes 78 are formed in a one-to-many correspondence with respect to a plurality of gate structures 25. In this configuration, the plurality of gate connection electrodes 78 respectively cover both ends of the corresponding gate structure 25 in a film-like manner and extend in a strip-like manner in the first direction X.

[0302] When viewed from above, a plurality of gate connection electrodes 78 are formed at intervals in the second direction Y with a plurality of first source structures 30, and a plurality of gate connection electrodes 78 are formed at intervals in the first direction X with a plurality of second source structures 40.

[0303] Multiple gate connection electrodes 78 expose multiple first source structures 30 and multiple second source structures 40, and are electrically disconnected from the multiple first source structures 30 and multiple second source structures 40. When viewed from above, the multiple gate connection electrodes 78 are arranged alternately with the multiple first source structures 30 in the second direction Y, and are not opposite to the multiple second source structures 40 in the second direction Y.

[0304] Multiple gate connection electrodes 78 are connected to the first buried electrode 28 in portions covering the corresponding gate structure 25, and each has a portion extending downward from the first buried electrode 28 onto the inorganic film 76. That is, the multiple gate connection electrodes 78 have portions that face the corresponding gate structure 25 in the vertical direction Z, and portions that face the body region 20 in the vertical direction Z.

[0305] In this configuration, a plurality of gate connection electrodes 78 are integrally formed with the first buried electrode 28 corresponding to the gate structure 25. That is, the plurality of gate connection electrodes 78 are each formed by a lead-out portion of the corresponding first buried electrode 28. Of course, the gate connection electrodes 78 may also be formed separately from the first buried electrode 28.

[0306] Each of the plurality of gate connection electrodes 78 has an electrode surface extending along the first face 8. In this configuration, the plurality of gate connection electrodes 78 are formed in cross-section as a pointed shape (frustum-shaped) facing the electrode surface. The electrode surface is preferably formed to be wider in the second direction Y compared to the gate configuration 25.

[0307] The thickness of the gate connection electrode 78 can be less than or greater than the depth of the first source structure 30. The thickness of the gate connection electrode 78 can be less than or greater than the depth of the second facet 9. The thickness of the gate connection electrode 78 can be less than or greater than the depth of the gate structure 25.

[0308] The thickness of the gate connection electrode 78 can be 0.05 μm or more and 3 μm or less. The thickness of the gate connection electrode 78 can have a value belonging to at least one of the following ranges: 0.05 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, and 2.5 μm or more and 3 μm or less. Preferably, the thickness of the gate connection electrode 78 is 1.5 μm or more and 2.5 μm or less.

[0309] Refer again Figures 8-16 The semiconductor device 1 includes a sidewall wiring 79 covering at least one of the first to fourth connecting surfaces 10A to 10D on the second surface 9. Specifically, the sidewall wiring 79 is located between a lower inorganic film 76 and an upper inorganic film 77. That is, the sidewall wiring 79 is disposed on the lower inorganic film 76 and covered by the upper inorganic film 77. The sidewall wiring 79 also functions as a "sidewall structure" to mitigate the step between the first surface 8 and the second surface 9.

[0310] The sidewall wiring 79 preferably extends in a strip shape along at least one of the third connecting face 10C and the fourth connecting face 10D. In this configuration, the sidewall wiring 79, when viewed from above, is formed as a polygonal loop (specifically a quadrilateral loop) extending along the first to fourth connecting faces 10A to 10D, surrounding the first face 8. The sidewall wiring 79 may have an edge portion where the portion extending in the first direction X and the portion extending in the second direction Y are connected in an arc shape (preferably a quarter arc shape).

[0311] The sidewall wiring 79 includes: a membrane-like portion extending along the second face 9, and a membrane-like portion extending along the first to fourth connecting faces 10A to 10D. The portion of the sidewall wiring 79 located above the second face 9 can membrane-likely cover the second face 9 in a region relative to the height of the first face 8 on the side of the second face 9. That is, the portion of the sidewall wiring 79 located above the second face 9 can have a thickness less than the depth of the second face 9.

[0312] Sidewall wiring 79 is formed at intervals from multiple field areas 72 toward the first face 8, and is opposed to the outer well region 70 across the lower inorganic membrane 76. Sidewall wiring 79 is formed at intervals from the outer edge of the outer well region 70 toward the first face 8.

[0313] In this configuration, the sidewall wiring 79 is formed at intervals from the outer edge of the outer contact area 71 toward the first face surface 8, and has a portion that faces the outer contact area 71 across the lower inorganic membrane 76. Alternatively, the sidewall wiring 79 may be formed at intervals from the inner edge of the outer contact area 71 toward the first face surface 8.

[0314] The sidewall wiring 79 covers the first to fourth connecting surfaces 10A to 10D through the lower inorganic membrane 76. The sidewall wiring 79 covers the body region 20, the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, the sixth well region 69 and the outer well region 70 through the lower inorganic membrane 76 at the first to fourth connecting surfaces 10A to 10D.

[0315] The sidewall wiring 79 is electrically connected to the first to fourth connection faces 10A to 10D and to a plurality of first source structures 30 (second buried electrodes 33), a plurality of second source structures 40 (third buried electrodes 43), a plurality of dummy gate structures 50 (fourth buried electrodes 53), a plurality of third source structures 55 (fifth buried electrodes 58) and a plurality of fourth source structures 65 (sixth buried electrodes 68).

[0316] The sidewall wiring 79 has an overlapping portion 79a that overlaps the edge of the first face 8 from at least one of the first to fourth connecting faces 10A to 10D. In this configuration, the overlapping portion 79a overlaps the first face 8 entirely from the first to fourth connecting faces 10A to 10D, forming a ring (specifically a four-sided ring) surrounding the interior of the first face 8. When viewed from above, the overlapping portion 79a covers the first face 8 in a membrane-like manner and extends in a strip along the edge of the first face 8.

[0317] The overlapping portion 79a covers the periphery of the first face portion 8 at intervals, spaced apart from the plurality of gate structures 25. The overlapping portion 79a is electrically connected to the periphery of the first face portion 8 to a plurality of first source structures 30 (second buried electrodes 33), a plurality of second source structures 40 (third buried electrodes 43), a plurality of dummy gate structures 50 (fourth buried electrodes 53), a plurality of third source structures 55 (fifth buried electrodes 58), and a plurality of fourth source structures 65 (sixth buried electrodes 68).

[0318] The sidewall wiring 79 comprises one or both of p-type and n-type conductive polysilicon. Preferably, the sidewall wiring 79 comprises the same conductive material as the conductive material of the first embedded electrode 28.

[0319] In this configuration, the sidewall wiring 79 is integrally formed with the second embedded electrode 33, the third embedded electrode 43, the fourth embedded electrode 53, the fifth embedded electrode 58, and the sixth embedded electrode 68. Of course, the sidewall wiring 79 can also be formed separately from the second embedded electrode 33, the third embedded electrode 43, the fourth embedded electrode 53, the fifth embedded electrode 58, and the sixth embedded electrode 68.

[0320] Refer again Figures 5-7 The semiconductor device 1 includes a plurality of source openings 80 formed in an active region 12 on a first inorganic film 75. The plurality of source openings 80 penetrate the first inorganic film 75, selectively exposing a plurality of first source structures 30. Specifically, the plurality of source openings 80 are formed in a one-to-one correspondence with the plurality of source structures, and extend in a strip shape along the corresponding first source structure 30.

[0321] Of course, the multiple source openings 80 can also be formed in a one-to-many correspondence with respect to the corresponding first source structure 30. In this case, multiple source openings 80 can be formed at intervals along the corresponding first source structure 30 in the second direction Y. The multiple source openings 80 expose the corresponding first source structure 30, the source region 21, and the multiple contact regions 37 respectively.

[0322] Refer again Figures 8-16 The semiconductor device 1 includes at least one (in this embodiment, one) external opening 81 formed in the outer peripheral region 19 on the first inorganic film 75. The external opening 81 extends through the first inorganic film 75, exposing both the outer contact region 71 and the sidewall wiring 79.

[0323] Specifically, the outer opening 81 penetrates the upper inorganic membrane 77, exposing the sidewall wiring 79. Additionally, the outer opening 81 penetrates both the lower inorganic membrane 76 and the upper inorganic membrane 77, exposing the outer contact area 71. When viewed from above, the outer opening 81 extends in a strip along the outer contact area 71 and the sidewall wiring 79.

[0324] In this configuration, the external opening 81 is formed as a polygonal ring (specifically a quadrilateral ring) surrounding the first face 8 when viewed from above. Of course, the semiconductor device 1 may also have multiple external openings 81. In this case, multiple external openings 81 can be formed at intervals along the external contact area 71, surrounding the first face 8.

[0325] Reference Figures 8-12 The semiconductor device 1 includes a plurality of gate openings 82 formed in an active region 12 on a first inorganic film 75. The plurality of gate openings 82 penetrate the first inorganic film 75, selectively exposing a plurality of gate structures 25.

[0326] Specifically, multiple gate openings 82 are formed in portions of the first inorganic film 75 that cover multiple gate connection electrodes 78, thereby exposing the multiple gate connection electrodes 78. The multiple gate openings 82 are formed in a one-to-one correspondence with the multiple gate connection electrodes 78, and extend in a strip shape in the first direction X when viewed from above.

[0327] Reference Figure 17 as well as Figure 18 The semiconductor device 1 includes at least one (in this embodiment, one) anchoring opening 83 formed in the outer peripheral region 19 of the first inorganic film 75. The anchoring opening 83 is selectively formed in the portion of the first inorganic film 75 that covers the periphery of the second face 9.

[0328] That is, the anchoring opening 83 is formed in the region between the first face 8 and the second face 9. Specifically, the anchoring opening 83 is formed in the region between the periphery of the second face 9 and the outer trap region 70. More specifically, the anchoring opening 83 is formed in the region between the periphery of the second face 9 and the plurality of field regions 72 (the outermost field region 72).

[0329] Anchoring opening 83 penetrates the first inorganic film 75, exposing the second face 9. Specifically, anchoring opening 83 exposes the second semiconductor region 7. Anchoring opening 83 can be recessed towards the bottom side of the second semiconductor region 7 relative to the height position of the second face 9. That is, the bottom wall of anchoring opening 83 can be located at the bottom side of the second semiconductor region 7 relative to the height position of the second face 9.

[0330] The anchoring opening 83 extends in a strip shape along the first face 8 when viewed from above. In this configuration, the anchoring opening 83 is formed as a polygonal ring (specifically a quadrilateral ring) surrounding the first face 8 when viewed from above. Of course, the semiconductor device 1 may have multiple anchoring openings 83. In this case, multiple anchoring openings 83 may be formed at intervals along the first face 8 in a manner that surrounds the first face 8.

[0331] Multiple anchoring openings 83 can be arranged in a matrix or staggered pattern, spaced apart in the first direction X and the second direction Y, surrounding the first face 8. Alternatively, the multiple anchoring openings 83 can be arranged in a striped or grid pattern surrounding the first face 8. Furthermore, multiple annular anchoring openings 83 can be arranged in a concentric circle pattern surrounding the first face 8.

[0332] The structure above the first main surface 3 will be described below. Figure 19 This is a top view showing an example of the layout of the main electrodes (source electrode 85, source wiring 90, gate electrode 95 and gate wiring 100) arranged on the first main surface 3. Figure 20 This is a top view showing a first layout example of the second inorganic membrane 110. Figure 21 This is an enlarged top view showing a major part of the second inorganic membrane 110.

[0333] Reference Figures 19-21 The semiconductor device 1 includes a source electrode 85 disposed on a first inorganic film 75. The source electrode 85 is a terminal electrode to which a source potential is applied from the outside. The source electrode 85 may also be referred to as an "electrode", "first electrode", "first pad electrode", "first main surface electrode", "first terminal electrode", "source pad electrode", etc.

[0334] The source electrode 85 has a thickness greater than the depth of the gate structure 25. The thickness of the source electrode 85 is preferably greater than the depth of the first source structure 30. The thickness of the source electrode 85 is preferably greater than the depth of the second facet 9. The thickness of the source electrode 85 is preferably greater than the thickness (total thickness) of the first inorganic film 75.

[0335] The thickness of the source electrode 85 can be 0.5 μm or more and 5 μm or less. The thickness of the source electrode 85 can have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0336] A source electrode 85 is disposed on a covering portion of the first inorganic film 75 relative to the first face portion 8. The source electrode 85, when viewed from above, at least covers the active region 12. The source electrode 85 covers the active region 12 at intervals from the first side end region 13 and the second side end region 14. That is, the source electrode 85 covers the first face portion 8 at intervals from both ends of the plurality of gate structures 25. Specifically, the source electrode 85 is formed at intervals from the plurality of gate connection electrodes 78 inwardly.

[0337] The source electrode 85 may cover one or both of the first terminal region 15 and the third terminal region 17. That is, the source electrode 85 may be positioned opposite to the plurality of dummy gate structures 50 and the plurality of third source structures 55 on the first terminal region 15 side, separated by the first inorganic film 75. The source electrode 85 may be positioned opposite to the plurality of fourth source structures 65 on the third terminal region 17 side. Of course, the source electrode 85 may also cover the active region 12 with a gap between it and one or both of the first terminal region 15 and the third terminal region 17.

[0338] In this embodiment, the source electrode 85 has a first pad portion 85a, a second pad portion 85b, and a third pad portion 85c. The first pad portion 85a has a relatively large planar area and forms the main body of the source electrode 85. In this embodiment, the first pad portion 85a is formed into a polygonal shape (quadrilateral shape in this embodiment) with four sides parallel to the periphery of the chip 2 when viewed from above, and is offset towards the second side portion 5B (second connection portion 10B) relative to the first side portion 5A (first connection portion 10A).

[0339] The second pad portion 85b has a planar area smaller than that of the first pad portion 85a, and extends in a strip shape (quadrilateral shape) from one end of the first pad portion 85a in the first direction X (the end on the side of the third connecting surface 10C) toward the first connecting surface 10A. The third pad portion 85c has a planar area smaller than that of the first pad portion 85a, and extends in a strip shape (quadrilateral shape) from the other end of the first pad portion 85a in the first direction X (the end on the side of the fourth connecting surface 10D) toward the first connecting surface 10A, and is opposite to the second pad portion 85b in the second direction Y.

[0340] The planar area of ​​the third pad portion 85c can also be approximately equal to the planar area of ​​the second pad portion 85b. Of course, the planar area of ​​the third pad portion 85c can be larger or smaller than the planar area of ​​the second pad portion 85b. One or both of the second pad portion 85b and the third pad portion 85c can also be used as a terminal portion for current monitoring.

[0341] The proportion of the source electrode 85 in the first face 8 is preferably 50% or more and less than 100%. The proportion of the source electrode 85 may have a value in any range of 50% or more and 60% or more, 60% or more and 70% or more, 70% or more and 80% or more, 80% or more and 90% or more, and 90% or more and less than 100%.

[0342] The source electrode 85 does not necessarily need to have both the second pad portion 85b and the third pad portion 85c. The source electrode 85 may have only one of the second pad portion 85b and the third pad portion 85c. Of course, the source electrode 85 may also be composed only of the first pad portion 85a, without both the second pad portion 85b and the third pad portion 85c.

[0343] The source electrode 85 extends from the first inorganic film 75 into multiple source openings 80, and is electrically connected to multiple first source structures 30, source regions 21 and multiple contact regions 37 within the multiple source openings 80.

[0344] The source electrode 85 includes a first electrode surface 86 and a first electrode sidewall 87. The first electrode surface 86 extends along the first inorganic film 75. The first electrode surface 86 may have multiple recesses that are recessed towards the first electrode surface 80 in portions covering multiple source openings 80. The first electrode sidewall 87 is located on the first inorganic film 75. The first electrode sidewall 87 slopes downward from the first electrode surface 86 toward the first inorganic film 75. In this embodiment, the first electrode sidewall 87 slopes downward in a curved manner from the first electrode surface 86 toward the first inorganic film 75.

[0345] In this embodiment, the source electrode 85 has a laminated structure comprising a first lower electrode film 88 and a first upper electrode film 89 sequentially stacked from the side of the first inorganic film 75. The first lower electrode film 88, as the lower film (barrier film) of the source electrode 85, is laminated in a film-like manner on the first inorganic film 75, forming the lower layer of the first electrode sidewall 87 of the source electrode 85.

[0346] In this embodiment, the first lower electrode film 88 has a laminated structure comprising a Ti film and a TiN film sequentially stacked from the side of the first inorganic film 75. The first lower electrode film 88 may have a monolayer structure composed of a Ti film or a TiN film. The first lower electrode film 88 has a thickness (total thickness) that is less than the thickness (total thickness) of the first inorganic film 75.

[0347] The thickness (total thickness) of the first lower electrode film 88 can be greater than 0.01 μm and less than 1 μm. The thickness (total thickness) of the first lower electrode film 88 can be less than 0.75 μm, less than 0.5 μm, less than 0.25 μm, or less than 0.1 μm.

[0348] The first lower electrode film 88 covers the region in the first inorganic film 75 where multiple source openings 80 are formed in a film-like manner, and extends from the first inorganic film 75 into the multiple source openings 80. The first lower electrode film 88 has: a portion that covers the insulating main surface of the first inorganic film 75 in a film-like manner, a portion that covers the wall surface of the multiple source openings 80 in a film-like manner, and a portion that covers the first surface 8 in a film-like manner within the multiple source openings 80.

[0349] Specifically, the first lower electrode film 88 directly covers the insulating main surface of the first inorganic film 75 and is opposed to the plurality of gate structures 25 through the first inorganic film 75. The first lower electrode film 88 extends from the insulating main surface of the first inorganic film 75 into the plurality of source openings 80, and covers the walls of the plurality of source openings 80 in a film-like manner.

[0350] The first lower electrode film 88 covers the first face 8 in a film-like manner within the plurality of source openings 80. The first lower electrode film 88 is mechanically and electrically connected to the plurality of first source structures 30, source regions 21 and the plurality of contact regions 37 within the plurality of source openings 80.

[0351] The first upper electrode film 89, serving as the main body of the source electrode 85, is laminated in a film-like manner on top of the first lower electrode film 88, forming the upper layer of the first electrode surface 86 and the first electrode sidewall 87 of the source electrode 85. The first upper electrode film 89 contains a different conductive material than the first lower electrode film 88. The first upper electrode film 89 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0352] The first upper electrode film 89 has a thickness greater than the thickness (total thickness) of the first lower electrode film 88. The thickness of the first upper electrode film 89 is preferably greater than the thickness of the first inorganic film 75. The thickness of the first upper electrode film 89 is preferably greater than the depth of the gate structure 25. The thickness of the first upper electrode film 89 is preferably greater than the depth of the first source structure 30. The thickness of the first upper electrode film 89 is preferably greater than the depth of the second facet 9.

[0353] The thickness of the first upper electrode film 89 can be 0.5 μm or more and 5 μm or less. The thickness of the first upper electrode film 89 can have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0354] The first upper electrode film 89 covers the region in the first inorganic film 75 where a plurality of source openings 80 are formed in a film-like manner, and backfills the plurality of source openings 80. The first upper electrode film 89 has: a portion covering the insulating main surface of the first inorganic film 75 through the first lower electrode film 88, a portion covering the wall surface of the plurality of source openings 80 through the first lower electrode film 88, and a portion covering the first surface 8 through the first lower electrode film 88.

[0355] Specifically, the first upper electrode film 89 covers the insulating main surface of the first inorganic film 75 through the first lower electrode film 88, and is opposed to the plurality of gate structures 25 through the first inorganic film 75 and the first lower electrode film 88. The first upper electrode film 89 extends from above the first inorganic film 75 into the plurality of source openings 80, and covers the walls of the plurality of source openings 80 in a film-like manner through the first lower electrode film 88.

[0356] The first upper electrode film 89 covers the first face portion 8 in a membrane form within the plurality of source openings 80, separated by the first lower electrode film 88. The first upper electrode film 89 is electrically connected to the plurality of first source structures 30, source regions 21 and multiple contact regions 37 within the plurality of source openings 80 via the first lower electrode film 88.

[0357] Semiconductor device 1 includes: a source wiring 90 disposed on a first inorganic film 75 around a source electrode 85. The source wiring 90 is given the same potential (source potential) as the potential (source potential) given to the source electrode 85. The source wiring 90 may also be referred to as "wiring", "first wiring", "finger electrode", "source finger", etc.

[0358] The source wiring 90 has a thickness greater than the depth of the gate structure 25. The thickness of the source wiring 90 is preferably greater than the depth of the first source structure 30. The thickness of the source wiring 90 is preferably greater than the depth of the second facet 9. The thickness of the source wiring 90 is preferably approximately equal to the thickness of the source electrode 85.

[0359] Of course, the thickness of the source wiring 90 can be greater than or less than the thickness of the source electrode 85. Preferably, the thickness of the source electrode 85 is greater than the thickness (total thickness) of the first inorganic film 75.

[0360] The thickness of the source wiring 90 can be greater than 0.5 μm and less than 5 μm. The thickness of the source wiring 90 can have a value belonging to at least one of the following ranges: greater than 0.5 μm and less than 1 μm, greater than 1 μm and less than 1.5 μm, greater than 1.5 μm and less than 2 μm, greater than 2 μm and less than 2.5 μm, greater than 2.5 μm and less than 3 μm, greater than 3 μm and less than 3.5 μm, greater than 3.5 μm and less than 4 μm, greater than 4 μm and less than 4.5 μm, and greater than 4.5 μm and less than 5 μm.

[0361] The source wiring 90 has a wiring width smaller than that of the source electrode 85 and is selectively wound onto the first inorganic film 75. The source wiring 90 extends in a strip shape along the first electrode sidewall 87, spaced apart from the first electrode sidewall 87 of the source electrode 85.

[0362] The source wiring 90 preferably extends in a strip shape along at least one of the third connection face 10C and the fourth connection face 10D. In this embodiment, the source wiring 90 is formed in a polygonal ring (specifically a quadrilateral ring) extending along the first to fourth connection faces 10A to 10D when viewed from above, surrounding the source electrode 85.

[0363] In this configuration, the source wiring 90, when viewed from above, is disposed above the first side region 13, the second side region 14, the first terminal region 15, the second terminal region 16, the third terminal region 17, and the fourth terminal region 18, and surrounds the active region 12. The source wiring 90 may have an edge portion where the portion extending in the first direction X and the portion extending in the second direction Y are connected in an arc shape (preferably a quarter arc shape).

[0364] The source wiring 90 is electrically connected to the source electrode 85 on the first surface portion 8. Specifically, the source wiring 90 has a portion extending in a strip shape toward the source electrode 85 (first pad portion 85a) in the second direction Y at a portion extending along the second connection surface portion 10B, and is connected to the end of the source electrode 85 (first pad portion 85a). That is, the source wiring 90 is formed as a lead-out wiring led out from the source electrode 85.

[0365] The source wiring 90 covers the second terminal region 16 and the fourth terminal region 18 at the connection with the source electrode 85. The source wiring 90 is positioned opposite the second terminal region 16 (multiple dummy gate structures 50 and multiple third source structures 55) across the first inorganic film 75 at the connection with the source electrode 85.

[0366] The source wiring 90 is positioned opposite the fourth terminal region 18 (multiple fourth source structures 65) at the connection point with the source electrode 85, separated by a first inorganic film 75. The connection point between the source electrode 85 and the source wiring 90 can also be considered as part of the source electrode 85.

[0367] Source wiring 90 extends from the first facet 8 across at least one (in this embodiment, all) of the first to fourth connecting faces 10A to 10D to the second facet 9. In this embodiment, source wiring 90 is formed as the outermost peripheral wiring on the second facet 9. That is, source wiring 90 is not opposed to other electrodes in the outer peripheral region 19 in the horizontal direction along the insulating main surface of the first inorganic film 75. In other words, other electrodes are not located in the region between the periphery of the second facet 9 and source wiring 90.

[0368] The source wiring 90 covers the sidewall wiring 79 over the first to fourth connecting surfaces 10A to 10D, separated by a first inorganic film 75 (upper inorganic film 77). The sidewall wiring 79 improves the film-forming properties of the source wiring 90. The source wiring 90 extends from the first inorganic film 75 into the outer opening 81, where it connects with both the outer contact area 71 and the sidewall wiring 79.

[0369] Thus, the source wiring 90 is electrically connected to the outer contact region 71 and the sidewall wiring 79. The source wiring 90 transmits the source potential applied to the source electrode 85 to the outer contact region 71 and the sidewall wiring 79. That is, the source wiring 90 transmits the source potential to the first source structure 30, the second source structure 40, the dummy gate structure 50, the third source structure 55, and the fourth source structure 65 via the sidewall wiring 79.

[0370] Source wiring 90 is spaced apart from multiple field regions 72 toward the first face surface 8 and is opposed to the outer well region 70 across the first inorganic film 75. In this configuration, source wiring 90 is spaced apart from the outer edge of the outer well region 70 toward the first face surface 8, covering the entire area of ​​the outer contact region 71.

[0371] The source wiring 90 can traverse the outer edge of the outer well region 70. That is, the source wiring 90 can cover the entire area of ​​the outer well region 70. In this case, it is preferable to form the source wiring 90 at intervals from the plurality of field regions 72 toward the first face surface 8. Of course, the source wiring 90 can also cover at least one of the plurality of field regions 72.

[0372] The source wiring 90 includes: a first wiring surface 91, a first inner sidewall 92 on the inner side (source electrode 85 side), and a first outer sidewall 93 on the outer side (peripheral side of chip 2). The first inner sidewall 92 can also be referred to as the "first wiring sidewall", and the second inner sidewall 102 can be referred to as the "second wiring sidewall".

[0373] The first wiring surface 91 has a portion above the first face surface 8 and a portion above the second face surface 9. The portion of the first wiring surface 91 above the first face surface 8 is located at approximately the same height as the first electrode surface 86 of the source wiring 90.

[0374] The portion of the first wiring surface 91 located above the second face surface 9 is recessed towards the second face surface 9 than the portion of the first wiring surface 91 located above the first face surface 8. Preferably, the portion of the first wiring surface 91 located above the second face surface 9 is positioned above the height of the first face surface 8 (towards the portion of the first wiring surface 91 located above the first face surface 8). However, the portion of the first wiring surface 91 located above the second face surface 9 may also be positioned below the height of the first face surface 8 (towards the second face surface 9).

[0375] The first inner sidewall 92 is spaced apart from the first electrode sidewall 87 of the source electrode 85 and located on the covering portion of the first inorganic film 75 relative to the first surface 8. The first inner sidewall 92 slopes downward from the first wiring surface 91 toward the first inorganic film 75. In this configuration, the first inner sidewall 92 slopes downward in a curved shape from the first wiring surface 91 toward the first inorganic film 75.

[0376] The first outer sidewall 93 is located above the covering portion of the first inorganic membrane 75 relative to the second face 9. The first inner sidewall 92 slopes downward from the first wiring surface 91 toward the first inorganic membrane 75. In this configuration, the first inner sidewall 92 slopes downward in a curved shape from the first wiring surface 91 toward the first inorganic membrane 75.

[0377] In this configuration, the first outer sidewall 93 is opposed to the outer well region 70 via the first inorganic film 75. The first outer sidewall 93 may also be opposed to the outer contact region 71 via the first inorganic film 75. The first outer sidewall 93 may also be opposed to the second semiconductor region 7 via the first inorganic film 75. The first outer sidewall 93 may also be opposed to at least one of the plurality of field regions 72 via the first inorganic film 75.

[0378] Like the source electrode 85, the source wiring 90 has a stacked structure including a first lower electrode film 88 and a first upper electrode film 89. The first lower electrode film 88, as the lower film (barrier film) of the source wiring 90, is stacked on the first inorganic film 75 in a film-like manner, forming the lower layer of the first inner sidewall 92 and the first outer sidewall 93 of the source wiring 90.

[0379] The first lower electrode film 88 covers the area in the first inorganic film 75 where the outer opening 81 is formed in a film-like manner, extending from the first inorganic film 75 into the outer opening 81. The first lower electrode film 88 is mechanically and electrically connected to the outer contact area 71 and the sidewall wiring 79 within the outer opening 81.

[0380] The first upper electrode film 89 serves as the main body of the source wiring 90 and is stacked in a film-like manner on the first lower electrode film 88, forming the first wiring surface 91, the upper part of the first inner sidewall 92, and the upper part of the first outer sidewall 93 of the source wiring 90.

[0381] The first upper electrode film 89 covers the area in the first inorganic film 75 where the outer opening 81 is formed in a film-like manner, and backfills the outer opening 81. The first upper electrode film 89 is electrically connected to the outer contact area 71 and the sidewall wiring 79 within the outer opening 81 via the first lower electrode film 88.

[0382] Inside the chip 2, different electric field distributions are formed on the first face 8 side (active region 12 side) and the second face 9 side (peripheral region 19 side). For example, a substantially uniform electric field distribution is formed along the first main surface 3 on the first face 8 side. On the other hand, the electric field distribution formed on the first face 8 side is terminated on the second face 9 side, and the electric field tends to concentrate more easily compared to the first face 8 side.

[0383] That is, the source electrode 85 is disposed on the active region 12 (first region) which has a relatively low first electric field. On the other hand, the source wiring 90 is disposed on the peripheral region 19 (second region) which has a second electric field that is higher than the first electric field.

[0384] That is, the source wiring 90 is located in a region where the electric field is easily concentrated. Therefore, the second electric field relative to the source wiring 90 is sometimes locally higher than the first electric field relative to the source electrode 85. For example, the electric field within the chip 2 leaks from the inside of the chip 2 to the outside outside the source wiring 90. Therefore, the second electric field on the outer peripheral region 19 side is sometimes locally higher near the first outer wall 93 of the source wiring 90.

[0385] Semiconductor device 1 includes a gate electrode 95 disposed on a first inorganic film 75. The gate electrode 95 is a terminal electrode to which a gate potential is applied from the outside. The gate electrode 95 may also be referred to as an "electrode", "second electrode", "second pad electrode", "second main surface electrode", "second terminal electrode", "gate pad electrode", etc.

[0386] The gate electrode 95 has a thickness greater than the depth of the gate structure 25. The thickness of the gate electrode 95 is preferably greater than the depth of the first source structure 30. The thickness of the gate electrode 95 is preferably greater than the depth of the second facet 9. The thickness of the gate electrode 95 is preferably approximately equal to the thickness of the source electrode 85. The thickness of the gate electrode 95 is preferably greater than the thickness (total thickness) of the first inorganic film 75.

[0387] The thickness of the gate electrode 95 can be 0.5 μm or more and 5 μm or less. The thickness of the gate electrode 95 can have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0388] The gate electrode 95 is disposed on the first inorganic film 75 at a distance from the source electrode 85. Specifically, the gate electrode 95 is disposed on the cover portion of the first inorganic film 75 opposite to the first surface portion 8.

[0389] The gate electrode 95 is disposed in the region on the first connection surface 10A side relative to the first pad portion 85a, in the region between the second pad portion 85b and the third pad portion 85c. The gate electrode 95 is opposite to the first pad portion 85a in the second direction Y, and opposite to both the second pad portion 85b and the third pad portion 85c in the first direction X.

[0390] The gate electrode 95, when viewed from above, is formed as a polygon with four sides parallel to the periphery of the chip 2 (in this embodiment, it is a quadrilateral shape). The gate electrode 95 has a planar area smaller than that of the source electrode 85. The gate electrode 95 has a planar area smaller than that of the first pad portion 85a. The gate electrode 95 may also have a planar area smaller than that of the second pad portion 85b (third pad portion 85c).

[0391] The proportion of the gate electrode 95 in the first facet 8 is preferably 1% or more and 25% or less. The proportion of the gate electrode 95 may be any value within the range of 1% or more and 5% or more, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, and 20% or more and 25% or less. The proportion of the gate electrode 95 is preferably 10% or less.

[0392] The gate electrode 95, when viewed from above, at least covers the active region 12. That is, the gate electrode 95 is partially opposed to the plurality of gate structures 25 and the plurality of first source structures 30 through the first inorganic film 75. In addition, the gate electrode 95 is opposed to the body region 20, the source region 21, the plurality of first well regions 35, the plurality of second well regions 36, and the plurality of contact regions 37 through the first inorganic film 75.

[0393] The gate electrode 95 preferably covers the active region 12 at a distance from the first side region 13 and the second side region 14. That is, the gate electrode 95 preferably covers the first facet 8 at a distance from both ends of the plurality of gate structures 25. Specifically, the gate electrode 95 is preferably formed at a distance from the plurality of gate connection electrodes 78 toward the interior.

[0394] In this configuration, the gate electrode 95 does not have a direct electrical connection to the plurality of gate structures 25. Alternatively, the gate electrode 95 can be electrically connected to the plurality of gate structures 25 via a plurality of gate openings 82. It is also possible to remove the portion of the plurality of gate structures 25 located directly below the gate electrode 95.

[0395] The gate electrode 95 may cover one or both of the first terminal region 15 and the third terminal region 17. That is, the gate electrode 95 may be positioned opposite to the plurality of dummy gate structures 50 and the plurality of third source structures 55 on the first terminal region 15 side, separated by the first inorganic film 75. In addition, the gate electrode 95 may also be positioned opposite to the plurality of fourth source structures 65 on the third terminal region 17 side. Of course, the gate electrode 95 may also cover the active region 12 with a gap between it and both the first terminal region 15 and the third terminal region 17.

[0396] The gate electrode 95 includes a second electrode surface 96 and a second electrode sidewall 97. The second electrode surface 96 extends along the first inorganic film 75. The second electrode surface 96 is located at approximately the same height as the first electrode surface 86 of the source electrode 85. Of course, the second electrode surface 96 can be located below or above the first electrode surface 86.

[0397] The second electrode sidewall 97 is located above the first inorganic film 75. The second electrode sidewall 97 slopes downward from the second electrode surface 96 toward the first inorganic film 75. In this embodiment, the second electrode sidewall 97 slopes downward in a curved shape from the second electrode surface 96 toward the first inorganic film 75.

[0398] In this embodiment, the gate electrode 95 has a laminated structure comprising a second lower electrode film 98 and a second upper electrode film 99 sequentially stacked from the side of the first inorganic film 75. The second lower electrode film 98, as the lower film (barrier film) of the gate electrode 95, is laminated in a film-like manner on the first inorganic film 75, forming the lower layer of the second electrode sidewall 97 of the gate electrode 95.

[0399] In this embodiment, the second lower electrode film 98, like the first lower electrode film 88 of the source electrode 85, has a laminated structure comprising a Ti film and a TiN film sequentially stacked from the first inorganic film 75 side. The second lower electrode film 98 may also have a monolayer structure composed of a Ti film or a TiN film. The second lower electrode film 98 has a thickness less than the thickness (total thickness) of the first inorganic film 75. Preferably, the thickness of the second lower electrode film 98 is approximately equal to the thickness of the first lower electrode film 88.

[0400] The thickness (total thickness) of the second lower electrode film 98 can be greater than 0.01 μm and less than 1 μm. The thickness (total thickness) of the second lower electrode film 98 can be less than 0.75 μm, less than 0.5 μm, less than 0.25 μm, or less than 0.1 μm.

[0401] The second upper electrode film 99, serving as the main body of the gate electrode 95, is laminated in a film-like manner on top of the second lower electrode film 98, forming the upper layer of the second electrode surface 96 and the second electrode sidewall 97 of the gate electrode 95. The second upper electrode film 99 contains a different conductive material than the second lower electrode film 98. The second upper electrode film 99 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may also contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0402] The second upper electrode film 99 has a thickness greater than the thickness (total thickness) of the second lower electrode film 98. The thickness of the second upper electrode film 99 is preferably greater than the thickness of the first inorganic film 75. The thickness of the second upper electrode film 99 is preferably greater than the depth of the gate structure 25. The thickness of the second upper electrode film 99 is preferably greater than the depth of the first source structure 30. The thickness of the second upper electrode film 99 is preferably greater than the depth of the second face portion 9. The thickness of the second upper electrode film 99 is preferably approximately equal to the thickness of the first upper electrode film 89.

[0403] The thickness of the second upper electrode film 99 can be 0.5 μm or more and 5 μm or less. The thickness of the second upper electrode film 99 can have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0404] Semiconductor device 1 includes a gate wiring 100 disposed on a first inorganic film 75 around a source electrode 85. The gate wiring 100 is given the same potential (gate potential) as the potential (gate potential) given to the gate electrode 95. The gate wiring 100 may also be referred to as a "wiring", "second wiring", "finger electrode", "gate finger", etc.

[0405] The gate wiring 100 has a thickness greater than the depth of the gate structure 25. The thickness of the gate wiring 100 is preferably greater than the depth of the first source structure 30. The thickness of the gate wiring 100 is preferably greater than the depth of the second facet 9. The thickness of the gate wiring 100 is preferably approximately equal to the thickness of the source electrode 85 (gate electrode 95).

[0406] Of course, the thickness of the gate wiring 100 can be greater than or less than the thickness of the source electrode 85 (gate electrode 95). Preferably, the thickness of the gate electrode 95 is greater than the thickness (total thickness) of the first inorganic film 75.

[0407] The thickness of the gate wiring 100 can be 0.5 μm or more and 5 μm or less. The thickness of the gate wiring 100 can have a value belonging to at least one of the following ranges: 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less.

[0408] The gate wiring 100 has a wiring width smaller than the electrode width of the gate electrode 95 and is selectively wound onto the first inorganic film 75. The gate wiring 100 is arranged at intervals from the periphery of the first facet 8 inwards. Therefore, the gate wiring 100 is not located on the second facet 9.

[0409] The gate wiring 100 is electrically connected to the gate electrode 95 on the first facet 8. Specifically, the gate wiring 100 is connected to the end of the gate electrode 95 on the first connection facet 10A side. That is, the gate wiring 100 is formed as a lead-out wiring extending from the gate electrode 95. The connection portion between the gate electrode 95 and the gate wiring 100 can also be considered as part of the gate electrode 95.

[0410] The gate wiring 100 is wound around the source electrode 85 and the source wiring 90 at intervals on the first inorganic film 75. The gate wiring 100 extends in a strip shape along the first electrode sidewall 87 at intervals from the first electrode sidewall 87 of the source electrode 85.

[0411] The gate wiring 100 preferably extends in a strip shape along at least one of the third connection face 10C and the fourth connection face 10D. In this manner, the gate wiring 100 is formed as an ended loop (specifically an ended quadrilateral loop) extending along the first to fourth connection faces 10A to 10D in a manner that surrounds the gate electrode 95.

[0412] Specifically, the gate wiring 100 has: a portion extending along a first connection face 10A in a first direction X when viewed from above, a portion extending along a second connection face 10B in a second direction Y, a portion extending along a third connection face 10C in a second direction Y, and a portion extending along a fourth connection face 10D in a second direction Y.

[0413] The gate wiring 100 has a pair of open ends through which the source wiring 90 passes along a portion of the second connection face 10B. The gate wiring 100 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0414] The gate wiring 100 intersects (specifically runs in a straight line) with both ends of the plurality of gate structures 25 at portions along the third connection face 10C and along the fourth connection face 10D. The gate wiring 100 extends from above the first inorganic film 75 into the plurality of gate openings 82, and is electrically connected to the ends (both ends) of the plurality of gate structures 25 within the plurality of gate openings 82.

[0415] Specifically, the gate wiring 100 is mechanically and electrically connected to a plurality of gate connection electrodes 78 within a plurality of gate openings 82, and is electrically connected to a plurality of gate structures 25 via the plurality of gate connection electrodes 78. Thus, the gate potential applied to the gate electrode 95 is applied to the plurality of gate structures 25 via the gate wiring 100.

[0416] The gate wiring 100 can cover the active region 12 at intervals, spaced apart from the first side region 13 and the second side region 14. That is, the gate wiring 100 can be formed at intervals, spaced apart from the plurality of second source structures 40. Of course, the gate wiring 100 can also have portions that are opposite to the plurality of second source structures 40 through the first inorganic film 75.

[0417] The gate wiring 100 may cover at least one of the first terminal region 15, the second terminal region 16, the third terminal region 17, and the fourth terminal region 18. The gate electrode 95 may also be opposed to the plurality of dummy gate structures 50 and the plurality of third source structures 55 on the side of the first terminal region 15 (second terminal region 16) separated by the first inorganic film 75.

[0418] The gate electrode 95 can be positioned opposite the plurality of fourth source structures 65 on the side of the third terminal region 17 (fourth terminal region 18) across the first inorganic film 75. Alternatively, the gate electrode 95 can also cover the active region 12 at intervals from the first terminal region 15, the second terminal region 16, the third terminal region 17, and the fourth terminal region 18.

[0419] The gate wiring 100 includes: a second wiring surface 101, a second inner sidewall 102 on the inner side (source electrode 85 side), and a second outer sidewall 103 on the outer side (peripheral side of chip 2). The second inner sidewall 102 can also be referred to as the "first wiring sidewall" and the second inner sidewall 102 as the "second wiring sidewall".

[0420] The second wiring surface 101 is located at approximately the same height as the first electrode surface 86 of the source electrode 85. The second wiring surface 101 is located at approximately the same height as the portion of the first wiring surface 91 of the source wiring 90 that is above the first surface 8.

[0421] The second inner sidewall 102 is spaced apart from the first electrode sidewall 87 of the source electrode 85 and located on the covering portion of the first inorganic film 75 relative to the first surface area 8. The second inner sidewall 102 slopes downward from the second wiring surface 101 toward the first inorganic film 75. In this configuration, the second inner sidewall 102 slopes downward in a curved shape from the second wiring surface 101 toward the first inorganic film 75.

[0422] The second outer sidewall 103 is spaced apart from the first inner sidewall 92 of the source wiring 90 and located above the covering portion of the first inorganic film 75 relative to the first surface 8. The second outer sidewall 103 slopes downward from the second wiring surface 101 toward the first inorganic film 75. In this configuration, the second outer sidewall 103 slopes downward in a curved manner from the second wiring surface 101 toward the first inorganic film 75.

[0423] Like the gate electrode 95, the gate wiring 100 has a stacked structure including a second lower electrode film 98 and a second upper electrode film 99. The second lower electrode film 98, as the lower film (barrier film) of the gate wiring 100, is stacked in a film-like manner on the first inorganic film 75, forming the lower layer of the second inner sidewall 102 and the second outer sidewall 103 of the gate wiring 100.

[0424] The second lower electrode film 98 covers the region in the first inorganic film 75 where multiple gate openings 82 are formed in a film-like manner, extending from the first inorganic film 75 into the multiple gate openings 82. The second lower electrode film 98 is mechanically and electrically connected to the multiple gate structures 25 (multiple gate connection electrodes 78) within the multiple gate openings 82.

[0425] The second upper electrode film 99 serves as the main body of the gate wiring 100 and is stacked in a film-like manner on the second lower electrode film 98, forming the second wiring surface 101, the upper part of the second inner sidewall 102, and the upper part of the second outer sidewall 103 of the gate wiring 100.

[0426] The second upper electrode film 99 covers the region in the first inorganic film 75 where the plurality of gate openings 82 are formed in a film-like manner, and backfills the plurality of gate openings 82. The second upper electrode film 99 is electrically connected to the plurality of gate structures 25 (the plurality of gate connection electrodes 78) within the plurality of gate openings 82 via the second lower electrode film 98.

[0427] Semiconductor device 1 includes an insulating second inorganic film 110 selectively covering a first inorganic film 75. The second inorganic film 110 may also be referred to as an "inorganic insulating film (second inorganic insulating film)," an "upper insulating film," a "passivation film," etc. The second inorganic film 110 may also include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0428] The second inorganic membrane 110 preferably comprises an insulating material different from the insulating material of the first inorganic membrane 75. Specifically, the second inorganic membrane 110 preferably comprises an insulating material different from the insulating material of the upper inorganic membrane 77. In this embodiment, the second inorganic membrane 110 has a single-layer structure composed of a silicon nitride membrane.

[0429] The second inorganic film 110 preferably has a thickness less than that of the source electrode 85 (gate electrode 95). The thickness of the second inorganic film 110 is preferably greater than that of the lower inorganic film 76. The thickness of the second inorganic film 110 is preferably greater than that of the upper inorganic film 77. The thickness of the second inorganic film 110 is preferably greater than that of the first inorganic film 75 (total thickness).

[0430] Of course, the thickness of the second inorganic membrane 110 can also be less than the thickness (total thickness) of the first inorganic membrane 75. The thickness of the second inorganic membrane 110 can also be less than the thickness of the upper inorganic membrane 77. The thickness of the second inorganic membrane 110 can also be less than the thickness of the lower inorganic membrane 76.

[0431] The thickness of the second inorganic film 110 can be greater than or less than the depth of the second face portion 9. The thickness of the second inorganic film 110 can be greater than or less than the depth of the gate structure 25. The thickness of the second inorganic film 110 can be greater than or less than the depth of the first source structure 30.

[0432] The thickness of the second inorganic membrane 110 can be 0.01 μm or more and 5 μm or less. The thickness of the second inorganic membrane 110 can have a value belonging to at least one of the following ranges: 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The thickness of the second inorganic membrane 110 is preferably 0.1 μm or more and 2 μm or less.

[0433] The second inorganic film 110 selectively covers the source electrode 85, the source wiring 90, the gate electrode 95, and the gate wiring 100 on the first inorganic film 75. Specifically, the second inorganic film 110 has a first inner covering portion 111, a second inner covering portion 112, an outer covering portion 113, and a removal portion 114.

[0434] The first inner cover 111 selectively covers the source electrode 85. Specifically, the first inner cover 111 covers the first electrode surface 86 of the source electrode 85 in a film-like manner, exposing at least a portion of the first electrode sidewall 87 of the source electrode 85. In this configuration, the first inner cover 111 exposes the entire area of ​​the first electrode sidewall 87. Specifically, the first inner cover 111 covers the first electrode surface 86 at a distance from the first electrode sidewall 87, and also exposes the periphery of the first electrode surface 86 in addition to the first electrode sidewall 87.

[0435] The first inner cover portion 111 extends flatly over the first electrode surface 86. The first inner cover portion 111 covers the periphery of the first electrode surface 86 (source electrode 85), exposing the interior of the first electrode surface 86 (source electrode 85).

[0436] The first inner cover portion 111 extends in a strip shape along the first electrode sidewall 87 at the periphery of the first electrode surface 86. The first inner cover portion 111 has a portion extending along the first pad portion 85a, a portion extending along the second pad portion 85b, and a portion extending along the third pad portion 85c.

[0437] In this embodiment, the first inner cover portion 111 has an extension portion 115 extending from the source electrode 85 to the connection portion between the source electrode 85 and the source wiring 90. In this embodiment, the extension portion 115 is wider than the other portions. Of course, the extension portion 115 may also have a width approximately equal to the other portions.

[0438] The extension 115 covers the connection portion of the source electrode 85 and the source wiring 90 at intervals from the first electrode sidewall 87 of the source electrode 85 and the first outer sidewall 93 of the source wiring 90. Preferably, the extension 115 covers the connection portion of the source electrode 85 and the source wiring 90 at intervals from the second face portion 9 toward the first face portion 8. Alternatively, the extension 115 may also have a portion that crosses the second connection face portion 10B and covers the source wiring 90.

[0439] In this configuration, the first inner cover 111 is formed as an annular shape surrounding the interior of the first electrode surface 86 when viewed from above. The first inner cover 111 is also formed as a polygonal annular shape with four sides parallel to the periphery of the chip 2 when viewed from above. Specifically, the first inner cover 111 is formed as a polygonal annular shape (U-shaped) that matches the planar shape of the first electrode surface 86 when viewed from above.

[0440] The first inner cover portion 111 defines a first pad opening 116 that exposes the interior of the first electrode surface 86. The first pad opening 116, when viewed from above, is divided into a polygonal shape with four sides parallel to the periphery of the chip 2. In this embodiment, the first pad opening 116, when viewed from above, is divided into a polygonal shape (U-shape) that matches the planar shape of the first electrode surface 86.

[0441] The first inner cover portion 111 can be opposed to the active region 12 through the first inorganic film 75 and the source electrode 85. That is, the first inner cover portion 111 can be opposed to one or more gate structures 25 and / or one or more first source structures 30 through the first inorganic film 75 and the source electrode 85.

[0442] The first inner cover portion 111 may be opposed to one or both of the first terminal region 15 and the second terminal region 16 through the first inorganic film 75 and the source electrode 85. That is, the first inner cover portion 111 may be opposed to one or more dummy gate structures 50 and / or one or more third source structures 55 through the first inorganic film 75 and the source electrode 85.

[0443] The first inner cover portion 111 may be opposed to one or both of the third terminal region 17 and the fourth terminal region 18 through the first inorganic film 75 and the source electrode 85. That is, the first inner cover portion 111 may be opposed to one or more fourth source structures 65 through the first inorganic film 75 and the source electrode 85.

[0444] The first inner cover portion 111 preferably has a width larger than the thickness of the source electrode 85. Of course, the width of the first inner cover portion 111 may also be smaller than the thickness of the source electrode 85. The width of the first inner cover portion 111 may be more than 1 μm and less than 100 μm.

[0445] The width of the first inner cover 111 may have a value belonging to at least one of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, and 90 μm or more and 100 μm or less.

[0446] Preferably, the first inner cover portion 111 is formed at a distance from the first electrode sidewall 87 that is larger than the thickness of the source electrode 85. Of course, the spacing of the first inner cover portion 111 can also be smaller than the thickness of the source electrode 85. The spacing of the first inner cover portion 111 can be 0.1 μm or more and 100 μm or less.

[0447] The spacing of the first inner cover portion 111 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 1 μm or less, 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, and 90 μm or more and 100 μm or less.

[0448] The second inner cover 112 selectively covers the gate electrode 95. Specifically, the second inner cover 112 covers the second electrode surface 96 of the gate electrode 95 in a film-like manner, exposing at least a portion of the second electrode sidewall 97 of the gate electrode 95. In this configuration, the second inner cover 112 exposes the entire area of ​​the second electrode sidewall 97. Specifically, the second inner cover 112 covers the second electrode surface 96 at a distance from the second electrode sidewall 97, and also exposes the periphery of the second electrode surface 96 in addition to the second electrode sidewall 97.

[0449] The second inner cover portion 112 extends flatly over the second electrode surface 96. The second inner cover portion 112 covers the periphery of the second electrode surface 96 (gate electrode 95), exposing the interior of the second electrode surface 96 (gate electrode 95). The second inner cover portion 112 extends in a strip shape along the second electrode sidewall 97 at the periphery of the second electrode surface 96.

[0450] In this embodiment, the second inner cover 112 is formed as a ring surrounding the interior of the second electrode surface 96 when viewed from above. The second inner cover 112 is also formed as a polygonal ring with four sides parallel to the periphery of the chip 2 (in this embodiment, a quadrilateral ring). Specifically, the second inner cover 112 is formed as a polygonal ring (specifically, a quadrilateral ring) that matches the planar shape of the second electrode surface 96 when viewed from above.

[0451] The second inner cover 112 divides out a second pad opening 117 that exposes the interior of the second electrode surface 96. The second pad opening 117 is divided into a polygonal shape (in this embodiment, a quadrilateral shape) with four sides parallel to the periphery of the chip 2 when viewed from above.

[0452] The second inner cover portion 112 can be opposed to the active region 12 through the first inorganic film 75 and the gate electrode 95. That is, the second inner cover portion 112 can be opposed to one or more gate structures 25 and / or one or more first source structures 30 through the first inorganic film 75 and the gate electrode 95.

[0453] The second inner cover portion 112 can be opposed to the first terminal region 15 through the first inorganic film 75 and the gate electrode 95. That is, the second inner cover portion 112 can be opposed to one or more dummy gate structures 50 and / or one or more third source structures 55 through the first inorganic film 75 and the gate electrode 95.

[0454] The second inner cover portion 112 can be opposed to the third terminal region 17 through the first inorganic film 75 and the gate electrode 95. That is, the second inner cover portion 112 can be opposed to one or more fourth source structures 65 through the first inorganic film 75 and the gate electrode 95.

[0455] The second inner cover portion 112 preferably has a width greater than the thickness of the gate electrode 95. Of course, the width of the second inner cover portion 112 may also be less than the thickness of the gate electrode 95. The width of the second inner cover portion 112 may be approximately equal to the width of the first inner cover portion 111. Of course, the width of the second inner cover portion 112 may be less than or greater than the width of the first inner cover portion 111. The width of the second inner cover portion 112 may be 1 μm or more and 100 μm or less.

[0456] The width of the second inner cover 112 may have a value belonging to at least one of the following ranges: 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, and 90 μm or more and 100 μm or less.

[0457] Preferably, the second inner cover portion 112 is formed with a spacing greater than the thickness of the gate electrode 95, spaced from the second electrode sidewall 97. Of course, the spacing of the second inner cover portions 112 can also be less than the thickness of the gate electrode 95. The spacing between the second inner cover portions 112 can be approximately equal to the spacing of the first inner cover portions 111. The spacing of the second inner cover portions 112 can be less than or greater than the spacing of the first inner cover portions 111. The spacing of the second inner cover portions 112 can be 0.1 μm or more and 100 μm or less.

[0458] The spacing of the second inner cover 112 may have a value belonging to at least one of the following ranges: 0.1 μm or more and 1 μm or less, 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, and 90 μm or more and 100 μm or less.

[0459] The outer cover 113 selectively covers the first inorganic film 75 at intervals from the first inner cover 111 and the second inner cover 112. Specifically, the outer cover 113 is formed on the cover portion of the first inorganic film 75 opposite to the second face 9. The outer cover 113 extends in a strip shape along the first face 8 when viewed from above. The outer cover 113 is formed in a ring shape (in this embodiment, a quadrilateral ring) surrounding the first face 8 when viewed from above.

[0460] The outer cover 113 covers the outer well region 70 and multiple field regions 72 on the second face 9 side via the first inorganic film 75. The outer cover 113 extends from above the first inorganic film 75 into the anchoring opening 83 on the second face 9 side, and is mechanically connected to the second face 9 (second semiconductor region 7) within the anchoring opening 83.

[0461] The outer cover 113 extends in a membrane-like manner along the second face 9 within the anchoring opening 83. The outer cover 113 divides the cover portion relative to the anchoring opening 83 into an anchoring groove 118 that is recessed toward the anchoring opening 83.

[0462] When the first inorganic membrane 75 forms a plurality of anchoring openings 83, the outer cover 113 is divided into a plurality of anchoring grooves 118. The anchoring grooves 118 have a planar shape that is substantially similar to the planar shape of the anchoring openings 83. When viewed from above, the anchoring grooves 118 extend in a strip shape (in this embodiment, annular) along the anchoring openings 83.

[0463] In this configuration, the outer cover 113 extends from the anchoring opening 83 toward the periphery (first to fourth side surfaces 5A to 5D) of the second face surface 9. The outer cover 113 is formed at intervals from the periphery of the second face surface 9 toward the interior, so that the first inorganic membrane 75 is exposed from the periphery of the second face surface 9.

[0464] The outer cover 113 covers at least a portion of the source wiring 90 on the second face 9 side. The outer cover 113 preferably covers at least a portion of the first outer sidewall 93 of the source wiring 90. In this configuration, the outer cover 113 covers the entire area of ​​the source wiring 90 in cross-section.

[0465] The outer cover portion 113 forms a film covering the first wiring surface 91 of the source wiring 90 and extends flatly above the first wiring surface 91, mimicking the gradient of the first wiring surface 91. The outer cover portion 113 forms a film covering the first inner sidewall 92 of the source wiring 90 and has an inclined surface extending in mimicking the inclined surface of the first inner sidewall 92. The outer cover portion 113 forms a film covering the first outer sidewall 93 of the source wiring 90 and has an inclined surface extending in mimicking the inclined surface of the first outer sidewall 93.

[0466] In this configuration, the outer cover 113, when viewed from above, covers the entire area of ​​the source wiring 90 except for the connection between the source electrode 85 and the source wiring 90. The outer cover 113 exposes the first outer sidewall 93 of the source wiring 90 at the connection between the source electrode 85 and the source wiring 90. This allows the stress generated at the source electrode 85 to be suppressed from being transferred to the second inorganic film 110 via the source wiring 90.

[0467] The outer cover portion 113 extends from the second face portion 9 to the first face portion 8 via the source wiring 90. That is, the outer cover portion 113 has a portion that faces the outer opening 81 across the source wiring 90. In addition, the outer cover portion 113 has a portion that faces the sidewall wiring 79 across the first inorganic film 75 (upper inorganic film 77) and the source wiring 90.

[0468] The outer cover 113 covers at least a portion of the gate wiring 100 on the first face 8 side. The outer cover 113 preferably covers at least a portion of the second outer sidewall 103 of the gate wiring 100. In this configuration, the outer cover 113 covers the entire area of ​​the gate wiring 100 in cross-section.

[0469] The outer cover portion 113 forms a film covering the second wiring surface 101 of the gate wiring 100 and extends flatly above the second wiring surface 101 following the gradient of the second wiring surface 101. The outer cover portion 113 forms a film covering the second inner sidewall 102 of the gate wiring 100 and has an inclined surface extending following the inclined surface of the second inner sidewall 102. The outer cover portion 113 forms a film covering the second outer sidewall 103 of the gate wiring 100 and has an inclined surface extending following the inclined surface of the second outer sidewall 103.

[0470] In this configuration, the outer cover 113 covers the entire area of ​​the gate wiring 100 except for the connection between the gate electrode 95 and the gate wiring 100 when viewed from above. The outer cover 113 exposes the second outer sidewall 103 of the gate wiring 100 at the connection between the gate electrode 95 and the gate wiring 100. This allows the stress generated at the gate electrode 95 to be suppressed from being transferred to the second inorganic film 110 via the gate wiring 100.

[0471] The outer cover 113 covers the first inorganic film 75 at a distance from the first inner cover 111 and the second inner cover 112 on the side of the first face 8. The outer cover 113 covers the first inorganic film 75 in such a way that at least a portion of the first electrode sidewall 87 of the source electrode 85 is exposed.

[0472] In this configuration, the outer cover 113 covers the first inorganic film 75 at a distance from the first electrode sidewall 87, exposing the entire area of ​​the first electrode sidewall 87. In this configuration, the outer cover 113 has an inner edge located between the first electrode sidewall 87 of the source electrode 85 and the second inner sidewall 102 of the gate wiring 100. The inner edge of the outer cover 113 extends along the first electrode sidewall 87 at a distance from it.

[0473] The outer cover 113 covers the first inorganic film 75 in such a way that at least a portion of the second electrode sidewall 97 of the gate electrode 95 is exposed. In this manner, the outer cover 113 covers the first inorganic film 75 at a distance from the second electrode sidewall 97, thereby exposing the entire area of ​​the second electrode sidewall 97.

[0474] That is, when viewed from above, the outer cover portion 113 surrounds both the source electrode 85 and the gate electrode 95 at a distance, spaced apart from them. The inner edge of the outer cover portion 113 is located between the first inner sidewall 92 of the source wiring 90 and the second electrode sidewall 97 of the gate electrode 95. The inner edge of the outer cover portion 113 extends along the second electrode sidewall 97 at a distance, spaced apart from it.

[0475] The outer cover portion 113 may be opposed to the active region 12 through the first inorganic film 75. That is, the outer cover portion 113 may be opposed to one or more gate structures 25 and / or one or more first source structures 30 through the first inorganic film 75.

[0476] The outer cover portion 113 may be opposed to one or both of the first side end region 13 and the second side end region 14 through the first inorganic film 75. That is, the outer cover portion 113 may be opposed to one or more first source structures 30 and / or one or more second source structures 40 through the first inorganic film 75.

[0477] The outer cover portion 113 may be positioned opposite one or both of the first terminal region 15 and the second terminal region 16 through the first inorganic film 75. That is, the outer cover portion 113 may be positioned opposite one or more dummy gate structures 50 and / or one or more third source structures 55 through the first inorganic film 75.

[0478] The outer cover portion 113 may be positioned opposite one or both of the third terminal region 17 and the fourth terminal region 18 through the first inorganic membrane 75. That is, the outer cover portion 113 may be positioned opposite one or more fourth source structures 65 through the first inorganic membrane 75.

[0479] The removal section 114 includes a first removal section 114a, a second removal section 114b, and a third removal section 114c. The first removal section 114a is divided into a region between a first inner covering section 111 and an outer covering section 113, exposing the first electrode sidewall 87 of the source electrode 85. In this embodiment, the first removal section 114a extends in a strip along the first electrode sidewall 87, exposing the periphery of the first electrode surface 86, the first electrode sidewall 87, and the first inorganic film 75 between the source electrode 85 and the gate wiring 100.

[0480] The second removal portion 114b is divided into a region between the second inner covering portion 112 and the outer covering portion 113, and communicates with the first removal portion 114a. The second removal portion 114b exposes the second electrode sidewall 97 of the gate electrode 95. In this embodiment, the second removal portion 114b extends in a strip along the second electrode sidewall 97, exposing the periphery of the second electrode surface 96, the second electrode sidewall 97, and the first inorganic film 75 between the source wiring 90 and the gate electrode 95.

[0481] The third removal section 114c is divided into the region between the first inner covering section 111 and the second inner covering section 112, and communicates with the first removal section 114a and the second removal section 114b. The third removal section 114c exposes the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95.

[0482] In this method, the third removal portion 114c extends in a strip along the first electrode sidewall 87 and the second electrode sidewall 97, exposing the periphery of the first electrode surface 86, the first electrode sidewall 87, the periphery of the second electrode surface 96, the second electrode sidewall 97, and the first inorganic film 75 between the gate electrode 95 and the source electrode 85.

[0483] Semiconductor device 1 includes an insulating organic film 120 selectively covering a second inorganic film 110. The organic film 120 may also be referred to as an "organic insulating film," a "resin film," or the like. The organic film 120 preferably comprises a transparent resin or a light-transmitting resin.

[0484] The organic film 120 preferably comprises a photosensitive resin. The photosensitive resin can be negative or positive. The organic film 120 may comprise at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0485] The organic film 120 may have a thickness greater than the depth of the gate structure 25. The thickness of the organic film 120 may also be greater than the depth of the first source structure 30. The thickness of the organic film 120 may be greater than the thickness (total thickness) of the first inorganic film 75. The thickness of the organic film 120 may be greater than the thickness of the source electrode 85 (gate electrode 95).

[0486] The thickness of the organic film 120 can be greater than the thickness of the second inorganic film 110. Preferably, the thickness of the organic film 120 is less than the thickness of the chip 2. The thickness of the organic film 120 can be greater than or less than the thickness of the second semiconductor region 7.

[0487] The thickness of the organic film 120 can be greater than 1 μm and less than 25 μm. The thickness of the organic film 120 can have a value belonging to at least one of the following ranges: greater than 1 μm and less than 5 μm, greater than 5 μm and less than 10 μm, greater than 10 μm and less than 15 μm, greater than 15 μm and less than 20 μm, and greater than 20 μm and less than 25 μm.

[0488] Organic membrane 120 extends across the first face 8, passing through the first to fourth connecting faces 10A to 10D, and covers the second face 9. Organic membrane 120 fills the removal portion 114 of the second inorganic membrane 110 on the side of the first face 8, and directly covers the first inner covering portion 111, the second inner covering portion 112, and the outer covering portion 113 of the second inorganic membrane 110.

[0489] The organic membrane 120 spans the first inner cover portion 111 and the outer cover portion 113, and has a portion that fills the area between the first inner cover portion 111 and the outer cover portion 113 (i.e., the first removal portion 114a). The organic membrane 120 directly covers the first electrode sidewall 87 of the source electrode 85 in the first removal portion 114a.

[0490] In this configuration, the organic film 120 directly covers the periphery of the first electrode surface 86 and the first electrode sidewall 87 in the first removal portion 114a. The organic film 120 directly covers the portion of the first inorganic film 75 exposed between the first electrode sidewall 87 of the source electrode 85 and the outer cover portion 113 (gate wiring 100) in the first removal portion 114a.

[0491] The organic film 120 spans the second inner cover portion 112 and the outer cover portion 113, and has a portion that fills the area between the second inner cover portion 112 and the outer cover portion 113 (i.e., the second removal portion 114b). The organic film 120 directly covers the second electrode sidewall 97 of the gate electrode 95 in the second removal portion 114b.

[0492] In this configuration, the organic film 120 directly covers the periphery of the second electrode surface 96 and the second electrode sidewall 97 in the second removal portion 114b. The organic film 120 also directly covers the portion of the first inorganic film 75 exposed between the second electrode sidewall 97 of the gate electrode 95 and the outer cover portion 113 (source wiring 90) in the second removal portion 114b.

[0493] The organic film 120 spans the first inner cover portion 111 and the second inner cover portion 112, and has a portion that fills the area between the first inner cover portion 111 and the second inner cover portion 112 (i.e., the third removal portion 114c). The organic film 120 directly covers both the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95 in the third removal portion 114c.

[0494] In this embodiment, the organic film 120 directly covers the periphery of the first electrode surface 86, the first electrode sidewall 87, the periphery of the second electrode surface 96, and the second electrode sidewall 97 in the third removal section 114c. The organic film 120 also directly covers the portion of the first inorganic film 75 exposed between the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95 in the third removal section 114c.

[0495] The organic film 120 covers the first inner cover portion 111 all around the perimeter, dividing the first upper pad opening 121 to expose the interior of the first electrode surface 86 (see reference). Figures 1-3 Specifically, the organic film 120 covers the first inner cover portion 111 at intervals from the inner edge (inner wall) to the outer edge (outer wall) side, exposing the inner edge of the first inner cover portion 111. That is, the wall surface of the first upper pad opening 121 is located on the side closer to the first electrode sidewall 87 than the wall surface of the first pad opening 116, and is opposite to the first electrode surface 86 through the first inner cover portion 111.

[0496] The organic film 120 covers the second inner cover portion 112 all around the perimeter, dividing the second upper pad opening 122 to expose the interior of the second electrode surface 96 (see reference). Figures 1-3 Specifically, the organic film 120 covers the second inner cover portion 112 at intervals from the inner edge (inner wall) to the outer edge (outer wall) side, exposing the inner edge of the second inner cover portion 112. That is, the wall surface of the second upper pad opening 122 is located closer to the second electrode sidewall 97 than the wall surface of the second pad opening 117, and is opposite to the second electrode surface 96 across the second inner cover portion 112.

[0497] The organic film 120 extends from the source electrode 85 and the gate electrode 95 toward the gate wiring 100 side and covers at least a portion of the gate wiring 100 via the outer cover portion 113. The organic film 120 preferably covers the second outer sidewall 103 of the gate wiring 100 via the outer cover portion 113.

[0498] In this configuration, the organic film 120 covers the entire area of ​​the gate wiring 100 in cross-section, separated by the outer cover portion 113. That is, the organic film 120 has the following components in cross-section: a portion covering the second wiring surface 101 in cross-section, a portion covering the second inner sidewall 102 in cross-section, and a portion covering the second outer sidewall 103 in cross-section.

[0499] In this embodiment, the organic film 120 has a portion at the connection between the gate electrode 95 and the gate wiring 100 that directly covers the portion of the second outer sidewall 103 of the gate wiring 100 that is exposed from the second inner cover portion 112 and the outer cover portion 113. The organic film 120 also covers the second wiring surface 101 of the gate wiring 100 at the connection between the gate electrode 95 and the gate wiring 100.

[0500] An organic film 120 extends from the gate wiring 100 toward the source wiring 90 and covers at least a portion of the source wiring 90 via an outer cover portion 113. The organic film 120 has a portion that directly covers the outer cover portion 113 in the area between the source wiring 90 and the gate wiring 100.

[0501] The organic film 120 preferably covers the first outer sidewall 93 of the source wiring 90 through the outer cover portion 113. In this configuration, the organic film 120 covers the entire area of ​​the source wiring 90 through the outer cover portion 113 when viewed in cross-section. That is, the organic film 120 has: a portion covering the first wiring surface 91 through the outer cover portion 113 when viewed in cross-section, a portion covering the first inner sidewall 92 through the outer cover portion 113, and a portion covering the first outer sidewall 93 through the outer cover portion 113.

[0502] In this embodiment, the organic film 120 has a portion at the connection between the source electrode 85 and the source wiring 90 that directly covers the portion of the first outer sidewall 93 of the source wiring 90 that is exposed from the first inner cover portion 111 and the outer cover portion 113. In this embodiment, the organic film 120 also covers the first wiring surface 91 of the source wiring 90 at the connection between the source electrode 85 and the source wiring 90.

[0503] The organic film 120 extends from the first surface 8 side to the second surface 9 side via the source wiring 90. That is, the organic film 120 has a portion that faces the external opening 81 across the source wiring 90. In addition, the organic film 120 has a portion that faces the sidewall wiring 79 across the source wiring 90.

[0504] The organic membrane 120 covers the outer trap region 70 and multiple field regions 72 on the second face surface 9 side, separated by the first inorganic membrane 75 and the second inorganic membrane 110. The organic membrane 120 covers the anchoring opening 83 on the periphery of the second face surface 9, separated by the second inorganic membrane 110. The organic membrane 120 engages with the anchoring groove 118 of the second inorganic membrane 110 (the anchoring opening 83 of the first inorganic membrane 75).

[0505] In this configuration, the organic membrane 120 extends from the anchoring opening 83 toward the periphery of the second face surface 9 (first to fourth side surfaces 5A to 5D). The organic membrane 120 is formed at intervals from the periphery of the second face surface 9 toward the interior, so that the first inorganic membrane 75 is exposed from the periphery of the second face surface 9. In this configuration, the organic membrane 120 covers the outer cover portion 113 at intervals from the outer edge (outer wall) of the outer cover portion 113 toward the interior, so that the outer edge of the outer cover portion 113 is exposed.

[0506] Semiconductor device 1 includes a drain electrode 125 covering a second main surface 4. The drain electrode 125 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 125 may also be referred to as an "electrode", "third electrode", "third pad electrode", "third main surface electrode", "third terminal electrode", "drain pad electrode", etc.

[0507] The drain electrode 125 is electrically connected to the first semiconductor region 6. The drain electrode 125 may cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (first to fourth side surfaces 5A to 5D) of the second main surface 4. Alternatively, the drain electrode 125 may partially cover the second main surface 4 such that the periphery of the second main surface 4 is exposed.

[0508] The breakdown voltage that can be applied between the source electrode 85 and the drain electrode 125 (between the first main surface 3 and the second main surface 4) can be 500V or more and 3000V or less. The breakdown voltage can have a value belonging to at least one of the following ranges: 500V or more and 1000V or less, 1000V or more and 1500V or less, 1500V or more and 2000V or less, 2000V or more and 2500V or less, and 2500V or more and 3000V or less.

[0509] The semiconductor device 1 (electronic component) includes: an insulating first inorganic film 75 (covered object), a source electrode 85 (electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The source electrode 85 is disposed on the first inorganic film 75, and has a first electrode sidewall 87 on the first inorganic film 75. The source wiring 90 is disposed on the first inorganic film 75 around the source electrode 85.

[0510] The second inorganic film 110 has a first inner cover portion 111 that covers the source electrode 85 in a manner that exposes the sidewall 87 of the first electrode, and an outer cover portion 113 that covers the source wiring 90 at a distance from the first inner cover portion 111. An organic film 120 spans the first inner cover portion 111 and the outer cover portion 113, covering the source electrode 85 between the first inner cover portion 111 and the outer cover portion 113.

[0511] Based on this structure, a semiconductor device 1 with a novel layout is provided. Since the semiconductor device 1 is to be used in various environments depending on its application, it requires durability suitable for various operating conditions.

[0512] For example, when semiconductor device 1 is installed in vehicles such as hybrid vehicles, electric vehicles, and fuel cell vehicles that are driven by motors, excellent durability suitable for these operating environments is required. The durability of semiconductor device 1 is evaluated, for example, by a high-temperature and high-humidity bias test. In the high-temperature and high-humidity bias test, the electrical operation of semiconductor device 1 is evaluated under conditions of exposure to high temperature and high humidity.

[0513] Under high-temperature conditions, the stress caused by the thermal expansion of the source electrode 85 will concentrate near the first electrode sidewall 87 of the source electrode 85. When the second inorganic film 110 covers the first electrode sidewall 87, the second inorganic film 110 may peel off from the first electrode sidewall 87 due to the stress of the source electrode 85. In the event of peeling of the second inorganic film 110, moisture may penetrate from the peeled portion of the second inorganic film 110 in a high-humidity environment.

[0514] In this regard, in the semiconductor device 1, the first inner cover portion 111 of the second inorganic film 110 exposes the first electrode sidewall 87, and the outer cover portion 113 of the second inorganic film 110 is formed at a distance from the first inner cover portion 111. As a result, the peeling start point of the second inorganic film 110 caused by the stress of the source electrode 85 can be reduced, and the peeling of the second inorganic film 110 can be suppressed.

[0515] On the other hand, the organic film 120 covers the exposed portion of the source electrode 85 in the region between the first inner cover portion 111 and the outer cover portion 113. The organic film 120 has a lower hardness than the second inorganic film 110. Therefore, even if the source electrode 85 experiences stress caused by thermal expansion, the organic film 120 can elastically absorb the stress. As a result, it is possible to prevent the organic film 120 from peeling off from the sidewall 87 of the first electrode, and the source electrode 85 is protected by the organic film 120.

[0516] In the layout of the source wiring 90 around the source electrode 85, sometimes a higher electric field is concentrated near the source wiring 90 than on the source electrode 85 side. In a high-temperature environment, when moisture reaches the source wiring 90 from the stripping section, the high electric field near the source wiring 90 may accelerate the oxidation reaction of the moisture and the source wiring 90.

[0517] In this regard, in semiconductor device 1, the source wiring 90 is protected by the outer cover portion 113, thus suppressing the contact of moisture (water) with the source wiring 90. This suppresses oxidation of the source wiring 90. Consequently, it suppresses the reduction in adhesion of the organic film 120 and the reduction in wiring resistance of the source wiring 90 caused by oxidation.

[0518] The source wiring 90 has a first outer sidewall 93 (wiring sidewall) on the side opposite to the source electrode 85 when viewed in cross-section. In this case, the outer cover portion 113 of the second inorganic film 110 preferably covers the first outer sidewall 93 of the source wiring 90 when viewed in cross-section.

[0519] The organic film 120 preferably covers the first outer sidewall 93 of the source wiring 90 in cross-section, separated by the outer cover portion 113. According to this structure, oxidation of the source wiring 90 originating from the first outer sidewall 93 can be appropriately suppressed. Such a structure is particularly effective when the electric field is concentrated on the side of the first outer sidewall 93.

[0520] The outer cover 113 can cover the entire area of ​​the source wiring 90 when viewed in cross-section. In this case, the organic film 120 can cover the entire area of ​​the source wiring 90 through the outer cover 113 when viewed in cross-section. According to this structure, oxidation of the source wiring 90 is appropriately suppressed throughout the entire area of ​​the source wiring 90.

[0521] The first inner cover 111 preferably covers the source electrode 85 at a distance from the first electrode sidewall 87. According to this structure, peeling of the first inner cover 111 caused by thermal expansion of the source electrode 85 can be appropriately suppressed.

[0522] The outer cover 113 preferably exposes the first electrode sidewall 87. This structure effectively suppresses peeling of the outer cover 113 caused by thermal expansion of the source electrode 85. The outer cover 113 preferably covers the first inorganic film 75 at a distance from the first electrode sidewall 87.

[0523] The organic film 120 preferably has a portion that directly covers the first electrode sidewall 87. According to this structure, the first electrode sidewall 87 is suitably protected by the organic film 120. The first inner cover portion 111 preferably exposes the periphery of the source electrode 85. In this case, the organic film 120 preferably has a portion that directly covers both the first electrode sidewall 87 and the periphery of the source electrode 85.

[0524] The organic membrane 120 preferably has a portion in the region between the source electrode 85 and the source wiring 90 that directly covers the exposed portion between the source electrode 85 and the outer cover portion 113 in the first inorganic membrane 75.

[0525] The organic membrane 120 preferably has a portion that directly covers the exposed portion between the source electrode 85 and the outer cover portion 113 in the first inorganic membrane 75. According to these structures, while suppressing the peeling of the organic membrane 120, the intrusion of moisture can be suppressed by increasing the surface distance.

[0526] The first inner cover 111 preferably exposes the interior of the source electrode 85. According to this structure, the interior of the source electrode 85 is used as the potential application terminal. The organic film 120 may expose the edge of the first inner cover 111 on the interior side of the source electrode 85. The source wiring 90 may be electrically connected to the source electrode 85. The source wiring 90 may also be led out from the source electrode 85. The source wiring 90 may also be the outermost peripheral wiring.

[0527] Semiconductor device 1 may include: a gate wiring 100 (second wiring) disposed on a first inorganic film 75 in a region between a source electrode 85 and a source wiring 90. The gate wiring 100 is electrically disconnected from the source wiring 90. An organic film 120 may also cover the gate wiring 100. According to this structure, the gate wiring 100 is protected by the organic film 120.

[0528] The outer cover 113 can cover the gate wiring 100. In this case, the organic film 120 can cover the gate wiring 100 through the outer cover 113. According to this structure, the contact of moisture (water) with the gate wiring 100 is suppressed by the outer cover 113. As a result, oxidation of the gate wiring 100 can be suppressed.

[0529] The outer cover 113 can cover the entire area of ​​the gate wiring 100 when viewed in cross-section. In this case, the organic film 120 can also cover the entire area of ​​the gate wiring 100 through the outer cover 113 when viewed in cross-section. According to this structure, oxidation of the gate wiring 100 is appropriately suppressed throughout the entire area of ​​the gate wiring 100.

[0530] The first inorganic membrane 75 may have an anchoring opening 83. In this case, the second inorganic membrane 110 may have a portion located within the anchoring opening 83. According to this structure, the adhesion force of the second inorganic membrane 110 relative to the first inorganic membrane 75 is increased by the anchoring opening 83. This prevents the second inorganic membrane 110 from peeling off from the first inorganic membrane 75. Furthermore, by increasing the surface distance through the anchoring opening 83, the intrusion of moisture (water) can be suppressed.

[0531] The organic membrane 120 can cover the portion of the second inorganic membrane 110 that covers the anchoring opening 83. According to this structure, the adhesion force of the organic membrane 120 relative to the second inorganic membrane 110 is enhanced by the unevenness of the second inorganic membrane 110 caused by the anchoring opening 83. This suppresses the peeling of the organic membrane 120 from the second inorganic membrane 110.

[0532] Semiconductor device 1 may include chip 2. A first inorganic film 75 may be formed on chip 2. Semiconductor device 1 may include an active region 12 disposed inside chip 2 and an outer peripheral region 19 disposed at the periphery of chip 2. In this case, the first inorganic film 75 may cover both the active region 12 and the outer peripheral region 19. A source electrode 85 may be disposed on the active region 12. A source wiring 90 may be disposed on the outer peripheral region 19.

[0533] The electric field on the peripheral region 19 side is tending to be higher than that on the active region 12 side. Therefore, for the source wiring 90 on the peripheral region 19 side, the electric field concentration is sometimes higher than that on the source electrode 85 side. Consequently, when moisture (water) intrudes from the peripheral region 19 side, the risk of oxidation of the source wiring 90 is higher than that of the source electrode 85. Therefore, the structure that protects the source wiring 90 by the outer cover 113 is particularly effective in structures where the source wiring 90 is disposed in the peripheral region 19.

[0534] Chip 2 preferably comprises SiC. According to this structure, semiconductor device 1 is provided as a SiC semiconductor device. According to the SiC semiconductor device, it exhibits excellent electrical characteristics and durability under harsh operating environments.

[0535] From another perspective, the semiconductor device 1 (electronic component) includes: a source electrode 85 (terminal electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The source wiring 90 is disposed around the source electrode 85. The second inorganic film 110 covers the source wiring 90 at a distance from the source electrode 85. The organic film 120 has a portion that directly covers the source electrode 85 and a portion that covers the source wiring 90 through the second inorganic film 110.

[0536] According to this structure, a semiconductor device 1 with a novel layout is provided. For example, according to the semiconductor device 1, peeling of the second inorganic film 110 caused by stress on the source electrode 85 can be suppressed, and oxidation of the source wiring 90 is suppressed by the second inorganic film 110. In addition, both the source electrode 85 and the source wiring 90 are protected by an organic film 120.

[0537] From another perspective, the semiconductor device 1 (electronic component) includes: a first region (12), a second region (19), a source electrode 85 (terminal electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The first region (12) has a first electric field. The second region (19) has a second electric field around the first region (12) that is higher than the first electric field. In this embodiment, the active region 12 is exemplified as one embodiment of the first region (12), and the peripheral region 19 is exemplified as one embodiment of the second region (19).

[0538] A source electrode 85 is disposed in a first region (12). A source wiring 90 is disposed around the source wiring 90 in a second region (19). A second inorganic film 110 exposes the source electrode 85 and covers the source wiring 90. An organic film 120 has a portion that directly covers the source electrode 85 and a portion that covers the source wiring 90 through the second inorganic film 110.

[0539] According to this structure, a semiconductor device 1 with a novel layout is provided. For example, according to the semiconductor device 1, peeling of the second inorganic film 110 caused by stress on the source electrode 85 can be suppressed, and oxidation of the source wiring 90 is suppressed by the second inorganic film 110. In particular, according to this semiconductor device 1, moisture (water) and oxidation reactions of the source wiring 90 caused by a second electric field near the source wiring 90 can be suppressed. In addition, both the source electrode 85 and the source wiring 90 are protected by an organic film 120.

[0540] From another perspective, the semiconductor device 1 includes: a chip 2, an active region 12, a peripheral region 19, a transistor structure Tr (device structure), an outer well region 70 (impurity region), a source electrode 85 (electrode), a source wiring 90 (wiring), an insulating second inorganic film 110, and an insulating organic film 120.

[0541] Chip 2 has a first main surface 3. An active region 12 is disposed inside the first main surface 3. An outer peripheral region 19 is disposed at the periphery of the first main surface 3. A transistor structure Tr is formed in the active region 12 on the first main surface 3. An outer well region 70 is formed in the outer peripheral region 19 on the surface of the first main surface 3.

[0542] A source electrode 85 is disposed on the first main surface 3 in the active region 12 and electrically connected to the transistor structure Tr. A source wiring 90 is disposed on the first main surface 3 in the outer peripheral region 19 and electrically connected to the outer well region 70. A second inorganic film 110 exposes the source electrode 85 and covers the source wiring 90. An organic film 120 has a portion that directly covers the source electrode 85 and a portion that covers the source wiring 90 through the second inorganic film 110.

[0543] According to this structure, a semiconductor device 1 with a novel layout is provided. For example, according to the semiconductor device 1, peeling of the second inorganic film 110 caused by stress on the source electrode 85 can be suppressed, and oxidation of the source wiring 90 is suppressed by the second inorganic film 110. In particular, according to this semiconductor device 1, moisture (water) and oxidation reactions of the source wiring 90 caused by the electric field near the source wiring 90 can be suppressed. In addition, both the source electrode 85 and the source wiring 90 are protected by an organic film 120.

[0544] Here, the relationship between the source electrode 85 and the source wiring 90 is explained, but the source electrode 85 can also be replaced by the gate electrode 95, and the source wiring 90 can also be replaced by the gate wiring 100.

[0545] In other words, viewed from another perspective, the semiconductor device 1 (electronic component) includes: an insulating first inorganic film 75 (covered object), a gate electrode 95 (electrode), a gate wiring 100 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The gate electrode 95 is disposed on the first inorganic film 75, and has a second electrode sidewall 97 on the first inorganic film 75. The gate wiring 100 is disposed on the first inorganic film 75 around the gate electrode 95.

[0546] The second inorganic film 110 has a second inner cover portion 112 that covers the gate electrode 95 in a manner that exposes the second electrode sidewall 97, and an outer cover portion 113 that covers the gate wiring 100 at a distance spaced from the second inner cover portion 112. An organic film 120 spans the second inner cover portion 112 and the outer cover portion 113, and covers the gate electrode 95 between the second inner cover portion 112 and the outer cover portion 113.

[0547] According to this structure, a semiconductor device 1 with a novel layout is provided. For example, according to the semiconductor device 1, peeling of the second inorganic film 110 caused by stress on the gate electrode 95 can be suppressed, and oxidation of the gate wiring 100 is suppressed by the second inorganic film 110. In addition, both the gate electrode 95 and the gate wiring 100 are protected by an organic film 120.

[0548] From another perspective, the semiconductor device 1 (electronic component) includes: an insulating first inorganic film 75 (covered object), a source electrode 85 (electrode), a gate wiring 100 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The source electrode 85 is disposed on the first inorganic film 75, and has a first electrode sidewall 87 on the first inorganic film 75. The gate wiring 100 is disposed on the first inorganic film 75 around the source electrode 85.

[0549] The second inorganic film 110 has a first inner cover portion 111 that covers the source electrode 85 in a manner that exposes the first electrode sidewall 87, and an outer cover portion 113 that covers the gate wiring 100 at a distance from the first inner cover portion 111. An organic film 120 spans the first inner cover portion 111 and the outer cover portion 113, and covers the source electrode 85 between the first inner cover portion 111 and the outer cover portion 113.

[0550] According to this structure, a semiconductor device 1 with a novel layout is provided. For example, according to the semiconductor device 1, peeling of the second inorganic film 110 caused by stress on the source electrode 85 can be suppressed, and oxidation of the gate wiring 100 is suppressed by the second inorganic film 110. In addition, both the source electrode 85 and the gate wiring 100 are protected by an organic film 120.

[0551] From another perspective, the semiconductor device 1 (electronic component) includes: an insulating first inorganic film 75 (covered object), a gate electrode 95 (electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120. The gate electrode 95 is disposed on the first inorganic film 75, and has a second electrode sidewall 97 on the first inorganic film 75. The source wiring 90 is disposed on the first inorganic film 75 around the gate electrode 95.

[0552] The second inorganic film 110 has a second inner cover portion 112 that covers the gate electrode 95 in a manner that exposes the second electrode sidewall 97, and an outer cover portion 113 that covers the source wiring 90 at a distance from the second inner cover portion 112. An organic film 120 spans the second inner cover portion 112 and the outer cover portion 113, and covers the gate electrode 95 between the second inner cover portion 112 and the outer cover portion 113.

[0553] According to this structure, a semiconductor device 1 with a novel layout is provided. For example, according to the semiconductor device 1, peeling of the second inorganic film 110 caused by stress on the gate electrode 95 can be suppressed, and oxidation of the source wiring 90 is suppressed by the second inorganic film 110. In addition, both the gate electrode 95 and the source wiring 90 are protected by an organic film 120.

[0554] The following is for reference Figures 22A-22R, indicating the second to nineteenth layout examples of the second inorganic membrane 110. Figures 22A-22G This is a cross-sectional view showing the second to sixth layout examples of the second inorganic membrane 110. Figures 22F to 22H This is an enlarged top view showing the seventh to ninth layout examples of the second inorganic membrane 110. Figures 22I-22R This is a cross-sectional view showing the tenth to nineteenth layout examples of the second inorganic membrane 110.

[0555] The semiconductor device 1 may include features of any one of the second inorganic films 110 in the first to nineteenth layout embodiments. Of course, the features of the second inorganic films 110 in the first to nineteenth layout embodiments can be appropriately combined among them. Therefore, the semiconductor device 1 can simultaneously include at least two features of the second inorganic films 110 in the first to nineteenth layout embodiments in the same or different regions.

[0556] Reference Figure 22A (Second layout example) The second inorganic film 110 may have an outer cover portion 113 that exposes the second inner sidewall 102 of the gate wiring 100 and covers the second wiring surface 101 and the second outer sidewall 103 of the gate wiring 100. The outer cover portion 113 may have an inner edge portion located above the second wiring surface 101 of the gate wiring 100.

[0557] In this embodiment, the organic film 120 has a portion that directly covers the first inorganic film 75 in the region (first removal portion 114a) between the source electrode 85 and the gate wiring 100. The organic film 120 directly covers the second inner sidewall 102 of the gate wiring 100 and covers the second outer sidewall 103 of the gate wiring 100 through the outer covering portion 113. In this embodiment, the organic film 120 has a portion that directly covers the second wiring surface 101 of the gate wiring 100 and a portion that covers the second wiring surface 101 of the gate wiring 100 through the outer covering portion 113.

[0558] Reference Figure 22B (Third layout example) The second inorganic film 110 may have an outer cover portion 113 that exposes the entire area of ​​the gate wiring 100. The outer cover portion 113 may have an inner edge portion located in the region between the source wiring 90 and the gate wiring 100. The inner edge portion of the outer cover portion 113 may cover the first inorganic film 75 at intervals from the second outer sidewall 103 of the gate wiring 100 toward the source wiring 90 side.

[0559] In this embodiment, the organic film 120 has a portion in the first removal portion 114a that directly covers the second wiring surface 101, the second inner sidewall 102, and the second outer sidewall 103 of the gate wiring 100. In this embodiment, the organic film 120 has a portion in the region between the source wiring 90 and the gate wiring 100 that directly covers the first inorganic film 75, and a portion that covers the first inorganic film 75 through the second inorganic film 110.

[0560] Reference Figure 22C (Fourth layout example) The second inorganic film 110 may have an outer covering portion 113 that exposes the first inner sidewall 92 of the source wiring 90 and covers the first wiring surface 91 and the first outer sidewall 93 of the source wiring 90. The outer covering portion 113 may have an inner edge portion located above the first wiring surface 91 of the source wiring 90. The inner edge portion of the outer covering portion 113 may be opposed to the first surface 8 across the source wiring 90.

[0561] In this configuration, the organic film 120 directly covers the second wiring surface 101, the second inner sidewall 102, and the second outer sidewall 103 of the gate wiring 100 in the first removal section 114a. The organic film 120 also directly covers the first inorganic film 75 in the region between the source wiring 90 and the gate wiring 100.

[0562] The organic film 120 directly covers the first inner sidewall 92 of the source wiring 90 and covers the first outer sidewall 93 of the source wiring 90 through the outer cover portion 113. In this embodiment, the organic film 120 has a portion that directly covers the first wiring surface 91 of the source wiring 90 and a portion that covers the first wiring surface 91 of the gate wiring 100 through the outer cover portion 113.

[0563] Reference Figure 22D (Fifth layout example) The second inorganic film 110 may have an outer covering portion 113 that exposes the first inner sidewall 92 of the source wiring 90 and covers the first wiring surface 91 of the source wiring 90 and the first outer sidewall 93 of the source wiring 90.

[0564] The outer cover portion 113 may have an inner edge portion located above the first wiring surface 91 of the source wiring 90. The inner edge portion of the outer cover portion 113 may be opposed to the second surface portion 9 across the source wiring 90. The inner edge portion of the outer cover portion 113 may be located on the side closer to the first outer side wall 93 than the outer opening 81, or it may be located on the side closer to the first inner side wall 92 than the outer opening 81.

[0565] In this configuration, the organic film 120 directly covers the second wiring surface 101, the second inner sidewall 102, and the second outer sidewall 103 of the gate wiring 100 in the first removal section 114a. The organic film 120 also directly covers the first inorganic film 75 in the region between the source wiring 90 and the gate wiring 100.

[0566] The organic film 120 directly covers the first inner sidewall 92 of the source wiring 90 and covers the first outer sidewall 93 of the source wiring 90 through the outer cover portion 113. In this embodiment, the organic film 120 has a portion that directly covers the first wiring surface 91 of the source wiring 90 and a portion that covers the first wiring surface 91 of the gate wiring 100 through the outer cover portion 113.

[0567] Reference Figure 22E (Sixth layout example) The second inorganic membrane 110 may have an outer cover portion 113 that covers the first electrode sidewall 87 of the source electrode 85 at a distance from the first inner cover portion 111.

[0568] In this case, the outer cover 113 may have an inner edge portion located above the peripheral portion of the first electrode surface 86 of the source electrode 85. The outer cover 113, together with the first inner cover 111, may expose the peripheral portion of the first electrode surface 86 of the source electrode 85. The first removal portion 114a may also expose only the peripheral portion of the first electrode surface 86 of the source electrode 85.

[0569] In this configuration, the organic film 120 covers the first electrode sidewall 87 of the source electrode 85 via the outer cover portion 113. The organic film 120 has a portion that covers the peripheral portion of the first electrode surface 86 of the source electrode 85 via the outer cover portion 113. The organic film 120 also has a portion that directly covers the portion of the peripheral portion of the first electrode surface 86 exposed from the first inner cover portion 111 and the outer cover portion 113. Alternatively, the organic film 120 may directly cover only the peripheral portion of the first electrode surface 86 in the first removal portion 114a.

[0570] Reference Figure 22F (Seventh layout example) The second inorganic film 110 may have one or more first openings 131 formed in the first inner cover portion 111 in such a way that the first electrode surface 86 of the source electrode 85 is exposed. The multiple first openings 131 may be formed at intervals along the extension direction of the first inner cover portion 111. The multiple first openings 131 may also be divided into strip-shaped, quadrilateral, rectangular, polygonal, circular, etc. when viewed from above.

[0571] Similarly, the second inorganic film 110 may have one or more second openings 132 formed in the second inner cover portion 112 in such a way that the second electrode surface 96 of the gate electrode 95 is exposed. A plurality of second openings 132 may be formed at intervals along the extension direction of the second inner cover portion 112. The plurality of second openings 132 may also be divided into strip-shaped, quadrilateral, rectangular, polygonal, circular, etc., shapes when viewed from above.

[0572] In this configuration, the organic film 120 extends from the first inner cover 111 into a plurality of first openings 131, and is connected to the first electrode surface 86 of the source electrode 85 within the plurality of first openings 131. The adhesion of the organic film 120 to the first inner cover 111 (second inorganic film 110) is enhanced by the plurality of first openings 131.

[0573] Similarly, the organic film 120 extends from the second inner cover 112 into a plurality of second openings 132, and is connected to the second electrode surface 96 of the gate electrode 95 within the plurality of second openings 132. The adhesion of the organic film 120 to the second inner cover 112 (second inorganic film 110) is enhanced by the plurality of second openings 132.

[0574] Reference Figure 22G (Eighth layout example) The second inorganic film 110 may have a plurality of first inner covering portions 111 disposed at intervals from the first electrode sidewall 87 of the source electrode 85 toward the interior of the source electrode 85.

[0575] A first inner cover portion 111 disposed inside the source electrode 85 divides the first pad opening 116. The plurality of first inner cover portions 111 can be formed as either an ended strip or an endless strip extending along the first electrode sidewall 87 of the source electrode 85. The plurality of first inner cover portions 111 can also be formed as annular shapes surrounding the interior of the source electrode 85.

[0576] Similarly, the second inorganic film 110 may have a plurality of second inner covering portions 112 disposed at intervals from the second electrode sidewall 97 of the gate electrode 95 toward the interior of the gate electrode 95. The second inner covering portions 112 disposed inside the source electrode 85 divide the second pad openings 117. The plurality of second inner covering portions 112 may be formed as terminated strips or unterminated strips extending along the second electrode sidewall 97 of the gate electrode 95. The plurality of second inner covering portions 112 may also be formed as annular shapes surrounding the interior of the gate electrode 95.

[0577] In this configuration, the organic film 120 extends from above the plurality of first inner covers 111 into the region (opening) between the plurality of first inner covers 111, and is connected to the first electrode surface 86 of the source electrode 85 in the region between the plurality of first inner covers 111. The adhesion of the organic film 120 to the first inner covers 111 (second inorganic film 110) is enhanced by the plurality of first inner covers 111.

[0578] Similarly, in this embodiment, the organic film 120 extends from above the plurality of second inner covers 112 into the region (opening) between the plurality of second inner covers 112, and is connected to the second electrode surface 96 of the gate electrode 95 in the region between the plurality of second inner covers 112. The adhesion of the organic film 120 to the second inner covers 112 (second inorganic film 110) is enhanced by the plurality of second inner covers 112.

[0579] Reference Figure 22H (Ninth layout example) The second inorganic film 110 may have a plurality of first inner covering portions 111 arranged at intervals along the first electrode sidewall 87 of the source electrode 85. The plurality of first inner covering portions 111 may also be formed in the form of a strip, a quadrilateral shape, a rectangular shape, a polygonal shape, a circle, etc. when viewed from above.

[0580] Similarly, the second inorganic film 110 may have a plurality of second inner covering portions 112 arranged at intervals along the second electrode sidewall 97 of the gate electrode 95. The plurality of second inner covering portions 112 may also be formed in the form of a strip, a quadrilateral shape, a rectangular shape, a polygonal shape, a circle, etc. when viewed from above.

[0581] In this configuration, the organic film 120 extends from above the plurality of first inner covers 111 into the region (opening) between the plurality of first inner covers 111, and is connected to the first electrode surface 86 of the source electrode 85 in the region between the plurality of first inner covers 111. The adhesion of the organic film 120 to the first inner covers 111 (second inorganic film 110) is enhanced by the plurality of first inner covers 111.

[0582] Similarly, in this embodiment, the organic film 120 extends from above the plurality of second inner covers 112 into the region (opening) between the plurality of second inner covers 112, and is connected to the second electrode surface 96 of the gate electrode 95 in the region between the plurality of second inner covers 112. The adhesion of the organic film 120 to the second inner covers 112 (second inorganic film 110) is enhanced by the plurality of second inner covers 112.

[0583] Reference Figure 22I (Tenth layout example) The second inorganic membrane 110 may have an outer cover portion 113 exposed from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D. The outer cover portion 113 may be formed to be coplanar with at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.

[0584] Reference Figure 22J (Eleventh layout example) The second inorganic membrane 110 may have an outer covering portion 113 located inside the outer edge of the organic membrane 120. That is, the organic membrane 120 may protrude outward beyond the outer edge of the outer covering portion 113.

[0585] Reference Figure 22K (In the twelfth layout example), the second inorganic membrane 110 may have an outer covering portion 113 located inside the organic membrane 120. That is, the organic membrane 120 may cover the outer edge of the outer covering portion 113.

[0586] Reference Figure 22L (Thirteenth layout example) The first inorganic film 75 may have a notch 133 formed at intervals from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D, exposing the peripheral portion (second semiconductor region 7) of the second surface surface 9. In this case, the second inorganic film 110 may have an outer cover portion 113 having an outer edge portion disposed at intervals from the notch 133 on the first inorganic film 75.

[0587] Reference Figure 22M (Fourteenth layout example) The first inorganic membrane 75 may have a notch 133, similar to the case in the thirteenth layout example. In this case, the second inorganic membrane 110 may have an outer covering portion 113 that extends from above the first inorganic membrane 75 into the notch 133 and has a portion that directly covers the periphery of the second surface 9 within the notch 133. The outer covering portion 113 may also be formed inwardly at intervals from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.

[0588] Reference Figure 22N (Fifteenth layout example) The second inorganic membrane 110 may have an outer cover portion 113 located within the notch portion 133, similar to the case in the fourteenth layout example. The outer cover portion 113 may be exposed from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D. The outer cover portion 113 may be formed to be coplanar with at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.

[0589] Reference Figure 22O (Sixteenth layout example) The second inorganic membrane 110 may have a first inner covering portion 111 located further inside than the inner edge of the organic membrane 120. That is, the organic membrane 120 may extend into the interior of the source electrode 85 (first electrode surface 86) beyond the inner edge of the first inner covering portion 111.

[0590] The wall of the first upper pad opening 121 can be located on the inner side of the first electrode surface 86, closer to the wall of the first pad opening 116. Alternatively, the wall of the first upper pad opening 121 can be formed at intervals from the first electrode surface 86 in the stacking direction.

[0591] Similarly, the second inorganic film 110 may have a second inner cover portion 112 located further inside than the inner edge of the organic film 120. That is, the organic film 120 may extend into the interior of the gate electrode 95 (second electrode surface 96) beyond the inner edge of the second inner cover portion 112.

[0592] The wall surface of the second upper pad opening 122 can be located on the inner side of the second electrode surface 96, which is closer to the wall surface of the second pad opening 117. Alternatively, the wall surface of the second upper pad opening 122 can be formed at a distance from the second electrode surface 96 in the stacking direction.

[0593] Reference Figure 22P (Seventeenth layout example) The second inorganic membrane 110 may have a first inner covering portion 111 located inside the organic membrane 120. That is, the organic membrane 120 may cover the inner edge of the first inner covering portion 111. In this case, the organic membrane 120 may cover the entire area of ​​the first inner covering portion 111.

[0594] The organic film 120 can directly cover the source electrode 85 (first electrode surface 86) in a region closer to the inner edge of the first inner cover portion 111. The wall of the first upper pad opening 121 can be located in a position closer to the inner side of the first electrode surface 86 than the wall of the first pad opening 116. The wall of the first upper pad opening 121 can directly cover the first electrode surface 86 in a region closer to the inner edge of the first inner cover portion 111.

[0595] Similarly, the second inorganic membrane 110 may have a second inner covering portion 112 located inside the organic membrane 120. That is, the organic membrane 120 may cover the inner edge of the second inner covering portion 112. In this case, the organic membrane 120 may cover the entire area of ​​the second inner covering portion 112.

[0596] The organic film 120 can directly cover the gate electrode 95 (second electrode surface 96) in a region closer to the inner edge of the second inner cover portion 112. The wall of the second upper pad opening 122 can be located in a position closer to the inner side of the second electrode surface 96 than the wall of the second pad opening 117. The wall of the second upper pad opening 122 can directly cover the second electrode surface 96 in a region closer to the inner edge of the second inner cover portion 112.

[0597] Reference Figure 22Q (Eighteenth layout example) The second inorganic film 110 does not necessarily need to have a first inner cover portion 111, and the entire area of ​​the source electrode 85 can be exposed. In this case, the second inorganic film 110 only needs to have an outer cover portion 113. The second inorganic film 110 may or may not have a second inner cover portion 112.

[0598] In this configuration, the organic film 120 directly covers the periphery of the first electrode surface 86 and the first electrode sidewall 87 without passing through the first inner cover portion 111. That is, the wall surface of the first upper pad opening 121 can directly cover the periphery of the first electrode surface 86.

[0599] Reference Figure 22R (In the nineteenth layout example) the second inorganic film 110 does not necessarily need to have a second inner cover portion 112, and the entire area of ​​the gate electrode 95 can be exposed. In this case, the second inorganic film 110 only needs to have an outer cover portion 113. The second inorganic film 110 may or may not have a first inner cover portion 111.

[0600] In this configuration, the organic film 120 directly covers the periphery of the second electrode surface 96 and the second electrode sidewall 97 of the source electrode 85 without passing through the second inner cover portion 112. That is, the wall surface of the second upper pad opening 122 can directly cover the periphery of the second electrode surface 96.

[0601] The above method (including variations) can also be implemented in other ways. For example, in the above method, an example is shown in which a table 11 (first face 8, second face 9, and first to fourth connecting faces 10A to 10D) is divided into the first main surface 3. However, the first main surface 3 does not necessarily need to have a table 11, and can also be formed as flat.

[0602] In this case, the active region 12 and the peripheral region 19 are divided using the outer well region 70. Alternatively, in this case, the first side end region 13, the second side end region 14, the first terminal region 15, the second terminal region 16, the third terminal region 17, and the fourth terminal region 18 can also be removed.

[0603] The above description illustrates an example where the first inorganic membrane 75 has an anchoring opening 83. However, a first inorganic membrane 75 without an anchoring opening 83 may also be used.

[0604] The above description illustrates an example where the source wiring 90 is connected to the source electrode 85. However, the source wiring 90 can also be electrically disconnected from the source electrode 85. In this case, the source wiring 90 can be formed as a floating wiring or a field wiring (so-called field preform) in an electrically floating state.

[0605] In the above method, the conductivity type of the "n-type" semiconductor region can be reversed to "p-type", and the conductivity type of the "p-type" semiconductor region can be reversed to "n-type". The specific structure is obtained by replacing "n-type" with "p-type" and "p-type" with "n-type" in the above description and figures.

[0606] In the above method, a chip 2 containing SiC single crystal is used. However, chip 2 can also contain single-crystal silicon. Similarly, the first semiconductor region 6 can also contain single-crystal silicon. Likewise, the second semiconductor region 7 can also contain single-crystal silicon.

[0607] In the above-described manner, the p-type collector region can be formed on the surface layer of the second main surface 4 of chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific structure is obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure, and replacing the "drain" of the MISFET structure with the "collector" of the IGBT structure, as described above. In this case, chip 2 can have a single-layer structure made of an n-type semiconductor substrate.

[0608] In the above-described manner, the first semiconductor region 6 (second semiconductor region 7) may be formed as part or all of the cathode region of the semiconductor rectifier (diode), and the body region 20 may be formed as part or all of the anode region of the semiconductor rectifier (diode). In this case, the source electrode 85 is formed as the anode electrode, and the drain electrode 125 is formed as the cathode electrode. Of course, instead of the body region 20 (anode region) and the source electrode 85, a Schottky electrode (anode electrode) that forms a Schottky junction with the second semiconductor region 7 may be used.

[0609] The following are examples of features extracted from this specification and accompanying drawings. Hereinafter, the letters and numbers in parentheses indicate the corresponding constituent elements of the above-described method, but are not intended to limit the scope of each item (clause) to the above-described method. The term "electronic component" in the following items can be replaced as needed with "semiconductor device," "SiC semiconductor device," "wide bandgap semiconductor device," "semiconductor switching device," "MISFET device," "IGBT device," "semiconductor rectifier device," etc.

[0610] [A1] An electronic component (1) includes: a cover (75); electrodes (85, 95) disposed on the cover (75) and having electrode sidewalls (87, 97) on the cover (75); wiring (90, 100) disposed on the cover (75) around the electrodes (85, 95); and an insulating inorganic film (110) having an inner cover (111, 112) and an outer cover (113), wherein the inner cover (111) The outer cover (113) covers the electrodes (85, 95) in a manner that exposes the sidewalls (87, 97), and the wiring (90, 100) is covered by the inner cover (111, 112) spaced apart from the inner cover (111, 112); and an insulating organic film (120) spans the inner cover (111, 112) and the outer cover (113), and covers the electrodes (85, 95) between the inner cover (111, 112) and the outer cover (113).

[0611] [A2] According to the electronic component (1) of A1, the wiring (90, 100) has: wiring sidewalls (93, 103) on the opposite side of the electrodes (85, 95) in cross-section, the outer cover (113) covering the wiring sidewalls (93, 103) of the wiring (90, 100) in cross-section, and the organic film (120) covering the wiring sidewalls (93, 103) through the outer cover (113) in cross-section.

[0612] [A3] According to the electronic component (1) of A2, the outer cover (113) covers the entire area of ​​the wiring (90, 100) in cross-section, and the organic film (120) covers the entire area of ​​the wiring (90, 100) through the outer cover (113) in cross-section.

[0613] [A4] The electronic component (1) according to any one of A1 to A3, wherein the outer cover (113) exposes the electrode sidewalls (87, 97) when viewed in section, and the organic film (120) has a portion that directly covers the electrode sidewalls (87, 97) when viewed in section.

[0614] [A5] According to the electronic component (1) described in A4, the inner cover (111, 112) covers the electrode (85, 95) at a distance from the electrode sidewall (87, 97), and the outer cover (113) covers the covered object (75) at a distance from the electrode sidewall (87, 97).

[0615] [A6] According to the electronic component (1) of A5, wherein the inner cover (111, 112) exposes the periphery of the electrodes (85, 95), and the organic film (120) has a portion that directly covers the periphery of the electrodes (85, 95).

[0616] [A7] The electronic component (1) according to A5 or A6, wherein the organic film (120) has a portion that directly covers the exposed portion between the electrode (85, 95) in the covered object (75) and the outer cover (113).

[0617] [A8] The electronic component (1) according to any one of A1 to A7, wherein the inner cover (111, 112) exposes the interior of the electrodes (85, 95).

[0618] [A9] The electronic component (1) according to any one of A1 to A8, wherein the organic film (120) exposes the edge of the inner cover (111, 112) on the inner side of the electrodes (85, 95).

[0619] [A10] The electronic component (1) according to any one of A1 to A9, wherein the wiring (90, 100) is electrically connected to the electrodes (85, 95).

[0620] [A11] The electronic component (1) according to any one of A1 to A10, wherein the wiring (90, 100) is led out from the electrodes (85, 95).

[0621] [A12] The electronic component (1) according to any one of A1 to A11, wherein the wiring (90, 100) is the outermost peripheral wiring (90).

[0622] [A13] The electronic component (1) according to any one of A1 to A12, wherein the electrode (85, 95) is a source electrode (85) and the wiring (90, 100) is a source wiring (90).

[0623] [A14] The electronic component (1) according to any one of A1 to A13, wherein the electronic component (1) further comprises a chip (2), and the covering object (75) is formed on the chip (2).

[0624] [A15] According to the electronic component (1) of A14, the electronic component (1) further includes: an active region (12) disposed inside the chip (2); and a peripheral region (19) disposed at the periphery of the chip (2), the covering object (75) covering both the active region (12) and the peripheral region (19), the electrodes (85, 95) disposed on the active region (12), and the wiring (90) disposed on the peripheral region (19).

[0625] [A16] The electronic component (1) according to A14 or A15, wherein the chip (2) comprises SiC.

[0626] [A17] The electronic component (1) according to any one of A1 to A16, wherein the electronic component (1) further comprises: a second wiring (100) disposed on the cover object (75) in the region between the electrode (85) and the wiring (90), and the organic film (120) covers the second wiring (100).

[0627] [A18] According to the electronic component (1) of A17, the outer cover (113) covers the second wiring (100), and the organic film (120) covers the second wiring (100) through the outer cover (113).

[0628] [B1] An electronic component (1) includes: electrodes (85, 95) disposed in a first region (12) having a first electric field; wiring (90) disposed around the electrodes (85, 95) in a second region (19) having a second electric field higher than the first electric field; an insulating inorganic film (110) that exposes the electrodes (85, 95) and covers the wiring (90); and an insulating organic film (120) having a portion that directly covers the electrodes (85, 95) and a portion that covers the wiring (90) through the inorganic film (110).

[0629] [B2] According to the electronic component (1) described in B1, wherein the electrodes (85, 95) are terminal electrodes (85, 95).

[0630] [B3] The electronic component (1) according to B1 or B2, wherein the wiring (90) has a width smaller than the width of the electrodes (85, 95).

[0631] [B4] The electronic component (1) according to any one of B1 to B3, wherein the inorganic film (110) exposes the electrode sidewalls (87, 97) of the electrodes (85, 95).

[0632] [B5] According to the electronic component (1) of B4, the inorganic film (110) has: an inner cover (111, 112) that covers the electrode (85, 95) spaced apart from the electrode sidewall (87, 97); and an outer cover (113) that covers the wiring (90) spaced apart from the inner cover (111, 112), the organic film (120) spanning the inner cover (111, 112) and the outer cover (113) and covering the electrode sidewall (87, 97) of the electrode (85, 95) between the inner cover (111, 112) and the outer cover (113).

[0633] [B6] The electronic component (1) according to any one of B1 to B5, wherein the wiring (90) and the electrode (85) are at the same potential.

[0634] [B7] The electronic component (1) according to any one of B1 to B6, wherein the wiring (90) is connected to the electrode (85).

[0635] [B8] The electronic component (1) according to any one of B1 to B7, wherein the electronic component (1) further comprises a chip (2), a first region (12) formed on the chip (2), a second region (19) formed on the chip (2) around the first region (12), electrodes (85, 95) disposed on the first region (12), and wiring (90) disposed on the second region (19).

[0636] [B9] According to the electronic component (1) of B8, the first region (12) is an active region (12), the second region (19) is an outer peripheral region (19) surrounding the active region (12), the electrodes (85, 95) are disposed on the active region (12), and the wiring (90) is disposed on the outer peripheral region (19).

[0637] [B10] The electronic component (1) according to B8 or B9, wherein the chip (2) comprises SiC.

[0638] [C1] An electronic component (1) includes: a chip (2) having a main surface (3); an active region (12) disposed inside the main surface (3); a peripheral region (19) disposed at the periphery of the main surface (3); a device structure (Tr) formed on the main surface (3) in the active region (12); an impurity region (70) formed on the surface of the main surface (3) in the peripheral region (19); and an electrode (85) disposed on the active region (12). Above the main surface (3) and electrically connected to the device structure (Tr); wiring (90) disposed on the main surface (3) in the peripheral region (19) and electrically connected to the impurity region (70); an insulating inorganic film (110) that exposes the electrode (85) and covers the wiring (90); and an insulating organic film (120) having a portion that directly covers the electrode (85) and a portion that covers the wiring (90) through the inorganic film (110).

[0639] [C2] According to the electronic component (1) of C2, the conductivity type of the impurity region (70) is p-type.

[0640] [C3] The electronic component (1) according to C1 or C2, wherein the device configuration (Tr) includes a MISFET configuration.

[0641] [C4] The electronic component (1) according to C1 or C2, wherein the device configuration (Tr) comprises an IGBT configuration.

[0642] [D1] An electronic component (1) includes: a terminal electrode; wiring disposed around the terminal electrode; an insulating inorganic film that covers the wiring spaced apart from the terminal electrode; and an insulating organic film having a portion that directly covers the terminal electrode and a portion that covers the wiring through the inorganic film.

[0643] [E1] An electronic component (1) includes: a cover (75); a gate electrode (95) disposed on the cover (75) and having an electrode sidewall (97) on the cover (75); a gate wiring (100) disposed on the cover (75) around the gate electrode (95); an insulating inorganic film (110) having an inner cover (112) and an outer cover (113), wherein the inner cover (112) covers the gate electrode (95) in such a way that the electrode sidewall (97) is exposed, and the outer cover (113) covers the gate wiring (100) spaced apart from the inner cover (112); and an insulating organic film (120) spanning the inner cover (112) and the outer cover (113) and covering the gate electrode (95) between the inner cover (112) and the outer cover (113).

[0644] [F1] An electronic component (1) includes: a cover (75); a source electrode (85) disposed on the cover (75) and having an electrode sidewall (87) on the cover (75); a gate wiring (100) disposed on the cover (75) around the source electrode (85); an insulating inorganic film (110) having an inner cover (112) and an outer cover (113), wherein the inner cover (112) covers the source electrode (85) in such a way that the electrode sidewall (87) is exposed, and the outer cover (113) covers the gate wiring (100) spaced apart from the inner cover (112); and an insulating organic film (120) spanning the inner cover (112) and the outer cover (113) and covering the source electrode (85) between the inner cover (112) and the outer cover (113).

[0645] [G1] An electronic component (1) includes: a cover (75); a gate electrode (95) disposed on the cover (75) and having an electrode sidewall (97) on the cover (75); a source wiring (90) disposed on the cover (75) around the gate electrode (95); an insulating inorganic film (110) having an inner cover (111) and an outer cover (113), wherein the inner cover (111) covers the gate electrode (95) such that the electrode sidewall (97) is exposed, and the outer cover (113) covers the source wiring (90) spaced apart from the inner cover (111); and an insulating organic film (120) spanning the inner cover (111) and the outer cover (113) and covering the gate electrode (95) between the inner cover (111) and the outer cover (113).

[0646] The above provides a detailed explanation of the specific methods, but these are merely specific examples illustrating the technical content. The various technical ideas extracted from this specification are not limited to the order of description or the order of examples within the specification, and can be appropriately combined among them.

[0647] Symbol Explanation

[0648] 1. Semiconductor devices (electronic components)

[0649] 2 chips

[0650] 3 First Main Face

[0651] 12. Active region (region 1)

[0652] 19. Outer Periphery (Second District)

[0653] 70 Outer well region (impurity region)

[0654] 75 First Inorganic Membrane (Covered Object)

[0655] 85 Source electrode (electrode)

[0656] 87 First electrode sidewall

[0657] 90 Source wiring (wiring)

[0658] 93 First outer wall (wiring sidewall)

[0659] 95 Gate electrode (electrode)

[0660] 97 Second electrode sidewall

[0661] 100 Gate wiring (second wiring)

[0662] 110 Second Inorganic Membrane

[0663] 111 First Inner Cover Section

[0664] 112 Second Inner Cover Section

[0665] 113 Outer Covering

[0666] 120 Organic membrane

[0667] Tr Transistor construction (device construction).

Claims

1. An electronic component comprising: a cover object; an electrode disposed on the cover object and having an electrode side wall on the cover object; a wiring disposed around the electrode on the cover object; an inorganic film having an inner cover portion covering the electrode with the electrode side wall exposed and an outer cover portion covering the wiring at a distance from the inner cover portion; and an organic film covering the electrode between the inner cover portion and the outer cover portion.

2. The electronic component according to claim 1, wherein the wiring has a wiring side wall on the opposite side of the electrode in cross section, the outer cover portion covers the wiring side wall of the wiring in cross section, the organic film covers the wiring side wall through the outer cover portion in cross section.

3. The electronic component according to claim 2, wherein the outer cover portion covers the entire area of the wiring in cross section, the organic film covers the entire area of the wiring through the outer cover portion in cross section.

4. The electronic component according to any one of claims 1 to 3, wherein the outer cover portion exposes the electrode side wall in cross section, the organic film has a portion directly covering the electrode side wall in cross section.

5. The electronic component according to claim 4, wherein the inner cover portion covers the electrode at a distance from the electrode side wall, the outer cover portion covers the cover object at a distance from the electrode side wall.

6. The electronic component according to claim 5, wherein the inner cover portion exposes a peripheral portion of the electrode, the organic film has a portion directly covering the peripheral portion of the electrode.

7. The electronic component according to claim 5 or 6, wherein the organic film has a portion directly covering an area between the electrode and the outer cover portion in the cover object.

8. The electronic component according to any one of claims 1 to 7, wherein the inner cover portion exposes an inside of the electrode.

9. The electronic component according to any one of claims 1 to 8, wherein the organic film exposes a peripheral portion of the inner cover portion on an inside of the electrode.

10. The electronic component according to any one of claims 1 to 9, wherein the wiring is electrically connected to the electrode.

11. The electronic component according to any one of claims 1 to 10, wherein the wiring is drawn from the electrode.

12. The electronic component according to any one of claims 1 to 11, wherein the wiring is an outermost peripheral wiring.

13. The electronic component according to any one of claims 1 to 12, wherein the electrode is a source electrode, the wiring is a source wiring.

14. The electronic component according to any one of claims 1 to 13, wherein the electronic component further comprises a chip, the cover object is formed on the chip.

15. The electronic component according to claim 14, wherein the electronic component further comprises: ​ an active region provided inside the chip; and a peripheral region provided at a peripheral portion of the chip, the cover object covers both the active region and the peripheral region, the electrode is disposed on the active region, the wiring is disposed on the peripheral region.

16. The electronic component according to claim 14 or 15, wherein the chip contains SiC.

17. The electronic component according to any one of claims 1 to 16, wherein the electronic component further comprises a second wiring disposed on the cover object in a region between the electrode and the wiring, the organic film covers the second wiring.

18. The electronic component according to claim 17, wherein the outer cover portion covers the second wiring, the organic film covers the second wiring through the outer cover portion.

19. An electronic component comprising: a terminal electrode; a wiring disposed around the terminal electrode; an insulating inorganic film covering the wiring with a gap from the terminal electrode; and an insulating organic film having a portion directly covering the terminal electrode and a portion covering the wiring through the inorganic film.

20. An electronic component comprising: an electrode disposed in a first region having a first electric field; a wiring disposed in a second region around the electrode, the second region having a second electric field higher than the first electric field; an insulating inorganic film exposing the electrode and covering the wiring; and an insulating organic film having a portion directly covering the electrode and a portion covering the wiring through the inorganic film. ​

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