Semiconductor device with doped regions under gate layer and in barrier layer

Abstract

The present disclosure describes a semiconductor device having a doped region underlying a gate layer and in a barrier layer. In an example, a semiconductor device (100) includes a channel layer (106), a barrier layer (108), and a gate layer (120). The channel layer (106) is over a semiconductor substrate (102), and the barrier layer (108) is over the channel layer (106). The gate layer (120) is over the barrier layer (108), and the gate layer (120) is doped with a dopant. A first region (120) in the barrier layer (108) overlies a channel region (C) in the channel layer (106) and underlies the gate layer (120). The first region (120) has a first concentration of the dopant. A second region (A1) in the barrier layer (108) is laterally disposed with respect to the first region (120) and has a concentration of the dopant that is less than the first concentration.

Description

BACKGROUND

[0001] One type of semiconductor device is a high electron mobility transistor (HEMT). HEMTs typically employ different semiconductor materials to form a heterojunction, where a channel can be formed near the heterojunction and between a source region and a drain region. HEMTs can support high speed operation, which makes HEMTs attractive for high frequency applications, among others. SUMMARY

[0002] An example described herein is a semiconductor device. The semiconductor device includes a channel layer, a barrier layer, and a gate layer. The channel layer is over a semiconductor substrate, and the barrier layer is over the channel layer. The gate layer is over the barrier layer, and the gate layer is doped with a dopant. A first region in the barrier layer overlies a channel region in the channel layer and is under the gate layer. The first region has a first concentration of the dopant. A second region in the barrier layer is disposed laterally relative to the first region. The second region has a second concentration of the dopant, which is less than the first concentration.

[0003] Another example is a method. A doped gate layer is formed over a barrier layer. The doped gate layer is doped with a dopant while forming the doped gate layer. The barrier layer is over a channel layer, and the channel layer is over a semiconductor substrate. The doped gate layer is patterned. After patterning the doped gate layer, a thermal treatment is performed on the doped gate layer and the barrier layer. The thermal treatment causes the dopant to diffuse from the doped gate layer into the barrier layer.

[0004] Another example is a semiconductor device. The semiconductor device includes a GaN channel layer, an AlGaN barrier layer, a doped GaN gate layer, and a drain contact. The GaN channel layer is over a semiconductor substrate. The AlGaN barrier layer is over the GaN channel layer. The doped GaN gate layer is over the AlGaN barrier layer. The drain contact contacts the AlGaN barrier layer. The doped GaN gate layer includes a p-type dopant. A first portion of the AlGaN barrier layer under the doped GaN gate layer includes a first concentration of the p-type dopant. A second portion of the AlGaN barrier layer between the doped GaN gate layer and the drain contact includes a second concentration of the p-type dopant, which is less than the first concentration.

[0005] The foregoing summary of the preceding summary quite broadly illustrates the various features and advantages of examples of the present disclosure, so as to provide a better understanding of the following detailed description. Additional features and advantages of such examples will be described in the detailed description that follows. The examples described can be readily used as a basis for modifying or designing other examples that fall within the scope of the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0006] To understand the above features in detail, please refer to the following detailed description in conjunction with the accompanying drawings.

[0007] Figure 1 Cross-sectional views of semiconductor devices based on some examples are shown.

[0008] Figure 2 , 3 Numbers 4, 5, and 6 are based on some examples. Figure 1 Cross-sectional views of the semiconductor device at various stages of the first manufacturing method.

[0009] Figure 7 and 8 It is based on some examples Figure 1 Cross-sectional views of the semiconductor device at various stages of the second manufacturing method.

[0010] The drawings and accompanying detailed description are provided to understand the features of various examples and do not limit the scope of the appended claims. Examples shown in the drawings and described in the accompanying detailed description can be readily used as the basis for modifications or designs of other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to refer to common elements in the drawings. The drawings are drawn to clearly illustrate relevant elements or features and are not necessarily drawn to scale. Detailed Implementation

[0011] The following description of various features is based on the accompanying diagrams. Other examples may include any arrangement of the included or excluded aspects or features described. The examples shown may not possess all the aspects or advantages shown. The aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example, even if not so shown or explicitly described. Furthermore, the methods described herein may be described with a specific order of operations, but may be implemented with various other orders of operations (e.g., different serial or parallel executions involving various operations) depending on other methods in other examples.

[0012] The present disclosure generally relates, but is not exclusively related, to a semiconductor device having a doped region located beneath a gate layer and in a barrier layer. In some examples, the semiconductor device is or includes a high electron mobility transistor (HEMT), and more particularly is or includes an enhancement mode HEMT. The semiconductor device includes a channel layer over a semiconductor substrate, a barrier layer over the channel layer, and a gate layer over the channel layer. A first region is in the barrier layer, is located beneath the gate layer, and overlies a channel region in the channel layer. A second region is in the barrier layer and is laterally disposed relative to the first region. The first region has a dopant at a concentration greater than a concentration of the dopant in the second region. According to some examples, higher threshold voltage and improved drain current stability can be achieved by the semiconductor device implementing a region having such a dopant concentration, particularly in the barrier layer. Other benefits and advantages can also be achieved.

[0013] Various examples are subsequently described. Although specific examples can show various aspects of the features generally described above, the examples can incorporate any combination of the features generally described above (which are described in greater detail in the examples below).

[0014] Figure 1 A cross-sectional view of a semiconductor device 100 is shown in accordance with some examples. Figure 1 The semiconductor device 100 can be or include an HEMT. More particularly, the semiconductor device 100 can be or include an enhancement mode HEMT. Other examples can be or include other types of devices.

[0015] Figure 1 A semiconductor substrate 102 is shown along with one or more transition layers 104 over and on the semiconductor substrate 102. A channel layer 106 is over and on the uppermost transition layer 104. A barrier layer 108 is over and on the channel layer 106.

[0016] The semiconductor substrate 102 can be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or any other appropriate substrate. For example, the semiconductor substrate 102 can be or include a bulk silicon wafer. The transition layers 104 can include any number of layers of any material configured to accommodate a lattice mismatch between the semiconductor substrate 102 and the channel layer 106 (e.g., to reduce or minimize lattice defect generation and / or propagation in the channel layer 106). For example, the transition layers 104 can have a gradient concentration of one or more elements (e.g., aluminum) in a direction perpendicular to a top surface of the semiconductor substrate 102.

[0017] The channel layer 106 may be combined with the barrier layer 108 to be configured to conduct and confine charge carriers (e.g., electrons) in two dimensions. In some instances, the channel layer 106 is configured to contain a two-dimensional electron gas (2DEG). The 2DEG can be formed by band bending (or by conduction band shift, spontaneous polarization, piezoelectric polarization, etc.) caused by the barrier layer 108 above and on the channel layer 106. In some instances, the channel layer 106 contains a gallium nitride (GaN) layer, and in such instances, it may be referred to as a GaN channel layer. In some instances, the material of the channel layer 106 is or contains an unintentionally doped material, such as a material doped by diffusion of dopants from another layer or dopants (e.g., carbon) incorporated during the formation of the channel layer 106. In some instances, the barrier layer 108 may be or contain an aluminum gallium nitride (AlGaN) layer, and in such instances, it may be referred to as an AlGaN barrier layer. More generally, in some instances, the barrier layer 108 may be or contain indium aluminum gallium nitride (In... x Al y Ga 1-x-y N) (where 0≤x<1, 0≤y<1, and 0≤x+y≤1). Other materials may be implemented for the channel layer 106 and / or the barrier layer 108.

[0018] Gate layer 120 is located above and on the upper surface of barrier layer 108. Furthermore, gate layer 120 is doped with a dopant. In some instances, gate layer 120 is doped with a p-type dopant. In some instances, gate layer 120 may be or contain a gallium nitride (GaN) layer, or more generally, an indium aluminum gallium nitride (In... x Al y Ga 1-x-y N) (where 0 ≤ x < 1, 0 ≤ y < 1, and 0 ≤ x + y ≤ 1), and the dopant of the gate layer 120 is a p-type dopant, which may be or contain magnesium (Mg), carbon (C), or combinations thereof. In an example where the gate layer 120 is gallium nitride (GaN) doped with a p-type dopant, the gate layer 120 may be referred to as a p-type doped GaN (pGaN) layer. Furthermore, in an example where the gate layer 120 is gallium nitride (GaN) doped with magnesium, the gate layer 120 may be referred to as a magnesium-doped gallium nitride (GaN:Mg) layer. In some examples, the concentration of the dopant in the gate layer 120 (e.g., which may be chemically present through doping, and may contain electrically activated dopant) is equal to or greater than 1 × 10⁻⁶. 17 cm -3 For example, equal to or greater than 1×10 19 cm -3 And more specifically equal to or greater than 1 × 10 20 cm -3 In other instances, other materials, dopants, and / or concentrations may be implemented.

[0019] The doped region 122 is located in the barrier layer 108, below the gate layer 120. The doped region 122 can extend within the barrier layer 108 from the interface between the gate layer 120 and the barrier layer 108 to a depth within the barrier layer 108, such as... Figure 1 As depicted in the diagram. In some instances, the doped region 122 extends from the interface between the gate layer 120 and the barrier layer 108 to the interface between the barrier layer 108 and the channel layer 106. The doped region 122 may further extend laterally in the barrier layer 108 away from the nearest sidewall surface of the gate layer 120. The doped region 122 is doped with a dopant. In some instances, the dopant doped in the doped region 122 is the same as the dopant doped in the gate layer 120. For example, the dopant doped in the gate layer 120 and the doped region 122 may be a p-type dopant, and more specifically, may be magnesium (Mg), carbon (C), or a combination thereof. In other instances, the doped region 122 and the gate layer 120 may be doped with different dopants. In some instances, the concentration of the dopant in the doped region 122 (e.g., chemically present through doping) is equal to or greater than 1 × 10⁻⁶. 16 cm -3 For example, equal to or greater than 1×10 18 cm -3 And more specifically equal to or greater than 1 × 10 19 cm -3 .

[0020] Gate layer 120 may have a gradient concentration of dopant (e.g., a gradient dopant concentration distribution), for example, increasing from near the interface between gate layer 120 and barrier layer 108 to away from barrier layer 108. In some instances, the entire thickness of gate layer 120 may have a gradient concentration of dopant. In some instances, a first portion of gate layer 120 (e.g., away from barrier layer 108) may have a substantially uniform concentration of dopant, and a second portion of gate layer 120 (e.g., near barrier layer 108) may have a gradient concentration of dopant. Doped region 122 may also have a gradient concentration of dopant (e.g., the same dopant as gate layer 120 or different dopant than gate layer 120), for example, decreasing in concentration from the interface between gate layer 120 and barrier layer 108 to a depth in barrier layer 108 (e.g., in some cases, to the interface between barrier layer 108 and channel layer 106). Similarly, the concentration gradient of the doped region 122 may have a concentration that decreases with the lateral distance from the interface between the gate layer 120 and the barrier layer 108 to the barrier layer 108. The concentration distribution of the dopant in the gate layer 120 and the doped region 122 may be generated by the formation of the gate layer 120, and / or by a diffusion mechanism that allows the dopant to diffuse from one or more layers forming the gate layer 120 into the barrier layer 108 to form the doped region 122. Additional details of this formation and diffusion will be described later. The dopant concentration distribution may vary depending on the different formation and / or diffusion techniques.

[0021] Semiconductor device 100 includes a drain region D, a first access region A1, a channel region C, a second access region A2, a source region S, and a gate structure G. The gate structure includes a gate layer 120. The channel region C is located in a channel layer 106, below the gate structure G. The channel region C is laterally located between the drain region D and the source region S, which are also located in the channel layer 106. The first access region A1 is located in a barrier layer 108 and is laterally located between the channel region C and the drain region D, and the second access region A2 is located in the barrier layer 108 and is laterally located between the channel region C and the source region S. Access regions A1 and A2 may be located in the barrier layer 108 and the channel layer 106. A doped region 122 is laterally located in the barrier layer 108 between the first access region A1 and the second access region A2, and vertically located between the channel region C and the gate layer 120.

[0022] The concentration of dopant in doped region 122 (e.g., chemically present through doping) is greater than the concentration of dopant in the first access region A1 and / or the second access region A2 in barrier layer 108 (e.g., chemically present through doping). Furthermore, in some instances, the concentration of dopant in doped region 122 is one order of magnitude or more (e.g., two or three orders of magnitude or more) greater than the concentration of dopant in the first access region A1 and / or the second access region A2 in barrier layer 108. In some instances, the concentration of dopant (e.g., chemically present through doping) in the first access region A1 and / or the second access region A2 in barrier layer 108 (wherein the dopant is the dopant doped in doped region 122) may be equal to or less than 1 × 10⁻⁶. 19 cm -3 For example, equal to or less than 1×10 17 cm -3 And more specifically, equal to or less than 1 × 10 16 cm -3 .

[0023] Passivation layer 124 is above and on the barrier layer 108 and the gate layer 120. Passivation layer 124 may conformally be above and on the barrier layer 108 and the gate layer 120 (e.g., along the sidewall surface of the gate layer 120 and above and on the top surface of the gate layer 120). In some embodiments, passivation layer 124 may be or comprise silicon nitride, silicon oxide, etc., or combinations thereof. Passivation layer 124 may comprise one or more layers of the same or different materials. Passivation layer 124 may be referred to as a dielectric layer.

[0024] Gate contact 126 is connected to gate layer 120 through an opening in passivation layer 124. Gate contact 126 is above and contacts gate layer 120. A portion of gate contact 126 may cover passivation layer 124, near gate contact 126 to contact the opening in gate layer 120. Gate contact 126 may be or comprise a metal, such as titanium (Ti), tungsten titanate (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), or combinations thereof (e.g., comprising a stack of multiple layers comprising different metal layers). Gate contact 126 may be a metal in which a Schottky junction or an ohmic junction is formed at the interface between gate contact 126 and gate layer 120.

[0025] The first dielectric layer 130 is above and on the passivation layer 124 and the gate contact 126. The first dielectric layer 130 may be a single dielectric layer or may comprise multiple dielectric layers of the same or different dielectric materials. For example, the first dielectric layer 130 may comprise a silicon oxide-based material, such as phosphosilicate glass (PSG).

[0026] A metal via 132 extends through the first dielectric layer 130 and contacts the gate contact 126. A metal line 136 in the first metal layer is above and on the upper surface of the metal via 132 and the first dielectric layer 130. The metal via 132 may include one or more metal barrier layers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) conformally in a corresponding opening through the first dielectric layer 130, and fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or combinations thereof) above and / or on the metal barrier layers and / or adhesion layers. The metal line 136 may include one or more metal barrier layers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof), and body metal (e.g., aluminum (Al), copper (Cu), etc., or combinations thereof) above and / or on the metal barrier layers and / or adhesion layers.

[0027] The second dielectric layer 140 is above and on the first dielectric layer 130 and the metal line 136. The second dielectric layer 140 may comprise multiple dielectric layers of the same dielectric material or different dielectric materials. For example, the second dielectric layer 140 may comprise a silicon oxide-based material, such as PSG, and may further comprise one or more etch stop layers, such as silicon nitride (SiN).

[0028] Drain contact 142 extends through the second dielectric layer 140, the first dielectric layer 130, and the passivation layer 124 and contacts the barrier layer 108 on the drain region D. Source contact 144 extends through the second dielectric layer 140, the first dielectric layer 130, and the passivation layer 124 and contacts the barrier layer 108 on the source region S. Metal lines 152 and 154 in the second metal layer are above and on contacts 142 and 144, respectively, and above and on the upper surface of the second dielectric layer 140. Contacts 142 and 144 may each comprise one or more metal barrier layers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) conformally disposed in respective openings through dielectric layers 130 and 140 and passivation layer 124, and filler metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or combinations thereof) above and / or on the metal barrier layers and / or adhesion layers. Metal lines 152 and 154 may each comprise one or more metal barrier layers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof), and body metal (e.g., aluminum (Al), copper (Cu), etc., or combinations thereof) above and / or on the metal barrier layers and / or adhesion layers.

[0029] Although the drain contact 142 and source contact 144 are depicted as being located on the barrier layer 108 in the semiconductor device 100, this disclosure is not limited thereto. For example, the drain contact 142 and source contact 144 may extend into the depth of the barrier layer 108. In some instances, the drain contact 142 and source contact 144 may extend through the barrier layer 108 to be located on the channel layer 106. In some instances, the drain contact 142 and source contact 144 may extend into the depth of the channel layer 106.

[0030] Additional dielectric and metal layers may be formed above and on the second dielectric layer 140. The first dielectric layer 130, the second dielectric layer 140, the additional dielectric layer, the first metal layer, the second metal layer, and the additional metal layer may form an interconnect structure. Metal lines in adjacent metal layers may be electrically coupled through metal vias.

[0031] Figure 1 The semiconductor device 100 can achieve higher threshold voltage and improved drain current stability. In some cases, dopants, such as magnesium (Mg), doped in the access regions of the gate and barrier layers can increase the threshold voltage (V) of the enhancement-mode HEMT. t The amount of ) can be increased by using dopants to deplete the 2DEG in the channel layer of the HEMT, which can increase the threshold voltage (V t The value of ). Increase the threshold voltage (V) t The magnitude of this doping can reduce leakage current. However, having such doping in the access region may increase the drain current (Id) through the HEMT. D The drain current (I) is unstable, especially under high voltage stress. When doped in the access region, the drain current (Id) is... D The drain-source on-resistance (Rd) can be significantly reduced over a given stress event duration. Doping in the access region can either deplete the 2DEG and reduce the electron density, or create traps that trap electrons, thereby increasing the drain-source on-resistance (Rd) during high-voltage stress events. ds.on And reduce drain current (I) D ). Figure 1 The semiconductor device 100 can achieve a higher threshold voltage (V) by maintaining doping in the barrier layer 108 below the gate layer 120 (through the doped region 122). t The dopant in doped region 122, such as magnesium (Mg), can increase the threshold voltage (V). t The magnitude of the dopant. Furthermore, the relatively reduced dopant in the first access region A1 and the second access region A2 of the barrier layer can reduce the drain current (Id). D The instability of the barrier layer can be reduced by decreasing the dopant in the first access region A1 and the second access region A2. ds.on And reduce the connection resistance (R) access ).

[0032] Figures 2 to 6 The following are examples. Figure 1 Cross-sectional views of the semiconductor device 100 at various stages of the first manufacturing method. (Reference) Figure 2 One or more transition layers 104 are formed above and thereon on the semiconductor substrate 102. A channel layer 106 is formed above and thereon on the one or more transition layers 104, and a barrier layer 108 is formed above and thereon on the channel layer 106. Figure 2 The barrier layer 108, formed in the process, can be an undoped semiconductor material (e.g., an intrinsic semiconductor material free of p-type or n-type dopants). Furthermore, in some instances, the barrier layer 108 is neither in-situ doped with p-type nor in-situ doped with n-type dopants during epitaxial growth. In some instances, the transition layer 104, channel layer 106, and barrier layer 108 can be formed using any suitable deposition process, which can further be an epitaxial growth process. For example, the transition layer 104, channel layer 106, and barrier layer 108 can each be epitaxially grown using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), low-pressure chemical vapor deposition (LPCVD), or another epitaxial process. The materials of the semiconductor substrate 102, transition layer 104, channel layer 106, and barrier layer 108 can be as previously described.

[0033] refer to Figure 3 A doped gate layer 302 is formed above and thereon the barrier layer 108. In some instances, the doped gate layer 302 may be epitaxially grown, for example, by MOCVD, MBE, LPCVD, plasma-enhanced chemical vapor deposition (PECVD), atomic layer epitaxy, or another epitaxial process. The doped gate layer 302 may be doped in situ during deposition (e.g., during epitaxial growth, simultaneously with the formation of the doped gate layer 302) or by implantation after deposition. As formed, the doped gate layer 302 is doped with a dopant, such as a p-type dopant, at a concentration equal to or greater than 1 × 10⁻⁶. 17 cm -3 For example, equal to or greater than 1×10 19 cm -3 And more specifically equal to or greater than 1 × 10 20 cm -3 In some instances, the doped gate layer 302 may be or include a gallium nitride (GaN) layer, or more generally, an indium aluminum gallium nitride (In) layer. x Al y Ga 1-x-yThe doped gate layer 302 is a p-type dopant, which may be or include magnesium (Mg), carbon (C), or combinations thereof. As previously described, the doped gate layer 302 and / or the dopant may be other materials and / or dopant.

[0034] In instances where the doped gate layer 302 is doped in situ during deposition, the process parameters used for depositing the doped gate layer 302 can be adjusted to reduce dopant diffusion into the barrier layer 108. For example, the process temperature for deposition, such as MOCVD, can be reduced. Lowering the process temperature reduces the diffusion of dopants, such as magnesium (Mg), from the process environment and / or the doped gate layer 302 into the barrier layer 108. Similarly, the process pressure for deposition can be reduced. In some instances, the deposition of the doped gate layer 302 (e.g., epitaxial growth) is performed by MOCVD at a process temperature ranging from 800°C to 1,050°C and a process pressure ranging from 100 mbar to 500 mbar. In some instances, the deposition of the doped gate layer 302 is performed by MOCVD, wherein the doped gate layer 302 is in situ doped by flowing a dopant source gas as the dopant source. In some of these examples, the flow rate of the dopant source gas can be in the range of up to 1,000 standard cubic centimeters per minute (sccm). Furthermore, the flow rate of the dopant source gas (e.g., bis(cyclopentadienyl)magnesium (Cp₂Mg) gas as a source of magnesium (Mg)) can be initially low and subsequently increased during the deposition of the doped gate layer 302. By making the flow rate of the dopant source gas initially low, less dopant can be used to diffuse into the barrier layer 108 closer to it, which reduces the diffusion of dopant into the barrier layer 108 due to deposition. In such cases, as formed, the doped gate layer 302 can have a gradient concentration of dopant, wherein the gradient concentration increases from the interface between the barrier layer 108 and the doped gate layer 302 to away from the barrier layer 108.

[0035] refer to Figure 4 The doped gate layer 302 is patterned into a patterned doped gate layer 402. The doped gate layer 302 can be patterned using appropriate photolithography and etching processes.

[0036] refer to Figure 5 A heat treatment is performed to drive the dopant in the patterned doped gate layer 402 to diffuse into the barrier layer 108, thereby forming the doped region 122. The heat treatment can be an annealing step or any process step that can involve etching, deposition, etc., of another material. The heat treatment can be performed in processes such as... Figure 5 The structure shown is structurally and / or in the context of, for example, the following regarding Figure 6The described additional layers and / or features are implemented on the structure. In some instances, the heat treatment involves using a process temperature of at least 800°C, for example, a process temperature in the range of 800°C to 1,000°C. The heat treatment causes diffusion of the dopant doped in the patterned doped gate layer 402. Due to the heat treatment, diffusion can make the concentration of the dopant more uniform throughout the gate layer 120 (e.g., with a lower gradient concentration). Diffusion further causes the dopant to diffuse outward from the patterned doped gate layer 402 into the barrier layer 108, thereby forming the doped region 122. The patterning of the patterned doped gate layer 402 causes the dopant to diffuse into the vicinity of the patterned doped gate layer 402 (and thus into the vicinity of the gate layer 120). This makes the concentration of the dopant in the doped region 122 greater than the concentration of the dopant in the first access region A1 and / or the second access region A2 in the barrier layer 108. Although dopant diffusion or implantation into the first access region A1 and / or the second access region A2 in the barrier layer 108 can introduce dopant into the first access region A1 and / or the second access region A2 before heat treatment, the dopant diffusion caused by heat treatment results in a dopant concentration in the doped region 122 that is greater than the dopant concentration in the first access region A1 and / or the second access region A2 in the barrier layer 108. The dopant concentrations in the gate layer 120, the doped region 122, the first access region A1, and the second access region A2 can be as previously described.

[0037] refer to Figure 6 A passivation layer 124 is formed above and thereon on the gate layer 120 and the barrier layer 108. The passivation layer 124 may be deposited conformally above and thereon on the barrier layer 108, and along the sidewall surface of the gate layer 120 and above and thereon on the top surface of the gate layer. The passivation layer 124 can be formed using any suitable deposition process, such as LPCVD, atomic layer deposition (ALD), etc. In some instances, the deposition of the passivation layer 124 may be... Figure 5 The heat treatment drives the diffusion of dopants into the barrier layer 108. More specifically, in instances where LPCVD is used to form the passivation layer 124, the LPCVD process may include an annealing step, which may be... Figure 5 The heat treatment drives the dopant from the patterned doped gate layer 402 into the barrier layer 108. Example materials for the passivation layer 124 may be as previously described.

[0038] refer to Figure 1A gate contact 126 is formed. An opening through the passivation layer 124 is formed using appropriate photolithography and etching processes to expose the gate layer 120. A metal layer for the gate contact 126 is deposited on the passivation layer 124 and in the opening using appropriate deposition processes such as chemical vapor deposition (CVD) or physical vapor deposition (PVD) to contact the gate layer 120. The metal layer is patterned into the gate contact 126 using appropriate photolithography and etching processes.

[0039] A first dielectric layer 130 is formed above and thereon the passivation layer 124 and the gate contact 126. The first dielectric layer 130 can be deposited using any suitable deposition process, such as plasma-enhanced CVD (PECVD). The first dielectric layer 130 can be planarized, for example, by chemical mechanical polishing (CMP).

[0040] A metal via 132 is formed, extending through the first dielectric layer 130 to the gate contact 126, and a metal line 136 is formed above and thereon on the first dielectric layer 130. Appropriate photolithography and etching processes can be used to form the opening extending through the first dielectric layer 130 to the gate contact 126. Metal is deposited in the via 132 and the opening extending through the first dielectric layer 130. Appropriate deposition processes, such as CVD or PVD, can be used to deposit the metal. Appropriate photolithography and etching processes can be used to pattern the metal into the metal line 136. Metal located below the metal line 136 and in the opening extending through the first dielectric layer 130 forms the metal via 132.

[0041] A second dielectric layer 140 is formed above and thereon the first dielectric layer 130 and the metal line 136. The second dielectric layer 140 can be deposited using any suitable deposition process, such as PECVD. The second dielectric layer 140 can be planarized, for example, by CMP.

[0042] Drain contacts 142 and source contacts 144 are formed at the drain region D and source region S, respectively, passing through the second dielectric layer 140, the first dielectric layer 130, and the passivation layer 124 to reach the barrier layer 108. Metal lines 152 and 154 are formed above and on the second dielectric layer 140. Openings passing through the second dielectric layer 140, the first dielectric layer 130, and the passivation layer 124 to reach the barrier layer 108 can be formed at the drain region D and source region S using appropriate photolithography and etching processes. The metal of the drain contacts 142 and source contacts 144 and the metal lines 152 and 154 is deposited above the second dielectric layer 140 and in the openings passing through the second dielectric layer 140, the first dielectric layer 130, and the passivation layer 124. Appropriate deposition processes such as CVD and PVD can be used to deposit the metal. The metal can be patterned into metal lines 152 and 154 using appropriate photolithography and etching processes. The metal located below the metal lines 152 and 154 and in the corresponding openings passing through the second dielectric layer 140, the first dielectric layer 130 and the passivation layer 124 forms the drain contact 142 and the source contact 144.

[0043] Figure 7 and 8 The following are examples. Figure 1 Cross-sectional views of the semiconductor device 100 at various stages of the second manufacturing method. The process is as described above regarding... Figure 2 As described.

[0044] refer to Figure 7 An undoped gate layer 702 is formed above and thereon a barrier layer 108, and a doped gate layer 302 is formed above and thereon the undoped gate layer 702. In some examples, the undoped gate layer 702 and the doped gate layer 302 can be epitaxially grown, for example, by MOCVD, MBE, LPCVD, PECVD, atomic layer epitaxy, or another epitaxial process. In some examples, the thickness of the undoped gate layer 702 can be less than 20 nm, for example, greater than 0 nm and less than 20 nm. The undoped gate layer 702 can be an intrinsic semiconductor material (e.g., free of p-type or n-type dopants). The doped gate layer 302 can be doped in situ during deposition or by implantation after deposition. In some examples, the undoped gate layer 702 can be an intrinsic semiconductor material that includes the doped gate layer 302. In some examples, the undoped gate layer 702 is or includes gallium nitride (GaN), or more generally, is or includes indium aluminum gallium nitride (In). x Al y Ga 1-x-y N). In some instances, the undoped gate layer 702 is or contains a gallium nitride (GaN) layer, and the doped gate layer 302 is p-doped gallium nitride (pGaN). The doped gate layer 302 and / or the dopant may be as previously described.

[0045] refer toFigure 8 The undoped gate layer 702 and the doped gate layer 302 are patterned into a patterned undoped gate layer 802 and a patterned doped gate layer 402, respectively. The undoped gate layer 702 and the doped gate layer 302 can be patterned using appropriate photolithography and etching processes.

[0046] Then, handle matters such as... Figure 5 , 6 As described in 1. Figure 5 (or this article references) Figure 6 The heat treatment (described) diffuses the dopant into and through the patterned undoped gate layer 802 and further into the barrier layer 108 to form the doped region 122. The heat treatment allows for a more uniform concentration (e.g., a lower gradient concentration) of the dopant across the patterned undoped gate layer 802 and the patterned doped gate layer 402 after the heat treatment, thereby forming the gate layer 120. The undoped gate layer 702 (and subsequently the patterned undoped gate layer 802) can form a buffer layer between the barrier layer 108 and the doped gate layer 302 (and subsequently the patterned doped gate layer 402) prior to the heat treatment, through which the dopant is driven from the patterned doped gate layer 402 into the barrier layer 108. The undoped gate layer 702 (and subsequently the patterned undoped gate layer 802) serving as a buffer layer can prevent the diffusion of dopants to a certain extent during the processing prior to heat treatment, so that less dopants diffuse into, for example, the first access region A1 and the second access region A2.

[0047] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations may be made therein without departing from the scope defined by the appended claims.

Claims

1. A semiconductor device comprising: a channel layer over a semiconductor substrate; a barrier layer over the channel layer; and a gate layer over the barrier layer, the gate layer doped with a dopant, wherein: a first region in the barrier layer overlies a channel region in the channel layer and is under the gate layer, the first region having a first concentration of the dopant; and a second region in the barrier layer is disposed laterally relative to the first region, the second region having a second concentration of the dopant, the second concentration being less than the first concentration.

2. The semiconductor device of claim 1, wherein the first concentration is one order of magnitude or more greater than the second concentration.

3. The semiconductor device of claim 1, wherein the dopant is a p-type dopant.

4. The semiconductor device of claim 1, wherein the dopant comprises magnesium, carbon, or a combination thereof.

7. The semiconductor device of claim 1, wherein:

5. The semiconductor device of claim 1, wherein the first concentration is 1 x 10 16 cm -3 or more.

6. The semiconductor device according to claim 1, wherein the second concentration is 1 x 10 19 cm -3 or less. the channel layer comprises gallium nitride (GaN); the barrier layer comprises aluminum gallium nitride (AlGaN); and the gate layer comprises magnesium-doped gallium nitride (GaN:Mg).

8. The semiconductor device of claim 1, further comprising: a passivation layer over the gate layer and the barrier layer; and a gate contact over the gate layer and contacting the gate layer and through the passivation layer.

9. A method comprising: forming a doped gate layer over a barrier layer, the doped gate layer being doped with a dopant when forming the doped gate layer, wherein: the barrier layer is over a channel layer; and the channel layer is over a semiconductor substrate; patterning the doped gate layer; and after patterning the doped gate layer, performing a thermal treatment on the doped gate layer and the barrier layer, wherein the thermal treatment causes the dopant to diffuse from the doped gate layer into the barrier layer.

10. The method of claim 9, further comprising: forming an undoped gate layer over the barrier layer, wherein the doped gate layer is formed over the undoped gate layer.

11. The method of claim 9, wherein forming the doped gate layer includes epitaxially growing the doped gate layer, including: growing the doped gate layer at a process temperature in a range from 800 °C to 1,050 °C; growing the doped gate layer at a process pressure in a range from 100 millibars (mbar) to 500 mbar; and flowing a dopant source gas at a flow rate in a range up to 1,000 standard cubic centimeters per minute (seem), the dopant source gas being a source of the dopant.

12. The method of claim 11, wherein epitaxially growing the doped gate layer includes increasing the flow rate of the dopant source gas, the dopant source gas being a source of the dopant, when epitaxially growing the doped gate layer.

13. The method of claim 9, wherein the thermal treatment includes a process temperature of at least 800 °C. ​ ​ 14. The method of claim 9, wherein after performing the thermal treatment: a first region in the barrier layer overlies a channel region in the channel layer and is located below the doped gate layer; the first region has a first concentration of the dopant; a second region in the barrier layer is laterally disposed relative to the first region; and the second region has a second concentration of the dopant that is less than the first concentration.

15. The method of claim 14, wherein the first concentration is one order of magnitude or more greater than the second concentration.

16. The method of claim 9, wherein the dopant comprises magnesium, carbon, or a combination thereof.

17. The method of claim 9, further comprising: forming a passivation layer over the doped gate layer and the barrier layer; forming an opening through the passivation layer to the doped gate layer; forming a metal in the opening and contacting the doped gate layer; and patterning the metal to form a gate contact over and contacting the doped gate layer.

18. A semiconductor device, comprising: a GaN channel layer over a semiconductor substrate; an AlGaN barrier layer over the GaN channel layer; a doped GaN gate layer over the AlGaN barrier layer; a drain contact contacting the AlGaN barrier layer, wherein: the doped GaN gate layer includes a p-type dopant; a first portion of the AlGaN barrier layer under the doped GaN gate layer includes a first concentration of the p-type dopant; and a second portion of the AlGaN barrier layer between the doped GaN gate layer and the drain contact includes a second concentration of the p-type dopant that is less than the first concentration.

19. The semiconductor device of claim 18, wherein the first concentration is one order of magnitude or more greater than the second concentration.

20. The semiconductor device of claim 18, wherein: the first portion of the AlGaN barrier layer overlies a channel region in the GaN channel layer; and the second portion of the AlGaN barrier layer includes an access region in the AlGaN barrier layer.

21. The semiconductor device of claim 18, wherein the p-type dopant in the first portion of the AlGaN barrier layer extends from an interface between the doped GaN gate layer and the AlGaN barrier layer toward the GaN channel layer.

22. The semiconductor device of claim 18, further comprising: a passivation layer over the doped GaN gate layer and the AlGaN barrier layer; and a gate contact over and contacting the doped GaN gate layer and through the passivation layer. ​ ​

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