Power semiconductor device, power conversion device and method for manufacturing power semiconductor device

Abstract

The purpose of the present invention is to suppress damage to a chip of a trench gate type power semiconductor device. A SiC-MOSFET (101) is provided with: a trench (20) that penetrates a source region (4) and a base region (3) from the surface of the source region (4) and reaches the inside of a drift layer (2); a bottom base region (5) of a second conductivity type, which is formed in a portion of the drift layer (2) that is in contact with the bottom surface of the trench (20); a side wall base region (6) of a second conductivity type formed in a portion of the drift layer (2) that is in contact with a second side wall (22) of the trench (20); a gate electrode (8) formed inside the trench (20) via a gate insulating film (7); a source electrode 10 that is in contact with the source region 4; and a drain electrode (11) formed on a second main surface (S2), which is a main surface on the opposite side of the SiC substrate (1) from the first main surface (S1), in which the angle (beta) between the bottom surface of the trench (20) and the first side wall (21) is larger than the angle (gamma) between the bottom surface of the trench (20) and the second side wall (22), and the angle (gamma) between the bottom surface of the trench (20) and the second side wall (22) is less than 90 DEG.

Description

Technical Field

[0001] This invention relates to semiconductor devices for power applications. Background Technology

[0002] Compared to semiconductor devices using silicon (Si) substrates (hereinafter referred to as "Si semiconductor devices"), semiconductor devices using silicon carbide (SiC) substrates (hereinafter referred to as "SiC semiconductor devices") exhibit superior voltage and heat resistance. In order to achieve high voltage withstand capability, low loss, or operation in high-temperature environments, SiC semiconductor devices have historically been used in power semiconductor devices such as MOSFETs (metal-oxide-semiconductor field-effect transistors) or IGBTs (insulated-gate bipolar transistors).

[0003] Because SiC has a higher dielectric breakdown electric field strength than Si, SiC semiconductor devices can have a thinner drift layer, which serves as the withstand voltage layer for achieving the same breakdown voltage, compared to Si semiconductor devices. Furthermore, SiC semiconductor devices allow for higher impurity doping levels in the withstand voltage layer compared to Si semiconductor devices. For these reasons, SiC semiconductor devices can achieve a significantly lower on-resistance compared to Si semiconductor devices. For example, the on-resistance of a SiC-MOSFET with a withstand voltage of 1kV or higher but less than 1.2kV is 5mΩcm. 2 The following values ​​are less than half of those for Si-MOSFETs or Si-IGBTs with the same voltage rating.

[0004] In the future, with improvements in manufacturing costs, process technology, and other performance enhancements, it is anticipated that most Si-IGBTs used as inverter components will be replaced by SiC semiconductor devices. Currently, in order to reduce the power-on losses of SiC semiconductor devices, trench-gate SiC-MOSFETs or SiC-IGBTs have been developed.

[0005] However, in trench-gate SiC-MOSFETs or SiC-IGBTs, there is a problem where the electric field and current concentrate at the corner of the trench bottom in the cell region, causing chip damage.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: Japanese Patent Application Publication No. 9-275212 Summary of the Invention

[0009] The problem that the invention aims to solve

[0010] Patent Document 1 discloses a technique that suppresses the concentration of electric field and current at the trench gate electrode at the outer periphery of the chip, thereby preventing chip damage, by configuring the trench gate electrode at the outer periphery of the chip to not perform MOS operation when a gate voltage is applied. However, according to the configuration of Patent Document 1, since the electric field and current are concentrated at the bottom of the trench gate electrode outside the outer periphery of the chip, there is a problem of chip damage.

[0011] The present invention was proposed to eliminate the above-mentioned problems, and its purpose is to suppress the damage to the chip of a trench gate type power semiconductor device.

[0012] Methods for solving problems

[0013] The power semiconductor device of the present invention comprises: a SiC substrate; a drift layer of a first conductivity type formed on a first main surface of the SiC substrate; a base region of a second conductivity type formed on the surface of the drift layer; an impurity region of the first conductivity type partially formed on the surface of the base region; a trench extending from the surface of the impurity region through the impurity region and the base region to the interior of the drift layer, having a first sidewall and a second sidewall facing each other; a bottom base region of the second conductivity type formed on a portion of the drift layer in contact with the bottom surface of the trench; a sidewall base region of the second conductivity type formed on a portion of the drift layer in contact with the second sidewall of the trench; a gate electrode formed inside the trench with a gate insulating film in between; a surface electrode in contact with the impurity region; and a back electrode formed on a second main surface of the SiC substrate opposite to the first main surface; the angle between the bottom surface of the trench and the first sidewall is greater than the angle between the bottom surface of the trench and the second sidewall, and the angle between the bottom surface of the trench and the second sidewall is less than 90°.

[0014] Invention Effects

[0015] In the power semiconductor device of the present invention, the current path is confined to the first sidewall side of the trench via the bottom base region. Since the angle between the bottom surface of the trench and the first sidewall is greater than the angle between the bottom surface of the trench and the second sidewall, the electric field at the end of the bottom surface of the trench that contacts the first sidewall is less than the electric field at the end of the bottom surface of the trench that contacts the second sidewall. Thus, by reducing the electric field at the end of the bottom surface of the trench that forms the current path, it is possible to prevent both current and electric field from concentrating at the end of the bottom surface of the trench, thereby suppressing chip damage. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of the SiC-MOSFET in Embodiment 1.

[0017] Figure 2This is a flowchart illustrating the manufacturing method of SiC-MOSFET according to Embodiment 1.

[0018] Figure 3 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0019] Figure 4 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0020] Figure 5 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0021] Figure 6 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0022] Figure 7 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0023] Figure 8 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0024] Figure 9 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0025] Figure 10 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0026] Figure 11 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0027] Figure 12 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0028] Figure 13 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0029] Figure 14 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0030] Figure 15 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0031] Figure 16 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0032] Figure 17 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 1.

[0033] Figure 18 This is a cross-sectional view showing the current path of the SiC-MOSFET in Embodiment 1.

[0034] Figure 19 This is a cross-sectional view illustrating the electric field generated at the corner of the bottom surface of the trench in the SiC-MOSFET of Embodiment 1.

[0035] Figure 20 This is a cross-sectional view illustrating the electric field generated at the corner of the bottom surface of the trench in the SiC-MOSFET of Embodiment 1.

[0036] Figure 21 This is a cross-sectional view of the SiC-MOSFET in Embodiment 2.

[0037] Figure 22 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 2.

[0038] Figure 23 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 2.

[0039] Figure 24 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 2.

[0040] Figure 25 This is a cross-sectional view of the SiC-MOSFET in Embodiment 3.

[0041] Figure 26 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 3.

[0042] Figure 27 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 3.

[0043] Figure 28 This is a diagram showing the distribution of p-type ion concentration on the bottom surface of the trench of the SiC-MOSFET in Embodiment 3.

[0044] Figure 29 This is a cross-sectional view showing the manufacturing process of the SiC-MOSFET in Embodiment 3.

[0045] Figure 30 This is a cross-sectional view of the SiC-MOSFET in Embodiment 4.

[0046] Figure 31It is a cross-sectional view showing the manufacturing process of the SiC-MOSFET of Embodiment 4.

[0047] Figure 32 It is a block diagram showing the structure of a power conversion system to which the power semiconductor devices according to Embodiments 1, 2, 3, and 4 are applied. Specific Embodiments

[0048] <A. Embodiment 1>

[0049] <A-1. Structure>

[0050] Figure 1 It is a cross-sectional view of the power semiconductor device SiC-MOSFET 101 according to Embodiment 1. The SiC-MOSFET 101 is configured to include an n-type SiC substrate 1, an n-type drift layer 2, a p-type base region 3, an n-type source region 4, a trench 20, a p-type bottom base region 5, a p-type sidewall base region 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, a source electrode 10, and a drain electrode 11.

[0051] The SiC substrate 1 has a first main surface S1 and a second main surface S2, and the second main surface S2 is the main surface on the opposite side to the first main surface S1. The drift layer 2 is made of n-type SiC and is provided on the first main surface S1 of the SiC substrate 1. The SiC substrate 1, the drift layer 2, and the impurity regions formed on the surface layer of the drift layer 2 described later are collectively referred to as a semiconductor substrate 50. The semiconductor substrate 50 has a first main surface S11 and a second main surface S12, and the second main surface S12 is the main surface on the opposite side to the first main surface S11. The second main surface S12 coincides with the second main surface S2 of the SiC substrate 1.

[0052] The base region 3 is provided on the surface layer of the drift layer 2. The source region 4, which is an impurity region of the first conductivity type, is locally provided on the surface layer of the base region 3. The upper surface of the source region 4 and the upper surface in the region of the base region 3 where the source region 4 is not formed constitute the first main surface S11 of the semiconductor substrate 50.

[0053] The trench 20 penetrates the source region 4 and the base region 3 in their thickness directions from the first main surface S11 to reach the drift layer 2. The bottom base region 5 is provided at a portion of the drift layer 2 that is in contact with the bottom of the trench 20. The trench 20 has a first sidewall 21 and a second sidewall 22 that face each other. The sidewall base region 6 is provided at a portion of the drift layer 2 that is in contact with the second sidewall 22 of the trench 20, but is not provided at a portion of the drift layer 2 that is in contact with the first sidewall 21.

[0054] The bottom surface of the trench 20, that is, the upper surface of the bottom base region 5, is inclined with respect to the first main surface S1 of the SiC substrate 1. Here, the angle between the bottom surface of the trench 20 and the first sidewall 21 is defined as the first angle β, and the angle between the bottom surface of the trench 20 and the second sidewall 22 is defined as the second angle γ. The first angle β of the bottom surface of the trench 20 is greater than the second angle γ. In addition, the second angle γ is less than 90°.

[0055] The gate insulating film 7 is provided over the bottom and sidewalls of the trench 20 and over a partial region of the source region 4. The gate electrode 8 is provided in the trench 20隔着 the gate insulating film 7. The interlayer insulating film 9 is formed over the gate electrode 8 and over the gate insulating film 7 formed over the source region 4.

[0056] The source electrode 10 as a surface electrode is provided on the first main surface S11 of the semiconductor substrate 50 and on the interlayer insulating film 9, contacting the source region 4. The drain electrode 11 as a back surface electrode is provided on the second main surface S2 of the SiC substrate 1.

[0057] <A-2. Manufacturing method>

[0058] Figure 2 It is a flowchart showing the manufacturing method of the SiC-MOSFET 101. Figures 3 to 17 It is a cross-sectional view during the manufacturing of the SiC-MOSFET 101. Hereinafter, the manufacturing method of the SiC-MOSFET 101 will be described using these figures.

[0059] First, on the first main surface S1 of the SiC substrate 1, a drift layer 2 made of n-type SiC is formed as an epitaxial film (step S1). Thus, as Figure 3 shown, a semiconductor substrate 50 including the SiC substrate 1 and the drift layer 2 is obtained. Figure 3 The upper surface and the lower surface of the semiconductor substrate 50 in

[0060] are also referred to as the first main surface S11 and the second main surface S12, respectively. Figure 4 Then, a mask (not shown) based on a resist or the like is formed on the drift layer 2, and impurities are ion-implanted using this mask, thereby forming a p-type base region 3 on the surface layer of the drift layer 2 (step S2).

[0061] Figure 5 =31]] Figure 5 This state is shown. Examples of the p-type impurity for forming the base region 3 include boron (B) or aluminum (Al).

[0062] Thereafter, by subjecting the semiconductor substrate 50 to a heat treatment at a high temperature using a heat treatment device (not shown), the p-type ions implanted into the base region 3 and the n-type ions implanted into the source region 4 are electrically activated.

[0063] Next, the resist mask 12 is removed, and another resist mask 13 is formed on the first main surface S11. Then, a trench 20 is formed by plasma dry etching or the like using the resist mask 13 (step S4). Figure 6 This state is shown. The trench 20 penetrates through the source region 4 and the base region 3 from the first main surface S11 and reaches the drift layer 2. In Figure 6 the right sidewall of the trench 20 is the first sidewall 21, and the left sidewall is the second sidewall 22.

[0064] The thicker the resist mask 13 is, the deeper the trench 20 can be formed. In the case where the thickness of the resist mask 13 is insufficient with respect to the depth of the trench 20 to be formed, the following mask can be used instead of the resist mask 13. That is, an oxide film made of TEOS is formed on the upper surfaces of the source region 4 and the base region 3, and dry etching is performed using this oxide film as a mask, whereby a deep trench 20 can be formed.

[0065] Next, impurities such as boron (B) or aluminum (Al) are implanted into the bottom of the trench 20, and as Figure 7 shown, a p-type bottom base region 5 is formed (step S5).

[0066] Next, after removing the resist mask 13, ion implantation is performed in an inclined direction inside the trench 20, that is, ion implantation is performed in a direction inclined by an angle α toward the second sidewall 22 with respect to the depth direction of the trench 20 as Figure 8 shown. Thus, as Figure 9 shown, a p-type sidewall base region 6 is formed in a portion of the drift layer 2 that abuts on the second sidewall 22 of the trench 20 (step S6). Examples of the p-type impurity for forming the sidewall base region 6 include boron (B) or aluminum (Al).

[0067] The direction of the ion implantation for forming the sidewall base region 6 is as follows. As Figure 10 shown, if the width of the trench 20 is a and the thickness of the source region 4 is b, the angle α of the ion implantation with respect to the depth direction of the trench 20 is 0° < α. In addition, 0° < α < arctan(a / b) is preferable. This is because if arctan(a / b) ≤ α, the influence of the ion implantation for forming the sidewall base region 6 on the shape or concentration of the source region 4 becomes large.

[0068] As Figure 9As shown, the contact end of the upper surface of the bottom base region 5 with the first sidewall 21 is designated as A, and the contact end with the second sidewall 22 is designated as B. By performing ion implantation according to the angle α condition described above, the p-type ion concentration in the bottom base region 5 gradually increases from A to B.

[0069] Next, an oxide film 14 is formed inside the trench 20 and on the first main surface S11 using a thermal oxidation method (step S7). This removes plasma damage caused during the formation of the trench 20, and as... Figure 11 As shown, the upper surface of the bottom base region 5 is inclined relative to the first main surface S1 of the SiC substrate 1.

[0070] Here, the greater the amount of oxidation, the more plasma damage is removed, but the impurity layer formed in the drift layer 2 is reduced. When the thermal oxidation amount of the SiC drift layer 2 is 20 nm or more and 80 nm or less, more preferably 30 nm or more and 70 nm or less, the inventors of this application confirmed that plasma damage was sufficiently removed by measuring the leakage current between the gate electrode 8 and the source electrode 10.

[0071] At high ion concentrations, the density of what is known as pores (sites where atoms detach from their intended locations) in a semiconductor increases. Regions with high pore density are more susceptible to oxidation. Therefore, regions with higher ion concentrations experience greater thermal oxidation. Consequently, the thickness of the oxide film 14 is greater on side B and less on side A. That is, the upper surface of the bottom base region 5 is tilted.

[0072] Then, by removing the oxide film 14, the bottom surface of the trench 20 is inclined according to the shape of the upper surface of the bottom base region 5 (step S8). In other words, the bottom surface of the trench 20 has a slope in the width direction of the trench 20. Figure 12 This indicates the state. Figure 9 The greater the slope of the ion concentration between A and B in the bottom base region 5 before thermal oxidation treatment, the better. Figure 12 The greater the slope of the bottom of the groove 20 after the thermal oxidation treatment shown.

[0073] The first angle β, which is the angle between the bottom surface of the trench 20 and the first sidewall 21, is controlled by the ion implantation angle α and the ion implantation concentration when the sidewall base region 6 is formed.

[0074] Next, as Figure 13 As shown, a gate insulating film 7 is formed inside the trench 20 and on the source region 4 and base region 3 by a deposition method such as chemical vapor deposition (step S9). Here, the gate insulating film 7 is not formed by thermal oxidation. This is because when the gate insulating film 7 is formed by thermal oxidation, the first angle β of the bottom surface of the trench 20 will change.

[0075] Next, as Figure 14 As shown, a gate electrode 8 is formed on the gate insulating film 7 so as to fill the trench 20. And, as Figure 15 shown, the remaining portion of the gate electrode 8 outside the trench 20 is removed to pattern the gate electrode 8. By anisotropic etching such as plasma etching, only the portion of the gate electrode 8 outside the trench 20 can be removed. Thus, the gate electrode 8 is formed in the trench 20 (step S10).

[0076] Next, an interlayer insulating film 9 is deposited on the gate electrode 8 and the gate insulating film 7 by chemical vapor deposition (CVD: Chemical Vapor Deposition). Then, the interlayer insulating film 9 is patterned by photolithography and etching process. As Figure 16 shown, the interlayer insulating film 9 is formed on the gate electrode 8 (step S11). It is also possible to round the corners of the interlayer insulating film 9 by introducing impurities such as B (boron) or P (phosphorus) into the interlayer insulating film 9. The material of the interlayer insulating film 9 is, for example, silicon nitride (SixNy) or silicon oxide (SiO2). The thickness of the interlayer insulating film 9 is preferably 0.5 μm or more and 2.0 μm or less.

[0077] After that, as Figure 17 shown, a source electrode 10 is formed (step S12). The material of the source electrode 10 is aluminum, an aluminum alloy composed of aluminum and silicon, an aluminum alloy composed of aluminum and copper, or nickel, etc. A barrier metal composed of titanium or a titanium compound such as titanium nitride (TiN) can also be appropriately used based on the above materials.

[0078] Next, if necessary, the second main surface S2 of the SiC substrate 1 is machined using a grinding stone to thin the SiC substrate 1 (step S13).

[0079] After that, a nickel film of about 600 nm is formed on the second main surface S2 of the SiC substrate 1 by sputtering or the like to form a drain electrode 11 (step S14). Thus, the Figure 1 shown SiC-MOSFET 101 is obtained. It should be noted that since the outermost surface of the nickel film is oxidized, the wettability with the solder alloy becomes poor, and the bonding state during chip bonding deteriorates. Therefore, a metal that is less reactive with the outside, such as gold or silver, can also be formed on the surface of the nickel film as a protective film, and the laminated film composed of the nickel film and gold or silver, etc. is used as the drain electrode 11.

[0080] <A-3. Effects>

[0081] Figure 18Shows the current path when current is applied to the SiC-MOSFET 101. The solid line C represents the current path when a voltage above the threshold voltage, which is the reference for applying a voltage to the gate electrode 8 to allow current to flow through the semiconductor, is applied, and the potential of the source electrode 10 is higher than that of the drain electrode 11. In the drain electrode 11, the current flowing through the entire electrode surface is concentrated only on the first sidewall 21 where there is no sidewall base region 6 on the sidewall of the trench 20. The reason is that in the second sidewall 22 of the trench 20, due to the presence of the sidewall base region 6, an n-type MOS composed of the drift layer 2, the base region 3, and the source region 4 is not formed. Even when a voltage above the threshold voltage is applied to the gate electrode 8, no current path is formed. On the first sidewall 21 of the trench 20, an n-type MOS composed of the drift layer 2, the base region 3, and the source region 4 is formed. If a voltage above the threshold voltage is applied to the gate electrode 8, the n-type MOS becomes in the on state and current flows.

[0082] When the first angle β of the bottom surface of the trench 20 is larger than the second angle γ, the electric field at the end of the bottom surface of the trench 20 is mitigated. The reason will be explained below. The electric field at the end of the bottom surface of the trench 20 can be approximated by the electric field generated by a circular electrode. As Figure 19 shown, consider a circular electrode with a radius R1 whose vertical bisector of the bottom surface of the trench 20 passes through the center and is tangent to the bottom surface of the trench 20 and the first sidewall 21. If the potential difference between the source electrode 10 and the drain electrode 11 is set as V1, then according to Gauss's law, the electric field E1 applied to the end of the bottom surface of the trench 20 tangent to the first sidewall 21 is proportional to V1 / R1. That is, the larger R1 is, the smaller the electric field E1 is. Additionally, according to R1 / (d / 2) = tan(β / 2), the larger the first angle β is, the larger R1 is, and the smaller the electric field E1 is.

[0083] Next, as Figure 20 shown, consider a circular electrode with a radius R2 whose vertical bisector of the bottom surface of the trench 20 passes through the center and is tangent to the bottom surface of the trench 20 and the second sidewall 22. According to Gauss's law, the electric field E2 applied to the corner of the bottom surface of the trench 20 with the second angle γ is proportional to V1 / R2. Therefore, the larger R2 is, the smaller the electric field E2 is. Additionally, R2 / (d / 2) = tan(γ / 2). Thus, when γ < β, R2 < R1, and further E2 < E1. That is, it is possible to make the electric field E1 at the end of the bottom surface of the trench 20 tangent to the first sidewall 21, which is the current path, smaller than the electric field E2 at the end of the bottom surface of the trench 20 tangent to the second sidewall 22, which is not the current path. Thereby, the concentration of the electric field and current at the end of the bottom surface of the trench 20 and the destruction of the chip are suppressed.

[0084] According to Embodiment 1, the SiC-MOSFET 101 includes a SiC substrate 1, a drift layer 2 of a first conductivity type, a base region 3 of a second conductivity type, a source region 4 of a first conductivity type, a trench 20, a bottom base region 5 of the second conductivity type, a sidewall base region 6 of the second conductivity type, a gate electrode 8, a source electrode 10, and a drain electrode 11. The drift layer 2 is formed on a first main surface S1 of the SiC substrate 1. The base region 3 is formed on the surface of the drift layer 2. The source region 4 is partially formed on the surface of the base region 3. The trench 20 extends from the surface of the source region 4 through the source region 4 and the base region 3 to the interior of the drift layer 2, and has a first sidewall 21 and a second sidewall 22 facing each other. The bottom base region 5 is formed on the portion of the drift layer 2 that is in contact with the bottom surface of the trench 20. The sidewall base region 6 is formed on the portion of the drift layer 2 that is in contact with the second sidewall 22 of the trench 20. The gate electrode 8 is formed inside the trench 20, separated by the gate insulating film 7. The source electrode 10 is in contact with the source region 4. The drain electrode 11 is formed on the second main surface S2 of the SiC substrate 1. The angle β between the bottom surface of the trench 20 and the first sidewall 21 is greater than the angle γ between the bottom surface of the trench 20 and the second sidewall 22.

[0085] In the manufacturing method of the SiC-MOSFET 101 according to Embodiment 1, (a) a drift layer 2 of a first conductivity type is formed on the first main surface S1 of the SiC substrate 1, (b) a base region 3 of a second conductivity type is formed on the surface layer of the drift layer 2, (c) a source region 4 as an impurity region of the first conductivity type is locally formed on the surface layer of the base region 3, (d) a trench 20 is formed that penetrates the source region 4 from the surface of the source region 4 and reaches the inside of the drift layer 2 and has first sidewalls 21 and second sidewalls 22 facing each other, (e) a bottom base region 5 of the second conductivity type is formed in a portion of the drift layer 2 that abuts on the bottom surface of the trench 20, (f) after step (e), by performing ion implantation in the trench 20 in a direction inclined from the depth direction of the trench 20 toward the second sidewall 22 side, a sidewall base region 6 of the second conductivity type is formed in a region of the drift layer 2 that abuts on the second sidewall 22, and the concentration of the second conductivity type impurity on the upper surface of the bottom base region 5 increases from the second sidewall 22 side toward the first sidewall 21 side, (g) by thermal oxidation treatment, a thermal oxide film having a thickness increasing from the second sidewall 22 side to the first sidewall 21 side is formed on the bottom surface of the trench 20, (h) after removing the thermal oxide film, a gate insulating film 7 is formed in the trench 20, (i) a gate electrode 8 is formed inside the trench 20隔着栅极绝缘膜7, (j) a source electrode 10 in contact with the source region 4 is formed, (k) a drain electrode 11 is formed on the second main surface S2 of the SiC substrate 1, which is the main surface opposite to the first main surface S1. Thus, the angle β between the bottom surface of the trench 20 and the first sidewall 21 is greater than the angle γ with the second sidewall 22. And, the electric field E1 at the end of the bottom surface of the trench 20 that forms the current path and abuts on the first sidewall 21 is smaller than the electric field E2 at the end of the bottom surface of the trench 20 that does not form the current path and abuts on the second sidewall 22. As a result, at the end of the bottom surface of the trench 20, the electric field and current are concentrated simultaneously, and chip breakdown is suppressed.

[0086] <B. Embodiment 2>

[0087] <B-1. Structure>

[0088] Figure 21 is a cross-sectional view of the power semiconductor device, i.e., the SiC-MOSFET 102, according to Embodiment 2.

[0089] The SiC-MOSFET 102 is different from the SiC-MOSFET 101 of Embodiment 1 only in that the gate insulating film in the trench 20 has a double-layer structure of a first gate insulating film 71 and a second gate insulating film 72.

[0090] The first gate insulating film 71 is formed on the bottom surface of the trench 20 in contact with the bottom base region 5. The upper surface of the first gate insulating film 71 is located at a position lower than the lower surface of the base region 3. The second gate insulating film 72 is formed on the first gate insulating film 71 and the side walls of the trench 20 and is not in contact with the bottom base region 5. The gate electrode 8 is formed in the trench 20隔着第二栅极绝缘膜72形成在沟槽20内。

[0091] <B-2. Manufacturing method>

[0092] Next, the manufacturing method of the SiC-MOSFET 102 will be described. The manufacturing method of the SiC-MOSFET 102 is different from that of the SiC-MOSFET 101 in the first embodiment only in the step of forming the gate insulating film ( Figure 2 step S9).

[0093] First, perform Figure 2 steps S1 to S8 to form the structure shown in Figure 12 .

[0094] After that, by a deposition method such as chemical vapor deposition, as shown in Figure 22 , the first gate insulating film 71 is formed in the trench 20 and on the first main surface S11. The first gate insulating film 71 is not formed by thermal oxidation. This is because if the first gate insulating film 71 is formed by thermal oxidation, as described in the first embodiment, due to the difference in ion concentration in each part of the bottom surface of the trench 20, each part of the bottom surface of the trench 20 is oxidized with different film thicknesses, and the first angle β of the bottom surface of the trench 20 changes.

[0095] Next, by anisotropic etching, the first gate insulating film 71 is etched back, leaving the part in contact with the bottom base region 5 and removing the other parts. At this time, as shown in Figure 23 , the upper surface of the first gate insulating film 71 is located at a position lower than the base region 3.

[0096] After that, by a deposition method such as chemical vapor deposition, as shown in Figure 24 , the second gate insulating film 72 is formed on the first gate insulating film 71 and the side walls of the trench 20.

[0097] After that, by performing the processes of steps S10 to S14 in Figure 2 , the SiC-MOSFET 102 shown in Figure 21 is obtained.

[0098] When the depth of the gate electrode 8 is set to L1 and the depth of the base region 3 is set to L2, it is necessary that L2 < L1. This is because, when L1 < L2, even if a voltage equal to or higher than the threshold voltage is applied to the gate electrode 8, a part of the base region 3 near the second gate insulating film 72 on the side wall of the trench 20 does not invert and remains p-type, and does not function as a channel.

[0099] <B-3. Effect>

[0100] The SiC-MOSFET 102 according to Embodiment 2 includes: a first gate insulating film 71 that is filled in the trench 20 to a height lower than the lower surface of the base region 3; and a second gate insulating film 72 that is formed after the first gate insulating film 71 and covers the side wall of the trench 20 above the first gate insulating film 71. Thus, compared with the SiC-MOSFET 101, the SiC-MOSFET 102 can increase the distance L3 between the end portion of the bottom surface of the trench 20 that is in contact with the first side wall 21 and the gate electrode 8. In other words, the gate insulating film between the two can be made thicker. As a result, the dielectric breakdown of the gate insulating film is suppressed.

[0101] The manufacturing method of the SiC-MOSFET 102 according to Embodiment 2 includes: a process of filling the trench 20 with the first gate insulating film 71; a process of etching back the first gate insulating film 71 so that the upper surface of the first gate insulating film 71 is located at a position lower than the lower surface of the base region 3; and a process of forming the second gate insulating film 72 on the first gate insulating film 71 and the side wall of the trench 20 thereafter. Thus, compared with the SiC-MOSFET 101, the distance L3 between the end portion of the bottom surface of the trench 20 and the gate electrode 8 in the SiC-MOSFET 102 can be increased. In other words, the gate insulating film between the two can be made thicker. As a result, the dielectric breakdown of the gate insulating film is suppressed.

[0102] <C. Embodiment 3>

[0103] <C-1. Structure>

[0104] Figure 25 It is a cross-sectional view of the power semiconductor device, i.e., the SiC-MOSFET 103, according to Embodiment 3. The SiC-MOSFET 103 is different from the SiC-MOSFET 101 of Embodiment 1 only in that the bottom surface of the trench 20, i.e., the upper surface of the bottom base region 5, is composed of two surfaces with different slopes. However, the gate insulating film 7 of the SiC-MOSFET 103 may also adopt the double-layer gate insulating film described in Embodiment 2.

[0105] <C-2. Manufacturing method>

[0106] Next, the manufacturing method of the SiC-MOSFET 103 will be described. The manufacturing method of the SiC-MOSFET 103 differs from that of the SiC-MOSFET 101 of the first embodiment only in the forming process of the sidewall base region 6 ( Figure 2 step S6 in

[0107] First, steps S1 to S5 in Figure 2 are carried out to form the structure shown in Figure 7 .

[0108] Next, as shown in Figure 26 , a first resist mask 16 is formed to cover the part (B-C) on the second sidewall 22 side of the bottom base region 5 and the part of the first main surface S1 adjacent to the second sidewall 22. Then, similarly to the first embodiment, using the first resist mask 16, p-type ions are implanted into the inside of the trench 20 from an inclined direction. At this time, the direction of ion implantation is a direction inclined at an angle ω with respect to the depth direction of the trench 20 toward the second sidewall 22.

[0109] After removing the first resist mask 16, as shown in Figure 27 , a second resist mask 17 is formed to cover the part (C-A) on the first sidewall 21 side of the bottom base region 5 and the part of the first main surface S1 adjacent to the first sidewall 21. Then, similarly to the first embodiment, using the second resist mask 17, p-type ions are implanted into the inside of the trench 20 from an inclined direction. At this time, the direction of ion implantation is a direction inclined at an angle α with respect to the depth direction of the trench 20 toward the second sidewall 22. Here, it is not necessary that ω = α.

[0110] Figure 28 FIG. Figure 26 and Figure 27 show the p-type ion concentration distribution formed between A and B on the upper surface of the bottom base region 5 by the two ion implantations. In the present embodiment, the p-type ion concentration needs to monotonically decrease from B to A. In addition, the difference in the p-type ion concentration between B-C needs to be smaller than the difference in the p-type ion concentration between C-A.

[0111] Then, by performing the processes of steps S7 and S8 in Figure 2 , as shown in Figure 29 , the bottom surface of the trench 20, that is, the upper surface of the bottom base region 5, has a structure with two surfaces having different slopes.

[0112] After that, through the processes of steps S9 to S14 in Figure 2 , the SiC-MOSFET 103 shown in Figure 25 is obtained.

[0113] <C-3. Effect>

[0114] In the SiC-MOSFET 103, the angle between the bottom surface of the trench 20 and the first sidewall 21 is defined as the first angle θ, and the angle between the bottom surface of the trench 20 and the second sidewall 22 is defined as the second angle δ. In the SiC-MOSFET 103, the bottom surface of the trench 20 is composed of two surfaces with different slopes, so that the first angle θ of the bottom surface of the trench 20 can be made larger than the first angle β of the first embodiment. In addition, when the first angle θ is equal to the first angle β of the first embodiment, that is, when θ = β, the second angle δ can be made larger than the second angle γ of the first embodiment, that is, γ < δ. Therefore, when β < θ, the electric field E1 applied to the end portion of the bottom surface of the trench 20 in contact with the first sidewall 21 can be made smaller than that of the first embodiment. In addition, when θ = β, the electric field E1 applied to the end portion of the bottom surface of the trench 20 in contact with the second sidewall 22 can be made smaller than that of the first embodiment.

[0115] In the manufacturing method of the SiC-MOSFET 103, the ion implantation for forming the sidewall base region 6 includes: a first ion implantation using the first resist mask 16 covering the second sidewall 22 side in the trench 20; and a second ion implantation using the second resist mask 17 covering the first sidewall 21 side in the trench 20 not covered by the first resist mask 16. Thus, through the subsequent thermal oxidation treatment, the bottom surface of the trench 20 can be composed of two surfaces with different slopes.

[0116] <D. Embodiment 4>

[0117] <D-1. Structure>

[0118] Figure 30 It is a cross-sectional view of the power semiconductor device SiC-MOSFET 104 according to Embodiment 4. The SiC-MOSFET 104 is different from the SiC-MOSFET 101 of the first embodiment only in that the upper surface of the bottom base region 5, which is the bottom surface of the trench 20, is a curved surface.

[0119] The tangent line of the gate oxide film 7 at the point that bisects the first sidewall 21 of the trench 20 in the depth direction with reference to the first main surface S11 and the deepest position is set as the tangent line X. The tangent line of the gate oxide film 7 at the point P where the dividing line Q that equally divides the trench 20 into four parts in the lateral direction intersects the gate oxide film 7 is set as the tangent line Y. The angle formed by the tangent line X and the tangent line Y is set as the third angle ε.

[0120] The tangent line of the gate oxide film 7 at the point that bisects the second sidewall 22 of the trench 20 longitudinally with reference to the surface of the source region 4 and the deepest position of the trench 20 is set as the tangent line Z. The angle formed by the tangent line Z and the tangent line Y is set as the fourth angle ζ.

[0121] The third angle ε is greater than the fourth angle ζ. Additionally, the fourth angle ζ is less than 90°.

[0122] <D-2. Manufacturing Method>

[0123] Next, the manufacturing method of the SiC-MOSFET 104 will be described. The manufacturing method of the SiC-MOSFET 104 is different from that of the SiC-MOSFET 101 of Embodiment 1 only in the step of forming the trench 20 ( Figure 2 step S4).

[0124] First, steps S1 to S3 are carried out to form the Figure 2 structure shown. Figure 6 Next, as shown in

[0125] , isotropical etching is carried out to make the corners of the bottom surface of the trench 20 curved. Figure 31 Then, through the processes of steps S5 to S14 of

[0126] , it becomes a structure in which the bottom surface of the trench 20, that is, the bottom base region 5 has a curved surface, and the SiC-MOSFET 104 shown in Figure 2 is obtained. Figure 30

[0127] <D-3. Effects>

[0128] In the SiC-MOSFET 104, the bottom surface of the trench 20 is curved. Additionally, the third angle ε, which is the angle formed by the tangent X of the gate oxide film 7 and the first side wall 21 at the point where the dividing line Q that equally divides the trench 20 into four parts in the lateral direction and is closest to the first side wall intersects the bottom surface of the trench 20, is larger than the fourth angle ζ, which is the angle formed by the tangent X of the gate oxide film 7 and the second side wall 22. Additionally, the fourth angle ζ is less than 90°. In the SiC-MOSFET 104 with this structure, since the bottom surface of the trench 20 is a curved surface, the concentration of the electric field applied to the end portion of the bottom surface of the trench 20 is dispersed. As a result, at the end portion of the bottom surface of the trench 20, the concentration of the electric field and current simultaneously is suppressed, and chip breakdown is inhibited.

[0129] <E. Embodiment 5>

[0130] In this embodiment, the power semiconductor device according to Embodiments 1-4 is applied to a power conversion device. The application of the power semiconductor device according to Embodiments 1-4 is not limited to a specific power conversion device. Below, as Embodiment 5, the case where the power semiconductor device according to Embodiments 1-4 is applied to a three-phase inverter will be described.

[0131] Figure 32 ​This is a block diagram showing the structure of a power conversion system using the power conversion device of this embodiment.

[0132] Figure 32 The power conversion system shown consists of a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source, supplying DC power to the power conversion device 200. The power source 100 can be composed of various power sources, such as a DC system, solar cells, or batteries, or it can be composed of a rectifier circuit connected to an AC system or an AC / DC converter. Alternatively, the power source 100 can also be composed of a DC / DC converter that converts DC power output from a DC system into a specified power.

[0133] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, which converts the DC power supplied from the power source 100 into AC power and supplies AC power to the load 300. For example... Figure 32 As shown, the power conversion device 200 includes: a main conversion circuit 201 that converts DC power into AC power output; a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201; and a control circuit 203 that outputs control signals to control the drive circuit 202.

[0134] Load 300 is a three-phase motor driven by AC power supplied from power conversion device 200. It should be noted that load 300 is not limited to a specific purpose; it is a motor mounted on various electrical equipment, such as motors used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0135] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements on and off, it converts the DC power supplied from the power source 100 into AC power, which is then supplied to the load 300. Various specific circuit structures exist for the main conversion circuit 201, but the main conversion circuit 201 in this embodiment is a two-level three-phase full-bridge circuit, which can be constructed from six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. Any one of the power semiconductor devices described in embodiments 1-4 is used for each switching element of the main conversion circuit 201. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower bridge arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0136] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to the control signals from the control circuit 203 (described later), drive signals that turn the switching elements on and off are output to the control electrodes of each switching element. When the switching element is kept on, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is kept off, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0137] Control circuit 203 controls the switching elements of main conversion circuit 201 to supply the desired power to load 300. Specifically, based on the power to be supplied to load 300, the time (on-time) for each switching element of main conversion circuit 201 to be in the on state is calculated. For example, main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements in accordance with the output voltage. Then, control command (control signal) is output to drive circuit 202 to output on-signal to the switching elements that should be in the on state at each time and off-signal to the switching elements that should be in the off state. Drive circuit 202 outputs on-signal or off-signal as drive signal to the control electrode of each switching element according to the control signal.

[0138] In the power conversion device according to this embodiment, the power semiconductor device of embodiments 1-4 is used as the switching element of the main conversion circuit 201, so that chip damage of the switching element can be suppressed.

[0139] In this embodiment, an example of applying the power semiconductor device of Embodiments 1-4 to a 2-level three-phase inverter has been described. However, the application of the power semiconductor device of Embodiments 1-4 is not limited to this, and it can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but it can also be a 3-level or multi-level power conversion device. When supplying power to a single-phase load, the power semiconductor device of Embodiments 1-4 can also be applied to a single-phase inverter. In addition, when supplying power to DC loads, the power semiconductor device of Embodiments 1-4 can also be applied to DC / DC converters and AC / DC converters.

[0140] Furthermore, the power conversion device using the power semiconductor device of embodiments 1-4 is not limited to the case where the load is an electric motor. For example, it can also be used as a power supply device for electrical discharge machining, laser processing machine, induction heating cooker, contactless power supply system, and power regulator for solar power generation system, energy storage system, etc.

[0141] The preferred embodiments have been described in detail above, but are not limited to the embodiments described above. Various modifications and substitutions can be made to the embodiments described above without departing from the scope of the claims.

[0142] The following is a summary of the various methods of disclosure, as a note.

[0143] (Note 1)

[0144] A power semiconductor device comprising:

[0145] SiC substrate;

[0146] A drift layer of the first conductivity type is formed on the first main surface of the SiC substrate;

[0147] The base region of the second conductivity type is formed on the surface of the drift layer;

[0148] A first conductivity type of impurity region is locally formed on the surface of the base region;

[0149] A trench that extends from the surface of the impurity region through the impurity region and the base region to the interior of the drift layer, having a first sidewall and a second sidewall that are opposite to each other.

[0150] The bottom base region of the second conductivity type is formed in the portion of the drift layer that is in contact with the bottom surface of the trench;

[0151] The second conductivity type sidewall base region is formed in the portion of the drift layer that is in contact with the second sidewall of the trench;

[0152] A gate electrode is formed inside the trench, separated by a gate insulating film;

[0153] Surface electrode, which is in contact with the impurity region; and

[0154] The back electrode is formed on the second main surface, which is opposite to the first main surface of the SiC substrate.

[0155] The angle between the bottom surface of the trench and the first sidewall is greater than the angle between the bottom surface of the trench and the second sidewall.

[0156] The angle between the bottom surface of the trench and the second sidewall is less than 90°.

[0157] (Note 2)

[0158] According to the power semiconductor device described in Note 1, wherein,

[0159] The gate insulating film has:

[0160] A first gate insulating film is buried within the trench, extending to a height lower than the lower surface of the base region; and

[0161] A second gate insulating film is formed after the first gate insulating film and covers the sidewalls of the trench on the first gate insulating film.

[0162] (Note 3)

[0163] According to the power semiconductor device described in Note 1 or 2, the bottom surface of the trench is composed of two surfaces with different slopes.

[0164] (Note 4)

[0165] The power semiconductor device according to any one of Notes 1 to 3, wherein,

[0166] The bottom surface of the trench is curved.

[0167] The angle between the tangent of the gate oxide film and the first sidewall at the point where the dividing line closest to the first sidewall intersects the bottom surface of the trench (the third angle) is greater than the angle between the tangent of the gate oxide film and the second sidewall (the fourth angle).

[0168] The fourth angle is less than 90°.

[0169] (Note 5)

[0170] A power conversion device comprising:

[0171] The main conversion circuit has a power semiconductor device as described in any one of Notes 1 to 4, which converts the input power and outputs it.

[0172] A driving circuit that outputs a driving signal to the semiconductor device to drive the semiconductor device; and

[0173] The control circuit outputs control signals to the drive circuit to control the drive circuit.

[0174] (Note 6)

[0175] A method for manufacturing a semiconductor device for power applications, wherein,

[0176] (a) A drift layer of a first conductivity type is formed on the first main surface of a SiC substrate;

[0177] (b) A base region of a second conductivity type is formed on the surface of the drift layer;

[0178] (c) A first conductivity type impurity region is formed locally on the surface layer of the base region;

[0179] (d) A trench is formed by penetrating the impurity region from the surface of the impurity region to the interior of the drift layer, having a first sidewall and a second sidewall that are opposite to each other.

[0180] (e) A bottom base region of a second conductivity type is formed in the portion of the drift layer that is in contact with the bottom surface of the trench;

[0181] (f) After step (e), ion implantation is performed in the trench in a direction inclined from the depth direction of the trench toward the second sidewall side, thereby forming a second conductivity type sidewall base region in the region of the drift layer in contact with the second sidewall, and increasing the concentration of the second conductivity type impurity in the upper surface of the bottom base region from the second sidewall side toward the first sidewall side.

[0182] (g) A thermal oxidation film with increasing thickness from the second sidewall side to the first sidewall side is formed on the bottom surface of the trench by thermal oxidation treatment;

[0183] (h) After removing the thermal oxide film, a gate insulating film is formed in the trench;

[0184] (i) A gate electrode is formed inside the trench, with the gate insulating film in between;

[0185] (j) Forming a surface electrode in contact with the impurity region;

[0186] (k) A back electrode is formed on the second main surface, which is opposite to the first main surface, of the SiC substrate.

[0187] (Note 7)

[0188] According to the method for manufacturing a power semiconductor device as described in Note 6, the angle α between the ion implantation direction and the depth direction of the trench in step (f) satisfies 0° < α.

[0189] (Note 8)

[0190] According to the manufacturing method of the power semiconductor device described in Note 6 or 7, wherein,

[0191] The gate insulating film includes a first gate insulating film and a second gate insulating film, and the process (h) includes:

[0192] (h1) The process of filling the trench using the first gate insulating film;

[0193] (h2) The step of etching back the first gate insulating film to position the upper surface of the first gate insulating film below the lower surface of the base region; and

[0194] (h3) A step after step (h2) to form the second gate insulating film on the first gate insulating film and the sidewall of the trench.

[0195] (Note 9)

[0196] The method for manufacturing a power semiconductor device according to any one of Notes 6 to 8, wherein,

[0197] The ion implantation in step (f) includes:

[0198] The first ion implantation uses a first resist mask covering the second sidewall side within the trench; and

[0199] The second ion implantation uses a second resist mask covering the first sidewall side of the trench that was not covered by the first resist mask.

[0200] Symbol Explanation

[0201] 1 SiC substrate, 2 Drift layer, 3 Base region, 4 Source region, 5 Bottom base region, 6 Sidewall base region, 7 Gate insulating film, 8 Gate electrode, 9 Interlayer insulating film, 10 Source electrode, 11 Drain electrode, 12, 13 Resist mask, 14 Oxide film, 16 First resist mask, 17 Second resist mask, 20 Trench, 21 First sidewall, 22 Second sidewall, 50 Semiconductor substrate, 71 First gate insulating film, 72 Second gate insulating film, S1, S11 First main surface, S2, S12 Second main surface.

Claims

1. A power semiconductor device comprising: a SiC substrate; a drift layer of a first conductivity type formed on a first main surface of the SiC substrate; a base region of a second conductivity type formed on a surface layer of the drift layer; an impurity region of the first conductivity type formed partially on a surface layer of the base region; a trench passing through the impurity region and the base region from a surface of the impurity region to an inside of the drift layer, having a first sidewall and a second sidewall facing each other; a bottom base region of the second conductivity type formed in a portion of the drift layer facing a bottom surface of the trench; a sidewall base region of the second conductivity type formed in a portion of the drift layer facing the second sidewall of the trench; a gate electrode formed in the inside of the trench through a gate insulating film; a surface electrode in contact with the impurity region; and a back surface electrode formed on a second main surface of the SiC substrate opposite to the first main surface, an angle of the bottom surface of the trench and the first sidewall is larger than an angle of the bottom surface of the trench and the second sidewall, and the angle of the bottom surface of the trench and the second sidewall is smaller than 90°.

2. The power semiconductor device according to claim 1, wherein the gate insulating film has: a first gate insulating film buried in the trench up to a level lower than a lower surface of the base region; and a second gate insulating film formed after the first gate insulating film, covering sidewalls of the trench on the first gate insulating film, the bottom surface of the trench is composed of two surfaces having different slopes.

4. The power semiconductor device according to claim 1, wherein the bottom surface of the trench is curved, a tangent line of the gate insulating film at a point where a division line equally dividing the trench into four in a lateral direction intersects the bottom surface of the trench is closer to the first sidewall, a third angle formed by the tangent line of the gate insulating film and the first sidewall is larger than a fourth angle formed by the tangent line of the gate insulating film and the second sidewall, and the fourth angle is smaller than 90°.

5. A power conversion device comprising: a main conversion circuit having the power semiconductor device according to claim 1, converting input power and outputting; a drive circuit outputting a drive signal for driving the semiconductor device to the semiconductor device; and a control circuit outputting a control signal for controlling the drive circuit to the drive circuit.

6. A method of manufacturing a power semiconductor device, comprising: (a) forming a drift layer of a first conductivity type on a first main surface of a SiC substrate; (b) forming a base region of a second conductivity type on a surface layer of the drift layer; (c) forming an impurity region of the first conductivity type partially on a surface layer of the base region; (d) forming a trench having a first sidewall and a second sidewall facing each other by passing through the impurity region from a surface of the impurity region to an inside of the drift layer; (e) forming a bottom base region of the second conductivity type in a portion of the drift layer facing a bottom surface of the trench; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 3. The power semiconductor device according to claim 1, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ (f) after the step (e), performing ion implantation in the trench in a direction inclined from a depth direction of the trench toward the second side wall side, thereby forming a side wall base region of the second conductivity type in a region of the drift layer which is in contact with the second side wall, and increasing a second conductivity type impurity concentration in an upper surface of the bottom base region from the second side wall side toward the first side wall side; (g) forming a thermal oxidation film which is thicker from the second side wall side to the first side wall side, by a thermal oxidation treatment on a bottom surface of the trench; (h) after removing the thermal oxidation film, forming a gate insulating film in the trench; (i) forming a gate electrode in an inside of the trench through the gate insulating film; (j) forming a surface electrode in contact with the impurity region; (k) forming a back surface electrode on a main surface of the SiC substrate which is opposite to the first main surface, i.e., a second main surface.

7. The method of manufacturing a power semiconductor device according to claim 6, wherein an angle a of the ion implantation direction in the step (f) with respect to the depth direction of the trench satisfies 0° < a.

8. The method of manufacturing a power semiconductor device according to claim 6, wherein the gate insulating film includes a first gate insulating film and a second gate insulating film, the step (h) includes: (hl) a step of filling the trench with the first gate insulating film; (h2) a step of performing etch-back on the first gate insulating film so that an upper surface of the first gate insulating film is located at a position lower than a lower surface of the base region; and (h3) a step of forming the second gate insulating film on the first gate insulating film and on a side wall of the trench after the step (h2).

9. The method of manufacturing a power semiconductor device according to claim 6, wherein the ion implantation in the step (f) includes: first ion implantation using a first resist mask which covers the second side wall side in the trench; and second ion implantation using a second resist mask which covers the first side wall side in the trench which is not covered by the first resist mask.

Images