Stacked transistor with dielectric insulating layer

Abstract

A semiconductor structure includes a first stacked device having a first field effect transistor including one or more first nanosheet layers, a second field effect transistor including one or more second nanosheet layers; and a first dielectric insulating layer between the first field effect transistor and the second field effect transistor, the first dielectric insulating layer having a first width. The semiconductor structure also includes a second stacked device adjacent to the first stacked device. The second stacked device has a third field effect transistor comprising one or more third nanosheet layers, a fourth field effect transistor comprising one or more fourth nanosheet layers, and a second dielectric insulating layer between the third field effect transistor and the fourth field effect transistor. The second dielectric insulating layer has a second width less than the first width of the first dielectric insulating layer.

Description

Background Technology

[0001] A field-effect transistor (FET) is a transistor with a source, a gate, and a drain. Its operation depends on the flow of charge carriers (electrons or holes) along a channel extending between the source and drain. The current through the channel between the source and drain can be controlled by a lateral electric field below the gate. FETs are widely used for switching, amplification, filtering, and other tasks. Summary of the Invention

[0002] The illustrative embodiments of this disclosure include techniques for semiconductor manufacturing. In one illustrative embodiment, a semiconductor structure includes a first stacked device comprising: a first field-effect transistor (FET) including one or more first nanosheet layers; a second FET vertically stacked above the first FET, the second FET including one or more second nanosheet layers; and a first dielectric insulating layer located between the first and second FETs, the first dielectric insulating layer having a first width. The semiconductor structure also includes a second stacked device adjacent to the first stacked device. The second stacked device includes: a third FET including one or more third nanosheet layers; a fourth FET vertically stacked above the third FET, the fourth FET including one or more fourth nanosheet layers; and a second dielectric insulating layer located between the third and fourth FETs. The second dielectric insulating layer has a second width smaller than the first width of the first dielectric insulating layer.

[0003] The semiconductor structure of the illustrative embodiment advantageously allows the formation of a first dielectric insulating layer for a first stacked device, the width of which differs from the second dielectric insulating layer of a second stacked device adjacent to the first stacked device, thereby resulting in shared gate integration and independent gate devices.

[0004] In one or more other illustrative embodiments that may be combined with the foregoing paragraphs, the first width of the first dielectric insulating layer is equal to the third width of one or more second nanosheet layers, and the second width of the second dielectric insulating layer is equal to the fourth width of one or more third nanosheet layers.

[0005] In one or more other exemplary embodiments that may be combined with the foregoing paragraphs, the semiconductor structure further includes a third dielectric insulating layer disposed on the bottom surface of the first stacked device and a fourth dielectric insulating layer disposed on the bottom surface of the second stacked device.

[0006] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the first stacked device and the second stacked device are separated by isolation dielectric pillars.

[0007] In one or more additional exemplary embodiments, as may be combined with the foregoing paragraphs, the first field-effect transistor further includes a first gate structure, and the second field-effect transistor further includes a second gate structure separated from the first gate structure by a first dielectric insulating layer.

[0008] In one or more other exemplary embodiments, as may be combined with the foregoing paragraphs, the semiconductor structure further includes a first front gate contact connected to the first gate structure and the front-side back-end process layer.

[0009] In one or more other exemplary embodiments, as may be combined with the foregoing paragraphs, the semiconductor structure further includes a back-side gate contact connected to the second gate structure and the back-side back-end process layer.

[0010] In one or more additional exemplary embodiments, as may be combined with the foregoing paragraphs, the second stacked device further includes a third gate structure disposed above the third field-effect transistor and the fourth field-effect transistor.

[0011] In one or more other exemplary embodiments, as may be combined with the foregoing paragraphs, the semiconductor structure further includes a second front gate contact connected to the third gate structure and the front-side back-end process layer.

[0012] In another illustrative embodiment, the semiconductor structure includes a first stacked device structure comprising a first field-effect transistor (FET) configured to include a first source / drain region, and a second FET vertically stacked above the first FET, the second FET including a second source / drain region. The first stacked device structure also includes a first portion of the sidewall of the second source / drain region and a front-side source / drain contact on the top surface, and a first metal via connecting the front-side source / drain contact and a first back-side power line. The semiconductor structure also includes a second stacked device structure adjacent to the first stacked device structure. The second stacked device structure includes a third FET and a fourth FET, the third FET including a third source / drain region, and the fourth FET vertically stacked above the third FET, the fourth FET including a fourth source / drain region. The second stacked device structure also includes a second portion of the sidewall of the third source / drain region and a first back-side source / drain contact on the bottom surface, and a second metal via connecting the first back-side source / drain contact and a back-end process layer.

[0013] The semiconductor structure of the illustrative embodiment advantageously allows the formation of a first dielectric insulating layer for a first stacked device, the width of which differs from the second dielectric insulating layer of a second stacked device adjacent to the first stacked device, thereby resulting in shared gate integration and independent gate devices.

[0014] In one or more additional exemplary embodiments, as may be combined with the foregoing paragraphs, the third gate structure is a shared gate structure between the third stacked device and the fourth stacked device.

[0015] In one or more other exemplary embodiments, as may be combined with the foregoing paragraphs, the semiconductor structure further includes a first front gate contact connected to the third gate structure and the front-side back-end process layer.

[0016] In one or more other exemplary embodiments, as may be combined with the foregoing paragraphs, the semiconductor structure further includes a second front gate contact connected to the first gate structure and the front-side back-end process layer.

[0017] In one or more other exemplary embodiments, as may be combined with the foregoing paragraphs, the semiconductor structure further includes a back-side gate contact connected to the second gate structure and the back-side back-end process layer.

[0018] In one or more other illustrative embodiments, as may be combined with the foregoing paragraphs, the first dielectric insulating layer has a first width, and the second dielectric insulating layer has a second width that is smaller than the first width of the first dielectric insulating layer.

[0019] In one or more additional illustrative embodiments, as may be combined with the preceding paragraphs, the first stacked device and the second stacked device are separated by isolation dielectric pillars.

[0020] Another exemplary embodiment includes an integrated circuit comprising one or more semiconductor structures. At least one of the one or more semiconductor structures is a semiconductor structure according to one or more of the foregoing embodiments.

[0021] These and other exemplary embodiments will be described or become apparent in the following detailed description of exemplary embodiments, which will be read in conjunction with the accompanying drawings. Attached Figure Description

[0022] Exemplary embodiments will now be described in more detail with reference to the accompanying drawings, in which:

[0023] Figure 1A This is a top view illustrating a semiconductor structure for use in a first intermediate manufacturing stage according to an illustrative embodiment.

[0024] Figure 1B According to the illustrative embodiment, in the first intermediate manufacturing stage along Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0025] Figure 1C According to the illustrative embodiment, in the first intermediate manufacturing stage along Figure 1AA cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0026] Figure 1D According to the illustrative embodiment, in the first intermediate manufacturing stage along Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0027] Figure 2A According to the illustrative embodiment, in the second intermediate manufacturing stage along Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0028] Figure 2B According to the illustrative embodiment, in the second intermediate manufacturing stage along Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0029] Figure 2C According to the illustrative embodiment, in the second intermediate manufacturing stage along Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0030] Figure 3A It is shown, according to an illustrative embodiment, along the third intermediate manufacturing stage Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0031] Figure 3B The illustrative embodiment illustrates the process along the third intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0032] Figure 3C The illustrative embodiment illustrates the process along the third intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0033] Figure 4A It is shown, according to an illustrative embodiment, along the fourth intermediate manufacturing stage Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0034] Figure 4B The illustrative embodiment illustrates the process along the fourth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0035] Figure 4C The illustrative embodiment illustrates the process along the fourth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0036] Figure 5AIt is shown, according to an illustrative embodiment, along the fifth intermediate manufacturing stage Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0037] Figure 5B The illustrative embodiment illustrates the process along the fifth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0038] Figure 5C The illustrative embodiment illustrates the process along the fifth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0039] Figure 6A According to the illustrative embodiment, in the sixth intermediate manufacturing stage along Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0040] Figure 6B It is along the sixth intermediate manufacturing stage according to the illustrative embodiment. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0041] Figure 6C It is along the sixth intermediate manufacturing stage according to the illustrative embodiment. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0042] Figure 7A The illustrative embodiment illustrates the process along the seventh intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0043] Figure 7B The illustrative embodiment illustrates the process along the seventh intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0044] Figure 7C The illustrative embodiment illustrates the process along the seventh intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0045] Figure 8A It is along the eighth intermediate manufacturing stage according to the illustrative embodiment. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0046] Figure 8B It is along the eighth intermediate manufacturing stage according to the illustrative embodiment. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0047] Figure 8C It is along the eighth intermediate manufacturing stage according to the illustrative embodiment. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0048] Figure 9A This is illustrated according to an illustrative embodiment, showing the process along the ninth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0049] Figure 9B The illustrative embodiment illustrates the process along the ninth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0050] Figure 9C The illustrative embodiment illustrates the process along the ninth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0051] Figure 10A The illustrative embodiment illustrates the process along the tenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0052] Figure 10B The illustrative embodiment illustrates the process along the tenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0053] Figure 10C The illustrative embodiment illustrates the process along the tenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0054] Figure 11A It is shown, according to an illustrative embodiment, along the eleventh intermediate manufacturing stage Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0055] Figure 11B The illustrative embodiment illustrates the process along the eleventh intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0056] Figure 11C The illustrative embodiment illustrates the process along the eleventh intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0057] Figure 12A It is shown, according to an illustrative embodiment, along the twelfth intermediate manufacturing stage Figure 1AA cross-sectional view of the semiconductor structure taken along the XX axis.

[0058] Figure 12B The illustrative embodiment illustrates the process along the twelfth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0059] Figure 12C The illustrative embodiment illustrates the process along the twelfth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0060] Figure 13A The illustrative embodiment illustrates the process at the thirteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0061] Figure 13B The illustrative embodiment illustrates the process along the thirteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0062] Figure 13C The illustrative embodiment illustrates the process along the thirteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0063] Figure 14A The illustrative embodiment illustrates the process at the fourteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0064] Figure 14B The illustrative embodiment illustrates the process along the fourteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0065] Figure 14C The illustrative embodiment illustrates the process along the fourteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0066] Figure 15A The illustrative embodiment illustrates the process at the fifteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0067] Figure 15B The illustrative embodiment illustrates the process along the fifteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0068] Figure 15C The illustrative embodiment illustrates the process along the fifteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0069] Figure 16A The illustrative embodiment illustrates the process at the sixteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0070] Figure 16B The illustrative embodiment illustrates the process along the sixteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0071] Figure 16C The illustrative embodiment illustrates the process along the sixteenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis.

[0072] Figure 17A This is an example illustrating the process at the seventeenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the XX axis.

[0073] Figure 17B The illustrative embodiment illustrates the process along the seventeenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y1-Y1 axis.

[0074] Figure 17C The illustrative embodiment illustrates the process along the seventeenth intermediate manufacturing stage. Figure 1A A cross-sectional view of the semiconductor structure taken along the Y2-Y2 axis. Detailed Implementation

[0075] Exemplary embodiments of the present invention may be described in the context of exemplary methods for forming a first dielectric insulating layer of a first stacked device, the width of which differs from a second dielectric insulating layer of a second stacked device adjacent to the first stacked device, thereby producing shared gate integration and independent gate devices, as well as exemplary apparatus, structures, and devices formed using such methods. However, it should be understood that embodiments of the present invention are not limited to the illustrative methods, apparatus, structures, and devices, but are more broadly applicable to other suitable methods, apparatus, structures, and devices.

[0076] It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic diagrams not drawn to scale. Furthermore, for ease of interpretation, one or more layers, structures, and regions of the type typically used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown have been omitted from an actual semiconductor structure.

[0077] Furthermore, the same or similar reference numerals are used throughout the accompanying drawings to denote the same or similar features, elements, or structures; therefore, detailed descriptions of the same or similar features, elements, or structures will not be repeated for each drawing. Additionally, the terms "exemplary" and "illustrative" as used herein mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" or "illustrative" should not be construed as preferred or advantageous over other embodiments or designs.

[0078] Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, regarding semiconductor processing steps, it is emphasized that the description provided herein is not intended to cover all processing steps that may be necessary to form a functional semiconductor integrated circuit device. Rather, for the sake of economics, certain processing steps commonly used to form semiconductor devices, such as wet cleaning and annealing steps, are not intentionally described herein. It should be understood that, as used herein, the terms “about” or “substantially” with respect to thickness, width, percentage, range, etc., are intended to indicate approximation or approximation, but are not precise. For example, the terms “about” or “substantially” as used herein mean that a small margin of error may exist, such as 1% or less than the stated amount.

[0079] References to the principles of this specification as "one embodiment" or "embodiment" and other variations thereof mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment of the principles. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as the appearance of any other variations, do not necessarily refer to the same embodiment. The term "located on..." means that a first element (e.g., a first structure) is present on a second element (e.g., a second structure), wherein an intermediate element (e.g., an interface structure, such as an interface layer) may be present between the first and second elements. The term "direct contact" means that the first element (such as a first structure) and the second element (such as a second structure) are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0080] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the scope of this concept, the first element discussed below may be referred to as the second element.

[0081] As used herein, “height” refers to the vertical dimension of an element (e.g., layer, trench, hole, opening, etc.) in a cross-sectional view, measured from the bottom surface of the element to the top surface, and / or relative to the surface on which the element is situated. Conversely, “depth” refers to the vertical dimension of an element (e.g., layer, trench, hole, opening, etc.) in a cross-sectional view, measured from the top surface of the element to the bottom surface. Where indicated, terms such as “thickness,” “thickness,” “thin,” or their derivatives may be used instead of “height.”

[0082] As used herein, “width” or “length” refers to the dimension of a component (e.g., layer, trench, hole, opening, etc.) in a drawing, measured from the side of the component to the opposite surface. Terms such as “thickness,” “thickness,” “thin,” or their derivatives may be used instead of the indicated “width” or “length.”

[0083] In the IC chip manufacturing industry, there are three segments typically mentioned in IC chip construction: front-end process (FEOL), back-end process (BEOL), and the segment connecting these two—middle-end process (MOL). FEOL consists of semiconductor devices (e.g., transistors), BEOL consists of interconnects and wiring, and MOL is the interconnect between FEOL and BEOL, which includes materials to prevent BEOL metal from diffusing into FEOL devices. Therefore, the illustrative embodiments described herein may relate to BEOL semiconductor processing and structure. BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. Contacts (pads), interconnects, vias, and dielectric structures are formed in the BEOL, representing some of the manufacturing stages. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0084] The embodiments described below can be applied to FEOL processing and structure, BEOL processing and structure, or both FEOL and BEOL processing and structure. Specifically, although an exemplary processing scheme can be illustrated using an FEOL processing scenario, such a method can also be applied to BEOL processing. Similarly, although an exemplary processing scheme can be illustrated using a BEOL processing scenario, such a method can also be applied to FEOL processing.

[0085] Current stacked FETs utilize a dielectric insulating layer of uniform width between transistors. Therefore, current stacked FETs do not allow for both shared gate integration and independent gate devices. Consequently, there is a need to form stacked FETs that do not suffer from the aforementioned drawbacks. Therefore, the non-limiting illustrative embodiments described herein overcome the drawbacks discussed above by forming a first dielectric insulating layer of the first stacked device having a different width than the second dielectric insulating layer of the second stacked device adjacent to the first stacked device, to allow for both shared gate integration and independent gate devices.

[0086] Now for reference Figure 1A-17C , Figure 1A A top view of the semiconductor structure 100 is shown. Figure 1B The first side sectional view is along Figure 1A The line XX in the top view is used to cut off the view. Figure 1C The second side section view is along Figure 1A The line Y1-Y1 in the top view is used as the cutoff point, and Figure 1D The third side sectional view is along Figure 1A The line Y2-Y2 is used to cut the view from the top.

[0087] Semiconductor structure 100 shows a substrate 102. The substrate 102 can be formed of any suitable semiconductor structure, including various silicon-containing materials, including but not limited to silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and their multilayers. Although silicon is the primary semiconductor material used in wafer fabrication, alternative semiconductor materials can be used as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), etc. In one illustrative embodiment, the substrate 102 is silicon.

[0088] An etch stop layer 104 is formed in the substrate 102. The etch stop layer 104 may include a buried oxide (BOX) layer or silicon germanium (SiGe), or another suitable material, such as a III-V semiconductor epitaxial layer.

[0089] Nanosheet stacks 116-1 and 116-2 are formed on the substrate 102, and each nanosheet stack contains nanosheet devices 112-1 and 112-2. Nanosheet devices 112-1 and 112-2 include sacrificial layers 106-1 and 106-2 (collectively referred to as sacrificial layer 106), sacrificial layers 108-1 and 108-2 (collectively referred to as sacrificial layer 108), and nanosheet channel layers 110-1 and 110-2 (collectively referred to as nanosheet channel layer 110).

[0090] Sacrificial layers 106 and 108 are illustratively formed of different sacrificial materials, allowing them to be selectively etched or otherwise removed from each other. In some embodiments, both sacrificial layers 106 and 108 are formed of SiGe, but with different percentages of Ge. For example, sacrificial layer 106 may have a relatively high percentage of Ge (e.g., 55% Ge), and sacrificial layer 108 may have a relatively low percentage of Ge (e.g., 25% Ge). Other combinations of different sacrificial materials may be used in other embodiments.

[0091] In a non-limiting illustrative embodiment, the nanosheet channel layer 110-1 has a first width, and the nanosheet channel layer 110-2 has a second width smaller than the first width (see [link]). Figure 1C and 1D ).

[0092] The nanosheet channel layer 110 can be formed of Si or another suitable material (e.g., a material similar to that used for the substrate 102).

[0093] Nanosheet stacks 116-1 and 116-2 are formed by depositing a hard mask (HM) layer 114 followed by photolithography and etching. The HM layer 114 may consist of a multilayer of silicon nitride (SiN), SiN and SiO2, or another suitable material.

[0094] Figure 2A-2C Semiconductor structure 100 in a second intermediate manufacturing stage is shown. During this stage, a mask layer 118 (such as an organic planarization layer (OPL) or spin-coated carbon (SOC)) is deposited on semiconductor structure 100 using any conventional deposition process such as spin coating or any other suitable deposition process. Next, mask layer 118 is patterned and then selectively etched using, for example, reactive ion etching (RIE) to remove exposed portions of sacrificial layer 106-2 of nanosheet stack 116-2.

[0095] Figures 3A-3C A semiconductor structure 100 is shown in the third intermediate manufacturing stage. During this stage, the mask layer 118 is removed using any conventional technique such as ashing. Next, as... Figure 3B and 3CAs shown, an isolation dielectric pillar 120 is formed by first depositing a dielectric material over a semiconductor structure 100 using any conventional deposition technique, such as physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. Then, an etch-back process, such as wet etching, is performed to remove the dielectric material from the semiconductor structure 100, leaving the isolation dielectric pillar 120 between the nanosheet stacks 116-1 and 116-2. Suitable dielectric materials include, for example, SiN, SiO2, SiOC, SiOCN, SiBCN, SiC, etc.

[0096] Figures 4A-4C A semiconductor structure 100 in a fourth intermediate manufacturing stage is shown. During this stage, shallow trench isolation (STI) regions 122 can be formed on a substrate 102. STI regions 122 comprise a dielectric material such as silicon oxide or silicon oxynitride and are formed using methods known in the art. For example, in one illustrative embodiment, STI region 122 is a shallow trench isolation oxide layer. The HM layer 114 can then be removed using any suitable etching technique.

[0097] Figures 5A-5C A semiconductor structure 100 in the fifth intermediate manufacturing stage is shown. During this stage, a dummy gate 124 can be filled over the structure, followed by patterning using a gate hard mask (HM) layer 126. Figure 5A and Figure 5C As shown, the dummy gate 124 can be formed by blanket deposition of a dummy gate material (e.g., amorphous silicon (a-Si) or amorphous silicon germanium (a-SiGe) or another suitable material above a thin SiO2 or titanium nitride (TiN) layer) and a material of the gate HM layer 126 (e.g., a multilayer of silicon nitride (SiN), SiN and SiO2 or another suitable material), followed by photolithography to produce a patterned gate HM layer 126 and a dummy gate 124 below.

[0098] Figures 6A-6C The semiconductor structure 100 is shown in the sixth intermediate manufacturing stage. During this stage, the sacrificial layer 106 is removed using any suitable selective etching process. For example, sacrificial layer 106-1 may be removed first to form opening 128, and then sacrificial layer 106-2 may be removed to form opening 130.

[0099] Figures 7A-7CA semiconductor structure 100 in the seventh intermediate manufacturing stage is shown. During this stage, a bottom dielectric insulator (BDI) layer 132-1, an intermediate dielectric insulator (MDI) layer 132-2, and sidewall spacers 134 are formed. The BDI layer 132-1 and the MDI layer 132-2 (collectively referred to as dielectric insulating layer 132) can be formed from any suitable insulator or dielectric material, such as SiN, silicon boron carbonitride (SiBCN), silicon carbonitride oxycarbonitride (SiOCN), etc. The BDI layer 132-1 is formed in the region previously occupied by the sacrificial layer 106-1, and the MDI layer 132-2 is formed in the region previously occupied by the sacrificial layer 106-2, and can have similar dimensions to the sacrificial layer.

[0100] In a non-limiting illustrative embodiment, the MDI layer 132-2 between the nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-1 is formed with a first width, while the MDI layer 132-2 between the nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-2 is formed with a second width smaller than the first width, as shown below. Figure 7C As shown. In an illustrative embodiment, the first width of the MDI layer 132-2 between nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-1 is the same as the width of the nanosheet channel layer 110-1 of the nanosheet device 112-1, and the second width of the MDI layer 132-2 between nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-2 is the same as the width of the nanosheet channel layer 110-2 of the nanosheet device 112-2.

[0101] The sidewall spacer 134 may be formed of a material similar to that of the BDI layer 132-1. In one embodiment, the sidewall spacer 134 is formed of the same insulator or dielectric material (e.g., SiN or SiBCN) as the BDI layer 132-1.

[0102] Figures 8A-8C Semiconductor structure 100 at the eighth intermediate manufacturing stage is shown. During this stage, a bottom source / drain region 136, a bottom interlayer dielectric (ILD) layer 138, a top source / drain region 140, a top ILD layer 142, and an internal spacer 144 are formed. In the illustrative embodiment, the bottom source / drain region 136 is first formed on a substrate 102, followed by the deposition of the bottom ILD layer 138 on the bottom source / drain region 136 and the STI region 122, then the top source / drain region 140 is formed, followed by the deposition of the top ILD layer 142 on the top source / drain region 140, the bottom ILD layer 138, and over the isolation dielectric pillar 120, followed by polysilicon aperture CMP to expose the dummy gate 124.

[0103] The bottom source / drain region 136 and the top source / drain region 140 can be formed using epitaxial growth processes. The bottom source / drain region 136 and the top source / drain region 140 can be appropriately doped, such as using ion implantation, vapor phase doping, plasma doping, plasma immersion ion implantation, cluster doping, implantation doping, liquid phase doping, solid phase doping, etc. The N-type dopant can be selected from the group consisting of phosphorus (P), arsenic (As), and antimony (Sb), and the P-type dopant can be selected from the group consisting of boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (Tl). In some embodiments, the epitaxial process includes in-situ doping (incorporating the dopant into the epitaxial material during epitaxy).

[0104] Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), low-pressure chemical vapor deposition (LPCVD), finite-reaction process CVD (LRPCVD), or other suitable processes. Epitaxial silicon, silicon-germanium (SiGe), germanium (Ge), and / or carbon-doped silicon (Si:C) can be doped during deposition by adding dopants (in-situ doping), such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor to be formed. The dopant concentration in the source / drain regions can be as high as 1 x 10¹⁹ cm⁻¹. -3 Up to 3x1021cm -3 Within the range, or preferably within 2x1020cm -3 Up to 3x1021cm -3 between.

[0105] The bottom ILD layer 138 and the top ILD layer 142 can be independently formed from any suitable insulating material, such as SiO2, SiOC, SiON, etc.

[0106] Internal spacers 144 can be formed to fill recessed spaces (e.g., created by recessed etching of sacrificial layer 108 before removal of sacrificial layer 108). Internal spacers 144 can be formed of silicon nitride (SiN) or another suitable material (such as SiBCN, silicon oxycarbide (SiCO), SiOCN, etc.).

[0107] Figures 9A-9CA semiconductor structure 100 at a ninth intermediate manufacturing stage is shown. During this stage, the dummy gate 124 and sacrificial layer 108 are removed, followed by the formation of a replacement gate 146 (e.g., using a replacement HKMG process). The replacement gate 146 includes a gate stack layer that may include a gate dielectric layer and a gate conductor layer. The gate dielectric layer may be formed of a high-k dielectric material. Examples of high-k materials include, but are not limited to, metal oxides such as HfO2, hafnium silicon oxide (Hf-Si-O), hafnium silicon nitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon nitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. High-k materials can also include dopants such as lanthanum (La), aluminum (Al), and magnesium (Mg). The gate dielectric layer can have a uniform thickness ranging from 1 nm to 3 nm.

[0108] The gate conductor layer may include a metal gate or a work function metal (WFM). The WFM used for the gate conductor layer may be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), combinations of Ti and Al alloys, including barrier layers (e.g., TiN, TaN, etc.), and subsequent stacks of one or more of the above WFM materials. It should be understood that various other materials may be used for the gate conductor layer as needed.

[0109] Figures 10A-10C The semiconductor structure 100 is shown in the tenth intermediate manufacturing stage. During this stage, a first gate dicing is performed by replacing the gate 146 to expose a portion of the STI region 122 (see [link]). Figure 10C Gate dicing is performed using standard photolithography and etching processes (such as RIE).

[0110] Figure 11A-11C Semiconductor structure 100 at the eleventh intermediate manufacturing stage is shown. In this stage, a second gate dicing is performed by replacing the gate 146 to expose a portion of the MDI layer 132-2 between nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-1, leaving the MDI layer 132-2 between nanosheet devices 112-1 and 112-2 of the nanosheet stack 116-2 within the replaced gate 146. (See also...) Figure 11C Gate dicing is performed using standard photolithography and etching processes (such as RIE).

[0111] Figures 12A-12CSemiconductor structure 100 is shown in the twelfth intermediate manufacturing stage. During this stage, dielectric filler 148 is deposited in the opening, followed by a planarization process, such as CMP. The dielectric filler 148 is deposited using any conventional deposition technique such as PVD, ALD, CVD, etc. Suitable dielectric materials for the dielectric filler 148 include, for example, SiO2.

[0112] Figures 13A-13C A semiconductor structure 100 at the thirteenth intermediate manufacturing stage is shown. During this stage, a front-side top source / drain contact 150, a front-side bottom source / drain contact 152, and a front-side gate contact 154 are formed. For example, in an illustrative embodiment, the top source / drain contact opening and the bottom source / drain contact opening are formed by first depositing a mask layer on the semiconductor structure 100, and then using conventional photolithography and etching processes such as RIE in at least one mask layer. Next, a high-conductivity metal is deposited in the top source / drain contact opening and the bottom source / drain contact opening to form the corresponding front-side top source / drain contact 150 and front-side bottom source / drain contact 152. Suitable high-conductivity metals may comprise, for example, a silicide liner (such as Ti, Ni, NiPt), followed by a binder metal liner (such as TiN) and a metal filler material (such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), or any other suitable conductive material). In various embodiments, the high-conductivity metal can be deposited by ALD, CVD, PVD, and / or electroplating. The high-conductivity metal can be planarized using, for example, planarization processes (such as CMP). Other planarization processes may include grinding and polishing.

[0113] The front gate contact 154 can be formed in at least the top ILD layer 142 using conventional photolithography and etching processes, followed by deposition of a highly conductive metal as described above. The highly conductive metal can be planarized using, for example, a planarization process (such as CMP). Other planarization processes may include grinding and polishing.

[0114] Next, a front-side back-end (BEOL) structure 156 is formed on the semiconductor structure 100, and then this structure (e.g., front-side BEOL structure 156) is bonded to a carrier wafer 1158. The front-side BEOL structure 156 includes various BEOL interconnect structures. The carrier wafer 158 may be formed of a material similar to that of the substrate 102 and may be formed over the front-side BEOL structure 156 using wafer bonding processes such as dielectric-dielectric bonding.

[0115] Figures 14A-14CSemiconductor structure 100 is shown in the fourteenth intermediate manufacturing stage. During this stage, portions of substrate 102 can be removed from the back side using, for example, substrate grinding, CMP, and wet etching, to selectively remove substrate 102 until the etch stop layer 104 is reached. This can be achieved, for example, by flipping semiconductor structure 100 using carrier wafer 158 such that the back side (i.e., back surface) of substrate 102 faces upward.

[0116] Figures 15A-15C A semiconductor structure 100 at the fifteenth intermediate manufacturing stage is shown. During this stage, an etch stop layer 104 is selectively removed using, for example, wet etching, until the substrate 102 is reached. The remaining portion of the substrate 102 is then removed to expose the BDI layer 132-1, the isolation dielectric pillar 120, the STI region 122, and the bottom source / drain region 136. The remaining portion of the substrate 102 can be removed using a selective etching process such as wet etching.

[0117] Figures 16A-16C A semiconductor structure 100 at the sixteenth intermediate manufacturing stage is shown. During this stage, a back-side ILD layer 160, a back-side source / drain contact 162, and a back-side gate contact 164 are formed. The back-side ILD layer 160 can be formed from a similar material and using a similar process to the bottom ILD layer 138. The material of the back-side ILD layer 160 can initially be overfilled and then planarized (e.g., using CMP).

[0118] Next, the back-side source / drain contact 162 can be formed, for example, by first depositing a mask layer on the semiconductor structure 100, and then forming source / drain contact openings in the back-side ILD layer 160 using conventional photolithography and etching processes (such as RIE) in at least one mask layer. Next, a high-conductivity metal is deposited in the source / drain contact openings to form the corresponding back-side source / drain contact 162. Suitable conductive metals can be any metal discussed above. High-conductivity metals can be planarized using, for example, planarization processes (such as CMP). Other planarization processes may include grinding and polishing.

[0119] The back-side gate contact 164 can be formed in at least the back-side ILD layer 160 using conventional photolithography and etching processes, followed by deposition of a highly conductive metal as described above. The highly conductive metal can be planarized using, for example, a planarization process (such as CMP). Other planarization processes may include grinding and polishing.

[0120] Figures 17A-17CSemiconductor structure 100 at the seventeenth intermediate manufacturing stage is shown. During this stage, a back-side back-end process (BEOL) structure 166 is formed on the semiconductor structure 100, which includes a back-side source / drain contact 162 and a back-side gate contact 164, and the back-side back-end process (BEOL) structure 166 is based on the creation of a wiring scheme disposed on both sides of the device layer (front-end process structure).

[0121] Semiconductor devices and their fabrication methods according to the above-described technology can be used in various applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smartphones), solid-state storage devices, functional circuits, etc. Systems and hardware comprising semiconductor devices are contemplated embodiments of the present invention. In view of the teachings provided herein, those skilled in the art will be able to conceive of other implementations and applications of the embodiments of the present invention.

[0122] In some embodiments, the above-described technologies are used in conjunction with semiconductor devices that may require or otherwise utilize, for example, CMOS, MOSFET, and / or FinFET. As a non-limiting example, the semiconductor device may include, but is not limited to, CMOS, MOSFET, and FinFET devices, and / or semiconductor devices using CMOS, MOSFET, and / or FinFET technologies.

[0123] The various structures described above can be implemented in integrated circuits. The resulting integrated circuit chip can be distributed by the manufacturer in the form of a raw wafer (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a package. In the latter case, the chip is mounted in a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other more advanced carrier) or a multi-chip package (e.g., a ceramic carrier with one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either: (a) an intermediate product, such as a motherboard, or (b) a final product. The final product can be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and a central processing unit.

[0124] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to techniques found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: a first stacked device, comprising: a first field effect transistor comprising one or more first nanosheet layers; a second field effect transistor vertically stacked above the first field effect transistor, the second field effect transistor comprising one or more second nanosheet layers; and a first dielectric insulating layer located between the first field effect transistor and the second field effect transistor, the first dielectric insulating layer having a first width; and a second stacked device adjacent to the first stacked device, the second stacked device comprising: a third field effect transistor comprising one or more third nanosheet layers; a fourth field effect transistor vertically stacked above the third field effect transistor, the fourth field effect transistor comprising one or more fourth nanosheet layers; and a second dielectric insulating layer located between the third field effect transistor and the fourth field effect transistor, the second dielectric insulating layer having a second width that is less than the first width of the first dielectric insulating layer.

2. The semiconductor structure of claim 1, wherein, the first width of the first dielectric insulating layer is equal to a third width of the one or more second nanosheet layers, and the second width of the second dielectric insulating layer is equal to a fourth width of the one or more third nanosheet layers.

3. The semiconductor structure of claim 1 or 2, further comprising a third dielectric insulating layer disposed on a bottom surface of the first stacked device and a fourth dielectric insulating layer disposed on a bottom surface of the second stacked device.

4. The semiconductor structure according to any of the preceding claims, wherein, the first stacked device and the second stacked device are separated by an isolation dielectric pillar.

5. The semiconductor structure of any of the preceding claims, wherein, the first field effect transistor further comprises a first gate structure, and the second field effect transistor further comprises a second gate structure separated from the first gate structure by the first dielectric insulating layer.

6. The semiconductor structure of claim 5, further comprising a first frontside gate contact connected to the first gate structure and a frontside back end of line layer.

7. The semiconductor structure of claim 6, further comprising a backside gate contact connected to the second gate structure and a backside back end of line layer.

8. The semiconductor structure of any of the preceding claims, wherein, the second stacked device further comprises a third gate structure disposed above the third field effect transistor and the fourth field effect transistor.

9. The semiconductor structure of claim 8, further comprising a second frontside gate contact connected to the third gate structure and a frontside back end of line layer.

10. A semiconductor structure, comprising: a first stacked device, comprising: a first field effect transistor comprising a first gate structure; a second field effect transistor vertically stacked above the first field effect transistor, the second field effect transistor comprising a second gate structure; and a first dielectric insulating layer located between the first field effect transistor and the second field effect transistor and separating the first gate structure from the second gate structure; and a second stacked device adjacent to the first stacked device, the second stacked device comprising: a third field effect transistor; a fourth field effect transistor vertically stacked above the third field effect transistor; a second dielectric insulating layer located between the third field effect transistor and the fourth field effect transistor; and a third gate structure disposed above the third field effect transistor, the fourth field effect transistor, and the second dielectric insulating layer.

11. The semiconductor structure of claim 10, wherein, the third gate structure is a shared gate structure between the third field effect transistor and the fourth field effect transistor.

12. The semiconductor structure of claim 11, further comprising a first frontside gate contact connected to the third gate structure and a frontside back end of line layer.

13. The semiconductor structure of claim 12, further comprising a second frontside gate contact connected to the first gate structure and the frontside back end of line layer.

14. The semiconductor structure of claim 13, further comprising a backside gate contact connected to the second gate structure and a backside back end of line layer.

15. The semiconductor structure of any one of claims 10 to 14, wherein, the first dielectric insulating layer has a first width and the second dielectric insulating layer has a second width that is less than the first width of the first dielectric insulating layer.

16. The semiconductor structure of any one of claims 10 to 15, wherein, the first stacked device and the second stacked device are separated by an isolation dielectric pillar.

17. The semiconductor structure of any one of claims 10 to 16, wherein: the first field effect transistor comprises one or more first nanosheet layers; the second field effect transistor comprises one or more second nanosheet layers; the third field effect transistor comprises one or more third nanosheet layers; and the fourth field effect transistor comprises one or more fourth nanosheet layers.

18. An integrated circuit comprising: one or more semiconductor structures, wherein at least one semiconductor structure of the one or more semiconductor structures comprises: a first stacked device comprising: a first field effect transistor comprising a first gate structure; a second field effect transistor vertically stacked above the first field effect transistor, the second field effect transistor comprising a second gate structure; and a first dielectric insulating layer located between the first field effect transistor and the second field effect transistor and separating the first gate structure from the second gate structure; and a second stacked device adjacent to the first stacked device, the second stacked device comprising: a third field effect transistor; a fourth field effect transistor vertically stacked above the third field effect transistor; a second dielectric insulating layer located between the third field effect transistor and the fourth field effect transistor; and a third gate structure disposed above the third field effect transistor, the fourth field effect transistor, and the second dielectric insulating layer.

19. The integrated circuit of claim 18, wherein, the at least one semiconductor structure of the one or more semiconductor structures further comprises a first frontside gate contact connected to the third gate structure and a frontside back end of line layer.

20. The integrated circuit of claim 19, wherein, the at least one semiconductor structure of the one or more semiconductor structures further comprises a second frontside gate contact connected to the first gate structure and the frontside back end of line layer, and a backside gate contact connected to the second gate structure and a backside back end of line layer.

21. The integrated circuit of any one of claims 18-20, wherein, The first dielectric insulating layer has a first width, and the second dielectric insulating layer has a second width that is less than the first width of the first dielectric insulating layer.

22. The semiconductor structure of any one of claims 18-21, wherein: the first field effect transistor comprises one or more first nanosheet layers; the second field effect transistor comprises one or more second nanosheet layers; the third field effect transistor comprises one or more third nanosheet layers; and the fourth field effect transistor comprises one or more fourth nanosheet layers.

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